Module-oriented heat dissipation structure optimization method and system and medium

Abstract

The invention provides a module-oriented heat dissipation structure optimization method and system and a medium, and relates to the technical field of chip packaging, and the method comprises the steps: analyzing a chip module packaging structure, and constructing a module three-dimensional heat supply network model; combining a module working load scene to decompose heat dissipation and cooling requirements of each bare chip; and performing active heat dissipation mechanism search optimization according to the heat dissipation demand level of each bare chip in combination with spatial distribution, establishing a spatial mapping relationship, and obtaining heat dissipation structure parameters for chip module heat dissipation deployment and heat dissipation control. According to the invention, the technical problem that the system performance is limited by the hottest bare chip and the overall heat dissipation efficiency is affected due to the fact that the cooling capacity of a traditional overall heat dissipation device or a liquid cooling plate is uniformly distributed and on-demand cooling cannot be carried out according to the heat dissipation requirements of different areas in the module in the prior art is solved; a thermal environment is accurately analyzed by constructing a three-dimensional heat supply network model, differential heat dissipation requirements are decomposed according to workloads, and the heat dissipation efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip packaging, in particular to a module-oriented heat dissipation structure optimization method, system and medium. BACKGROUND

[0002] Chip modules generally adopt advanced packaging modules with high-density interconnection, containing multiple side-by-side or stacked dies. Heterogeneous chips such as computing units and storage units are integrated in a single package. However, while this integrated structure improves system performance, it also poses a serious thermal management challenge. Due to the extremely uneven distribution of heat flux density inside the module, the heat flux density of computing dies is much higher than that of storage dies, forming strong hot spots and hot zones. In 3D stacking, the heat of the upper dies is transferred to the lower dies, exacerbating the temperature rise of the bottom dies, resulting in significant longitudinal thermal coupling effects. Traditional integral heat sinks or liquid cooling plates have inherent uniform cooling characteristics, and their cooling capacity is uniformly distributed in space, which cannot match the highly heterogeneous heat dissipation needs inside the module, resulting in system performance being limited by the hottest die. In order to prevent overheating damage, the operating frequency of the entire module must be reduced, so that the performance of other dies with low temperature cannot be fully utilized, not only restricting the overall performance potential of the module, but also causing a huge waste of cooling energy.

[0003] In summary, the prior art has the technical problem that due to the extremely uneven heat flux density inside the advanced packaging module and the longitudinal thermal coupling effect, the cooling capacity of the traditional integral heat sink or liquid cooling plate is uniformly distributed, which cannot cool on demand according to the heat dissipation needs of different areas inside the module, resulting in system performance being limited by the hottest die, thereby affecting the overall heat dissipation efficiency. SUMMARY

[0004] The purpose of the present application is to provide a module-oriented heat dissipation structure optimization method, system and medium, to solve the technical problem in the prior art that due to the extremely uneven heat flux density inside the advanced packaging module and the longitudinal thermal coupling effect, the cooling capacity of the traditional integral heat sink or liquid cooling plate is uniformly distributed, which cannot cool on demand according to the heat dissipation needs of different areas inside the module, resulting in system performance being limited by the hottest die, thereby affecting the overall heat dissipation efficiency.

[0005] In order to achieve the above purpose, the present application provides a module-oriented heat dissipation structure optimization method, system and medium.

[0006] In a first aspect, the application provides a module-oriented heat dissipation structure optimization method, which is implemented by a module-oriented heat dissipation structure optimization system. The module-oriented heat dissipation structure optimization method comprises: analyzing a chip module packaging structure, constructing a module three-dimensional thermal network model based on the structure, spatial distribution and physical interaction relationship of the analyzed die; decomposing the heat dissipation cooling requirements of each die based on the module working load scenario and the module three-dimensional thermal network model, and obtaining the heat dissipation requirement level of each die; and establishing a thermoelectric refrigeration array, a micro-channel network and a die spatial mapping relationship according to the heat dissipation requirement level of each die and the space distribution for active heat dissipation mechanism search optimization, and obtaining heat dissipation structure parameters for chip module heat dissipation deployment and heat dissipation control.

[0007] Optionally, the packaging structure of the chip module is analyzed to obtain the size, spatial layout, interconnection mode and thermal physical parameters of the die and the packaging material; a thermal interaction relationship model between the dies and between the die and the packaging substrate is established according to the analyzed chip module packaging structure, and the thermal coupling strength is quantified; based on the thermal interaction relationship model and the thermal coupling strength, the heat flow path and the thermal blocking key area are identified, and the module three-dimensional thermal network model is constructed.

[0008] Optionally, the die, the interconnection bump, the through silicon via and the packaging substrate are discretized into thermal resistance network nodes, and a node topology relationship is established; based on the thermal resistance network nodes, the conduction thermal resistance between adjacent nodes is calculated using the Fourier law; for the interface with fluid gap or poor contact, an additional convective thermal resistance is introduced based on an empirical formula; the temperature data under different working conditions are measured by a thermal test chip, and the conduction thermal resistance and the convective thermal resistance are calibrated and verified; based on the verified thermal resistance network parameters and the node topology relationship, a parameterized compact thermal resistance network is constructed, and the thermal interaction relationship model is obtained; wherein, based on the calibrated thermal resistance parameters, the thermal coupling strength between the dies is quantified, and the thermal coupling strength is characterized by the equivalent thermal conductivity or the equivalent thermal resistance between the dies.

[0009] Optionally, the power load of the working load scenario is applied by using a finite element software to perform steady-state and transient thermal simulation, the main heat flow path is obtained by analyzing the temperature gradient field and the heat flow vector field in the simulation results, and the heat transfer channel from the heat source to the heat dissipation interface is identified; the area with a heat flux lower than the average value is defined as the thermal blocking key area; based on the main heat flow path, the thermal blocking key area and the quantified thermal coupling strength, the calibrated thermal resistance network model is reorganized to construct the module three-dimensional thermal network model.

[0010] Optionally, for the die pair with the thermal coupling strength higher than the first preset threshold, the corresponding die pair is node-aggregated in the three-dimensional thermal network and managed as a coupled heat source; for the die pair with the thermal coupling strength lower than the second preset threshold, a high-precision distributed thermal resistance is reserved on the die pair communication path; in the area with high thermal coupling strength and high heat flux density, the area is marked as a heat dissipation resource preferential allocation area.

[0011] Optionally, based on the working load scenario of the chip module, the power density distribution and dynamic power consumption characteristics of each die are analyzed, the temperature field distribution of the chip module under each working condition is predicted in combination with the three-dimensional thermal network model of the module, and based on the temperature field distribution, an overheating risk area is identified and a thermal management priority is configured, and the heat dissipation demand level of each die and the functional block inside the die is determined.

[0012] Optionally, an optimization deployment rule of the thermoelectric refrigeration array and the micro-channel network is established; the heat dissipation demand level, the spatial distribution characteristics, and the optimization deployment rule are matched to identify a mapping relationship maximizing the matching optimization target, and a spatial mapping relationship between the thermoelectric refrigeration array, the micro-channel network, and the die is obtained; a control parameter relationship between the thermoelectric refrigeration array, the micro-channel network, and the die is generated according to the spatial mapping relationship, and the heat dissipation structure parameters are obtained; wherein the optimization deployment rule of the thermoelectric refrigeration array is that the driving circuit of each thermoelectric refrigeration unit adopts an independent H-bridge topology structure, the layout and wiring of the H-bridge driving circuit are optimized according to the position and power demand of the thermoelectric refrigeration unit, and an independent current and temperature monitoring function is configured for each H-bridge driving circuit; the optimization deployment rule of the micro-channel network is that a piezoelectric micro-valve array is integrated in the micro-channel, and each micro-valve is driven by an independent H-bridge circuit; the micro-valve opening degree is adjusted dynamically according to the real-time thermal load, and the cooling liquid is distributed on demand.

[0013] Optionally, a temperature sensor network is integrated in the optimized heat dissipation structure and is configured on a plurality of dies of the chip module to collect temperature field data of the chip module in real time; the real-time temperature field data are compared with target temperature conditions, a target hotspot area for heat dissipation enhancement is identified based on the comparison result, a corresponding control instruction set is generated in combination with the heat dissipation structure parameters; and thermoelectric refrigeration and fluid guidance are synchronously executed according to the control instruction set, wherein the thermoelectric refrigeration is active refrigeration of the micro-thermoelectric refrigeration unit in the thermoelectric refrigeration array corresponding to the target hotspot area, and the fluid guidance is adjustment of the opening degree of the micro-valve in the embedded micro-channel network corresponding to the target hotspot area to increase the cooling liquid flow to the target hotspot area.

[0014] In a second aspect, the present application also provides a module-oriented heat dissipation structure optimization system for performing the module-oriented heat dissipation structure optimization method as described in the first aspect, wherein the module-oriented heat dissipation structure optimization system comprises: a package analysis module configured to analyze a chip module package structure, construct a module three-dimensional heat network model based on the structure, spatial distribution and physical interaction relationship of the analyzed dies; a requirement decomposition module configured to decompose the heat dissipation cooling requirements of each die based on a module working load scenario in combination with the module three-dimensional heat network model, and obtain the heat dissipation requirement levels of each die; and a heat dissipation optimization module configured to perform active heat dissipation mechanism search optimization according to the heat dissipation requirement levels of each die in combination with the spatial distribution, establish a spatial mapping relationship between a thermoelectric refrigeration array, a micro-channel network and the dies, and obtain heat dissipation structure parameters for chip module heat dissipation deployment and heat dissipation control.

[0015] In a third aspect, a computer-readable storage medium is provided, and the computer-readable storage medium stores a computer program. The computer program, when executed, implements the steps of the module-oriented heat dissipation structure optimization method of any one of the first aspect.

[0016] The one or more technical solutions provided in the present application have at least the following technical effects or advantages: By analyzing the chip module package structure, constructing a module three-dimensional heat network model based on the structure, spatial distribution and physical interaction relationship of the analyzed dies, decomposing the heat dissipation cooling requirements of each die based on a module working load scenario in combination with the module three-dimensional heat network model, obtaining the heat dissipation requirement levels of each die, and performing active heat dissipation mechanism search optimization according to the heat dissipation requirement levels of each die in combination with the spatial distribution, a spatial mapping relationship between a thermoelectric refrigeration array, a micro-channel network and the dies is established, and heat dissipation structure parameters are obtained for chip module heat dissipation deployment and heat dissipation control. That is, by analyzing the chip module package structure, constructing a module three-dimensional heat network model, determining the heat dissipation requirement levels of each die based on the model and the actual working scenario, and mapping the thermoelectric refrigeration array and the adjustable micro-channel network with the spatial positions of the dies, it is ensured that each die can be effectively cooled, and the overall heat dissipation efficiency is improved.

[0017] The above description is only a summary of the technical solutions of the present application. In order to enable a clearer understanding of the technical means of the present application, the present application can be implemented in accordance with the content of the specification, and in order to enable the above and other purposes, features and advantages of the present application to be more apparent and easy to understand, the following specific embodiments of the present application are described. It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only exemplary, and other drawings can be obtained by those skilled in the art without creative effort on the basis of the provided drawings.

[0019] Figure 1 The flowchart of the module-oriented heat dissipation structure optimization method of the application.

[0020] Figure 2 The structural diagram of the module-oriented heat dissipation structure optimization system of the application.

[0021] Legend: encapsulation analysis module 11, requirement decomposition module 12, heat dissipation optimization module 13. DETAILED DESCRIPTION

[0022] The application provides a module-oriented heat dissipation structure optimization method, system and medium, which solves the technical problem in the prior art that due to the extremely uneven heat flux density in the advanced packaging module and the longitudinal thermal coupling effect, the cooling capacity of the traditional overall heat sink or liquid cooling plate is uniformly distributed, and the on-demand cooling cannot be performed according to the heat dissipation requirements of different areas in the module, so that the system performance is limited by the hottest die, thereby affecting the overall heat dissipation efficiency. By analyzing the chip module packaging structure, a three-dimensional heat network model of the module is constructed, the heat dissipation requirement level of each die is determined based on the model and the actual working scene, the spatial position of the thermoelectric refrigeration array and the adjustable micro-channel network is mapped with the die, and it is ensured that each die can be effectively cooled, thereby improving the overall heat dissipation efficiency.

[0023] The technical solutions in the application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments of the application. It should be understood that the application is not limited by the example embodiments described herein. Based on the embodiments of the application, all other embodiments obtained by those skilled in the art without creative effort fall within the scope of protection of the application. In addition, it should be noted that only parts related to the application are shown in the drawings for convenience of description, rather than all parts.

[0024] Embodiment one, please refer to the attached Figure 1 The application provides a module-oriented heat dissipation structure optimization method, wherein the module-oriented heat dissipation structure optimization method is applied to a module-oriented heat dissipation structure optimization system, and the module-oriented heat dissipation structure optimization method specifically includes the following steps: Analyze the chip module packaging structure, construct a three-dimensional heat network model of the module based on the structure, spatial distribution and physical interaction relationship of the analyzed die.

[0025] Further, the application further comprises the following steps: analyzing the packaging structure of the chip module, obtaining the size, spatial layout, interconnection mode of the die, and the thermal physical parameters of the packaging material; establishing a thermal interaction relationship model between the dies and between the die and the packaging substrate according to the analyzed chip module packaging structure, quantifying the thermal coupling strength; identifying the heat flow path and the thermal blocking key area based on the thermal interaction relationship model and the thermal coupling strength, and constructing a three-dimensional thermal network model of the module.

[0026] Further, the application further comprises the following steps: discretizing the die, the interconnection bump, the through silicon via, and the packaging substrate into thermal resistance network nodes, and establishing a node topology relationship; calculating the conduction thermal resistance between adjacent nodes based on the thermal resistance network nodes using the Fourier law; for the interface with fluid gap or poor contact, introducing an additional convective thermal resistance based on an empirical formula; through the actual measurement of temperature data under different working conditions by the thermal test chip, calibrating and verifying the conduction thermal resistance and the convective thermal resistance; based on the verified thermal resistance network parameters and the node topology relationship, constructing a parameterized compact thermal resistance network, and obtaining the thermal interaction relationship model; wherein, based on the calibrated thermal resistance parameters, the thermal coupling strength between the dies is quantified, and the thermal coupling strength is characterized by the equivalent thermal conductivity or the equivalent thermal resistance between the dies.

[0027] Specifically, the chip module packaging structure refers to the layout mode of multiple dies in the package, the electrical connection mode between them, and the packaging material used. The die refers to a chip that has not been packaged, which is usually made of semiconductor material, and the die internally includes a computing unit, a storage unit, etc. In the packaging structure, the die directly exposes its heat source and electrical connection.

[0028] By analyzing the chip module packaging structure in detail, the size, spatial layout, interconnection method (such as through silicon via TSV, micro bump) and thermal physical parameters (such as thermal conductivity, specific heat capacity, etc.) of each die are first obtained. By consulting the chip design file and packaging specification, the size of all dies and their accurate spatial coordinates on the silicon interposer are accurately obtained. Among them, the spatial layout is the physical position and relative orientation relationship of each die on the packaging substrate, such as side-by-side arrangement through the silicon interposer in 2.5D packaging. The interconnection method is the way of electrical connection and physical fixation between dies and between dies and packaging substrates, mainly including micro bumps, through silicon vias, etc. Micro bumps are micron-level solder bumps used for flip-chip connection of dies and interposers or substrates, with a typical height of 20-50 μm and a diameter of 30-80 μm; through silicon vias are vertical interconnection structures penetrating the silicon substrate or silicon interposer, with a typical diameter of 5-10 μm and a depth of 50-100 μm, and the filling material is copper. Thermal physical parameters are inherent properties related to heat conduction of materials, mainly including thermal conductivity, specific heat capacity, density, etc. Thermal conductivity is the ability of a material to conduct heat, with a unit of W / (m·K). For example, silicon is about 150 W / (m·K), copper is about W / (m·K), and epoxy resin packaging material is about 0.8-1.5 W / (m·K). Specific heat capacity is the heat required to raise the temperature of a unit mass of a substance by a unit temperature, with a unit of J / (kg·K). Density is the mass per unit volume, with a unit of kg / m 3 . For example, a CPU die is 20 mm x 20 mm x 0.7 mm, and four HBM dies are each 8 mm x 5 mm x 0.5 mm. The interconnection method is copper micro bump (diameter 50 μm, height 25 μm) and through silicon via TSV (diameter 8 μm, depth 60 μm).

[0029] Based on the obtained packaging structure data, a thermal interaction relationship model between dies and dies, and between dies and packaging substrates is established. The dies, interconnection bumps, through silicon vias, packaging substrates, etc. are discretized into thermal resistance network nodes, that is, the continuous physical structure is conceptually divided into many small units, each unit is represented by a centralized thermal resistance to represent its thermal conductivity characteristics, and these units are called nodes. The connection relationship of the nodes constitutes a network. For example, a 10 mm x 10 mm die is discretized into 3 layers in the thickness direction and divided into a 5x5 grid in the plane direction, thereby generating 75 thermal resistance nodes; similarly, a micro bump with a diameter of 50 μm, a TSV with a diameter of 10 μm, and different layers of a packaging substrate are also modeled as single or multiple thermal resistance nodes. Subsequently, the node topology is established according to the actual physical connection relationship, such as a node at the bottom of a die connected to a node of a silicon interposer through a micro bump node.

[0030] A thermal resistance network is a network model representing heat flow transfer through thermal resistances between nodes and connections, each node representing a heat source or heat capacity, and connections between nodes representing conduction paths of heat flow. Based on the thermal resistance network nodes, conductive thermal resistances between all adjacent nodes are calculated using the Fourier law, which is a basic law of heat conduction indicating that the heat quantity (heat flow density) per unit time through a unit area is proportional to the temperature gradient, with the proportionality coefficient being the thermal conductivity of the material, and the formula is q = -k▽T, where q is the heat flow density, k is the thermal conductivity, and▽T is the temperature gradient.

[0031] For interfaces with fluid gaps or poor contact, such as the contact surface between a die and a packaging substrate, due to the low efficiency of heat transfer through the interface with poor contact or the fluid gap, a convective thermal resistance is often introduced. The convective thermal resistance is an additional thermal resistance due to the existence of microscopic gaps or fluid gaps between two solid contact surfaces. The convective thermal resistance is estimated by an empirical formula or measured data, for example, it is estimated to be 5.0 x 10 -5 m 2 K / W.

[0032] After establishing the thermal resistance network and calculating the corresponding thermal resistance values, the accuracy of the model is verified by actual thermal test chips. Temperature data under different working conditions are measured, and the conduction thermal resistance and the convective thermal resistance are calibrated and verified. Specifically, a module packaged with a thermal test chip is placed in a controllable environment, and under different working conditions, the temperature rise data at multiple positions are recorded by integrated temperature sensors. The simulation results of the initial thermal resistance network under the same power consumption conditions are compared with the measured data, and usually a deviation is found. According to this deviation, an inverse problem solving algorithm is used to iteratively optimize and calibrate the key uncertain parameters in the network.

[0033] According to the verified thermal resistance network parameters and node topological relationship, a parameterized compact thermal resistance network is constructed to obtain a thermal interaction relationship model. That is, the thermal interaction relationship model is specifically constructed as a parameterized compact thermal resistance network. The parameterized compact thermal resistance network is a simplified thermal model in which the key thermal characteristics are retained. The thermal resistance values in the network are not fixed values, but can be calculated or adjusted by basic parameters such as geometric dimensions and material properties, so that the model has good adaptability and scalability.

[0034] According to the calibrated thermal resistance parameters, the thermal coupling strength between the dies is quantified by calculating the equivalent thermal conductance or equivalent thermal resistance between the dies. The thermal coupling strength reflects the degree of influence of one die heat source on other die heat sources, helping to analyze which areas have faster heat transfer and which areas have heat accumulation. The greater the equivalent thermal conductance or the smaller the equivalent thermal resistance, the easier the heat is to conduct between the two dies, and the stronger the thermal coupling. For example, when an 80W power is applied on the first die, the temperature rise of the second die (adjacent to it through the silicon interposer and micro bumps) is measured to be 12℃, the equivalent thermal resistance between the two dies is 0.15K / W, and the equivalent thermal conductance is 6.67W / K.

[0035] On the calibrated model, a simulation of a typical working condition is run, and by analyzing the heat flow vector diagram, the main heat flow path is identified, and the thermal blocking key area is located, for example, CPU→micro bump→silicon interposer→thermal conductive glue→heat dissipation cover, a certain interposer area located directly below the center of a large die and having a low TSV density, has a local heat flux 30% lower than the periphery. Based on all this information, the detailed finite element model is simplified into a three-dimensional compact thermal network model consisting of hundreds of thermal resistance nodes, which is experimentally verified, and the model can greatly improve the speed of subsequent simulation optimization while ensuring accuracy.

[0036] Further, the application further includes the following steps: using finite element software to apply power load of working load scene, performing steady-state and transient thermal simulation, obtaining the main heat flow path by analyzing the temperature gradient field and heat flow vector field in the simulation results, and identifying the heat transfer channel from the heat source to the heat dissipation interface; defining the area with heat flux lower than the average value as the thermal blocking key area; based on the main heat flow path, the thermal blocking key area, and the quantified thermal coupling strength, recombining the calibrated thermal resistance network model to construct the modular three-dimensional thermal network model.

[0037] Further, the application further includes the following steps: for the die pair with a thermal coupling strength higher than a first preset threshold, the corresponding die pair is aggregated in the three-dimensional thermal network as a coupled heat source for management; for the die pair with a thermal coupling strength lower than a second preset threshold, a high-precision distributed thermal resistance is reserved on the die pair communication path; in the area with high thermal coupling strength and high heat flux density, it is marked as a heat dissipation resource preferential allocation area.

[0038] Specifically, the calibrated detailed thermal resistance network is intelligently simplified and reorganized to build a three-dimensional thermal network model with both computational efficiency and key accuracy, providing a lightweight and sufficiently accurate tool for subsequent system-level thermal optimization and control. Using finite element software, the detailed model containing millions of grids is subjected to power loads of workload scenarios, and steady-state and transient thermal simulations are performed. Through post-processing, the temperature gradient field and heat flow vector field are visualized and analyzed, and it is observed that heat is mainly generated from the CPU and HBM dies, passes through the silicon interposer, thermal interface material, and finally converges to the heat sink cover, which is the main heat flow path. At the same time, a quantitative indicator is defined in the simulation results, and the area with a heat flux density lower than the average value is defined as a thermal blocking key area. These areas are prone to heat accumulation due to low thermal transfer efficiency. For example, the average heat flux density of the entire model cross-section is 50 W / cm 2 Then all the areas with a local heat flux density lower than 30% of this average value, i.e., < 35 W / cm 2 , are identified as thermal blocking key areas, such as the area under a die edge or the local area of the interposer due to insufficient TSV density.

[0039] The temperature gradient field is a vector field of the rate of temperature change in space, with the direction pointing to the direction of the fastest temperature increase and the size indicating the degree of change. Heat flow always flows from high temperature to low temperature, against the direction of the temperature gradient. The heat flow vector field is used to describe the vector field of the direction and size of the heat flow at each point in space. By analyzing the heat flow vector field, we can intuitively see how heat flows from the heat source (die) to the heat dissipation interface (such as the heat sink cover). The main heat flow path refers to the dominant heat conduction channel connecting the heat source and the heat dissipation interface in the heat flow vector field, with a heat flux density significantly higher than other areas. The thermal blocking key area refers to the area with a heat flux density lower than the average value, which is prone to local temperature rise due to low thermal conduction efficiency or limited heat transfer, affecting the overall heat dissipation effect.

[0040] Based on the heat flow path and the thermal blocking key area, and combined with the quantitative thermal coupling strength, the calibrated thermal resistance network model is reorganized. The first preset threshold and the second preset threshold are determined, respectively, for identifying strong coupling and weak coupling. The first preset threshold is a critical value for determining whether there is strong thermal coupling between two dies. When the coupling strength of a die pair is higher than the first preset threshold, it means that their thermal behavior is highly consistent and can be considered as a whole in thermal management. The second preset threshold is a critical value for determining weak thermal coupling between two dies. When the coupling strength of a die pair is lower than the second preset threshold, it means that the mutual thermal influence between them is minimal and can be considered as independent thermal domains.

[0041] By sensitivity analysis, in the base thermal model, the thermal coupling strength between a pair of dies is gradually increased to observe its impact on the maximum temperature of the whole module. When the coupling strength increases to a certain extent, the temperature behavior of the pair of dies shows high consistency, for example, the temperature change of one die affects the temperature of the other die by more than a certain percentage, such as 15%, and they are combined into a node pair. The loss of accuracy of system-level thermal analysis is within an acceptable range, for example, the maximum temperature prediction error is <2%, and the coupling strength value at this time is set as the first preset threshold.

[0042] Similarly, by analysis, when the thermal coupling strength between a pair of dies is low, and their mutual thermal influence can be ignored, for example, when one die is fully loaded, the temperature rise contribution to the other die is less than 1%, the coupling strength value at this time is the second preset threshold. Below this value, it means that they are almost independent thermal domains.

[0043] For all pairs of dies, calculate their equivalent thermal conductance or equivalent thermal resistance. If the thermal coupling strength of the die pair is higher than the first preset threshold, it is considered that the thermal coupling strength between them is strong enough, and the corresponding die pair is aggregated in the three-dimensional thermal network as a coupled heat source for management. For the die pair whose thermal coupling strength is lower than the second preset threshold, a high-precision distributed thermal resistance is retained on their connected path to accurately capture the weak interaction. Distributed thermal resistance refers to retaining multiple small thermal resistance elements in the heat conduction path to simulate the transfer of heat.

[0044] Mark the area with high thermal coupling strength and high heat flux density itself as the priority allocation area of heat dissipation resources. Some areas may cause overheating due to high heat generation, so cooling capacity should be increased, such as strengthening the cooling fins, thermoelectric refrigeration or micro-channel network, etc. For example, in a module integrating 1 GPU die (450W, heat flux density ~200 W / cm 2), 2 HBM dies (60 W each), and 1 SerDes die (20 W) is applied. The equivalent thermal conductance between the GPU and HBM1 is calculated to be 8.5 W / K, which is higher than the first preset threshold 7 W / K, so the GPU and HBM1 nodes are aggregated; the equivalent thermal conductance between the GPU and SerDes is 0.3 W / K, which is lower than the second preset threshold 0.5 W / K, so the distributed thermal resistance is retained on the path between them; the aggregated GPU-HBM1 region is marked as a heat dissipation resource priority allocation area due to its high heat flux density and strong coupling. The high-precision model before reorganization has 5000 nodes, and the transient simulation takes 45 minutes, and the maximum junction temperature is predicted to be 92.4℃; the compact model after reorganization has only 550 nodes, and the transient simulation only takes 3 minutes; under the same dynamic workload, the maximum junction temperature predicted by the compact model is 93.1℃, with an error of only 0.76% compared with the detailed model, far lower than the target of 2%, fully meeting the engineering accuracy requirements.

[0045] Through this series of operations, the detailed finite element model originally containing thousands of nodes is reconstructed into a compact three-dimensional thermal network model that may only contain hundreds of nodes and has clear physical meaning, and the calculation speed can be improved by one to two orders of magnitude, while retaining the key characteristics affecting the thermal behavior. Through the rules driven by physics, the high-precision but computationally expensive detailed model is converted into a lightweight, efficient three-dimensional thermal network model that retains key thermal characteristics at the system level, not only greatly improving the calculation speed of subsequent system-level simulation and optimization, but more importantly, through node aggregation and priority area marking, the focus of heat dissipation design is directly guided from the model level, ensuring that the most valuable heat dissipation resources can be invested in the most needed and most effective areas.

[0046] Based on the module workload scenario and the module three-dimensional thermal network model, the heat dissipation cooling requirements of each die are decomposed to obtain the heat dissipation requirement level of each die.

[0047] Further, the application further includes the following steps: based on the workload scenario of the chip module, analyzing the power density distribution and dynamic power consumption characteristics of each die, combining the module three-dimensional thermal network model, predicting the temperature field distribution of the chip module under each working condition; based on the temperature field distribution, identifying the overheating risk area and configuring the heat management priority, determining the heat dissipation requirement level of each die and the functional block inside the die.

[0048] Specifically, the workload scenario of the chip module is defined, i.e., the working state and task load of the chip module under different working conditions. According to the workload scenario of the chip module, the power density distribution and dynamic power consumption characteristics of each die are analyzed. The power density distribution refers to the power consumption value per unit area inside the die, which describes the spatial non-uniformity of heat generation on the surface of the die. The dynamic power consumption characteristics describe the law of change of the power consumption of the die over time, including the peak value, average value, transient change rate of the power consumption, and the phase relationship of the power consumption of different functional units.

[0049] The power density of each die is analyzed, including the power consumption of each region of the chip under different workloads. Considering the factors such as frequency adjustment, clock switching, load fluctuation, etc. of the chip during operation, its instantaneous power consumption is predicted. For example, the power consumption of a GPU die jumps from 200W to 320W within 1ms, and then drops after maintaining at a high level for 500us, while the power density of the tensor core block inside it is as high as 180W / cm 2 .

[0050] The power density distribution and dynamic power consumption characteristics are input into the three-dimensional thermal network model of the module for transient thermal simulation. After the simulation is completed, the complete temperature field distribution sequence of the chip module from startup to steady state under this dynamic scenario is obtained, and it is observed how the hot spots are generated, moved and evolved with the change of power consumption. The three-dimensional thermal network model of the module will predict the temperature change of the module under different working conditions according to the power load, thermal conductivity and thermal coupling relationship of each die. In the steady state, heat transfer reaches equilibrium, and the temperature field distribution tends to be stable; in the transient state, the temperature changes with time, mainly reflecting the temperature response of the chip when the load changes. The temperature field distribution refers to the temperature change at different positions, which can reflect how heat is conducted and distributed between different regions inside the chip module.

[0051] Based on the peak temperature field obtained by simulation, a temperature threshold is set to automatically identify the overheating risk area. For example, the safe upper limit of junction temperature is 105℃, and the performance reduction threshold is 95℃. The peak value of 98℃ in the tensor core area of the GPU is marked as high risk. Configure the thermal management priority, based on the temperature field distribution and the overheating risk area, determine which areas need to be given priority to heat dissipation management. Generally, areas with high power density and high temperature need more heat dissipation resources. While low load and low temperature areas can relatively reduce cooling resources. The priority rule comprehensively considers the absolute temperature (the closer to the upper limit, the higher the priority), the temperature change rate (the faster the temperature rises, the higher the priority), the functional criticality of the area (such as the calculation core priority higher than the cache), and the heat coupling strength of the heat source to others. Finally, the heat dissipation demand level of each part is determined, which is used to represent the urgency of cooling capacity of a die or its internal functional block, usually divided into high, medium and low levels. For example, areas with peak temperature > 95℃ or temperature rise rate > 10℃ / ms are classified as the highest heat dissipation demand level; the temperature is between 85℃-95℃ or the function area affected by strong thermal coupling is classified as the medium demand level; the temperature < 85℃ and the heat impact is small area is classified as the basic demand level.

[0052] By combining the workload scenario, power density distribution and three-dimensional thermal network model, the temperature field distribution of the chip module is accurately predicted, and the overheating risk area is identified based on the temperature field distribution, which helps to monitor and optimize the heat dissipation strategy in real time during operation, and avoid damage caused by local overheating. By configuring the thermal management priority, cooling resources can be reasonably allocated according to the heat dissipation demand level of each area, ensuring that limited cooling resources are prioritized for high-temperature and high-load areas, and improving overall heat dissipation efficiency.

[0053] According to the heat dissipation demand level of each die combined with the spatial distribution, the active heat dissipation mechanism is searched and optimized, the spatial mapping relationship between the thermoelectric refrigeration array, the micro-channel network and the die is established, and the heat dissipation structure parameters are obtained, which are used for chip module heat dissipation deployment and heat dissipation control.

[0054] Further, the application further comprises the following steps: establishing an optimized deployment rule of the thermoelectric refrigeration array and the micro-channel network; matching the heat dissipation requirement level, the spatial distribution characteristics, and the optimized deployment rule to identify a mapping relationship that maximizes the matching optimization target, and obtaining a mapping relationship between the thermoelectric refrigeration array, the micro-channel network, and the die space; generating a control parameter relationship between the thermoelectric refrigeration array, the micro-channel network, and the die according to the mapping relationship between the thermoelectric refrigeration array, the micro-channel network, and the die space, and obtaining the heat dissipation structure parameters; wherein the optimized deployment rule of the thermoelectric refrigeration array is that the driving circuit of each thermoelectric refrigeration unit adopts an independent H-bridge topology structure, the layout and wiring of the H-bridge driving circuit are optimized according to the position and power requirement of the thermoelectric refrigeration unit, and an independent current and temperature monitoring function is configured for each H-bridge driving circuit; and the optimized deployment rule of the micro-channel network is that a piezoelectric micro-valve array is integrated in the micro-channel, each micro-valve is driven by an independent H-bridge circuit, the micro-valve opening degree is adjusted dynamically according to the real-time heat load, and the cooling liquid is distributed on demand.

[0055] Specifically, the optimized deployment rule of the thermoelectric refrigeration array and the micro-channel network is a series of guidelines and constraints for guiding how the thermoelectric refrigeration array and the micro-channel network are arranged, designed, and controlled in space. The layout of the thermoelectric refrigeration unit is determined according to the heat dissipation requirement of the chip module and the temperature distribution of each die. The thermoelectric refrigeration unit is usually located in a high-power density or high-temperature area to provide precise local cooling. The driving circuit of each thermoelectric refrigeration unit needs to be equipped with an independent H-bridge circuit to control the current flow, thereby adjusting the refrigeration capacity of the thermoelectric unit. This means that unit A can be commanded to work at full capacity, while unit B adjacent to it can be operated at half power, or even unit C can be slightly heated (for precise temperature adjustment), without interfering with each other. In addition, each H-bridge driving circuit is configured with an independent current and temperature monitoring function. The current monitoring function can track the working current of each thermoelectric unit in real time to ensure that it is within the set working range. The temperature monitoring function is used to monitor the temperature of the thermoelectric refrigeration unit to prevent overheating and protect the equipment.

[0056] The layout of the micro-channel network should also be optimized according to the heat dissipation requirements and the cooling fluid flow requirements. The piezoelectric micro-valve array should be integrated in the micro-channel. Each micro-valve is driven by an independent H-bridge circuit. The piezoelectric micro-valve can dynamically adjust its opening degree according to real-time thermal load data to accurately control the cooling fluid flow. According to the thermal requirements of different areas, the micro-channel network can adjust the opening degree of the micro-valve to allocate the cooling fluid flow as needed, thereby achieving precise cooling. The H-bridge circuit controls the opening degree of the micro-valve to adjust the cooling fluid flow to the target hotspot area. Each micro-valve is independently controlled and can dynamically adjust the flow and flow direction according to the real-time change of the thermal load, ensuring that the cooling fluid can flow through the area with higher temperature most effectively. For example, in the area corresponding to the highest heat dissipation requirement level, the flow channel cross-section changes from the standard 200μm×300μm to a flat rectangle of 150μm×400μm to increase the contact area, and a dense micro-prism or porous structure is processed on the bottom surface to strengthen the turbulent flow and heat exchange.

[0057] According to the heat dissipation requirement level and the spatial distribution characteristics of the chip module, such as the power density of the die, the heat flow path, etc., match with the optimization deployment rules of the thermoelectric refrigeration array and the micro-channel network. Through matching, it can be ensured that the layout of the thermoelectric refrigeration unit and the micro-channel can maximize the optimization of the heat dissipation effect of the chip module. The matching process will consider multiple optimization objectives at the same time, including minimizing the highest temperature of the module, optimizing temperature uniformity, minimizing the energy consumption of the heat dissipation system, and optimizing the compactness of the structure, etc., and select one or more as the optimization objective. For example, taking the minimization of the highest temperature of the module and the minimization of the energy consumption of the heat dissipation system as the double objectives.

[0058] Based on the spatial mapping relationship with the die, thousands of schemes are evaluated to finally find a set of optimal solutions, i.e. the control parameters of each thermoelectric refrigeration unit and micro-channel network. Under this mapping relationship, it is difficult to find a scheme that can improve one objective without sacrificing another objective. For the thermoelectric refrigeration array, the driving current and operating temperature range of each thermoelectric unit need to be determined. For the micro-channel network, the opening degree and flow control range of each micro-valve need to be determined.

[0059] According to the layout and requirements, the driving circuit of each thermoelectric refrigeration unit adopts an independent H-bridge topology structure to facilitate the independent adjustment of the refrigeration capacity of each unit. The layout and wiring of the H-bridge circuit should be optimized according to the current requirements, location and system design to ensure the reliability and efficiency of the system. The opening degree of the micro-valve is adjusted dynamically according to the thermal load to optimize the distribution of the cooling fluid flow. In addition, the cross-sectional shape and surface microstructure of the micro-channel can also be optimized according to the flow requirements to increase the heat exchange surface area and thereby improve the heat exchange efficiency.

[0060] According to the optimal mapping relationship determined by optimization, a control parameter relationship is generated. All these physical layout sizes, driving circuit parameters and control logic relationships jointly constitute the final deliverable heat dissipation structure parameters, including the cell position and size of the TEC array, the layout and cross-sectional size of the micro-channel, and the control lookup table or function relationship of the driving circuit. By establishing clear optimization deployment rules and performing multi-objective optimization matching, it ensures that the designed TEC array and micro-channel network are highly matched with the thermal characteristics of the chip module in physical space and control logic. The final output of the heat dissipation structure parameters and the control parameter relationship enables the subsequent heat dissipation deployment and control to achieve real on-demand allocation and dynamic precise adjustment, thereby significantly improving the energy efficiency of the entire heat dissipation system while ensuring the safety temperature and temperature uniformity of the chip module.

[0061] Further, the application further includes the following steps: integrating a temperature sensor network in the optimized heat dissipation structure, which is configured on multiple dies of the chip module for real-time collection of temperature field data of the chip module; comparing the real-time temperature field data with the target temperature condition, identifying the target hotspot area for enhanced heat dissipation based on the comparison result, and generating corresponding control instruction set in combination with the heat dissipation structure parameters; and synchronously executing the thermoelectric refrigeration and fluid guidance according to the control instruction set, wherein the thermoelectric refrigeration and fluid guidance are independently executed, the thermoelectric refrigeration is to actively refrigerate the micro thermoelectric refrigerator unit in the thermoelectric refrigeration array corresponding to the target hotspot area, and the fluid guidance is to adjust the opening of the micro valve in the embedded micro-channel network corresponding to the target hotspot area, thereby increasing the flow of cooling liquid to the target hotspot area.

[0062] Specifically, a temperature sensor network is integrated on the optimized internal heat dissipation structure of the chip module to cover all key die areas. Each sensor will collect temperature data on the chip surface in real time to form temperature field data. The real-time collected temperature data is compared with the target temperature condition, which is a pre-set ideal temperature range or upper limit value expected to be maintained. Based on the comparison result, the target hotspot area for enhanced heat dissipation is identified. The target hotspot area for enhanced heat dissipation is a local area in the real-time temperature field that is identified as having a current temperature exceeding or approaching the target temperature condition and requiring immediate enhanced cooling measures.

[0063] According to the heat dissipation target hotspot area, the corresponding control instruction set is generated combined with the heat dissipation structure parameters, which contains how to adjust the working state of the thermoelectric refrigeration unit and the opening of the micro valve in the micro channel network. The control instruction set will ensure that the temperature of the hotspot area is effectively controlled, thereby avoiding temperature exceeding and chip damage. According to the control instruction set, the thermoelectric refrigeration and fluid guidance are executed synchronously, which means that the current control of TEC and the opening control of micro valve are processed by different subsystems in parallel, without waiting for each other, which ensures the fastest response speed.

[0064] According to the control instruction, the thermoelectric refrigeration unit will actively refrigerate the hotspot area. The thermoelectric refrigeration unit controls its refrigeration effect by adjusting the current size, ensuring that the temperature of the hotspot area is reduced to the safe range. At the same time, the micro valve in the micro channel network adjusts its opening according to the control instruction to accurately adjust the flow of the cooling liquid. Increasing the flow of the cooling liquid helps to further take away heat and enhance the heat dissipation effect. The operation of thermoelectric refrigeration specifically shows that the four micro TEC units corresponding to the target hotspot area receive a driving current of 2.8A within 100 microseconds, starting to refrigerate powerfully. The fluid guidance operation shows that the piezoelectric driver of the two micro valves corresponding to the target area deflects the valve plate to a position of 85% opening within 10 milliseconds, significantly increasing the flow of the cooling liquid to the hotspot area.

[0065] By integrating the temperature sensor network and quickly processing real-time data, the ability to dynamically perceive the thermal state and quickly identify the hotspot is achieved. By generating control instruction set combined with heat dissipation structure parameters, precise matching of cooling instructions and physical positions is achieved. Through the synchronous but independent execution of thermoelectric refrigeration and fluid guidance, a multi-modal and collaborative active heat dissipation response mechanism is formed.

[0066] In summary, the module-oriented heat dissipation structure optimization method provided by the present application has the following technical effects: By analyzing the chip module packaging structure, based on the structure, spatial distribution and physical interaction relationship of the analyzed die, a three-dimensional thermal network model of the module is constructed. Based on the module work load scene combined with the three-dimensional thermal network model of the module, the heat dissipation cooling demand of each die is decomposed, and the heat dissipation demand level of each die is obtained. According to the heat dissipation demand level of each die combined with the spatial distribution, the active heat dissipation mechanism is searched and optimized, the spatial mapping relationship between the thermoelectric refrigeration array, the micro channel network and the die is established, and the heat dissipation structure parameters are obtained, which are used for chip module heat dissipation deployment and heat dissipation control. That is, by analyzing the chip module packaging structure, constructing a three-dimensional thermal network model of the module, determining the heat dissipation demand level of each die based on the model and the actual working scene, and mapping the thermoelectric refrigeration array and the adjustable micro channel network with the spatial position of the die, it is ensured that each die can be effectively cooled, and the overall heat dissipation efficiency is improved.

[0067] Embodiment two, based on the same inventive concept as the module-oriented heat dissipation structure optimization method in the foregoing embodiment one, the present application also provides a module-oriented heat dissipation structure optimization system, please refer to the accompanying drawings Figure 2 , the module-oriented heat dissipation structure optimization system comprises: The package analysis module 11 is used for analyzing the chip module package structure, constructing a three-dimensional thermal network model of the module based on the structure, spatial distribution and physical interaction relationship of the die; the demand decomposition module 12 is used for decomposing the heat dissipation cooling demand of each die based on the module working load scene combined with the three-dimensional thermal network model of the module, obtaining the heat dissipation demand level of each die; the heat dissipation optimization module 13 is used for searching and optimizing the active heat dissipation mechanism according to the heat dissipation demand level of each die combined with the spatial distribution, establishing the space mapping relationship of the thermoelectric refrigeration array, micro-channel network and die, obtaining the heat dissipation structure parameters, and used for chip module heat dissipation deployment and heat dissipation control.

[0068] Further, the package analysis module 11 in the module-oriented heat dissipation structure optimization system is also used for: analyzing the package structure of the chip module, obtaining the size, spatial layout, interconnection mode of the die and the thermal physical parameters of the packaging material; according to the analyzed chip module package structure, establishing a thermal interaction relationship model between the die and the die, between the die and the packaging substrate, and quantifying the thermal coupling strength; based on the thermal interaction relationship model and the thermal coupling strength, identifying the heat flow path and the thermal blocking key area, and constructing a three-dimensional thermal network model of the module.

[0069] Further, the package analysis module 11 in the module-oriented heat dissipation structure optimization system is also used for: discretizing the die, interconnection bump, through silicon via and packaging substrate into thermal resistance network nodes, establishing node topological relationship; based on the thermal resistance network nodes, using Fourier's law to calculate the conduction thermal resistance between adjacent nodes; for the interface with fluid gap or poor contact, introducing additional convective thermal resistance based on empirical formula; through the temperature data measured by the thermal test chip under different working conditions, calibrating and verifying the conduction thermal resistance and the convective thermal resistance; based on the verified thermal resistance network parameters and the node topological relationship, constructing a parameterized compact thermal resistance network, and obtaining the thermal interaction relationship model; wherein, based on the calibrated thermal resistance parameters, quantifying the thermal coupling strength between the die and the die, and the thermal coupling strength is characterized by the equivalent thermal conductivity or equivalent thermal resistance between the dies.

[0070] Further, the package analysis module 11 in the module-oriented heat dissipation structure optimization system is further used for: applying power load of a working load scenario by using finite element software, performing steady-state and transient thermal simulation, obtaining a main heat flow path by analyzing temperature gradient field and heat flow vector field in simulation results, and identifying a heat transfer channel from a heat source to a heat dissipation interface; defining an area with a heat flow density lower than an average value as a thermal blocking key area; and recombining a calibrated thermal resistance network model based on the main heat flow path, the thermal blocking key area, and in combination with quantified thermal coupling strength, to construct the module three-dimensional thermal network model.

[0071] Further, the package analysis module 11 in the module-oriented heat dissipation structure optimization system is further used for: for a die pair with thermal coupling strength higher than a first preset threshold, performing node aggregation on corresponding dies in a three-dimensional thermal network, and regarding the die pair as a coupled heat source for management; for a die pair with thermal coupling strength lower than a second preset threshold, reserving high-precision distributed thermal resistance on a die pair communication path; and for an area with high thermal coupling strength and high heat flow density, marking the area as a heat dissipation resource preferential allocation area.

[0072] Further, the requirement decomposition module 12 in the module-oriented heat dissipation structure optimization system is further used for: based on a working load scenario of a chip module, analyzing power density distribution and dynamic power consumption characteristics of each die, combining the module three-dimensional thermal network model, and predicting temperature field distribution of the chip module under each working condition; based on the temperature field distribution, identifying an overheating risk area and configuring a thermal management priority, and determining heat dissipation requirement levels of each die and a functional block inside the die.

[0073] Further, the heat dissipation optimization module 13 in the module-oriented heat dissipation structure optimization system is further used for: establishing optimization deployment rules of the thermoelectric refrigeration array and the micro-channel network; matching the heat dissipation requirement levels, spatial distribution characteristics, and the optimization deployment rules, identifying a mapping relationship maximizing a matching optimization target, and obtaining a thermoelectric refrigeration array-micro-channel network-die spatial mapping relationship; generating a thermoelectric refrigeration array-micro-channel network-die control parameter relationship according to the thermoelectric refrigeration array-micro-channel network-die spatial mapping relationship, and obtaining the heat dissipation structure parameters; wherein the thermoelectric refrigeration array optimization deployment rules are: a driving circuit of each thermoelectric refrigeration unit adopts an independent H-bridge topology structure, the layout and wiring of the H-bridge driving circuit are optimized according to the position and power requirement of the thermoelectric refrigeration unit, and an independent current and temperature monitoring function is configured for each H-bridge driving circuit; and the micro-channel network optimization deployment rules are: a piezoelectric micro-valve array is integrated in the micro-channel, each micro-valve is driven by an independent H-bridge circuit, the micro-valve opening degree is adjusted dynamically according to real-time thermal load, and cooling liquid is distributed on demand.

[0074] Further, the heat dissipation optimization module 13 in the module-oriented heat dissipation structure optimization system is further configured to integrate a temperature sensor network in the optimized heat dissipation structure, the temperature sensor network being configured on a plurality of dies of the chip module and used to collect temperature field data of the chip module in real time; compare the real-time temperature field data with a target temperature condition, identify a target hotspot area for heat dissipation enhancement based on a comparison result, and generate a corresponding control instruction set in combination with the heat dissipation structure parameters; and execute thermoelectric refrigeration and fluid guidance in a synchronous manner according to the control instruction set, the thermoelectric refrigeration and the fluid guidance being executed independently, wherein the thermoelectric refrigeration is to drive a micro thermoelectric refrigerator unit in the thermoelectric refrigeration array corresponding to the target hotspot area to actively refrigerate, and the fluid guidance is to adjust an opening degree of a micro valve in an embedded microfluidic network corresponding to the target hotspot area to increase a flow of cooling liquid to the target hotspot area.

[0075] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The foregoing Figure 1 The module-oriented heat dissipation structure optimization method and specific examples in Embodiment One are also applicable to the module-oriented heat dissipation structure optimization system of the present embodiment. As can be clearly understood by those skilled in the art from the foregoing detailed description of the module-oriented heat dissipation structure optimization method, the module-oriented heat dissipation structure optimization system of the present embodiment is not described in detail herein for the sake of brevity.

[0076] Embodiment Three, based on the same inventive concept as the module-oriented heat dissipation structure optimization method in Embodiment One, the present application also provides a computer-readable storage medium, the computer-readable storage medium storing a computer program, the computer program implementing the steps of the module-oriented heat dissipation structure optimization method in any one of Embodiment One when executed.

[0077] The above description of the disclosed embodiments enables a person skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

[0078] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the present application and its equivalents, the present application is intended to include these modifications and variations.

Claims

1. A method for optimizing the heat dissipation structure of a module, characterized in that, include: Analyze the chip module packaging structure, and construct a three-dimensional thermal network model of the module based on the analysis of the structure, spatial distribution and physical interaction of the bare die. Based on the module's workload scenario and the module's three-dimensional thermal network model, the heat dissipation and cooling requirements of each bare chip are decomposed to obtain the heat dissipation requirement level of each bare chip. Based on the heat dissipation requirements of each die and their spatial distribution, an active heat dissipation mechanism is searched and optimized. A spatial mapping relationship between the thermoelectric cooling array, the microfluidic network and the die is established to obtain heat dissipation structure parameters for chip module heat dissipation deployment and control.

2. The heat dissipation structure optimization method for modules according to claim 1, characterized in that, The construction of the three-dimensional heating network model includes: Analyze the chip module's packaging structure to obtain the die's dimensions, spatial layout, interconnection method, and thermophysical parameters of the packaging material; Based on the analyzed chip module packaging structure, a thermal interaction model is established between bare dies and between bare dies and the packaging substrate to quantify the thermal coupling strength. Based on the thermal interaction model and thermal coupling strength, the heat flow path and key thermal blockage areas are identified, and a three-dimensional heat network model of the module is constructed.

3. The heat dissipation structure optimization method for modules according to claim 2, characterized in that, Based on the module's workload scenario and the module's 3D thermal network model, the heat dissipation and cooling requirements of each die are decomposed to obtain the heat dissipation requirement level of each die, including: Based on the workload scenarios of the chip module, the power density distribution and dynamic power consumption characteristics of each die are analyzed. Combined with the three-dimensional thermal network model of the module, the temperature field distribution of the chip module under various operating conditions is predicted. Based on the temperature field distribution, overheating risk areas are identified and thermal management priorities are configured to determine the heat dissipation requirements of each die and its internal functional blocks.

4. The heat dissipation structure optimization method for modules according to claim 2, characterized in that, Establish thermal interaction models between bare dies and between bare dies and the packaging substrate, including: The bare die, interconnect bumps, through-silicon vias, and packaging substrate are discretized into thermal resistance network nodes, and the node topology is established. Based on the thermal resistance network nodes, Fourier's law is used to calculate the thermal resistance between adjacent nodes. For interfaces with fluid gaps or poor contact, additional convective thermal resistance is introduced based on empirical formulas. Temperature data under different operating conditions were measured using a thermal testing chip to calibrate and verify the thermal resistance network parameters of the conductive thermal resistance and the convective thermal resistance. Based on the verified thermal resistance network parameters and node topology, a parameterized compact thermal resistance network is constructed to obtain the thermal interaction relationship model. Specifically, based on the calibrated thermal resistance parameters, the thermal coupling strength between the dies is quantified, and the thermal coupling strength is characterized by the equivalent thermal conductance or equivalent thermal resistance between the dies.

5. The heat dissipation structure optimization method for modules according to claim 4, characterized in that, The process of identifying heat flow paths and key areas of thermal blockage, and constructing a three-dimensional heat network model of the module, includes: Using finite element software, a power load is applied to the working load scenario, and steady-state and transient thermal simulations are performed. By analyzing the temperature gradient field and heat flow vector field in the simulation results, the main heat flow path is obtained, and the heat transfer channel from the heat source to the heat dissipation interface is identified. The region with heat flux density below the average value is defined as the critical region for thermal blockage. Based on the main heat flow path, key thermal blockage areas, and quantified thermal coupling strength, the calibrated thermal resistance network model is reorganized to construct the module's three-dimensional thermal network model.

6. The heat dissipation structure optimization method for modules according to claim 5, characterized in that, The calibrated thermal resistance network model is reorganized, including: For die pairs with thermal coupling strength higher than the first preset threshold, the corresponding die pairs are aggregated into nodes in the three-dimensional thermal network and managed as a single coupled heat source. For die pairs with thermal coupling strength lower than the second preset threshold, high-precision distributed thermal resistance is retained on the connection path of the die pair. Regions with high thermal coupling strength and high heat flux density are marked as priority allocation zones for heat dissipation resources.

7. The heat dissipation structure optimization method for modules according to claim 1, characterized in that, Based on the heat dissipation requirements of each die and their spatial distribution, an active heat dissipation mechanism is searched and optimized. A spatial mapping relationship is established between the thermoelectric cooling array, the microfluidic network, and the die to obtain heat dissipation structure parameters, including: Establish optimized deployment rules for the aforementioned thermoelectric cooling array and microfluidic network; By matching the heat dissipation requirement level, spatial distribution characteristics and the optimization deployment rules, the mapping relationship that maximizes the matching optimization target is identified, and the spatial mapping relationship between the thermoelectric cooling array, microfluidic network and bare die is obtained. Based on the spatial mapping relationship with the die, the control parameter relationship between the thermoelectric cooling array, the microchannel network and the die is generated, and the heat dissipation structure parameters are obtained. The optimized deployment rule for the thermoelectric cooling array is as follows: the driving circuit of each thermoelectric cooling unit adopts an independent H-bridge topology. The layout and routing of the H-bridge driving circuit are optimized according to the position and power requirements of the thermoelectric cooling unit. Each H-bridge driving circuit is configured with independent current and temperature monitoring functions. The optimized deployment rule of the microfluidic network is as follows: a piezoelectric microvalve array is integrated within the microfluidic channel, and each microvalve is driven by an independent H-bridge circuit; the opening of the microvalve is dynamically adjusted according to the real-time heat load to distribute the coolant as needed.

8. The method for optimizing the heat dissipation structure of a module according to claim 1, characterized in that, Implement heat dissipation deployment and control for chip modules, including: A temperature sensor network is integrated into the optimized heat dissipation structure and configured on multiple bare dies of the chip module to collect temperature field data of the chip module in real time. The real-time temperature field data is compared with the target temperature conditions. Based on the comparison results, the target hot spot area for enhanced heat dissipation is identified, and a corresponding set of control instructions is generated in combination with the heat dissipation structure parameters. According to the control instruction set, thermoelectric cooling and fluid guidance are executed synchronously. The thermoelectric cooling and fluid guidance are executed independently. The thermoelectric cooling is to drive the micro thermoelectric cooler unit in the thermoelectric cooling array corresponding to the target hot spot area to perform active cooling. The fluid guidance is to adjust the opening of the micro valve in the embedded microchannel network corresponding to the target hot spot area to increase the flow rate of coolant to the target hot spot area.

9. A heat dissipation structure optimization system for modules, characterized in that, The step of implementing the module-oriented heat dissipation structure optimization method according to any one of claims 1 to 8, wherein the module-oriented heat dissipation structure optimization system comprises: The packaging analysis module is used to analyze the chip module packaging structure and construct a three-dimensional thermal network model of the module based on the analysis of the structure, spatial distribution and physical interaction of the bare die. The demand decomposition module is used to decompose the heat dissipation and cooling requirements of each bare chip based on the module's workload scenario and the module's three-dimensional thermal network model, and to obtain the heat dissipation requirement level of each bare chip. The heat dissipation optimization module is used to search and optimize the active heat dissipation mechanism based on the heat dissipation requirements of each die and the spatial distribution, establish the spatial mapping relationship between the thermoelectric cooling array, the microfluidic network and the die, and obtain the heat dissipation structure parameters for chip module heat dissipation deployment and heat dissipation control.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed, implements the steps of the module-oriented heat dissipation structure optimization method according to any one of claims 1 to 8.

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