High-speed anti-radiation SerDes circuit and method for large-scale physical experiment device

Abstract

The invention relates to the technical field of microelectronic chips, and discloses a high-speed anti-radiation SerDes circuit and method for a large-scale physical experiment device, and the circuit comprises a PMA layer and a PCS layer. The PMA layer and the PCS layer work cooperatively, the PMA layer is used for processing signals related to physical media, the PCS layer is used for encoding and decoding data and connecting with an interface of the data link layer, and the PMA layer and the PCS layer carry out data interaction to jointly realize transmission of high-speed serial data; the PMA layer comprises a PLL, a transmitter and a receiver; the PLL is a key module in the PMA layer, provides a clock signal for the whole circuit, and carries out anti-radiation reinforcement on the PLL; the receiver is used for receiving the serial differential signal Rx and outputting a parallel signal to the PCS layer after processing the serial differential signal Rx; the transmitter is used for receiving the parallel signals transmitted by the PCS layer. According to the invention, radiation resistance and data transmission speed can be both considered.

Description

Technical Field

[0001] This invention relates to the field of microelectronic chip technology, and in particular to a high-speed radiation-hardened SerDes circuit and method for use in large-scale physical experimental setups. Background Technology

[0002] With the development of information technology, data transmission rates also need to be significantly improved, leading to the widespread application of SerDes, which enables high-speed data transmission. In addition to its applications in conventional fields, the radiation background in applications such as aerospace and particle physics experiments places even higher demands on the radiation resistance of SerDes.

[0003] In particle physics experiments, experimental results, after being acquired by the front-end detector system, need to be transmitted to the back-end system for data processing. Therefore, the data transmission system is a crucial component of large-scale physics experimental facilities. As the amount of data output from the front-end detector increases, higher-speed radiation-hardened SerDes are required. However, radiation hardening design and speed are contradictory, necessitating the selection of a suitable compromise. Therefore, how to balance the radiation hardening capability of SerDes with data transmission speed has become a pressing technical problem that needs to be solved. Summary of the Invention

[0004] To address the aforementioned problems, the purpose of this invention is to provide a high-speed radiation-resistant SerDes circuit and method for large-scale physical experimental devices, which can balance radiation resistance and data transmission speed.

[0005] To achieve the above objectives, in a first aspect, the technical solution adopted by the present invention is as follows: a high-speed radiation-hardened SerDes circuit for large-scale physical experimental devices, comprising: a PMA layer and a PCS layer; the PMA layer and the PCS layer work together, the PMA layer is used for signal processing related to the physical medium, and the PCS layer is used for data encoding, decoding, and interface with the data link layer, and the two interact to jointly realize high-speed serial data transmission; the PMA layer includes a PLL, a transmitter, and a receiver; the PLL is a key module in the PMA layer, providing a clock signal for the entire circuit and performing radiation hardening on the PLL; the receiver is used to receive the serial differential signal Rx, process it, and output a parallel signal to the PCS layer; the transmitter is used to receive the parallel signal transmitted from the PCS layer.

[0006] Furthermore, the transmitter includes a serializer, an FFE, and an output terminal; The Serializer converts the parallel data transmitted from the PCS layer into serial data and then transmits it to the FFE. The FFE pre-emphasizes the serial data, and the output terminal performs output driving, impedance matching, and bandwidth expansion.

[0007] Furthermore, the receiver includes a deserializer, CDR, CTLE, DFE, and an input terminal; The input terminal receives the serial differential signal, performs impedance matching and bandwidth expansion, and then transmits it sequentially to CTLE and DFE. CTLE and DFE equalize the received serial data, and CDR recovers the clock from the received serial data to DFE. At the same time, DFE makes a decision on the data. Deserializer converts the serial data output by DFE into parallel data and transmits it to the PCS layer.

[0008] Furthermore, the CDR is a key module for clock recovery in the receiver and adopts a radiation-resistant structure.

[0009] Furthermore, the transmitter and receiver employ full-swing CMOS levels.

[0010] Furthermore, the PCS layer includes an FEC encoder, a scrambler, an FEC decoder, a descrambler, a PRBS generator, a PRBS detector, and a FIFO; Parallel data transmitted from the PMA layer is synchronized by an asynchronous FIFO and then sequentially transmitted to the FEC decoder and descrambler to decode and descramble the encoded and scrambled data, respectively; at the same time, the PRBS detector checks whether the data is PRBS code. Parallel data is input into an asynchronous FIFO and then output to a scrambler. The scrambler performs DC balanced encoding on the data and transmits the data to the FEC encoder for error control encoding to obtain parallel data. At the same time, the PRBS generator generates parallel PRBS codes for testing. The FEC encoder and PRBS generator output parallel data to the Serializer in the PMA layer after passing through a two-to-one multiplexing circuit.

[0011] Furthermore, the PCS layer adopts a triple-redundant structure.

[0012] Secondly, the technical solution adopted by the present invention is: a method of using a high-speed radiation-resistant SerDes circuit for a large-scale physical experimental device, which is based on the above-mentioned high-speed radiation-resistant SerDes circuit for a large-scale physical experimental device, and includes two modes: working mode and test mode.

[0013] Furthermore, when sending and receiving data in working mode, this includes: Data transmission: X bits of parallel data are input into an asynchronous FIFO, synchronized, and then transmitted to a scrambler to scramble the X bits of parallel data, resulting in Y bits of parallel data. The FEC encoder performs error control encoding on the scrambled Y bits of parallel data, resulting in Z bits of parallel data. The Z bits of parallel signal output from the FEC encoder are selected by a 2-to-1 multiplexer circuit and sent to the PMA layer, where they are converted into a 1-bit differential serial signal by the serializer. The FFE pre-emphasizes the serial signal and finally outputs Tx through the output terminal. Data reception: A 1-bit serial differential signal Rx arrives at the CTLE through the receiving terminal and is equalized by the CTLE; the equalized data from the CTLE is handed over to the CDR to recover the clock; the DFE further equalizes the output data from the CTLE and completes the decision process based on the clock recovered by the CDR; the data output from the DFE is converted into a Z-bit parallel signal by the Deserializer; the Z-bit parallel signal is synchronized by the asynchronous FIFO and transmitted to the FEC decoder to obtain Y-bit parallel data; the descrambler then descrambles the Y-bit parallel data to obtain X-bit parallel data, which is finally output.

[0014] Furthermore, when sending and receiving data in test mode, the following are included: Sending test: The PRBS generator generates a Z-bit parallel signal; the Z-bit parallel signal output by the PRBS generator is selected by a 2-to-1 selector circuit and sent to the PMA layer, and then converted into a 1-bit differential serial signal by the serializer; the FFE pre-emphasizes the serial signal and finally outputs it through the output terminal; Receiver test: The 1-bit serial differential signal Rx reaches the CTLE through the receiving terminal and is equalized by the CTLE; the equalized data of the CTLE is handed over to the CDR and the clock is recovered; the DFE further equalizes the output data of the CTLE and completes the decision process according to the clock recovered by the CDR; the data output by the DFE is converted into a Z-bit parallel signal by the Deserializer; the Z-bit parallel signal is synchronized by the asynchronous FIFO and transmitted to the PRBS detector to check whether the data is correct.

[0015] The present invention has the following advantages due to the adoption of the above technical solutions: 1. This invention employs radiation hardening only on key modules within the PMA layer, which can improve radiation resistance while ensuring the circuit's operating speed.

[0016] 2. By adding FEC encoding and decoding to the PCS layer, the FEC decoder in the receiver can detect and correct data errors when they occur, thereby further reducing the system error rate.

[0017] 3. By adopting a triple-modular redundancy structure in the PCS layer, this invention can enhance the radiation resistance of the PCS layer, ensure the correctness of scrambling / decoding and FEC encoding / decoding, and thus balance the radiation resistance of SerDes and the data transmission speed. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the high-speed radiation-resistant SerDes circuit structure used in a large-scale physical experiment device in an embodiment of the present invention. Detailed Implementation

[0019] Since radiation hardening of circuits increases the load and affects circuit speed, a trade-off must be struck between radiation hardening and speed. Therefore, this invention provides a high-speed radiation-hardened SerDes circuit and method for large-scale physics experimental setups. It includes a PMA layer and a PCS layer. The PMA layer contains a PLL, a transmitter, and a receiver. The PCS layer contains an FEC encoder / decoder, a scrambling / decoder, a PRBS generator / verifier, and a FIFO. The transmitter in the PMA layer includes a serializer, an FFE, and an output terminal, while the receiver includes a deserializer, a CDR, a CTLE, a DFE, and an input terminal. This invention hardens only the critical modules in the PMA layer and adds an FEC encoder / decoder to the PCS layer, reducing the system error rate while balancing radiation hardening and data transmission speed.

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention are within the scope of protection of the present invention.

[0021] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0022] In one embodiment of the present invention, a high-speed radiation-hardened SerDes circuit for large-scale physical experimental setups is provided. In this embodiment, as shown... Figure 1As shown, the circuit includes a PMA layer and a PCS layer. The PMA layer and PCS layer work together. The PMA layer is used for physical medium-related signal processing, while the PCS layer is used for data encoding, decoding, and interfacing with the data link layer. They interact to achieve high-speed serial data transmission. Specifically: The PMA layer includes a PLL (phase-locked loop), a transmitter, and a receiver; The PLL is a key module in the PMA layer, providing clock signals for the entire circuit and hardening the PLL to improve the radiation resistance of the PMA layer. The receiver is used to receive the serial differential signal Rx, process it, and output a parallel signal to the PCS layer. The transmitter is used to receive parallel signals transmitted from the PCS layer.

[0023] In the above embodiments, the transmitter in the PMA layer includes a serializer, a feedforward equalizer (FFE), and an output terminal. The serializer converts the parallel data transmitted from the PCS layer into serial data and then transmits it to the FFE. The FFE pre-emphasizes the serial data (to compensate for the frequency response characteristics of the channel, thereby extending the transmission distance and increasing the data transmission rate). The output terminal performs output driving, impedance matching, and bandwidth expansion.

[0024] The receiver includes a deserializer, a clock and data recovery module (CDR), a continuous-time linear equalizer (CTLE), a decision feedback equalizer (DFE), and an input terminal. The input terminal performs impedance matching and bandwidth expansion on the received serial differential signal Rx, then transmits it sequentially to the CTLE and DFE. The CTLE and DFE equalize the received serial data, and the CDR recovers the clock from the received serial data to the DFE. Simultaneously, the DFE makes a decision on the data. The deserializer converts the serial data output from the DFE into parallel data and transmits it to the PCS layer.

[0025] In the above embodiments, the PCS layer includes an FEC (Forward Error Correction) encoder, a scrambler, an FEC decoder, a descrambler, a PRBS generator, a PRBS detector, and a FIFO.

[0026] Parallel data transmitted from the PMA layer is synchronized by an asynchronous FIFO and then sequentially transmitted to the FEC decoder and descrambler to decode and descramble the encoded and scrambled data, respectively; at the same time, the PRBS detector checks whether the data is PRBS code. Parallel data is input to an asynchronous FIFO and then output to a scrambler. The scrambler performs DC-balanced encoding on the data to ensure DC balance during data transmission and transmits the data to an FEC encoder for error control encoding to obtain parallel data. At the same time, a PRBS generator generates parallel PRBS codes for testing. The FEC encoder and PRBS generator output parallel data to the Serializer in the PMA layer after passing through a two-to-one multiplexing circuit.

[0027] In this embodiment, the system error rate can be further reduced by using an FEC encoder and an FEC decoder.

[0028] In the above embodiments, the CDR is a key module for clock recovery in the receiver and adopts a radiation-hardened structure. Other modules in the transmitter and receiver do not adopt a radiation-hardened structure in order to improve circuit operating speed.

[0029] In the above embodiments, the transmitter and receiver employ full-swing CMOS levels to improve radiation resistance.

[0030] In the above embodiments, the PCS layer adopts a triple-redundant structure to further enhance the radiation resistance of the PCS layer.

[0031] In one embodiment of the present invention, a method for using a high-speed radiation-hardened SerDes circuit for a large-scale physics experimental apparatus is provided. This method is implemented based on the circuit structure described in the above embodiments. In this embodiment, the method includes a working mode and a test mode, with different methods for sending data and receiving data in each mode, such as... Figure 1 As shown. Specifically: (1) When sending and receiving data in working mode, the following steps are included: (1.1) Data transmission: X-bit parallel data is input into an asynchronous FIFO, and after synchronization, it is transmitted to a scrambler; the scrambler scrambles the X-bit parallel data to obtain Y-bit parallel data; the FEC encoder performs error control encoding on the scrambled Y-bit parallel data to obtain Z-bit parallel data; the Z-bit parallel signal output by the FEC encoder is selected by a 2-to-1 selector circuit and sent to the PMA layer, and is converted into a 1-bit differential serial signal by the serializer; the FFE pre-emphasizes the serial signal and finally outputs Tx through the output terminal.

[0032] (1.2) Data reception: The 1-bit serial differential signal Rx reaches CTLE through the receiving terminal and is equalized by CTLE; the equalized data of CTLE is handed over to CDR and the clock is recovered; DFE further equalizes the output data of CTLE and completes the decision process according to the clock recovered by CDR; the data output by DFE is converted into Z-bit parallel signal by Deserializer; the Z-bit parallel signal is synchronized by asynchronous FIFO and transmitted to FEC decoder to obtain Y-bit parallel data; the descrambler then descrambles the Y-bit parallel data to obtain X-bit parallel data and finally outputs it.

[0033] (2) When sending and receiving data in test mode, the following steps are included: (2.1) Sending test: The PRBS generator generates a Z-bit parallel signal; the Z-bit parallel signal output by the PRBS generator is selected by a two-to-one selector circuit and sent to the PMA layer, and is converted into a 1-bit differential serial signal by the serializer; the FFE pre-emphasizes the serial signal and finally outputs it through the output terminal.

[0034] (2.2) Receiver test: The 1-bit serial differential signal Rx reaches CTLE through the receiving terminal and is equalized by CTLE; the equalized data of CTLE is handed over to CDR and the clock is recovered; DFE further equalizes the output data of CTLE and completes the decision process according to the clock recovered by CDR; the data output by DFE is converted into Z-bit parallel signal by Deserializer; the Z-bit parallel signal is synchronized by asynchronous FIFO and transmitted to PRBS detector to detect whether the data is correct.

[0035] In summary, the high-speed radiation-hardened SerDes circuit of the present invention can improve radiation resistance while ensuring circuit operating speed by hardening key modules in the PMA layer only. In addition, by adding FEC encoding and decoding in the PCS layer, the system bit error rate can be further reduced, thereby balancing radiation resistance and data transmission speed.

[0036] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high-speed radiation-hardened SerDes circuit for large-scale physical experimental setups, characterized in that, include: PMA layer and PCS layer; The PMA layer and the PCS layer work together. The PMA layer is used for signal processing related to the physical medium, while the PCS layer is used for data encoding, decoding and interface with the data link layer. The two interact with each other to jointly achieve high-speed serial data transmission. The PMA layer includes a PLL, a transmitter, and a receiver; The PLL is a key module in the PMA layer, providing clock signals for the entire circuit and hardening the PLL against radiation. The receiver is used to receive the serial differential signal Rx, process it, and output a parallel signal to the PCS layer. The transmitter is used to receive parallel signals transmitted from the PCS layer.

2. The high-speed radiation-hardened SerDes circuit for large-scale physical experimental devices as described in claim 1, characterized in that, The transmitter includes a serializer, an FFE, and an output terminal; The Serializer converts the parallel data transmitted from the PCS layer into serial data and then transmits it to the FFE. The FFE pre-emphasizes the serial data, and the output terminal performs output driving, impedance matching, and bandwidth expansion.

3. The high-speed radiation-hardened SerDes circuit for large-scale physical experimental devices as described in claim 2, characterized in that, The receiver includes a deserializer, CDR, CTLE, DFE, and input terminal; The input terminal receives the serial differential signal, performs impedance matching and bandwidth expansion, and then transmits it sequentially to CTLE and DFE. CTLE and DFE equalize the received serial data, and CDR recovers the clock from the received serial data to DFE. At the same time, DFE makes a decision on the data. Deserializer converts the serial data output by DFE into parallel data and transmits it to the PCS layer.

4. The high-speed radiation-hardened SerDes circuit for large-scale physical experimental devices as described in claim 3, characterized in that, The CDR is a key module for clock recovery in the receiver and employs a radiation-resistant structure.

5. The high-speed radiation-hardened SerDes circuit for large-scale physics experimental apparatus as described in claim 3, characterized in that, The transmitter and receiver use full-swing CMOS levels.

6. The high-speed radiation-hardened SerDes circuit for large-scale physics experimental apparatus as described in claim 1, characterized in that, The PCS layer includes an FEC encoder, scrambler, FEC decoder, descrambler, PRBS generator, PRBS detector, and FIFO; Parallel data transmitted from the PMA layer is synchronized by an asynchronous FIFO and then sequentially transmitted to the FEC decoder and descrambler to decode and descramble the encoded and scrambled data, respectively; at the same time, the PRBS detector checks whether the data is PRBS code. Parallel data is input into an asynchronous FIFO and then output to a scrambler. The scrambler performs DC balanced encoding on the data and transmits the data to the FEC encoder for error control encoding to obtain parallel data. At the same time, the PRBS generator generates parallel PRBS codes for testing. The FEC encoder and PRBS generator output parallel data to the Serializer in the PMA layer after passing through a two-to-one multiplexing circuit.

7. The high-speed radiation-hardened SerDes circuit for large-scale physics experimental apparatus as described in claim 6, characterized in that, The PCS layer adopts a triple-redundant structure.

8. A method of using a high-speed radiation-hardened SerDes circuit for a large-scale physics experimental setup, implemented based on the high-speed radiation-hardened SerDes circuit for a large-scale physics experimental setup as described in any one of claims 1-7, characterized in that, It includes two modes: working mode and testing mode.

9. The method of using the high-speed radiation-hardened SerDes circuit for large-scale physical experimental devices as described in claim 8, characterized in that, When sending and receiving data in working mode, the following applies: Data transmission: X bits of parallel data are input into an asynchronous FIFO, synchronized, and then transmitted to a scrambler to scramble the X bits of parallel data, resulting in Y bits of parallel data. The FEC encoder performs error control encoding on the scrambled Y bits of parallel data, resulting in Z bits of parallel data. The Z bits of parallel signal output from the FEC encoder are selected by a 2-to-1 multiplexer circuit and sent to the PMA layer, where they are converted into a 1-bit differential serial signal by the serializer. The FFE pre-emphasizes the serial signal and finally outputs Tx through the output terminal. Data reception: A 1-bit serial differential signal Rx arrives at the CTLE through the receiving terminal and is equalized by the CTLE; the equalized data from the CTLE is handed over to the CDR to recover the clock; the DFE further equalizes the output data from the CTLE and completes the decision process based on the clock recovered by the CDR; the data output from the DFE is converted into a Z-bit parallel signal by the Deserializer; the Z-bit parallel signal is synchronized by the asynchronous FIFO and transmitted to the FEC decoder to obtain Y-bit parallel data; the descrambler then descrambles the Y-bit parallel data to obtain X-bit parallel data, which is finally output.

10. The method of using the high-speed radiation-hardened SerDes circuit for large-scale physical experimental apparatus as described in claim 8, characterized in that, When sending and receiving data in test mode, the following applies: Sending test: The PRBS generator generates a Z-bit parallel signal; the Z-bit parallel signal output by the PRBS generator is selected by a 2-to-1 selector circuit and sent to the PMA layer, and then converted into a 1-bit differential serial signal by the serializer; the FFE pre-emphasizes the serial signal and finally outputs it through the output terminal; Receiver test: The 1-bit serial differential signal Rx reaches the CTLE through the receiving terminal and is equalized by the CTLE; the equalized data of the CTLE is handed over to the CDR and the clock is recovered; the DFE further equalizes the output data of the CTLE and completes the decision process according to the clock recovered by the CDR; the data output by the DFE is converted into a Z-bit parallel signal by the Deserializer; the Z-bit parallel signal is synchronized by the asynchronous FIFO and transmitted to the PRBS detector to check whether the data is correct.

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