Varactor driving system of phased-array antenna

Abstract

The invention discloses a varactor driving system of a phased-array antenna, which relates to the field of phased-array antennas and comprises an upper computer, a driving control panel and a varactor phased-array antenna. The upper computer is in communication connection with the driving control panel, and the driving control panel is in signal connection with the varactor phased-array antenna; the driving control board receives a control instruction of an upper computer, generates a corresponding SPI protocol control signal through the FPGA, controls the DAC to output a plurality of analog signals through the SPI protocol control signal, controls the varactors of the corresponding units of the varactor phased-array antenna through the analog signals, and carries out phased-array antenna phase control. Through multi-dimensional optimization of precision, synchronism, expansibility and response speed, an efficient and reliable varactor driving solution is provided for the RIS phased-array antenna, and the phase control precision, environment adaptation capability and engineering practicability of the phased-array antenna are remarkably improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of phased array antennas, and more particularly to a variable capacitance tube driving system of a phased array antenna. BACKGROUND

[0002] RIS phased array technology is an emerging antenna technology. In order to save the equipment, energy consumption and deployment cost of communication base stations, the global communication industry has begun to research RIS technology. RIS is a brand-new revolutionary technology for future mobile communication systems, which is usually a large-scale array surface composed of reconfigurable units, can intelligently reconfigure wireless transmission environment, and significantly improves the performance of mobile communication networks.

[0003] The adjustable phase element of the RIS phased array antenna is divided into many types, such as variable capacitance diode, PIN diode, MEMS switch, etc. By changing the state (such as capacitance value) of the element, the phase of the reflected electromagnetic wave can be changed in real time and programmably. However, the variable capacitance tube phased array realizes phase adjustment by changing the voltage at both ends, which puts forward higher requirements for voltage control range and control precision. The traditional driving scheme is difficult to balance the wide voltage range and high precision control. Moreover, the RIS phased array is usually a large-scale array composed of units (up to several hundred to thousands of units), which needs to realize the synchronization of multi-channel voltage output to avoid phase adjustment deviation caused by driving delay. The traditional driving method is difficult to meet the synchronization control requirements of large-scale array.

[0004] Therefore, how to provide a variable capacitance tube driving system of a phased array antenna that meets the voltage control precision and large-scale array synchronization control is a problem that needs to be solved by those skilled in the art. SUMMARY

[0005] Therefore, the present application provides a variable capacitance tube driving system of a phased array antenna to solve the above problems.

[0006] In order to achieve the above purpose, the present application adopts the following technical scheme: The present application discloses a variable capacitance tube driving system of a phased array antenna, comprising: an upper computer, a driving control board and a variable capacitance tube phased array antenna; the upper computer is in communication connection with the driving control board, and the driving control board is in signal connection with the variable capacitance tube phased array antenna. The driving control board receives the control instruction of the upper computer, generates a corresponding SPI protocol control signal through FPGA, controls the DAC to output a plurality of analog signals by using the SPI protocol control signal, controls the variable capacitance tube of the corresponding unit of the variable capacitance tube phased array antenna by the analog signals, and performs phased array antenna phase control.

[0007] Further, the SPI protocol control signal is generated through a GPIO port of the FPGA, and the SPI protocol control signal is one or more.

[0008] Further, the SPI protocol control signal includes a data signal, a synchronous clock signal and a chip selection signal, and occupies three GPIO ports of the FPGA.

[0009] Further, the DAC is provided with DIN, CLK and CS pins for receiving the data signal, the synchronous clock signal and the chip selection signal, respectively. The DAC is provided with 8 OUT pins corresponding to 8 analog signal output voltages. The DAC is provided with two groups of REFH and REFL pins, REFH is the positive electrode of the sampling voltage, REFL is the negative electrode of the sampling voltage, and the range of the sampling voltage is REFH minus REFL, each group of REFH and REFL pins corresponds to 4 analog signals. The DAC is provided with GND and VSS pins, which are both used as the negative electrode of the DAC chip. The DAC is provided with a VDD pin, which is used as the positive electrode of the DAC chip.

[0010] Further, the power supply voltage of the DAC is 15V, the reference voltage VREF input to the REFH pin is 12V, the REFL pin is grounded and the voltage is 0V, and the voltage control accuracy of the DAC is 12 / 256=0.046V.

[0011] Further, in each control cycle of the SPI protocol control signal, the chip selection control binary data string of the 8 analog signals is sequentially sent, and then the 8-bit binary voltage data string of each analog signal with the chip selection signal being 1 is sequentially sent in order.

[0012] According to the above technical solution, compared with the prior art, the present application provides a varactor driving system for a phased array antenna, which has the following technical effects: (1) The present application optimizes the power supply and reference voltage configuration of the DAC chip, so that the varactor driving voltage covers the engineering requirement range of 0V~12V; at the same time, relying on the 8-bit resolution design of the DAC chip, the voltage control accuracy of 12V / 256=0.046V is realized, which not only meets the basic accuracy requirement of 0.1V, but also provides 256-level subdivision gears for phase adjustment, which is much higher than the accuracy level of traditional diode high-low level control, realizing the coordinated control of wide voltage range and ultra-high accuracy.

[0013] (2) The application adopts FPGA as a core control unit, generates multiple independent and synchronous SPI protocol control signals by using the GPIO port resources thereof, all SPI control signals share the same clock system, ensures that the analog signal outputs of multiple DAC chips have no time difference, completely adapts to large-scale RIS phased array antennas of hundreds to thousands of units, meets the synchronous driving requirements of large-scale arrays, and guarantees the beamforming precision of array antennas.

[0014] (3) The application is based on the modular design of FPGA and DAC, each DAC chip can provide 8 independent analog signal outputs, the number of DAC chips can be flexibly increased or decreased to match the phased array antenna requirements of different scales through the expansion capability of the FPGA GPIO port, has super strong expansion flexibility and adaptability, and significantly improves the universality and scene adaptation capability of the system.

[0015] (4) The FPGA has high-speed parallel processing characteristics, the transmission delay of the SPI protocol control signals generated thereby is low, the control instructions of the upper computer can be quickly responded, the real-time adjustment of the varactor voltage is realized, the phased array antenna can quickly adapt to the dynamic changes of the wireless transmission environment, and the driving response speed and real-time control performance are improved.

[0016] In summary, the application provides an efficient and reliable varactor driving solution for RIS phased array antennas through multi-dimensional optimization of precision, synchronism, expansibility and response speed, significantly improves the phase control precision, environmental adaptation capability and engineering practicability of the phased array antenna, and lays a core hardware foundation for the large-scale application of RIS technology in future mobile communication systems. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the application, and those skilled in the art can obtain other drawings according to the provided drawings without creative labor.

[0018] Figure 1 The overall structure schematic diagram provided by the application.

[0019] Figure 2 The DAC driving principle schematic diagram provided by the application.

[0020] Figure 3 The schematic diagram of four DACs in parallel provided by the application.

[0021] Figure 4 The SPI timing diagram and OUT1-OUT8 configuration definition schematic diagram provided by the application. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present application.

[0023] The embodiments of the present application disclose a varactor driving system of a phased array antenna, as shown in the figure, comprising: a host computer, a driving control board and a varactor phased array antenna; the host computer is in communication connection with the driving control board, and the driving control board is in signal connection with the varactor phased array antenna. Figure 1 The driving control board receives the control instruction of the host computer, generates a corresponding SPI protocol control signal through FPGA, controls the DAC to output a plurality of analog signals by using the SPI protocol control signal, controls the varactor of the corresponding unit of the varactor phased array antenna by the analog signals, and performs phased array antenna phase control. The driving control board receives the control instruction of the host computer, generates a corresponding SPI protocol control signal through FPGA, controls the DAC to output a plurality of analog signals by using the SPI protocol control signal, controls the varactor of the corresponding unit of the varactor phased array antenna by the analog signals, and performs phased array antenna phase control.

[0024] Specifically, the varactor phased array is phase-regulated by changing the voltage between the two ends of the varactor, and the engineering requires that the varactor voltage change is between 0V and 12V, and the voltage precision requirement is 0.1V. Therefore, the present application provides an efficient control method for such driving requirements. Moreover, the number of units of the phased array antenna is numerous, ranging from several hundred to thousands, and the use of FPGA for control is the best choice to realize the rapid response of the RIS phased array. The present application generates N-way SPI interface protocol by using the resource advantage of the FPGA port, and then controls the digital-to-analog conversion chip (DAC) by using the SPI protocol, so as to realize the accurate control of the multiple varactors through the multiple voltage analog signals of the DAC.

[0025] In one specific embodiment, the SPI protocol control signal is generated through the GPIO port of the FPGA, and the SPI protocol control signal is one way or multiple ways.

[0026] In one specific embodiment, the SPI protocol control signal includes a data signal, a synchronous clock signal and a chip selection signal, and occupies 3 GPIO ports of the FPGA.

[0027] In one specific embodiment, the DAC is provided with DIN, CLK and CS pins for receiving data signals, synchronous clock signals and chip selection signals, respectively. The DAC is provided with 8-way OUT pins corresponding to 8-way analog signal output voltages. The DAC is provided with two groups of REFH and REFL pins, REFH is a positive electrode of a sampling voltage, REFL is a negative electrode of the sampling voltage, and the range of the sampling voltage is REFH minus REFL, each group of REFH and REFL pins corresponds to four analog signals respectively; The DAC is provided with GND and VSS pins, which are used as the negative electrode of the DAC chip. The DAC is provided with a VDD pin, which is used as the positive electrode of the DAC chip.

[0028] In a specific embodiment, the power supply voltage of the DAC is 15V, the reference voltage VREF input into the REFH pin is 12V, the REFL pin is grounded and the voltage is 0V, and the voltage control accuracy of the DAC is 12 / 256 = 0.046V.

[0029] Specifically, as shown in the figure, Figure 2 The driving principle of the DAC is as follows: the DIN pin is a data input; the CLK pin is a synchronous clock; the DOUT pin is a chip data output (not used in the application); CS is a chip selection signal working at a low level; SHDN is an enable pin, which only works at a high level; REFH is a positive electrode of a sampling voltage, REFL is a negative electrode of the sampling voltage, and the range of the sampling voltage is REFH minus REFL, which has two groups, each group has four paths, and the separated advantage is that each group can define the voltage range, which is more flexible; GND and VSS are the negative electrodes of the entire system, NC is not used in the application, VDD is a power supply of the chip, OUT0-OUT8 are specific voltage values, and the voltage range is the difference between REFH and REFL. Among them, R5 and R6 resistances are used for impedance matching, two resistances of the 15 pin are used for reserving the enable and disable functions, and the eight resistances of the OUT output are used for making the chip output have an initialized fixed steady state.

[0030] In order to meet the highest 12V DAC output, the power supply of the DAC chip must exceed 12V, so the power supply is selected as 15V (VCC_15V), the VREF reference voltage is 12V, and the REFL is 0V, which ensures that the output range of the DAC chip is between 0-12V, wherein REFH / L has two groups, each group controls four outputs, OUT1-4 is a group, OUT5-8 is a group, and there are eight output paths in total.

[0031] MOSI is the data input end of the DAC chip, and all external control data is input from this pin to provide a data stream for controlling the DAC chip, CLK is a synchronous clock accompanying the data, and CS is a chip selection signal of the DAC chip. The above three signals are typical SPI communication protocols, mainly responsible for configuring various voltage parameters of each path of the chip, and these control signals come from the FPGA.

[0032] Based on the above principle, a group of SPI protocol 3 pins, control 8-way OUT output, suppose we need 256-way output, need 32 groups of SPI protocol, the 32 groups of SPI protocol are completely independent and completely synchronized, 32 groups use the same clock system, so the data sent can be completely synchronized, the time of each chip OUT output can be completely aligned, that is, the output of 32 DAC chips can be completely synchronized, almost no time difference, which is the advantage of the application controlled by FPGA. In addition, the most important core advantage is that the DAC chip with high precision analog chip can output from 0V to 12V with a precision of 0.046V, which makes the driving voltage precision of the varactor very high, from 0V to 12V, there are 256 different voltage values, which is equivalent to 256 levels. If it is 256-way, the combination precision is amazing, which makes the phase precision of the varactor very high, much higher than the precision of the ordinary diode high and low two levels, which is the originality and uniqueness of the current RIS phased array field development of the driving scheme of the varactor diode.

[0033] Based on the control principle of the above DAC, it can be applied to the driving of RIS phased array, as shown in Figure 3 For example, control 32 units, each DAC chip has 8-way output, 32-way needs 4 DAC chips. If you need to control 256-way RIS unit, you need 32 DAC chips, which needs to occupy 96 general-purpose GPIO of FPGA, which is the advantage of the number of IO of FPGA.

[0034] In a specific embodiment, the SPI protocol control signal sends 8-way analog signal chip selection control binary data string in each control cycle, and then sends 8-bit binary voltage data string of each analog signal with chip selection signal 1 in sequence.

[0035] Specifically, as shown in 4, A0~A7 correspond to the address of OUT1~OUT8 each channel, and the following D0~D7 correspond to the specific voltage value of each OUT channel. The voltage precision is 12 / 256=0.046V, which meets the requirement of 0.1V precision. For example, assign a voltage of 5V to OUT6 channel, then A7~A0 except A5 is 1, the rest are 0, keep the last voltage unchanged, D7~D0 value is 5V / 0.046≈109, corresponding to binary is 01101101, so the final data string sent by SPI is A7~A0 is 00100000, 01101101, that is, a group of varactor voltage driving is completed.

[0036] The various embodiments described in this specification are implemented in a progressive manner, each embodiment focusing on the differences from other embodiments, and the same or similar parts between embodiments can be mutually referred to. For the apparatus disclosed by the embodiments, since it corresponds to the method disclosed by the embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method part.

[0037] The above description of disclosed embodiments enables one of ordinary skill in the art to make or use the application. Various modifications to these embodiments will be readily apparent to those of ordinary skill in the art, and the generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Therefore, the application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A varactor tube driving system for a phased array antenna, characterized by, The utility model relates to a kind of variable capacitance tube phased array antenna control system, including: Host computer, drive control board and variable capacitance tube phased array antenna; The host computer is connected with the drive control board, and the drive control board is signal connected with the variable capacitance tube phased array antenna; The drive control board receives the control instruction of the host computer, and generates corresponding SPI protocol control signal by FPGA, controls DAC to output several analog signals using the SPI protocol control signal, controls the variable capacitance tube of the corresponding unit of the variable capacitance tube phased array antenna by each analog signal, and carries out phased array antenna phase control.

2. A varactor tube drive system for a phased array antenna as recited in claim 1, wherein, The SPI protocol control signal is generated through the GPIO port of the FPGA, and the SPI protocol control signal is one or more.

3. A varactor tube drive system for a phased array antenna as defined in claim 2, wherein, The SPI protocol control signal includes data signal, synchronous clock signal and chip selection signal, and occupies 3 GPIO ports of the FPGA.

4. A varactor tube drive system for a phased array antenna according to claim 3, wherein, The DAC is provided with DIN, CLK and CS pins for receiving the data signal, the synchronous clock signal and the chip selection signal respectively. The DAC is provided with 8 OUT pins, respectively corresponding to 8 analog signal output voltages. The DAC is provided with two groups of REFH and REFL pins, and REFH is the positive electrode of sampling voltage, REFL is the negative electrode of sampling voltage, and the range of sampling voltage is REFH minus REFL. Each group of REFH and REFL pins corresponds to 4 analog signals. The DAC is provided with GND and VSS pins, which are used as the negative electrode of the DAC chip. The DAC is provided with VDD pin, which is the positive electrode of the DAC chip.

5. A varactor tube drive system for a phased array antenna as defined in claim 4, wherein, The power supply voltage of the DAC is 15V, the reference voltage VREF input into the REFH pin is 12V, the REFL pin is grounded, and the voltage is 0V. The voltage control accuracy of the DAC is 12 / 256=0.046V.

6. A varactor tube drive system for a phased array antenna as recited in claim 4, wherein, In each control cycle of the SPI protocol control signal, chip selection control binary data string of the 8 analog signals is sent in turn, and then 8-bit binary voltage data string of each analog signal with chip selection signal being 1 is sent in turn.

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