Forced test signal generation circuit of chip

Abstract

The invention relates to the technical field of chip testing, in particular to a forced test signal generation circuit of a chip. The circuit comprises a first target bonding pad, a second target bonding pad, a target pull-up resistor, a third target three-state gate, a fourth target three-state gate, a power-on reset signal, a power-on reset delay signal, a third target inverter and a latch corresponding to an interactive interface, generation of a forced test signal is controlled through a power-on reset signal and a power-on reset delay signal obtained through self delay of the power-on reset signal, other signals are not needed, it is guaranteed that the forced test signal can respond to the generation requirement in time, the power-on reset signal serves as clock input of a latch to sample a signal received by an interaction interface, and the power-on reset signal is used as the clock input of the latch. Therefore, the level of the signal received by the interaction interface needs to be maintained for a certain period of time to be accurately sampled, and the reliability of forced test signal generation is improved.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and in particular to a forced test signal generation circuit for a chip. Background Technology

[0002] In chip testing scenarios, to improve the ease of entering chip sub-test modes and further save chip area and chip design and manufacturing costs, a chip sub-test mode entry system is proposed. This system involves configuring the second and third interfaces of the first communication module to enter the test sub-mode. Both the second and third interfaces are general-purpose interfaces that can input signals into the chip and output signals from the chip. When configuring the first communication module, it is necessary to ensure that both the second and third interfaces are in input state.

[0003] In order to ensure that the second and third interfaces of the chip remain in the input state in the test mode to receive the test sub-mode configuration, and to make the priority of the test sub-mode configuration higher than the priority of the ROM program, a chip's forced test circuit forces the second and third interfaces to be in the input state through a forced test signal.

[0004] However, since the ROM program starts executing after the chip is powered on and reset, the custom ROM program may configure the second and third interfaces as output states. This may result in the tester being unable to enter the test sub-mode after the chip is powered on and reset, requiring the generation of a forced test signal to force the second and third interfaces to be in the input state.

[0005] However, the need to generate a forced test signal may arise shortly after power-on reset. At this time, some circuits in the chip may not be able to work in time. Therefore, how to ensure that the forced test signal can respond to the generation requirement in a timely manner has become an urgent problem to be solved. Summary of the Invention

[0006] To address the aforementioned technical problems, the technical solution adopted by this invention is as follows: A forced test signal generation circuit for a chip, the circuit comprising: a first target pad, a second target pad, a target pull-up resistor, a third target tri-state gate, a fourth target tri-state gate, a power-on reset signal, a power-on reset delay signal, a third target inverter, and a latch corresponding to an interactive interface.

[0007] The first target pad is connected to the target pull-up resistor.

[0008] The first target pad is also bidirectionally connected to the second target pad.

[0009] The second target pad is connected to the output terminal of the third target tri-state gate and the input terminal of the fourth target tri-state gate, respectively.

[0010] The power-on reset delay signal is connected to the enable terminal of the third target tri-state gate through the third target inverter.

[0011] The power-on reset delay signal is also connected to the enable terminal of the fourth target tri-state gate.

[0012] The output of the fourth target tri-state gate is connected to the input of the latch.

[0013] The power-on reset signal is connected to the control terminal of the latch.

[0014] The output of the latch is used to output a forced test signal.

[0015] Compared with the prior art, the present invention has significant advantages. Through the above technical solution, the forced test signal generation circuit for a chip provided by the present invention achieves considerable technical progress and practicality, and has broad industrial application value. It has at least the following advantages: This invention provides a forced test signal generation circuit for a chip. The circuit includes: a first target pad, a second target pad, a target pull-up resistor, a third target tri-state gate, a fourth target tri-state gate, a power-on reset signal, a power-on reset delay signal, a third target inverter, and a latch. The first target pad is connected to the target pull-up resistor and is also bidirectionally connected to the second target pad. The second target pad is connected to the output terminal of the third target tri-state gate and the input terminal of the fourth target tri-state gate, respectively. The power-on reset delay signal is connected to the enable terminal of the third target tri-state gate through the third target inverter and is also connected to the enable terminal of the fourth target tri-state gate. The output terminal of the fourth target tri-state gate is connected to the input terminal of the latch. The power-on reset signal is connected to the control terminal of the latch. The output terminal of the latch is used to output a forced test signal.

[0016] It can be seen that the generation of the forced test signal is controlled by the power-on reset signal and the power-on reset delay signal obtained by its own delay. No other signal is needed, which ensures that the forced test signal can respond to the generation requirements in a timely manner. Moreover, by using the power-on reset signal as the clock input of the latch to sample the signal received by the interaction interface, the level of the signal received by the interaction interface needs to be maintained for a certain period of time in order to be accurately sampled, which improves the reliability of the forced test signal generation. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating a method for entering a chip test mode according to Embodiment 1 of the present invention. Figure 2 This is a schematic diagram of the first circuit structure in a power-on reset monitoring circuit provided in Embodiment 2 of the present invention; Figure 3 This is a schematic diagram of the structure of a chip test sub-mode entry system provided in Embodiment 3 of the present invention; Figure 4 This is a schematic diagram of the circuit structure of a chip reset circuit provided in Embodiment 4 of the present invention; Figure 5 This is a schematic diagram of the circuit structure of a chip scanning circuit provided in Embodiment 5 of the present invention; Figure 6 This is a schematic diagram of the structure of a systematic chip packaging test system provided in Embodiment Six of the present invention; Figure 7 This is a schematic diagram of the connection test circuit of a systematic packaged chip provided in Embodiment 7 of the present invention; Figure 8 This is a schematic diagram of the forced test circuit for the chip provided in Embodiment 8 of the present invention; Figure 9 This is a schematic diagram of the forced test signal generation circuit of the chip provided in Embodiment 9 of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] This embodiment provides a method for entering chip test mode, see [link to documentation]. Figure 1 This is a flowchart illustrating a method for entering a chip test mode according to Embodiment 1 of the present invention. The method includes: S101, monitor the power-on reset signal through the chip's reset pin, and take the time point when the power-on reset signal changes from a preset first level to a preset second level as the first time point; S102, determine the second time point based on the first time point and the preset delay duration; S103, a first time interval is formed by the first time point and the second time point; S104, if the first interface in the chip receives N pulse signals within the first time interval, then the chip enters the test mode, where N is a positive integer.

[0021] Here, the chip can refer to a digital chip or an analog chip. The chip can be packaged or unpackaged. The power-on reset signal output by the power-on reset circuit cannot be directly accessed from the outside. Therefore, the power-on reset signal is monitored through the reset pin packaged outside the casing. Furthermore, when the chip is a chip in a system package, the reset pin can be connected to the output terminal of the power-on reset circuit or to the reset pin of other chips. When the chip is in an independent package, the reset pin can be connected to the output terminal of the power-on reset circuit. For example, the chips in a system package can include digital chips and analog chips. After the chip is packaged, the ports used for interconnection between the digital chip and the analog chip, as well as the ports of the digital chip, are packaged inside the casing and are not visible, making it difficult to test the digital chip. In this embodiment, even when the digital chip ports are not visible, the power-on reset signal can still be monitored to enter the chip test mode.

[0022] In this embodiment, the default initial power-on reset signal is a preset first level, and the time point when the power-on reset signal is withdrawn, that is, the time point when the power-on reset ends, is the time point when the power-on reset signal changes from the preset first level to the preset second level.

[0023] The delay duration can be determined by the actual performance of the power-on reset circuit in the chip after production. The actual performance of the power-on reset circuit depends on both design and manufacturing. Based on the monitoring of the power-on reset signal inside the chip, the first time interval can be dynamically determined. It can be known that even if the delay duration is the same, the first time interval of different chips may be different due to the different times when the power-on reset signal is removed.

[0024] The first interface can be used to receive input information from the tester. When the chip is packaged, the first interface is located outside the package and can be directly accessed. Pulse signals can be generated through the external button corresponding to the first interface, or through a clock signal connected to the first interface, etc., without limitation.

[0025] The first time interval and the number of pulse signals N need to be provided to the tester by the chip designer. In this embodiment, N is set to 32. That is, the tester can only enter the test mode if he inputs 32 pulse signals into the first interface within the first time interval. If the number of pulse signals input within the first time interval is not 32, the test mode cannot be entered.

[0026] Specifically, the chip design can also inform the tester of a fixed first sub-interval and the number of pulse signals. The first sub-interval belongs to the first time interval, without having to inform the tester of the method for determining the first time interval and the delay duration. This makes it impossible for ordinary users to enter the chip's test mode. Testers can enter the chip's test mode with the permission of the chip designer, further improving the security of entering the chip's test mode.

[0027] In one specific implementation, step S102 includes: S1021, Starting from the first time point, count the number of pulses generated by the oscillator to obtain the first pulse count; S1022, when the number of the first pulses is the same as the preset number, the reset extended signal is changed from the preset first level to the preset second level, and the preset number corresponds to the delay duration; S1023, the time point at which the reset extended signal changes from the preset first level to the preset second level is determined as the second time point.

[0028] The delay duration is achieved by a reset extension signal, which is generated by an internal oscillator and a first counter. The first counter is used to count the number of pulses generated by the oscillator. The preset number can be determined by the chip design, and the preset number corresponds to the delay duration.

[0029] Specifically, after the chip is powered on, its various components gradually reach a working state. The power-on reset signal is removed after ensuring the chip powers on normally. To ensure the chip can function properly, a reset extension signal is needed. This signal keeps the chip in a reset state for a period of time after the power-on reset signal is removed, waiting for all components to reach a working state. The duration of this reset state is called the delay duration. The initial level of the reset extension signal is a preset first level.

[0030] However, since the circuitry in the chip is not necessarily operational after power-on, it is not possible to use the chip's circuitry to generate a clock to control the reset extension signal. In this embodiment, an oscillator is used to implement the reset extension signal. The oscillator starts working immediately after the chip is powered on and can output a stable pulse signal after a certain period of time. Therefore, if the chip designer has prior information about the typical power-on waiting time, the delay time can be freely set while ensuring that the delay time is greater than or equal to the typical power-on waiting time. In this case, the time before the oscillator outputs a stable pulse signal can be disregarded, and the reset extension signal can be implemented using the oscillator immediately after the chip is powered on.

[0031] In one specific implementation, the oscillator is an LC oscillator.

[0032] The oscillator can also be an RC oscillator. The implementer can select the type of oscillator according to the actual situation, without any restrictions. The frequency of the oscillator can be lower than the operating frequency of the chip to reduce the number of counts of the first counter corresponding to the delay time. For example, the frequency of the oscillator can be set to 12MHz.

[0033] In one specific implementation, the first interface is a general interface.

[0034] Among them, the general-purpose interface can refer to the general-purpose input / output port (GPIO), which can be configured to input, output, bidirectional or high-impedance states to meet different application requirements. The working modes of the general-purpose interface can include input mode, output mode, multiplexed function mode, analog input mode, etc.

[0035] In one specific implementation, the preset first level is a low level, and the preset second level is a high level.

[0036] The implementer can determine the level information corresponding to the preset first level and the preset second level according to the specific circuit design.

[0037] In one specific implementation, the method further includes: S105, after entering the test mode of the chip, configure the first communication module to enter the test sub-mode, the test sub-mode including at least scan mode and memory self-test.

[0038] The chip includes a first communication module, which can adopt I2C, UART, SPI, or other protocols. The first communication module includes at least two interfaces. The tester configures the first communication module through the two interfaces to enter the test sub-mode. It should be noted that the above protocols usually require at least two interfaces. If the implementer uses a single-interface protocol, the first communication module may contain only one interface. This embodiment aims to minimize the number of interfaces, thereby saving on the number of interfaces on the chip.

[0039] Test sub-modes can also include self-test, scan test, boundary scan test, etc. In a system-packaged scenario, test sub-modes can also include scan tests and memory self-tests for each chip.

[0040] In one specific implementation, the test mode corresponds to the first register, and the method further includes: S106, when the read-only memory program of the chip detects that the first register is a first preset value, it changes the second register to a second preset value to wait for the first communication module to complete the configuration, and the initial value of the second register is a third preset value.

[0041] The first register is used to record whether the chip has entered test mode. When the chip enters test mode, the first register is set to the first preset value; otherwise, it is set to the fourth preset value. When the second register is not set to the third preset value, the chip does not continue to execute the read-only memory program (ROM program). The read-only memory program can refer to the program that is executed first after the chip is powered on.

[0042] Specifically, the first preset value can be set to one, the second preset value can be a non-zero positive integer, and the third and fourth preset values ​​can both be zero.

[0043] This embodiment can effectively avoid the situation where the chip's read-only memory program runs before the test sub-mode due to the first communication module's configuration time being too long, thus causing the interface of the first communication module to be reconfigured, and ensuring the normal operation of the test sub-mode.

[0044] In one specific implementation, the method further includes: S107, write the performance test program into the random access memory; S108, write the performance test program to the address corresponding to the random access memory into the second register; S109, when the read-only memory program of the chip detects that the second register is not the third preset value, it jumps to the address in the random access memory.

[0045] Among them, the performance test program can refer to the program that needs to be executed when the chip performs performance testing. The performance test program usually needs to be tested in the chip's functional mode rather than the test mode, so it cannot enter the performance test through the test mode.

[0046] In this embodiment, the performance test program is written into the random access memory (RAM), and then the address corresponding to the performance test program in the random access memory is written into the second register. When the ROM program is executed, the execution jumps to this address to execute the performance test program.

[0047] In this first embodiment, the first time interval is determined by the power-on reset signal monitored by the chip's reset pin combined with the delay time. The tester enters the chip's test mode by inputting a specified number of pulse signals within the first time interval, without needing to enter the chip's test mode through a test mode interface. Moreover, the first time interval is dynamically determined by the chip's own power-on reset signal. The test mode can only be entered when a specified number of pulse signals are input within the first time interval, which improves the security of the test mode entry process. Furthermore, the chip does not need to provide an interface for entering the test mode, effectively saving chip costs.

[0048] This second embodiment provides a power-on reset monitoring circuit, see [link]. Figure 2 The present invention provides a schematic diagram of the first circuit structure in a power-on reset monitoring circuit according to Embodiment 2. The circuit includes: a power supply, a pull-up resistor, a first inverter, a first tri-state gate, a second tri-state gate, a first pad, and a second pad corresponding to the reset pin. The output terminal of the power-on reset circuit is connected to the input terminal of the first inverter. The output terminal of the first inverter is connected to the first output enable terminal of the first tri-state gate; The input terminal of the first tri-state gate is grounded, the output terminal of the first tri-state gate is connected to the first pad, the first pad is bidirectionally connected to the second pad, and the first pad is also connected to the input terminal of the second tri-state gate; The input enable terminal of the second tri-state gate is connected to a preset second level; The second pad is also connected to the power supply via a pull-up resistor; When the power-on reset signal output by the power-on reset circuit is a preset first level, the first tri-state gate is turned on, and the second pad corresponding to the reset pin is at the preset first level; When the power-on reset signal output by the power-on reset circuit changes from the preset first level to the preset second level, the first tri-state gate closes, and the second pad corresponding to the reset pin gradually changes from the preset first level to the preset second level.

[0049] Specifically, when the power-on reset signal output by the power-on reset circuit is at a preset first level, it indicates that the chip is in a power-on reset state. When the power-on reset signal output by the power-on reset circuit changes from the preset first level to a preset second level, it indicates that the chip's power-on reset signal is removed. When the power-on reset signal output by the power-on reset circuit is at a preset second level, it indicates that the chip is not in a power-on reset state.

[0050] However, since the power-on reset signal is usually inside the chip, it may be sent from one chip in the package to another, or it may be generated by the power-on reset circuit inside the chip. It is difficult to effectively monitor the changes of the power-on reset signal outside the chip. As a result, in the chip test mode entry method provided in Embodiment 1, the first time point is difficult to determine accurately because the power-on reset signal cannot be monitored. This makes it impossible even for the chip designer to accurately determine the first time interval, thus making the chip test mode entry method unreliable.

[0051] Specifically, when the power-on reset signal output by the power-on reset circuit is a preset first level, the first tri-state gate is turned on. Since the input terminal of the first tri-state gate is grounded, the second pad corresponding to the reset pin will remain at the preset first level.

[0052] When the power-on reset signal output by the power-on reset circuit changes from the preset first level to the preset second level, the first tri-state gate closes, and the second pad corresponding to the reset pin gradually changes from the preset first level to the preset second level. It can be seen that the change of the power-on reset signal corresponds to the change of the level of the second pad corresponding to the reset pin.

[0053] In addition, the second pad corresponds to the reset pin, which is reused to monitor the power-on reset signal. This eliminates the need for additional pins for monitoring, effectively saving on chip design and manufacturing costs as well as chip area.

[0054] In one specific implementation, when the power-on reset monitoring circuit is powered on, the second pad corresponding to the reset pin is at a preset second level.

[0055] In order to ensure that the second pad maintains a preset level when the power-on reset signal is not applied to the power-on reset monitoring circuit, in this embodiment, the second pad is connected to the power supply through a pull-up resistor. When the power-on reset monitoring circuit is powered on and before the power-on reset signal is applied to the power-on reset monitoring circuit, the second pad maintains a stable preset second level.

[0056] In one specific implementation, the power-on reset monitoring circuit is deployed in the chip, and the second pad corresponding to the reset pin is deployed outside the chip.

[0057] In one specific implementation, the reset pin is also used for hot reset. When the reset pin is used for hot reset, a preset first level is input to the reset pin, and the preset first level is transmitted to the chip by the output of the second tri-state gate.

[0058] The second pad corresponding to the reset pin is located outside the chip, making it easy to monitor and thus helping chip designers or testers to accurately determine the timing of the power-on reset signal removal.

[0059] In one specific implementation, the preset first level is a low level, and the preset second level is a high level.

[0060] In one specific implementation, the power-on reset monitoring circuit is used to monitor the power-on reset signal by monitoring the reset pin, and to take the time point when the power-on reset signal changes from the preset first level to the preset second level as the first time point; The second time point is determined based on the first time point and the preset delay duration; The first time interval is formed by the first time point and the second time point; If the first interface in the chip receives N pulse signals within the first time interval, the chip enters the test mode, where N is a positive integer.

[0061] In one specific implementation, the first interface is a general interface.

[0062] In one specific implementation, N is set to 32.

[0063] In this second embodiment, the power-on reset monitoring circuit makes the changes in the power-on reset signal correspond to the changes in the level of the reset pin. This allows the monitoring of the power-on reset signal, which cannot be directly monitored inside the chip, by monitoring the changes in the level of the reset pin. This enables the acquisition of a more accurate time point for the chip's power-on reset signal to leave the chip, thereby improving the reliability of the chip's test mode entry.

[0064] This embodiment provides a chip test sub-mode entry system, the system including: a first communication module and its corresponding second and third interfaces, an AND gate and a test selector corresponding to M test sub-modes respectively, where M is a positive integer; The first communication module includes a mode input decoder, a mode register, and a mode decoder; The second interface is used to input the encoded information corresponding to M test sub-modes to the mode input decoder; The mode input decoder is used to write the encoded information corresponding to the M test sub-modes into the mode register; The third interface is used to input sub-mode entry information to the first communication module; The mode decoder sets the signal of the test sub-mode corresponding to the sub-mode entry information to a preset second level according to the sub-mode entry information and the encoding information corresponding to the M test sub-modes in the mode register. For any test sub-mode, the signal of the test sub-mode and the test mode signal are used as the input of the AND gate corresponding to the test sub-mode, and the AND gate corresponding to the test sub-mode is used as the input of the test selector; When both the test sub-mode signal and the test mode signal are at a preset second level, the test selector enters the test sub-mode.

[0065] When the test mode signal is at the preset second level, it indicates that the chip is currently in test mode. At this time, if the signal of any test sub-mode is also at the preset second level, the AND gate corresponding to that test sub-mode will output the preset second level.

[0066] When the test mode signal is not at the preset second level, it means that the chip is not currently in test mode. At this time, even if there is a test sub-mode signal at the preset second level, the AND gate output corresponding to the test sub-mode will still be at the preset first level and cannot enter the test sub-mode.

[0067] In one specific implementation, the encoded information is represented by a K-bit binary code; Accordingly, the mode register includes K sub-registers; Wherein, K satisfies condition 2 K+1 ≥M and K are positive integers and min(K).

[0068] For example, when M=4, it needs to be represented by two-bit binary code, which requires two sub-registers to represent the encoded information. When M=5, it needs to be represented by three-bit binary code, which requires three sub-registers to represent the encoded information.

[0069] In one specific implementation, the encoded information is represented by one-hot encoding; Accordingly, the mode register includes M sub-registers, each sub-register corresponding to the encoding information of a test sub-mode.

[0070] One-hot encoding, also known as one-bit valid encoding, uses M M-bit registers to encode M test sub-modes respectively in this embodiment. Each test sub-mode has a unique corresponding register bit, and only one register bit is valid in a single encoded information.

[0071] In one specific implementation, the first communication module uses the I2C protocol.

[0072] The first communication module can also use I2C protocol, UART protocol, SPI protocol, etc. The implementer needs to ensure that the first communication module includes at least two interfaces as the second interface and the third interface.

[0073] In one specific implementation, the preset second level is a high level.

[0074] In one specific implementation, both the second interface and the third interface are general-purpose interfaces.

[0075] Among them, the general-purpose interface can refer to the general-purpose input / output port (GPIO), which can be configured to input, output, bidirectional or high-impedance states to meet different application requirements. The working modes of the general-purpose interface can include input mode, output mode, multiplexed function mode, analog input mode, etc.

[0076] In one specific implementation, when entering any test sub-mode, both the second interface and the third interface are mapped to the interfaces required by the test sub-mode.

[0077] In this embodiment, the second and third interfaces are reused as the interfaces required for the test sub-mode after entering the test sub-mode, thereby further saving the number of interfaces, saving chip area, and reducing the cost of chip design and manufacturing.

[0078] In one specific implementation, the M test sub-modes include at least a scan mode and a memory self-test.

[0079] The test sub-modes can also include self-test, scan test, boundary scan test, etc. In the case of systematic packaging, the test sub-modes can also include scan test and memory self-test corresponding to each chip.

[0080] See Figure 3 This is a schematic diagram of the structure of an entry system for a chip test sub-mode provided in Embodiment 3 of the present invention. The entry system can be applied to a system-packaged chip scenario. Taking a system-packaged chip scenario that includes a first chip and a second chip as an example, the entry system can be applied to the first chip. In this case, the test sub-mode can include a first chip scanning mode, a first chip memory self-test mode, a second chip test mode, etc.

[0081] In this third embodiment, only two interfaces of the first communication port are needed to configure the mode register and enter the test sub-mode. After entering the test sub-mode, the two interfaces can be released to participate in the test stimulus input, which improves the reusability of the interface, effectively saves chip area, reduces the cost of chip design and manufacturing, and also improves the convenience of entering the chip sub-test mode.

[0082] This fourth embodiment provides a chip reset circuit, see [link to documentation]. Figure 4 This is a schematic diagram of the circuit structure of a chip reset circuit provided in Embodiment 4 of the present invention. The circuit includes: a hot reset signal, a power-on reset signal, a first AND gate, an oscillator, a first communication module, a register corresponding to the test mode, and registers corresponding to M test sub-modes, where M is a positive integer. The power-on reset signal is connected to the oscillator, the register corresponding to the test mode, and the first input terminal of the first AND gate; The thermal reset signal is connected to the second input terminal of the first AND gate; The output of the first AND gate is used to output a global reset signal; The global reset signal is connected to the registers corresponding to the first communication module and the M test sub-modes, respectively.

[0083] The oscillator can be used to count the number of pulses in conjunction with the first counter, thereby determining the delay duration. The delay duration and the first time point when the power-on reset signal changes from a preset first level to a preset second level form a first time interval. Within the first time interval, when the first interface in the chip receives N pulse signals, the chip enters the test mode. In this embodiment, the register corresponding to the test mode may include a first counter, a second counter that counts the number of pulse signals from the first interface, and a first register corresponding to the test mode.

[0084] The registers corresponding to the M test sub-modes may include the mode registers corresponding to the test sub-modes.

[0085] In one specific implementation, when the power-on reset signal is a preset first level, both the oscillator and the register corresponding to the test mode are in a reset state.

[0086] The power-on reset signal being at a preset first level indicates that the power-on reset signal is active, at which point the oscillator and the registers corresponding to the test mode are both in a reset state.

[0087] Specifically, the power-on reset signal is connected to the registers corresponding to the oscillator and the test mode respectively through NOT gates. When the power-on reset signal is at the preset first level, the registers corresponding to the oscillator and the test mode receive the preset second level.

[0088] In one specific implementation, when the power-on reset signal or the thermal reset signal is a preset first level, the global reset signal is the preset first level; When the global reset signal is the preset first level, the registers corresponding to the first communication module and the M test sub-modes are all in a reset state.

[0089] The global reset signal being at a preset first level indicates that the global reset signal is active. The global reset signal is connected to the registers corresponding to the first communication module and the M test sub-modes respectively through NOT gates. When the global reset signal is at the preset first level, the registers corresponding to the first communication module and the M test sub-modes respectively receive a preset second level.

[0090] In one specific implementation, the preset first level is a low level.

[0091] In one specific implementation, when the power-on reset signal is a preset second level, neither the oscillator nor the register corresponding to the test mode is in a reset state.

[0092] The power-on reset signal being a preset second level indicates that the power-on reset signal is not in effect, and at this time, neither the oscillator nor the registers corresponding to the test mode are in a reset state.

[0093] In one specific implementation, when both the power-on reset signal and the thermal reset signal are at a preset second level, the global reset signal is at the preset second level; When the global reset signal is the preset second level, the registers corresponding to the first communication module and the M test sub-modes are not in the reset state.

[0094] The global reset signal being at a preset second level indicates that the global reset signal is not in effect. At this time, the registers corresponding to the first communication module and the M test sub-modes are not in a reset state.

[0095] In one specific implementation, the preset second level is a high level.

[0096] In one specific implementation, the power-on reset signal is output by the power-on reset circuit, and the thermal reset signal corresponds to the reset pin.

[0097] In this embodiment, the chip reset system can be deployed in the chip. Normally, the power-on reset circuit is located inside the chip and the power-on reset signal cannot be directly obtained. The reset pin can be located outside the chip, and the user or tester can directly input the hot reset signal through the reset pin.

[0098] In this fourth embodiment, the circuit design allows the power-on reset signal to act on the registers and oscillator related to the test mode, as well as the registers and the first communication module related to the test sub-mode. This ensures the effectiveness of the power-on reset. The hot reset signal can only act on the registers and the first communication module related to the test sub-mode, without resetting the registers and oscillator related to the test mode. This avoids the hot reset signal affecting the normal operation of the test mode, improves the stability of the chip reset system, and thus improves the stability of entering the chip test mode and the test sub-mode. In addition, the implementer can quickly switch between sub-test modes through hot reset without switching modes through power-on or power-off, avoiding the additional time consumption introduced when switching modes through power-on reset, thereby introducing additional test costs.

[0099] This fifth embodiment provides a chip scanning circuit, see [link / reference] Figure 5 This is a schematic diagram of a chip scanning circuit according to Embodiment 5 of the present invention. The circuit includes: a scanning mode selection signal, and P first scanning units {q1, q2, ..., q...} p , ..., q P S second scan units {r1, r2, ..., r s , ..., r S}, second interface, third interface, fourth interface, fifth interface, first selector and second selector, where q p Let r be the p-th first scan unit, where p is an integer in the range [1, P]. s Let s be the s-th second scan unit, where s is an integer in the range [1, S]. The first selector includes a first enable terminal, a first select input port, a second select input port, and a first select output port. The second selector includes a second enable terminal, a third select input port, a fourth select input port, and a second select output port. The scan mode selection signal is connected to the first enable terminal of the first selector and the second enable terminal of the second selector, respectively. The second interface is connected to the input terminal of the first scanning unit q1; The u-th first scan unit q u The output terminal is connected to the (u+1)th first scan unit q u+1 The input terminals are connected, where u is an integer in the range [1, P-1]; The Pth first scan unit q P The output terminals are respectively connected to the second selection input port of the first selector and the third selection input port of the second selector; The fourth interface is connected to the fourth selection input port of the second selector; The second selection output port of the second selector is connected to the input of the first second scan unit r1; The vth second scan unit q v The output terminal is connected to the (v+1)th second scan unit q v+1 The input terminals are connected, where v is an integer in the range [1, S-1]. The Sth second scan unit r S The output terminals are connected to the fifth interface and the first selection input port of the first selector, respectively. The first selection output port of the first selector is connected to the third interface.

[0100] Once the chip is in test mode, it can be configured to perform the scan mode in the test sub-mode through the second and third interfaces. When the chip enters scan mode, the second interface can be configured to receive scan input signals, and the third interface can be configured to output scan output signals.

[0101] Both the first scanning unit and the second scanning unit are scanning units. Each scanning unit may include a data selector and a trigger. In this embodiment, the data selector may be a two-to-one data selector. The input of the data selector may include a function input and a scan input. The scan input may be connected to the second interface, the previous scanning unit, or the second selection output port of the second selector. The trigger may be a D trigger.

[0102] In one specific implementation, when the scan mode selection signal is at a preset first level, the first path formed by the first selection input port and the first selection output port in the first selector is turned on, and the second path formed by the second selection input port and the first selection output port in the first selector is turned off.

[0103] In one specific implementation, when the scan mode selection signal is the preset first level, the third path formed by the third selection input port and the second selection output port in the second selector is turned on, and the fourth path formed by the fourth selection input port and the second selection output port in the second selector is turned off.

[0104] In one specific implementation, when the scan mode selection signal is the preset first level, a first scan chain is formed by the second interface, all first scan units, all second scan units, and the third interface. The first scan chain is used to execute the full scan mode.

[0105] Here, the preset first level can refer to a low level. When the second path formed by the second selection input port and the first selection output port in the first selector is closed, and the third path formed by the third selection input port and the second selection output port in the second selector is open, the Pth first scan unit q P The output terminal is connected to the input terminal of the first second scan unit r1 through a third path. In this case, the second interface can be used to input the scan input signal of the first scan chain, and the third interface can be used to output the scan output signal of the first scan chain.

[0106] In one specific implementation, when the scan mode selection signal is at a preset second level, the first path formed by the first selection input port and the first selection output port in the first selector is closed, and the second path formed by the second selection input port and the first selection output port in the first selector is open.

[0107] In one specific implementation, when the scan mode selection signal is the preset second level, the third path formed by the third selection input port and the second selection output port in the second selector is closed, and the fourth path formed by the fourth selection input port and the second selection output port in the second selector is open.

[0108] In one specific implementation, when the scan mode selection signal is the preset second level, a second scan chain is formed by the second interface, all first scan units, and the third interface; When the scan mode selection signal is the preset second level, the third scan chain is formed by the fourth interface, all second scan units, and the fifth interface; The second and third scan chains are used to perform a compressed scan mode.

[0109] Here, the preset second level can refer to a high level. When the second path formed by the second selection input port and the first selection output port in the first selector is turned on, the Pth first scan unit q P The output terminal is connected to the third interface through the second path. In this case, the second interface can be used to input the scan input signal of the second scan chain, and the third interface can be used to output the scan output signal of the second scan chain.

[0110] When the fourth path formed by the fourth selection input port and the second selection output port in the second selector is turned on, the second selection output port of the second selector is connected to the input terminal of the first second scan unit r1. In this case, the fourth interface can be used to input the scan input signal of the third scan chain, and the fifth interface can be used to output the scan output signal of the third scan chain.

[0111] In this fifth embodiment, the circuit designed for the scanning mode allows for switching the connection mode of the scanning chain by changing the level of the scanning mode selection signal, thereby adapting to both full scan mode and compressed scan mode, greatly improving the flexibility of scanning tests and enabling it to meet complex testing requirements.

[0112] This sixth embodiment provides a systematic testing system for packaged chips. See [link to documentation]. Figure 6 This is a schematic diagram of a systematic chip packaging test system provided in Embodiment 6 of the present invention. The system includes: a second interface, a third interface, a first chip, a second chip, and a metal layer. The first chip includes a first communication module, a second communication module, a third pad, a fourth pad, a third selector, and a fourth selector. The second chip includes a fifth pad, a sixth pad, and a third communication module. The third pad of the first chip and the fifth pad of the second chip are connected through the metal layer. The fourth pad of the first chip and the sixth pad of the second chip are connected through the metal layer. The second interface transmits a first clock signal to the first communication module, and the third interface transmits a first data signal to the first communication module; The first clock signal and the second clock signal output by the second communication module are connected to the third pad after passing through the third selector. The third pad transmits the selection result of the third selector to the fifth pad through the metal layer. The first data signal and the second data signal output by the second communication module are connected to the fourth pad after passing through the fourth selector. The fourth pad transmits the selection result of the fourth selector to the sixth pad through the metal layer. The second clock signal and the second data signal are used to configure the third communication module to enter the test sub-mode of the second chip. When the system is in the first test state, the selection result of the third selector is the same as the first clock signal, and the selection result of the fourth selector is the same as the first data signal; When the system is in the second test state, the second communication module is controlled by the first communication module, the selection result of the third selector is the same as the second clock signal, and the selection result of the fourth selector is the same as the second data signal.

[0113] The metal layer can refer to the redistribution layer (RDL), the first chip can refer to a chip that includes an interface outside the package, and the second chip can refer to a chip that does not include an interface outside the package. Typically, the second chip is controlled by the first chip. In this embodiment, the first chip can be a digital chip and the second chip can be an analog chip.

[0114] In this embodiment, when the tester needs to test the second chip, the tester enters either the first test state or the second test state.

[0115] Specifically, when the system is in the first test state, the connection line between the second interface and the third selector, or the connection line between the third interface and the fourth selector, may be faulty, which may cause the second chip to fail to enter the test sub-mode normally.

[0116] When the system is in the second test state, the control logic of the first and second communication modules, or the control logic of the second and third communication modules, may also be faulty, which may cause the second chip to fail to enter the test sub-mode normally. Therefore, this embodiment adopts a test state switchable method, which effectively improves the reliability and flexibility of the second chip entering the test sub-mode.

[0117] In one specific embodiment, the first chip and the second chip are located inside the package housing, and the pads corresponding to the second interface and the third interface are located outside the package housing.

[0118] In one specific implementation, the test sub-mode includes at least a scan mode and a memory self-test.

[0119] The test sub-modes may also include self-test, scan test, boundary scan test, etc. In one specific implementation, the third communication module further includes a seventh pad.

[0120] In this embodiment, the test sub-mode of the first chip includes the test mode of the second chip. The seventh pad is connected to the signal corresponding to the test mode of the second chip. The seventh pad serves as the test mode trigger of the second chip. The seventh pad is not packaged outside the chip casing, which can save a lot of cost.

[0121] In one specific implementation, the third communication module includes a mode input decoder, a mode register, and a mode decoder; The selection result of the third selector is used to input the encoded information corresponding to M test sub-modes into the mode input decoder, where M is a positive integer. The mode input decoder is used to write the encoded information corresponding to the M test sub-modes into the mode register; The selection result of the fourth selector is used to input sub-mode entry information into the third communication module; The mode decoder, based on the sub-mode entry information and the encoding information corresponding to the M test sub-modes in the mode register, causes the second chip to enter the test sub-mode corresponding to the sub-mode entry information.

[0122] The coding information corresponding to each of the M test sub-modes is ANDed with the signal corresponding to the seventh pad to determine the test sub-mode that the second chip enters. When the signal corresponding to the seventh pad is at the preset first level, the second chip is in functional mode and cannot enter the test sub-mode. When the signal corresponding to the seventh pad is at the preset second level, the second chip is in test mode and can enter the test sub-mode normally.

[0123] In one specific implementation, the encoded information is represented by a K-bit binary code; Accordingly, the mode register includes K sub-registers; Wherein, K satisfies condition 2 K+1 ≥M and K are positive integers and min(K).

[0124] For example, when M=4, it needs to be represented by two-bit binary code, which requires two sub-registers to represent the encoded information. When M=5, it needs to be represented by three-bit binary code, which requires three sub-registers to represent the encoded information.

[0125] In one specific implementation, the encoded information is represented by one-hot encoding; Accordingly, the mode register includes M sub-registers, each sub-register corresponding to the encoding information of a test sub-mode.

[0126] In this embodiment, M M-bit registers are used to encode M test sub-modes respectively. Each test sub-mode has a unique corresponding register bit, and only one register bit is valid in a single encoded information.

[0127] In this sixth embodiment, only the second and third interfaces of the first chip are needed to control the second chip to enter the test sub-mode, which improves the convenience of chip testing in the system packaging scenario. Moreover, the test system can select the first test state and the second test state to realize different ways of entering the second chip test sub-mode, which effectively avoids the second chip being unable to enter the test sub-mode due to connection failures between chips, and also improves the reliability and flexibility of chip testing in the system packaging scenario.

[0128] This embodiment seven provides a connection test circuit for a systematically packaged chip. See [link to documentation]. Figure 7 This is a schematic diagram of a connection test circuit for a systematically packaged chip provided in Embodiment 7 of the present invention. The circuit includes: a first chip and a second chip, wherein the first chip includes a second interface, a third interface, and A first connection units {b1, b2, ..., b...} a , ..., b A}, the second chip includes A second connection units {c1, c2, …, c a , …, c A},b a is the a-th first connection unit in the first chip, a is an integer within the range of [1, A], c a is the a-th second connection unit in the second chip, and A is an even number; The input end of the second interface is used to receive the connection test sample signal, and the output end of the second interface is connected to b1; For the f-th second connection unit c f , if f is an odd number, then c f is connected to c f+1 , f is an integer within the range of [1, A]; If f is an even number, then c f is connected to b f ; For the e-th first connection unit b e , if e is an odd number, then b e is connected to c e ; If e is an even number and e < A, then b e is connected to b e+1 ; If e = A, then b e is connected to the input end of the third interface, and the output end of the third interface is used to output the connection test true signal, and the connection test true signal is used to be compared with the connection test sample signal to obtain the connection test result of the first chip and the second chip.

[0129] Among them, the second interface is configured as the input of the connection test in the connection test system, and the third interface is configured as the output of the connection test in the connection test system.

[0130] Specifically, when the connection test true signal is consistent with the connection test sample signal, it can indicate that the connection test between the first chip and the second chip passes, and when the connection test true signal is inconsistent with the connection test sample signal, it can indicate that the connection test between the first chip and the second chip fails.

[0131] Since the second chip does not include pins exposed outside the package case, the second chip needs to receive signals sent to it by the first chip. Similarly, the second chip also needs to output signals to the first chip. It can be seen that the number A of the second connection units included in the second chip is an even number. Since the connection between chips is tested in this embodiment, and each second connection unit in the second chip has a first connection unit with a unique connection relationship with it, the number of first connection units in the first chip that have a connection relationship with the second chip is also A.

[0132] It should be noted that in this embodiment, when performing something similar to b... e With c e When describing a connection, it specifically refers to the connection made by b. e To c e Send a signal, not c e To b e Send a signal.

[0133] In one specific implementation, the first connection unit includes a first reference input terminal, a first reference output terminal, a first reference tri-state gate, a first reference enable terminal, and a first connection terminal; The first reference input terminal is connected to the input terminal of the first reference tri-state gate; The first reference enable terminal is connected to the enable terminal of the first reference tri-state gate; The output terminal of the first reference tri-state gate is bidirectionally connected to the first connection terminal; The output terminal of the first reference tri-state gate is also connected to the first reference output terminal.

[0134] In one specific implementation, the second connection unit includes a second reference input terminal, a second reference output terminal, a second reference tri-state gate, a second reference enable terminal, and a second connection terminal; The second reference input terminal is connected to the input terminal of the second reference tri-state gate; The second reference enable terminal is connected to the enable terminal of the second reference tri-state gate; The output terminal of the second reference tri-state gate is bidirectionally connected to the second connection terminal; The output terminal of the second reference tri-state gate is also connected to the second reference output terminal.

[0135] In one specific implementation, for the e-th first connection unit b e If b e With c e If connected, then b e Through its first connecting end and c e Includes a second connection end connection; If b e With b e+1 If connected, then b e Through its included first reference output terminal and b e+1 Includes the first reference input connection; If b e If connected to the input of the third interface, then b e It is connected to the input of the third interface via its first reference output terminal.

[0136] Among them, the first reference tri-state gate can be enabled by a high level, and correspondingly, if b e With b e+1 If connected, then b e The first reference enable pin is low, b e+1 The first reference enable pin is high, if b e With c e If connected, then b e The first reference enable pin is high.

[0137] In one specific implementation, for the f-th second connection unit c f If c f With b f If connected, then c f Through its included second connection end and b f Includes a second connection end connection; If c f With c f+1 If connected, then c f Through its included second reference output terminal and c f+1 Includes a second reference input connection.

[0138] Among them, the second reference tri-state gate can be enabled by a high level, and correspondingly, if c f With b f If connected, then c f The second reference enable pin is high, if c f The second reference enable pin is low, c f+1 The second reference enable pin is high.

[0139] In one specific implementation, the first chip further includes a third connection unit; The output of the second interface is connected to b1, and includes: The output of the second interface is connected to b1 through the third connection unit.

[0140] In one specific implementation, the third connection unit includes a third reference input terminal, a third reference output terminal, a third reference tri-state gate, a third reference enable terminal, and a third connection terminal; The third reference input terminal is connected to the input terminal of the third reference tri-state gate; The third reference enable terminal is connected to the enable terminal of the third reference tri-state gate; The output terminal of the third reference tri-state gate is bidirectionally connected to the third connection terminal; The output terminal of the third reference tri-state gate is also connected to the third reference output terminal; The output of the second interface is connected to the third connection terminal.

[0141] The third reference tri-state gate can be enabled at a high level, and the third reference enable terminal can be enabled at a low level.

[0142] In one specific implementation, the first chip further includes a fourth connection unit; The b e Connected to the input terminal of the third interface, including: The b e The fourth connection unit is connected to the input terminal of the third interface.

[0143] The fourth connection unit includes a fourth reference input terminal, a fourth reference output terminal, a fourth reference tri-state gate, a fourth reference enable terminal, and a fourth connection terminal. The fourth reference input terminal is connected to the input terminal of the fourth reference tri-state gate. e The first reference output terminal is connected to the fourth reference input terminal, the fourth reference enable terminal is connected to the enable terminal of the fourth reference tri-state gate, the output terminal of the fourth reference tri-state gate is bidirectionally connected to the fourth connection terminal, the output terminal of the fourth reference tri-state gate is also connected to the fourth reference output terminal, and the fourth connection terminal is connected to the input terminal of the third interface.

[0144] Among them, the fourth reference tri-state gate can be enabled at a high level, and the fourth reference enable terminal is at a high level.

[0145] In this seventh embodiment, the connection relationship between the first chip and the second chip is tested through a single path. This can quickly and effectively determine whether there are any abnormalities in the connection between the first chip and the second chip, thereby accurately testing the effectiveness of the connection between the chips. This ensures that there are no interconnection failures between the first chip and the second chip due to defects in the production process such as inter-chip interconnection and packaging, thereby improving the reliability of entering the test sub-mode in the system packaging scenario.

[0146] This embodiment eight provides a forced test circuit for a chip, see [link to relevant documentation]. Figure 8 This is a schematic diagram of the forced test circuit of the chip provided in Embodiment 8 of the present invention. The circuit includes: a target interface, a forced test signal, a first target tri-state gate, a second target tri-state gate, a first target AND gate, a first target OR gate, a first target inverter, a second target inverter, a first target output terminal, a first target input terminal, a first control signal, and a second control signal. The forced test signal is connected to the first input terminal of the first target AND gate through the first target inverter; The first control signal is connected to the second input terminal of the first target AND gate; The output of the first target AND gate is connected to the enable terminal of the first target tri-state gate through the second target inverter; The output terminal of the first target is connected to the input terminal of the first target tri-state gate; The output of the first target tri-state gate is bidirectionally connected to the target interface; The output of the first target tri-state gate is also connected to the input of the second target tri-state gate; The forced test signal is also connected to the first input terminal of the first target or gate; The second control signal is connected to the second input terminal of the first target OR gate; The output terminal of the first target OR gate is connected to the enable terminal of the second target tri-state gate; The output of the second target tri-state gate is connected to the input of the first target.

[0147] In one specific implementation, the chip includes a second interface and a third interface, and the target interface is either the second interface or the third interface.

[0148] The chip has corresponding forced test circuits for its second and third interfaces to ensure that both interfaces are in the conducting state when controlled by the forced test signal.

[0149] In one specific implementation, the pads corresponding to the target interface are exposed outside the chip's package.

[0150] The pads corresponding to the target interface can be accessed by users or testers.

[0151] In one specific implementation, when the forced test signal is high, the first target AND gate outputs a low level, and the first target tri-state gate is in the off state.

[0152] The first target tri-state gate is enabled at a low level. When the forced test signal is high, it outputs a low level after passing through the first target inverter, then a low level after passing through the first target AND gate, and finally a high level after passing through the second target inverter. The first target tri-state gate is in the off state, meaning that it is impossible to send a signal from the first target output terminal to the target interface.

[0153] In one specific implementation, when the forced test signal is high, the first target OR gate outputs a high level, and the first target tri-state gate is in the on state.

[0154] Among them, the second target tri-state gate is enabled by a high level. When the forced test signal is high, it outputs a high level after passing through the first target OR gate, and the first target tri-state gate is in the conducting state, that is, it can send a signal from the target interface to the first target input terminal.

[0155] In one specific implementation, when the forced test signal is low, the circuit state of the first target tri-state gate is determined by the first control signal, and the circuit state includes the cut-off state and the conduction state.

[0156] Specifically, when the forced test signal is low, if the first control signal is high, the first target tri-state gate is in the on state; if the first control signal is low, the first target tri-state gate is in the off state.

[0157] In one specific implementation, when the forced test signal is low, the circuit state of the second target tri-state gate is determined by the second control signal.

[0158] Specifically, when the forced test signal is low, if the second control signal is high, the second target tri-state gate is in the on state; if the second control signal is low, the second target tri-state gate is in the off state.

[0159] It should be noted that in this embodiment, a high level indicates that the forced test signal is active. The implementer can, according to the actual situation, indicate that the forced test signal is active when it is low. Accordingly, the forced test signal can be directly connected to the first input terminal of the first target AND gate. Similarly, the forced test signal can be connected to the first input terminal of the first target OR gate through an inverter. In particular, the implementer can also adjust the enabling mode of the first target tri-state gate and the second target tri-state gate to ensure that the target interface is in the input state when the forced test signal is active. This will not be elaborated further here. The implementer should know that the above circuit adjustments are all within the protection scope of this invention.

[0160] In one specific implementation, the forced test signal is generated by a forced test signal generation circuit.

[0161] In this embodiment eight, a forced test signal is introduced into the test circuit. When the forced test signal is high, the first target tri-state gate is in the off state and the second target tri-state gate is in the on state, thereby ensuring that the target interface is in the input state. The target interface can be the second interface and the third interface, thereby ensuring that the second interface and the third interface maintain the input state in the test mode to receive the configuration of the test sub-mode, that is, to increase the priority of the test sub-mode configuration.

[0162] This embodiment nine provides a forced test signal generation circuit for a chip, see [link to relevant documentation]. Figure 9 This is a schematic diagram of the forced test signal generation circuit of the chip provided in Embodiment 9 of the present invention. The circuit includes: a first target pad, a second target pad, a target pull-up resistor, a third target tri-state gate, a fourth target tri-state gate, a power-on reset signal, a power-on reset delay signal, a third target inverter, and a latch corresponding to the interaction interface. The first target pad is connected to the target pull-up resistor; The first target pad is also bidirectionally connected to the second target pad; The second target pad is connected to the output terminal of the third target tri-state gate and the input terminal of the fourth target tri-state gate, respectively; The power-on reset delay signal is connected to the enable terminal of the third target tri-state gate through the third target inverter; The power-on reset delay signal is also connected to the enable terminal of the fourth target tri-state gate; The output terminal of the fourth target tri-state gate is connected to the input terminal of the latch; The power-on reset signal is connected to the control terminal of the latch; The output of the latch is used to output a forced test signal.

[0163] The target pull-up resistor is connected to the power supply. When the power-on reset delay signal is high, the third target tri-state gate is turned off and the fourth target tri-state gate is turned on, and the latch can receive signals sent by the interactive interface. When the power-on reset delay signal is low, the third target tri-state gate is turned on and the fourth target tri-state gate is turned off, and the latch can receive signals sent by the interactive interface.

[0164] In one specific implementation, the first target pad is exposed outside the chip's package housing.

[0165] In one specific implementation, the circuit further includes an oscillator, a first target flip-flop, a second target flip-flop, and a fourth target inverter; The oscillator is connected to the clock terminals of the first target flip-flop and the second target flip-flop, respectively. The power-on reset signal is connected to the input terminal of the first target trigger. The output of the first target flip-flop is connected to the input of the second target flip-flop; The output of the second target flip-flop is used to output the power-on reset delay signal after passing through the fourth target inverter.

[0166] In this embodiment, the oscillator starts working immediately after the chip is powered on. Therefore, in order to ensure that the forced test signal can respond to the generation requirements in a timely manner, the oscillator is used as the clock source for the first target flip-flop and the second target flip-flop to delay the power-on reset signal.

[0167] In one specific implementation, the oscillator is an LC oscillator.

[0168] Alternatively, an RC oscillator can be used. The implementer can select the type of oscillator according to the actual situation, and there are no restrictions here.

[0169] In one specific implementation, the interaction interface is a general interface, and correspondingly, the circuit further includes a second target input terminal and a second target output terminal; The output of the fourth target tri-state gate is connected to the input of the latch through the second target input; The output terminal of the second target is connected to the input terminal of the tri-state gate of the third target.

[0170] The general interface can refer to a general purpose input / output port (GPIO), which can be configured as input, output, bidirectional or high impedance to meet different application requirements. Therefore, it needs to include a second target input terminal and a second target output terminal to facilitate configuration by users or testers.

[0171] In one specific implementation, the time point when the power-on reset signal changes from low level to high level is taken as the first target time point, and the time point when the power-on reset delay signal changes from high level to low level is taken as the second target time point. The first target time point and the second target time point form a first target time interval. If the first target pad is grounded at any time point from any time point before the first target time point to any time point within the first target time interval, then the latch outputs a high-level forced test signal.

[0172] The latch can be triggered by a low level. When the power-on reset signal, which serves as the control signal, changes from low to high, the signal received by the interactive interface is sampled. Since the power-on reset delay signal is delayed compared to the power-on reset signal, the power-on reset delay signal is still high at this time. That is, the fourth target tri-state gate is still in the on state, and the signal received by the interactive interface can continue to be sent to the latch. When the first target pad is grounded at any time point from any time point before the first target time point to any time point in the first target time interval, the latch outputs a high-level forced test signal, which makes the level of the signal received by the interactive interface need to be maintained for a certain period of time to be accurately sampled, thus improving the reliability of the forced test signal generation.

[0173] In one specific implementation, if the first target pad is not grounded at any time point from any time point before the first target time point to any time point within the first target time interval, then the second target pad is at a high level, and the latch outputs a low-level forced test signal.

[0174] When the first target pad is not grounded, it is connected to the power supply through the target pull-up resistor. The level of the first target pad gradually rises to a high level. Correspondingly, the second target pad is at a high level, and the latch outputs a low-level forced test signal.

[0175] In one specific implementation, the forced test signal is used to control the forced test circuit.

[0176] In this embodiment nine, the generation of the forced test signal is controlled by the power-on reset signal and the power-on reset delay signal obtained by its own delay. No other signals are needed, which ensures that the forced test signal can respond to the generation requirements in a timely manner. Moreover, the power-on reset signal is used as the clock input of the latch to sample the signal received by the interactive interface, so that the level of the signal received by the interactive interface needs to be maintained for a certain period of time to be accurately sampled, which improves the reliability of the forced test signal generation.

[0177] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of this invention is defined by the appended claims.

Claims

1. A forced test signal generation circuit of a chip, characterized by, The circuit comprises a first target pad, a second target pad, a target pull-up resistor, a third target tri-state gate, a fourth target tri-state gate, a power-on reset signal, a power-on reset delay signal, a third target inverter and a latch corresponding to the interactive interface; The first target pad is connected with the target pull-up resistor; The first target pad is also bidirectionally connected with the second target pad; The second target pad is connected with an output end of the third target tri-state gate and an input end of the fourth target tri-state gate respectively; The power-on reset delay signal is connected with an enable end of the third target tri-state gate through the third target inverter; The power-on reset delay signal is also connected with an enable end of the fourth target tri-state gate; An output end of the fourth target tri-state gate is connected with an input end of the latch; The power-on reset signal is connected with a control end of the latch; An output end of the latch is used for outputting a forced test signal.

2. The forced test signal generation circuit of claim 1, wherein, The first target pad is exposed outside a package shell of the chip.

3. The forced test signal generation circuit of claim 1, wherein, The circuit further comprises an oscillator, a first target flip-flop and a second target flip-flop and a fourth target inverter; The oscillator is connected with a clock end of the first target flip-flop and a clock end of the second target flip-flop respectively; The power-on reset signal is connected with an input end of the first target flip-flop; An output end of the first target flip-flop is connected with an input end of the second target flip-flop; An output end of the second target flip-flop is used for outputting the power-on reset delay signal through the fourth target inverter.

4. The forced test signal generation circuit of claim 3, wherein, The oscillator is an LC oscillator.

5. The forced test signal generation circuit of claim 1, wherein, The interactive interface is a general interface, and correspondingly, the circuit further comprises a second target input end and a second target output end; An output end of the fourth target tri-state gate is connected with an input end of the latch through the second target input end; The second target output end is connected with an input end of the third target tri-state gate.

6. The forced test signal generation circuit of claim 1, wherein, A time point when the power-on reset signal is changed from a low level to a high level is taken as a first target time point, a time point when the power-on reset delay signal is changed from a high level to a low level is taken as a second target time point, and a first target time interval is formed by the first target time point and the second target time point; If the first target pad is grounded at any time point before the first target time point or at any time point in the first target time interval, the latch outputs a high-level forced test signal.

7. The forced test signal generation circuit of claim 6, wherein, If the first target pad is not grounded at any time point before the first target time point or at any time point in the first target time interval, the second target pad is a high level, and the latch outputs a low-level forced test signal.

8. The forced test signal generation circuit of claim 1, wherein, The forced test signal is used for controlling a forced test circuit.

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