Heterojunction battery and preparation method thereof

Abstract

The invention discloses a heterojunction cell and a preparation method thereof, and belongs to the field of solar cells. The heterojunction cell comprises a silicon substrate, wherein a silicon oxide-amorphous silicon fusion passivation layer, an intrinsic silicon seed layer and an intrinsic silicon main body layer are sequentially arranged on the textured surface of the silicon substrate from inside to outside; the silicon oxide-amorphous silicon fusion passivation layer comprises a silicon oxide body and amorphous silicon deposits, the silicon oxide body is provided with holes, and the amorphous silicon deposits are deposited in at least part of the holes; amorphous silicon in the intrinsic silicon seed layer is the same as amorphous silicon in the silicon oxide-amorphous silicon fusion passivation layer, and the density of the intrinsic silicon seed layer is lower than that of the intrinsic silicon main body layer. According to the heterojunction cell provided by the invention, the open-circuit voltage and the filling factor can be effectively improved, and the photoelectric conversion efficiency of the cell can be further improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of solar cells, in particular to a heterojunction cell and a preparation method thereof. BACKGROUND

[0002] As a representative of high-efficiency photovoltaic solar cells, heterojunction (HJT) solar cells have attracted much attention in the industry in recent years due to their excellent photoelectric conversion efficiency and low-temperature process compatibility. The current HJT texturing process generally uses alkaline wet etching to form a surface pyramid structure, and then removes organic residues and natural oxide layers through post-cleaning, and then performs intrinsic passivation layer coating based on PECVD. However, in the above process, the silicon surface after texturing is highly active, and if it is cleaned too much, it may cause the interface defects to be exposed, even introducing secondary pollution risk, significantly reducing the charge selectivity of the passivation layer, and restricting the improvement of the open-circuit voltage and the fill factor of the cell.

[0003] In view of this, the present application is proposed. SUMMARY

[0004] The present application aims to provide a heterojunction cell and a preparation method thereof to solve or improve the above technical problems.

[0005] The present application can be achieved as follows: In a first aspect, the present application provides a heterojunction cell, comprising a silicon substrate, and a silicon oxide-amorphous silicon fusion passivation layer, an intrinsic silicon seed layer and an intrinsic silicon main body layer arranged in sequence from inside to outside on the surface of the silicon substrate after texturing. The silicon oxide-amorphous silicon fusion passivation layer comprises a silicon oxide body and an amorphous silicon deposit, and the silicon oxide body has pores, and the amorphous silicon deposit is deposited in at least part of the pores. The amorphous silicon in the intrinsic silicon seed layer is the same as the amorphous silicon in the silicon oxide-amorphous silicon fusion passivation layer, and the density of the intrinsic silicon seed layer is lower than the density of the intrinsic silicon main body layer.

[0006] In an optional embodiment, the thickness of the silicon oxide body is 0.8nm-1.2nm; And / or, the thickness of the intrinsic silicon seed layer is 1.5nm-2nm; And / or, the thickness of the intrinsic silicon main body layer is 4nm-4.5nm.

[0007] In an optional embodiment, the front surface of the silicon substrate is sequentially provided with a first silicon oxide-amorphous silicon fusion passivation layer, a first intrinsic silicon seed layer, a first intrinsic silicon main body layer, a first doped amorphous / microcrystalline silicon layer, a first transparent conductive layer and a first metal electrode. The back surface of the silicon substrate is sequentially provided with a second silicon oxide-amorphous silicon fusion passivation layer, a second intrinsic silicon seed layer, a second intrinsic silicon main body layer, a second doped amorphous / microcrystalline silicon layer, a second transparent conductive layer and a second metal electrode.

[0008] In an optional embodiment, the surface of the first metal electrode is further provided with a first metal protective layer; and the surface of the second metal electrode is further provided with a second metal protective layer.

[0009] In a second aspect, the present application provides a preparation method of a heterojunction cell, comprising the following steps: preparing a silicon oxide body on the surface of a silicon substrate after texturing by means of photocatalytic oxidation passivation, depositing amorphous silicon deposits into at least part of the pores of the silicon oxide body to form a silicon oxide-amorphous silicon fusion passivation layer; and then depositing an intrinsic silicon seed layer and an intrinsic silicon main body layer.

[0010] In an optional embodiment, the photocatalytic oxidation passivation comprises: immersing the silicon substrate after texturing into a reaction solution containing a semiconductor catalyst and an oxidizing agent, and then performing photocatalytic film plating.

[0011] In an optional embodiment, the surface after texturing is cleaned before the photocatalytic oxidation passivation.

[0012] In an optional embodiment, the obtained silicon oxide body is cleaned after the photocatalytic oxidation passivation, and then the amorphous silicon deposits are deposited.

[0013] In an optional embodiment, the reaction solution comprises at least one of the following characteristics: Characteristic 1: the pH value of the reaction solution is 4-6; Characteristic 2: the content of the semiconductor catalyst in the reaction solution is 0.1 g / L-0.3 g / L; Characteristic 3: the content of the oxidizing agent in the reaction solution is 0.2wt%-0.4wt%; Characteristic 4: the semiconductor catalyst comprises TiO2; Characteristic 5: the oxidizing agent comprises hydrogen peroxide.

[0014] In an optional embodiment, the photocatalytic film plating comprises at least one of the following characteristics: Characteristic 6: the wavelength of the light source is 360 nm-370 nm; Characteristic 7: the irradiation intensity of the light source is 10 mW / cm 2 -30 mW / cm 2 ; Characteristic 8: the irradiation time of the light source is 10 s-15 s; Characteristic 9: the irradiation temperature of the light source is 20℃-30℃; Characteristic 10: oxygen is introduced into the reaction solution during the photocatalytic film plating process.

[0015] In optional embodiments, the light source is arranged in an array during the photocatalytic coating process.

[0016] In optional embodiments, the difference in light intensity received by different positions on the surface of the silicon substrate during the photocatalytic coating process is no more than 5%.

[0017] In optional embodiments, the deposition conditions of the amorphous silicon deposit and the intrinsic silicon seed layer include: a power of 10 mW / cm 2 ~30 mW / cm 2 , a volume ratio of H2 to SiH4 of 15:1 to 20:1, and a temperature of 120℃ to 150℃. The deposition conditions of the intrinsic silicon bulk layer include: a power of 30 mW / cm 2 ~60 mW / cm 2 , a volume ratio of H2 to SiH4 of 10:1 to 12:1, and a temperature of 170℃ to 200℃.

[0018] In optional embodiments, the doped amorphous / microcrystalline silicon layer, the transparent conductive layer, and the metal electrode are sequentially prepared on the surface of the intrinsic silicon bulk layer from inside to outside.

[0019] In optional embodiments, a metal protective layer is prepared on the surface of the metal electrode.

[0020] The beneficial effects of the present application include: The present application can significantly reduce the surface defect state density and reduce carrier recombination by forming Si-O covalent bonds to convert dangling bonds into a chemical passivation layer, and balance the light trapping effect and electrical performance. Furthermore, the above-mentioned silicon oxide-amorphous silicon fusion passivation layer can also protect the textured structure. By depositing an amorphous silicon deposit in the pores of the silicon oxide body, the density of the silicon oxide body can be improved, the interface quality can be improved to a certain extent, and the energy band matching can be optimized, thereby facilitating the improvement of the open-circuit voltage and the fill factor.

[0021] In addition, the amorphous silicon in the above-mentioned silicon oxide-amorphous silicon fusion passivation layer is the same as the amorphous silicon in the intrinsic silicon seed layer, which can make the intrinsic silicon seed layer play a certain transition role between the silicon oxide-amorphous silicon fusion passivation layer and the intrinsic silicon bulk layer, and facilitate the effective transmission of the passivation ability of the fusion passivation layer to the dense intrinsic amorphous silicon bulk layer. By controlling the density of the intrinsic silicon seed layer to be lower than the density of the intrinsic silicon bulk layer, the silicon oxide-amorphous silicon fusion passivation layer, the intrinsic silicon seed layer, and the intrinsic silicon bulk layer can provide passivation performance while effectively blocking the diffusion of atoms in the doped layer. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor.

[0023] Figure 1 Structure diagram of a heterojunction cell provided by the present application; Figure 2 Structure diagram of a HJT cell provided by a comparative example; Figure 3 Performance result diagram of a heterojunction cell prepared in Example 1 in the test example; Figure 4 Performance result diagram of a HJT cell prepared in the comparative example in the test example.

[0024] Figure legend: 10-silicon substrate; 21-first silicon oxide-amorphous silicon fusion passivation layer; 22-first intrinsic silicon layer; 221-first intrinsic silicon seed layer; 222-first intrinsic silicon bulk layer; 23-first doped amorphous / microcrystalline silicon layer; 24-first transparent conductive layer; 25-first metal electrode; 31-second silicon oxide-amorphous silicon fusion passivation layer; 32-second intrinsic silicon layer; 321-second intrinsic silicon seed layer; 322-second intrinsic silicon bulk layer; 33-second doped amorphous / microcrystalline silicon layer; 34-second transparent conductive layer; 35-second metal electrode; 41-first silicon oxide layer; 42-second silicon oxide layer. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below. If the specific conditions are not specified in the embodiments, the conventional conditions or the conditions recommended by the manufacturer are used. If the reagents or instruments used are not specified by the manufacturer, they are all conventional products that can be purchased on the market.

[0026] The heterojunction cell provided by the present application and the preparation method thereof will be described in detail below.

[0027] The present application provides a heterojunction cell, which comprises a silicon substrate, a first silicon oxide-amorphous silicon fusion passivation layer, a first intrinsic silicon layer, a first doped amorphous / microcrystalline silicon layer, a first transparent conductive layer and a first metal electrode. Figure 1As shown, it comprises a silicon substrate 10, and the surface of the silicon substrate 10 after texturing is sequentially provided, from inside to outside, with a silicon oxide-amorphous silicon fusion passivation layer, an intrinsic silicon seed layer and an intrinsic silicon main body layer. The silicon oxide-amorphous silicon fusion passivation layer comprises a silicon oxide body and an amorphous silicon deposit, the silicon oxide body has pores, and the amorphous silicon deposit is deposited in at least part of the pores; the amorphous silicon in the intrinsic silicon seed layer is the same as the amorphous silicon in the silicon oxide-amorphous silicon fusion passivation layer, and the density of the intrinsic silicon seed layer is lower than the density of the intrinsic silicon main body layer.

[0028] In some optional embodiments, the thickness of the silicon oxide body can be 0.8nm-1.2nm, such as 0.8nm, 0.9nm, 1nm, 1.1nm or 1.2nm, etc., or other values within the range of 0.8nm-1.2nm.

[0029] The thickness of the intrinsic silicon seed layer can be 1.5nm-2nm, such as 1.5nm, 1.6nm, 1.7nm, 1.8nm, 1.9nm or 2nm, etc., or other values within the range of 1.5nm-2nm. The hydrogen content in the intrinsic silicon seed layer can be ≥18at%.

[0030] The thickness of the intrinsic silicon main body layer can be 4nm-4.5nm, such as 4nm, 4.1nm, 4.2nm, 4.3nm, 4.4nm or 4.5nm, etc., or other values within the range of 4nm-4.5nm.

[0031] It should be noted that if the conventional intrinsic amorphous silicon layer is too thick, the parasitic absorption of short-wave light will increase. The refractive index of silicon oxide is between that of air and silicon, forming a refractive index gradient and reducing optical reflection loss. The silicon atoms on the textured surface form a large number of dangling bonds due to the fracture of the crystal surface, which are easy to become surface recombination centers. The present application forms a silicon oxide-amorphous silicon fusion passivation layer with a relatively thin thickness on the textured surface, which can convert the dangling bonds into a chemical passivation layer by forming Si-O covalent bonds, significantly reducing the surface defect state density and reducing carrier recombination, balancing the light trapping effect and electrical performance. Moreover, the above-mentioned silicon oxide-amorphous silicon fusion passivation layer can also protect the textured structure, and by depositing an amorphous silicon deposit in the pores of the silicon oxide body, the interface quality can be improved to a certain extent, and the energy band matching can be optimized.

[0032] In other words, the silicon oxide-amorphous silicon fusion passivation layer uniformly covering the surface of the silicon substrate 10 after texturing can passivate the surface defects of the silicon substrate 10, reduce carrier recombination, and protect the textured structure to prevent subsequent damage such as amorphous silicon deposition, improve the interface quality, and thus be conducive to improving the open-circuit voltage and the fill factor.

[0033] And, the amorphous silicon in the silicon oxide-amorphous silicon fusion passivation layer is the same as the amorphous silicon in the intrinsic silicon seed layer, which can make the intrinsic silicon seed layer play a certain transition role between the silicon oxide-amorphous silicon fusion passivation layer and the intrinsic silicon bulk layer, and is conducive to effectively transmitting the passivation ability of the fusion passivation layer to the dense intrinsic amorphous silicon bulk layer; and by controlling the density of the intrinsic silicon seed layer to be lower than the density of the intrinsic silicon bulk layer, the silicon oxide-amorphous silicon fusion passivation layer, the intrinsic silicon seed layer and the intrinsic silicon bulk layer can provide passivation performance while effectively blocking the diffusion of atoms in the doped layer.

[0034] The front surface of the silicon substrate 10 is sequentially provided with a first silicon oxide-amorphous silicon fusion passivation layer 21, a first intrinsic silicon seed layer 221, a first intrinsic silicon bulk layer 222 (the first intrinsic silicon seed layer 221 and the first intrinsic silicon bulk layer 222 are uniformly denoted as a first intrinsic silicon layer 22 in the drawings), a first doped amorphous / microcrystalline silicon layer 23, a first transparent conductive layer 24 and a first metal electrode 25. The back surface of the silicon substrate 10 is sequentially provided with a second silicon oxide-amorphous silicon fusion passivation layer 31, a second intrinsic silicon seed layer 321, a second intrinsic silicon bulk layer 322 (the second intrinsic silicon seed layer 321 and the second intrinsic silicon bulk layer 322 are uniformly denoted as a second intrinsic silicon layer 32 in the drawings), a second doped amorphous / microcrystalline silicon layer 33, a second transparent conductive layer 34 and a second metal electrode 35.

[0035] Further, the surface of the first metal electrode 25 can be further provided with a first metal protective layer; and the surface of the second metal electrode 35 can be further provided with a second metal protective layer.

[0036] Correspondingly, the application further provides a preparation method of a heterojunction cell, which comprises the following steps: preparing a silicon oxide body on the surface of a silicon substrate 10 after texturing by using a photocatalytic oxidation passivation method, and depositing amorphous silicon deposits in at least part of the pores of the silicon oxide body to form a silicon oxide-amorphous silicon fusion passivation layer; and then depositing an intrinsic silicon seed layer and an intrinsic silicon bulk layer.

[0037] In the conventional process, the acid or deionized water cleaning step after texturing aims to completely remove etching residues, but also eliminates the naturally generated silicon oxide layer on the silicon surface. Although the artificial passivation layer generated by ozone oxidation can alleviate the above problems to a certain extent. However, the ozone or H2O2 oxidation cannot accurately control the thickness of the silicon oxide layer, resulting in a decrease in interface conductivity; at the same time, the wet process cannot accurately control the thickness of the silicon oxide layer, resulting in unstable passivation effect.

[0038] The application utilizes a light source (such as ultraviolet light) to excite a semiconductor catalyst (such as TiO2) to generate high-activity oxidizing substances on the surface of the textured surface, drive the oxidation reaction, and increase the uniformity of the film layer. Furthermore, the above-mentioned photocatalytic oxidation passivation method can generate a silicon oxide body with controllable thickness in situ, and then repair the pores in the silicon oxide body through a PECVD process to secondarily modify the oxidation passivation layer, thereby forming a silicon oxide-amorphous silicon fusion passivation layer and greatly improving the open-circuit voltage of the battery and the battery efficiency.

[0039] In the above-mentioned photocatalytic oxidation passivation process, the free radicals generated by photocatalysis are small in size and strong in diffusivity, and can penetrate into the microscopic recessed areas of the textured surface to avoid the problem of uneven coverage caused by the gas-phase diffusion limitation of ozone oxidation in conventional technologies. Photocatalysis generates a silicon oxide body under low-temperature green and environmentally friendly conditions, which can protect the integrity of the textured surface. Furthermore, the silicon oxide body generated by photocatalysis contains high-density dangling bond hydrogen, which can passivate the interface defect states, reduce the recombination rate, and improve the open-circuit voltage.

[0040] The following is the main process of photocatalysis: (1) Catalyst activation: a light source (such as ultraviolet light) irradiates a semiconductor catalyst (such as TiO2) to generate an electron-hole pair (e - -h + ); the hole has strong oxidizing properties and is the driving force for subsequent reactions.

[0041] TiO2+hv(UV)→TiO2(e - +h + ); (2) Active free radical generation: holes react with water molecules / adsorbed oxygen to produce reactive oxygen species (ROS), and hydroxyl radicals (·OH) have an oxidation potential of +2.8V and act as strong oxidizing agents for oxidation reactions.

[0042] h + +H2O→·OH+H + ; e - +O2→·O2 - →·OH / H2O2; (3) Silicon surface oxidation reaction: free radicals attack silicon surface dangling bonds (Si-H / Si-Si) to build SiO2 layer by layer.

[0043] Si (surface) + 2·OH → SiO2 + H2.

[0044] Furthermore, amorphous silicon is deposited into the pores of the silicon oxide body through PECVD deposition to form a silicon oxide-amorphous silicon fusion passivation layer, which can repair the pores of the silicon oxide body, restructure the interface energy band and chemical bonding structure, and achieve passivation and efficiency enhancement.

[0045] As described above, the silicon oxide body formed on the suede surface by the photocatalytic oxidation passivation method is uniform and dense and rich in high-density dangling bond hydrogen, which can passivate the interface defect state, reduce the recombination rate, and improve the open-circuit voltage. When amorphous silicon deposits are deposited into at least part of the pores of the silicon oxide body by PECVD, the silicon oxide body formed by photocatalysis contains high-density Si-OH bonds, which react with the PECVD deposition to form Si-O-Si covalent bonds, increase the interfacial adhesion, improve the passivation effect, and can increase the open-circuit voltage by more than 2 mV and the cell efficiency by more than 0.1%.

[0046] In some optional embodiments, the surface after texturing is cleaned before photocatalytic oxidation passivation. After photocatalytic oxidation passivation, the obtained silicon oxide body is cleaned, and then amorphous silicon deposits are deposited. Further, a doped amorphous / microcrystalline silicon layer, a transparent conductive layer, and a metal electrode are sequentially prepared on the surface of the intrinsic silicon bulk layer from inside to outside. Optionally, a metal protective layer is prepared on the surface of the metal electrode.

[0047] In some more specific embodiments, the silicon substrate 10 can be subjected to gettering, initial polishing, texturing, pre-cleaning, photocatalytic oxidation passivation to prepare a silicon oxide body and deposition of amorphous silicon deposits to form a silicon oxide-amorphous silicon fusion passivation layer, followed by deposition of an intrinsic silicon seed layer, an intrinsic silicon bulk layer, a doped amorphous / microcrystalline silicon layer, a transparent conductive layer, and a metal electrode.

[0048] The gettering can eliminate metal impurities (such as Fe and Cu) in the silicon substrate 10, for example, traditional tube-type gettering or chain-type gettering can be used.

[0049] The initial polishing can remove the PSG layer and the damage layer, for example, NaOH and / or KOH can be used to selectively remove the PSG based on alkaline etching.

[0050] The texturing can mainly expose the (111) crystal surface based on anisotropic etching to form a light-trap pyramid structure.

[0051] The pre-cleaning can mainly clean and remove the natural oxide layer after texturing to avoid invalidation of the photocatalytic passivation effect.

[0052] The photocatalytic oxidation passivation can mainly form an ultra-thin and uniform silicon oxide body on the clean suede silicon surface.

[0053] In some optional embodiments, the photocatalytic oxidation passivation includes: immersing the silicon substrate 10 after texturing in a reaction solution containing a semiconductor catalyst and an oxidizing agent, and then performing photocatalytic plating.

[0054] The pH value of the reaction solution can be 4-6, such as 4, 4.5, 5, 5.5, or 6, or other values within the range of 4-6.

[0055] The content of the semiconductor catalyst in the reaction solution can be 0.1 g / L to 0.3 g / L, such as 0.1 g / L, 0.15 g / L, 0.2 g / L, 0.25 g / L or 0.3 g / L, etc., and can also be other values within the range of 0.1 g / L to 0.3 g / L. The above semiconductor catalyst can exemplarily but non-limitingly include TiO2.

[0056] The content of the oxidizing agent in the reaction solution can be 0.2 wt% to 0.4 wt%, such as 0.2 wt%, 0.25 wt%, 0.3 wt%, 0.35 wt% or 0.4 wt%, etc., and can also be other values within the range of 0.2 wt% to 0.4 wt%. The above oxidizing agent can exemplarily but non-limitingly include hydrogen peroxide.

[0057] The solvent in the reaction solution can be deionized water, for example.

[0058] By using the above reaction solution, hydroxyl radicals can be generated in the photocatalytic process.

[0059] In some optional embodiments, the wavelength of the light source used for photocatalytic plating can be 360 nm to 370 nm, such as 360 nm, 365 nm or 370 nm, etc., and can also be other values within the range of 360 nm to 370 nm.

[0060] The above wavelength range can excite the TiO2 band gap.

[0061] The irradiation intensity of the light source can be 10 mW / cm 2 ~30 mW / cm 2 , such as 10 mW / cm 2 , 15 mW / cm 2 , 20 mW / cm 2 , 25 mW / cm 2 or 30 mW / cm 2 , etc., and can also be other values within the range of 10 mW / cm 2 ~30 mW / cm 2 .

[0062] At the irradiation intensity, the oxidation rate can be increased, such as the oxidation rate ≥ 0.017 nm / s.

[0063] The irradiation time of the light source can be 10 s to 15 s, such as 10 s, 11 s, 12 s, 13 s, 14 s or 15 s, etc., and can also be other values within the range of 10 s to 15 s.

[0064] At the irradiation time range, the thickness of the silicon oxide body can be precisely controlled.

[0065] The irradiation temperature of the light source can be 20-30°C, such as 20°C, 22°C, 25°C, 28°C or 30°C, or other values within the range of 20-30°C.

[0066] At the irradiation temperature, thermal damage to the velvet structure can be avoided.

[0067] During the photocatalytic coating process, oxygen is introduced into the reaction solution to promote the oxidation cycle.

[0068] In some alternative embodiments, the light source is arranged in an array during the photocatalytic coating process. Preferably, the light intensity received by each position on the surface of the silicon substrate 10 during the photocatalytic coating process does not differ by more than 5%. For example, LED lights can be uniformly distributed on the inner walls of the photocatalytic coating device, arranged at equal intervals, and combined with the settings of LED light power and spacing to specifically compensate for the light shadow effect caused by the pyramid structure in the valley of the velvet, so that the valley area which originally receives the weakest light can obtain additional light intensity gain, reduce the deviation of the global ultraviolet light intensity distribution of the silicon wafer, and ensure that the uniformity of the silicon oxide body growth reaches atomic level precision (±0.05 nm). Illustratively, the power of the LED lights corresponding to the area that may receive weaker light is set to be higher than that of the area that may receive stronger light (for example, the former is set to 115%-125%, and the latter is set to 100%-105%); illustratively, the spacing of the LED lights corresponding to the area that may receive weaker light is set to be smaller than that of the area that may receive stronger light (for example, the former is set to 20-22.5 mm, and the latter is set to 23-25 mm).

[0069] In some alternative embodiments, after the photocatalytic coating is completed, cleaning is performed to remove photocatalytic residues (to prevent TiO2 particles from being contaminated). Illustratively, ultrapure water (18 MΩ) combined with megasonic waves (0.8-1.2 MHz) can be used, the cleaning temperature can be 20-30°C, and the cleaning time can be 160-200 s. After cleaning, the wafer can be dried at 55-65°C under a protective atmosphere such as nitrogen for 280-320 s. The water vapor generated during the above drying process can maintain the stability of the silicon oxide body.

[0070] In some alternative embodiments, an intrinsic seed layer is deposited using a low-temperature, high-hydrogen method (e.g., 115°C~125°C, hydrogen content ≥18 at%), utilizing its superior interfacial bonding ability to directly saturate the dangling bonds on the silicon oxide bulk surface. For example, during PECVD deposition at 115°C~125°C, the intrinsic seed layer precursor SiH3 radicals undergo dehydration condensation with the silanol groups (Si-OH) on the silicon oxide bulk surface, forming a Si-O-Si covalent bridging network (bond energy approximately 452 kJ / mol), which is 103% stronger than traditional Si-Si bonds (approximately 222 kJ / mol). Furthermore, the intrinsic silicon seed layer SiH3 groups penetrate into SiO through quantum tunneling. x Nanopores fill the nanopores in silicon oxide and form a silicon oxide-amorphous silicon fusion passivation layer, which plays a role in repairing defects in silicon oxide and reducing carrier recombination.

[0071] In some alternative embodiments, the deposition conditions for the amorphous silicon deposit and the intrinsic silicon seed layer include: a power of 10 mW / cm². 2 ~30mW / cm 2 (e.g., 10mW / cm) 2 15mW / cm 2 20mW / cm 2 25mW / cm 2 Or 30mW / cm 2 The volume ratio of H2 to SiH4 is 15:1 to 20:1 (e.g., 15:1, 16:1, 17:1, 18:1, 19:1 or 20:1), and the temperature is 120℃~150℃ (e.g., 120℃, 130℃, 140℃ or 150℃).

[0072] The deposition conditions for the intrinsic silicon host layer included: a power of 30 mW / cm². 2 ~60mW / cm 2 (e.g., 30mW / cm) 2 35mW / cm 2 40mW / cm 2 45mW / cm 2 50mW / cm 2 55mW / cm 2 Or 60mW / cm 2 The volume ratio of H2 to SiH4 is 10:1 to 12:1 (e.g., 10:1, 11:1 or 12:1), and the temperature is 170℃~200℃ (e.g., 170℃, 180℃, 190℃ or 200℃).

[0073] The deposition conditions of the intrinsic silicon seed layer are the same as the deposition conditions of the amorphous silicon deposit, and the selective hydrogen passivation of the incompletely saturated dangling bonds on the surface of the silicon oxide-amorphous silicon fusion passivation layer can be achieved by using low power and high dilution ratio conditions. At the same time, the low-temperature and low-power deposition mode repairs the metastable defects existing in the silicon oxide-amorphous silicon fusion passivation layer at the atomic scale, and then the passivation ability of the fusion passivation layer is basically transmitted to the dense intrinsic silicon bulk layer (the preparation conditions correspond to high power, low normal dilution ratio and high temperature) without damage, which effectively blocks the atomic diffusion of the doped layer while ensuring the provision of passivation performance. Finally, by thinning the intrinsic silicon bulk layer, parasitic absorption is reduced to ensure the interface passivation quality and carrier transport characteristics.

[0074] It should be noted that the specific preparation process and conditions of the texturing, doped amorphous / microcrystalline silicon layer, transparent conductive layer, metal electrode, metal protective layer, etc. in the present application can refer to related prior art, and will not be described or limited here.

[0075] The features and properties of the present application are further described in detail below in conjunction with the embodiments.

[0076] Embodiment 1 The present embodiment provides a heterojunction cell, which includes a silicon substrate 10, and the front surface of the silicon substrate 10 is sequentially provided with a first silicon oxide-amorphous silicon fusion passivation layer 21, a first intrinsic silicon seed layer 221, a first intrinsic silicon bulk layer 222, a first doped amorphous / microcrystalline silicon layer 23, a first transparent conductive layer 24 and a first metal electrode 25. The back surface of the silicon substrate 10 is sequentially provided with a second silicon oxide-amorphous silicon fusion passivation layer 31, a second intrinsic silicon seed layer 321, a second intrinsic silicon bulk layer 322, a second doped amorphous / microcrystalline silicon layer 33, a second transparent conductive layer 34 and a second metal electrode 35. Each silicon oxide-amorphous silicon fusion passivation layer includes a silicon oxide body and an amorphous silicon deposit, the silicon oxide body has pores, and at least part of the pores are deposited with the amorphous silicon deposit.

[0077] The preparation of the above-mentioned heterojunction cell includes: The silicon substrate 10 is subjected to gettering, initial polishing, texturing, pre-cleaning, and photo-catalytic oxidation passivation to prepare a silicon oxide body with a thickness of 1 nm.

[0078] The photo-catalytic oxidation passivation includes: immersing the above-mentioned pre-cleaned silicon substrate 10 in a reaction solution containing a semiconductor catalyst and an oxidizing agent, and then performing photo-catalytic coating. The pH value of the reaction solution is 5; the semiconductor catalyst is TiO2, and the content of TiO2 in the reaction solution is 0.2 g / L; the oxidizing agent is hydrogen peroxide, and the content of hydrogen peroxide in the reaction solution is 0.3 wt%; the solvent in the reaction solution is deionized water. The wavelength of the light source used for photo-catalytic coating is 365 nm; the irradiation intensity of the light source is 20 mW / cm 2The irradiation time of the light source is 10 s, and the irradiation temperature of the light source is 25°C. During the photocatalytic plating process, oxygen is introduced into the reaction solution to promote the oxidation cycle. During the photocatalytic plating process, the LED lamps are uniformly distributed on the inner walls of the photocatalytic plating device (equidistantly spaced). The power of the LED lamps corresponding to the areas with weaker light is set to 120%, and the power of the LED lamps corresponding to the areas with stronger light is set to 100%. The spacing of the LED lamps corresponding to the areas with weaker light is set to 20 mm, and the spacing of the LED lamps corresponding to the areas with stronger light is set to 25 mm.

[0079] After the photocatalytic plating is completed, the substrate is cleaned with ultrapure water (18 MΩ) and megasonic waves (1 MHz) at 25°C for 180 s, and then dried at 60°C under nitrogen protection for 300 s.

[0080] Then, the deposition of amorphous silicon in the pores of the silicon oxide body and the deposition of the intrinsic seed layer (thickness of 1.5 nm) are carried out in a low-temperature high-hydrogen mode (temperature of 120°C, hydrogen content of 18 at%). The deposition conditions include: power of 20 mW / cm 2 , volume ratio of H2 to SiH4 of 18:1, and temperature of 130°C. Then, the deposition of the intrinsic silicon main layer (thickness of 4.5 nm) is carried out under the following conditions: power of 45 mW / cm 2 , volume ratio of H2 to SiH4 of 12:1, and temperature of 180°C.

[0081] Then, the doped amorphous / microcrystalline silicon layer and the transparent conductive layer are sequentially deposited, and the metal electrode and the metal protective layer are prepared.

[0082] Example 2 The difference between this embodiment and Example 1 is that the preparation of the heterojunction cell includes: The silicon substrate 10 is subjected to gettering, initial polishing, texturing, pre-cleaning, and photocatalytic oxidation passivation to prepare a silicon oxide body with a thickness of 0.8 nm.

[0083] The photocatalytic oxidation passivation includes: immersing the silicon substrate 10 after the pre-cleaning in a reaction solution containing a semiconductor catalyst and an oxidizing agent, and then performing photocatalytic plating. The pH value of the reaction solution is 4. The semiconductor catalyst is TiO2, and its content in the reaction solution is 0.1 g / L. The oxidizing agent is hydrogen peroxide, and its content in the reaction solution is 0.2 wt%. The solvent in the reaction solution is deionized water. The wavelength of the light source used for photocatalytic plating is 360 nm, and the irradiation intensity of the light source is 10 mW / cm 2; the irradiation time of the light source was 12 s; the irradiation temperature of the light source was 20℃; during the photocatalytic plating process, oxygen was introduced into the reaction solution to promote the oxidation cycle. During the photocatalytic plating process, the LED lamps were uniformly distributed on the inner walls of the photocatalytic plating device (equidistantly spaced), the power of the LED lamps corresponding to the areas with weaker light was set to 115%, and the power of the LED lamps corresponding to the areas with stronger light was set to 100%; the spacing of the LED lamps corresponding to the areas with weaker light was set to 20mm, and the spacing of the LED lamps corresponding to the areas with stronger light was set to 23mm.

[0084] After the photocatalytic plating was completed, the silicon substrate was cleaned with ultrapure water (18MΩ) combined with megasonic waves (0.8MHz) at 25℃ for 200s, and then dried at 55℃ under nitrogen protection for 320s. Subsequently, amorphous silicon deposition in the pores of the silicon oxide body and deposition of the intrinsic seed layer (thickness of 1.8nm) were carried out in a low-temperature high-hydrogen mode (temperature of 115℃, hydrogen content of 18at%), and the deposition conditions included: power of 10mW / cm 2 , volume ratio of H2 to SiH4 of 15:1, and temperature of 120℃. Subsequently, the intrinsic silicon main layer (thickness of 4nm) was deposited under the following conditions: power of 30mW / cm 2 , volume ratio of H2 to SiH4 of 10:1, and temperature of 170℃.

[0085] Subsequently, a doped amorphous / microcrystalline silicon layer and a transparent conductive layer were sequentially deposited, and a metal electrode and a metal protective layer were prepared.

[0086] Example 3 The difference between this embodiment and Example 1 is that the preparation of the heterojunction cell includes: The silicon substrate 10 was subjected to gettering, initial polishing, texturing, pre-cleaning, and photocatalytic oxidation passivation to prepare a silicon oxide body with a thickness of 1.2nm.

[0087] The photocatalytic oxidation passivation includes: immersing the silicon substrate 10 after the pre-cleaning into a reaction solution containing a semiconductor catalyst and an oxidizing agent, and then performing photocatalytic plating. The pH value of the reaction solution is 6; the semiconductor catalyst is TiO2, and its content in the reaction solution is 0.3g / L; the oxidizing agent is hydrogen peroxide, and its content in the reaction solution is 0.4wt%; the solvent in the reaction solution is deionized water. The wavelength of the light source used for photocatalytic plating is 370nm; the irradiation intensity of the light source is 30mW / cm 2The irradiation time of the light source is 15 seconds; the irradiation temperature of the light source is 30℃; during the photocatalytic coating process, oxygen is introduced into the reaction solution to promote the oxidation cycle. During the photocatalytic coating process, LEDs (arranged at equal intervals) are evenly distributed on each inner wall of the photocatalytic coating device. The power of the LEDs in areas with weaker light is set to 125%, and the power of the LEDs in areas with stronger light is set to 105%. The spacing between the LEDs in areas with weaker light is set to 22.5 mm, and the spacing between the LEDs in areas with stronger light is set to 25 mm.

[0088] After photocatalytic coating, the film was cleaned at 25°C for 160 seconds using ultrapure water (18 MΩ) combined with megasonic wave (1.2 MHz). Subsequently, it was dried at 65°C for 280 seconds under nitrogen protection. Following this, amorphous silicon was deposited within the pores of the silicon oxide bulk and an intrinsic seed layer (2 nm thick) was deposited using a low-temperature, high-hydrogen method (125°C, 20 at%). The deposition conditions included a power of 30 mW / cm². 2 The volume ratio of H2 to SiH4 was 20:1, and the temperature was 150℃. Subsequently, an intrinsic silicon host layer (4.2 nm thick) was deposited under the following conditions: power 60 mW / cm². 2 The volume ratio of H2 to SiH4 is 11:1, and the temperature is 200℃.

[0089] Subsequently, a doped amorphous / microcrystalline silicon layer and a transparent conductive layer are deposited sequentially, followed by the fabrication of a metal electrode and a metal protective layer.

[0090] Comparison Example This comparative example provides an HJT battery prepared by conventional wet oxidation, the structure of which is as follows: Figure 2 As shown, it includes a silicon substrate 10. The front side of the silicon substrate 10 is sequentially provided with a first silicon oxide layer 41, a first intrinsic silicon layer 22, a first doped amorphous / microcrystalline silicon layer 23, a first transparent conductive layer 24, and a first metal electrode 25. The back side of the silicon substrate 10 is sequentially provided with a second silicon oxide layer 42, a second intrinsic silicon layer 32, a second doped amorphous / microcrystalline silicon layer 33, a second transparent conductive layer 34, and a second metal electrode 35.

[0091] The preparation method and conditions of this HJT battery are as follows: A silicon oxide body with a thickness of 1 nm was prepared by gouging, initial polishing, texturing, pre-cleaning, and wet oxidation of the silicon substrate 10.

[0092] The wet oxidation passivation process includes: placing the texturized silicon wafer into a mixed solution of H2O2:HCl:H2O=1:1:5, and immersing the texturized and cleaned silicon wafer with a hydrophilic surface into the hot solution at a temperature of 75°C for 50 seconds.

[0093] After the wet oxidation to form the silicon oxide layer, the sample was cleaned with ultrapure water (18 MΩ) at 25°C for 180 s under the action of megasonic waves (1 MHz), and then dried at 60°C for 300 s under the protection of nitrogen. Then, the intrinsic seed layer was deposited by using a low-temperature high-hydrogen method (temperature: 120°C, hydrogen content: 18 at%), and the deposition conditions included a power of 20 mW / cm 2 , a volume ratio of H2 to SiH4 of 18:1, and a temperature of 130°C. Then, the intrinsic silicon bulk layer (thickness: 4.5 nm) was deposited under the following conditions: a power of 45 mW / cm 2 , a volume ratio of H2 to SiH4 of 12:1, and a temperature of 180°C.

[0094] Then, the doped amorphous / microcrystalline silicon layer, the transparent conductive layer, the metal electrode, and the metal protective layer were sequentially deposited.

[0095] Test Example The heterojunction cells obtained in Example 1 and the comparative example were taken as examples, and the performance of the cells was compared under the same test conditions, and the results are shown in Tables Figure 3 and Figure 4 .

[0096] As can be seen from Figure 3 and Figure 4 , after multiple rounds of verification, the open-circuit voltage (Voc) and the fill factor (FF) of the heterojunction cells prepared in Example 1 are obviously higher than those of the HJT cells prepared in the comparative example, and the short-circuit current (Isc) is also higher in general.

[0097] And as can be seen from Figure 4 , the battery performance data corresponding to the silicon oxide layer prepared by the traditional wet method has obvious fluctuations in different rounds, and the reason is that the thickness of the silicon oxide layer prepared by this method is not easy to control, and the uniformity is poor. The thickness and uniformity of the silicon oxide layer will affect the deposition of the intrinsic silicon layer and the passivation effect. If the thickness of the silicon oxide layer is too thick or too thin, it will affect the light absorption and the short-circuit current.

[0098] In summary, the heterojunction cell provided by the present application can effectively improve the open-circuit voltage and the fill factor, which is beneficial to further improve the photoelectric conversion efficiency of the cell.

[0099] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A heterojunction battery, characterized in that, The substrate includes a silicon substrate, and the surface of the texturized silicon substrate is provided with a silicon oxide-amorphous silicon fusion passivation layer, an intrinsic silicon seed layer and an intrinsic silicon host layer from the inside to the outside. The silicon oxide-amorphous silicon fused passivation layer includes a silicon oxide bulk and an amorphous silicon deposit, wherein the silicon oxide bulk has pores, and at least a portion of the pores are in which the amorphous silicon deposit is deposited; The amorphous silicon in the intrinsic silicon seed layer is the same as the amorphous silicon in the silicon oxide-amorphous silicon fused passivation layer, and the density of the intrinsic silicon seed layer is lower than that of the intrinsic silicon host layer.

2. The heterojunction solar cell according to claim 1, characterized in that, The thickness of the silicon oxide bulk is 0.8 nm to 1.2 nm; And / or, the thickness of the intrinsic silicon seed layer is 1.5 nm to 2 nm; And / or, the thickness of the intrinsic silicon host layer is 4nm~4.5nm.

3. The heterojunction solar cell according to claim 1 or 2, characterized in that, The front side of the silicon substrate is sequentially provided with a first silicon oxide-amorphous silicon fusion passivation layer, a first intrinsic silicon seed layer, a first intrinsic silicon host layer, a first doped amorphous / microcrystalline silicon layer, a first transparent conductive layer, and a first metal electrode. The back side of the silicon substrate is sequentially provided with a second silicon oxide-amorphous silicon fusion passivation layer, a second intrinsic silicon seed layer, a second intrinsic silicon host layer, a second doped amorphous / microcrystalline silicon layer, a second transparent conductive layer, and a second metal electrode. Preferably, the surface of the first metal electrode is further provided with a first metal protective layer; the surface of the second metal electrode is further provided with a second metal protective layer.

4. A method for preparing a heterojunction solar cell, characterized in that, Includes the following steps: A silicon oxide body is prepared on the surface of a texturized silicon substrate using photocatalytic oxidation passivation. An amorphous silicon deposit is then deposited into at least some of the pores of the silicon oxide body to form the silicon oxide-amorphous silicon fusion passivation layer. Subsequently, an intrinsic silicon seed layer and an intrinsic silicon host layer are deposited.

5. The preparation method according to claim 4, characterized in that, Photocatalytic oxidation passivation includes: immersing a texturized silicon substrate in a reaction solution containing a semiconductor catalyst and an oxidant, followed by photocatalytic coating; Preferably, the texturized surface is cleaned before photocatalytic oxidation passivation; Preferably, after photocatalytic oxidation passivation, the obtained silicon oxide bulk is cleaned, and then the amorphous silicon deposit is deposited.

6. The preparation method according to claim 5, characterized in that, The reaction solution includes at least one of the following characteristics: Feature 1: The pH value of the reaction solution is 4~6; Feature 2: The content of the semiconductor catalyst in the reaction solution is 0.1 g / L to 0.3 g / L; Feature 3: The content of the oxidant in the reaction solution is 0.2wt%~0.4wt%; Feature 4: The semiconductor catalyst comprises TiO2; Feature 5: The oxidant includes hydrogen peroxide.

7. The preparation method according to claim 5 or 6, characterized in that, Photocatalytic coatings include at least one of the following characteristics: Feature 6: The wavelength of the light source is 360nm~370nm; Feature 7: The irradiance of the light source is 10 mW / cm². 2 ~30mW / cm 2 ; Feature 8: The illumination time of the light source is 10s~15s; Feature 9: The irradiation temperature of the light source is 20℃~30℃; Feature 10: During the photocatalytic coating process, oxygen is introduced into the reaction solution.

8. The preparation method according to claim 5, characterized in that, In the photocatalytic coating process, the light sources are distributed in an array; Preferably, during the photocatalytic coating process, the difference in light intensity received by different locations on the silicon substrate surface does not exceed 5%.

9. The preparation method according to claim 4, characterized in that, The deposition conditions for the amorphous silicon deposit and the intrinsic silicon seed layer include: a power of 10 mW / cm². 2 ~30mW / cm 2 The volume ratio of H2 to SiH4 is 15:1 to 20:1, and the temperature is 120℃ to 150℃. The deposition conditions for the intrinsic silicon host layer include: a power of 30 mW / cm². 2 ~60mW / cm 2 The volume ratio of H2 to SiH4 is 10:1 to 12:1, and the temperature is 170℃ to 200℃.

10. The preparation method according to claim 8, characterized in that, A doped amorphous / microcrystalline silicon layer, a transparent conductive layer, and a metal electrode are sequentially fabricated from the inside to the outside on the surface of the intrinsic silicon host layer. Preferably, a metal protective layer is prepared on the surface of the metal electrode.

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