Semiconductor device, method of manufacturing the same, and electronic apparatus

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, and the method comprises the steps: providing a first substrate and a second substrate, the first surface of the first substrate is opposite to the second surface of the second substrate, and a preset gap width is formed between the first surface of the first substrate and the second surface of the second substrate; bombardment is carried out on the first surface of the first substrate, so that generated sputtering particles are deposited on the second surface of the second substrate to form a to-be-bonded layer; and bonding the to-be-bonded layer with the bombarded first surface of the first substrate, so that the to-be-bonded layer and a part of thickness of the first substrate form an insulating trap layer. According to the invention, the insulating trap layer is directly formed in the bonding process, and the process complexity and cost are reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor device, a method for manufacturing the same, and an electronic device. Background Technology

[0002] To improve the performance of semiconductor devices, an insulating trap-rich layer is introduced between the structure wafer and the high-resistivity silicon wafer to trap escaped electrons, reduce electrical losses, and thus improve the performance of semiconductor devices.

[0003] In related technologies, a trap layer is usually grown on a high-resistivity silicon wafer first, so that the trap layer and the high-resistivity silicon wafer are integrated as a whole, and then the side of this whole with the trap layer is bonded to the structure wafer.

[0004] However, in order to meet the bonding strength requirements, the trap layer grown on the high-resistivity silicon wafer needs to be ground and polished to a high standard so that the roughness of the trap layer meets the bonding process requirements, which leads to a complex process and high cost.

[0005] In view of the above-mentioned technical problems, the present invention provides a new semiconductor device, a method for manufacturing the same, and an electronic device. Summary of the Invention

[0006] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0007] To address the existing problems, the present invention provides a method for manufacturing a semiconductor device, the method comprising:

[0008] A first substrate and a second substrate are provided, wherein a first surface of the first substrate and a second surface of the second substrate are disposed opposite to each other and a predetermined gap width is provided between them;

[0009] The first surface of the first substrate is bombarded so that the resulting sputtered particles are deposited on the second surface of the second substrate to form a bonding layer.

[0010] The layer to be bonded is bonded to the first surface of the first substrate after it has been bombarded, so that the layer to be bonded and a portion of the thickness of the first substrate form an insulating trap layer.

[0011] In some embodiments of this application, the first substrate comprises a high-resistivity silicon wafer.

[0012] In some embodiments of this application, the resistivity of the high-resistivity silicon wafer is greater than 5000 ohm·cm.

[0013] In some embodiments of this application, the second substrate includes a structured wafer.

[0014] In some embodiments of this application, the first surface of the first substrate after being bombarded is made of the same material as the surface of the layer to be bonded.

[0015] In some embodiments of this application, the layer to be bonded is a disordered silicon layer.

[0016] In some embodiments of this application, the bombardment is ion bombardment with the first substrate as the sputtering target.

[0017] In another aspect, the present invention provides a semiconductor device prepared by any of the aforementioned semiconductor device manufacturing methods.

[0018] In another aspect, the present invention provides an electronic device comprising the aforementioned semiconductor device.

[0019] The semiconductor device manufacturing method of the present invention bombards a first surface of a first substrate to deposit sputtered particles on a second surface of a second substrate to form a bonding layer. Then, the bonding layer is bonded to the bombarded first surface of the first substrate to form an insulating trap layer with the bonding layer and a portion of the thickness of the first substrate. This method achieves the direct formation of the insulating trap layer in the bonding process, reducing process complexity and cost. Attached Figure Description

[0020] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0021] In the attached image:

[0022] Figure 1 A schematic diagram of a semiconductor device obtained by first forming an insulating trap layer and then bonding it is shown in the related technology.

[0023] Figure 2 A flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown;

[0024] Figures 3A to 3C A schematic cross-sectional view of a semiconductor device substrate obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown.

[0025] Figure 4The image shows a TEM (Transmission Electron Microscope) section of a specific embodiment of the present invention after the layer to be bonded to the first surface of the first substrate after being bombarded.

[0026] Figure 5 A schematic diagram of an electronic device according to a specific embodiment of the present invention is shown. Detailed Implementation

[0027] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0028] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0029] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0030] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0032] To fully understand this invention, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0033] In related technologies, an insulating trap layer 102 is typically grown first on a high-resistivity silicon wafer 103 (e.g., through epitaxial growth, PECVD, sputtering, etc.), making the insulating trap layer 102 and the high-resistivity silicon wafer 103 a single unit. Then, the side of this unit with the insulating trap layer 102 is bonded to the structure wafer 101. The resulting semiconductor device is as follows: Figure 1 As shown.

[0034] However, in order to meet the bonding strength requirements, the insulating trap layer 102 grown on the high-resistivity silicon wafer 103 needs to be ground and polished to a high standard so that the roughness of the insulating trap layer 102 meets the bonding process requirements (typically the roughness of the insulating trap layer 102 is <0.5nm and TTV is <30um), which leads to a complex process and high cost.

[0035] Therefore, in view of the aforementioned technical problems, the present invention proposes a method for manufacturing a semiconductor device, such as... Figure 2 As shown, it includes:

[0036] Step S1: Provide a first substrate and a second substrate, wherein a first surface of the first substrate and a second surface of the second substrate are disposed opposite each other and there is a predetermined gap width between them;

[0037] Step S2: The first surface of the first substrate is bombarded so that the generated sputtered particles are deposited on the second surface of the second substrate to form a bonding layer.

[0038] Step S3: Bond the layer to be bonded to the first surface of the first substrate after it has been bombarded, so that the layer to be bonded and a portion of the thickness of the first substrate form an insulating trap layer.

[0039] The semiconductor device manufacturing method of the present invention bombards a first surface of a first substrate to deposit sputtered particles on a second surface of a second substrate to form a bonding layer. Then, the bonding layer is bonded to the bombarded first surface of the first substrate to form an insulating trap layer with the bonding layer and a portion of the thickness of the first substrate. This method achieves the direct formation of the insulating trap layer in the bonding process, reducing process complexity and cost.

[0040] Example 1

[0041] Below, for reference Figures 3A to 3C The method for manufacturing the semiconductor device of the present invention will be described in detail, wherein, Figures 3A to 3C A cross-sectional schematic diagram of an extended resistance test sample obtained by sequentially implementing a manufacturing method according to a specific embodiment of the present invention is shown.

[0042] For example, the method for manufacturing the semiconductor device of the present invention includes the following steps:

[0043] First, perform step one, as follows: Figure 3A As shown, a first substrate 210 and a second substrate 220 are provided, with a first surface 211 of the first substrate 210 and a second surface 221 of the second substrate 220 disposed opposite to each other and having a predetermined gap width between them.

[0044] The first substrate 210 and the second substrate 220 can be any suitable semiconductor substrate, such as a bulk silicon substrate. They can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), silicon on insulator (SSOI), silicon on insulator (S-SiGeOI), silicon on insulator (SiGeOI) and germanium on insulator (GeOI), or double-side polished wafers (DSP), or ceramic substrates such as alumina, quartz or glass substrates, etc.

[0045] In some embodiments, the first substrate 210 may be a high-resistivity silicon wafer, which is a silicon material with high resistivity. For example, in this embodiment, a high-resistivity silicon wafer with a resistivity greater than 5000 ohm·cm may be used.

[0046] In some embodiments, the second substrate 220 may be a structural wafer, which refers to a silicon wafer used to form a specific integrated circuit structure during semiconductor manufacturing.

[0047] It is understood that the first substrate 210 may have a first surface 211 and a second surface, with the first surface 211 being its upper surface and the second surface being its lower surface; the second substrate 220 may also have a first surface and a second surface 221, with the first surface being its upper surface and the second surface 221 being its lower surface.

[0048] In this embodiment, by arranging the first surface 211 of the first substrate 210 and the second surface 221 of the second substrate 220 opposite to each other with a predetermined gap width, it can be ensured that sputtered particles generated when the first surface 211 of the first substrate 210 is bombarded in subsequent steps can be deposited on the second surface 221 of the second substrate 220. The first substrate 210 and the second substrate 220 can be arranged vertically opposite each other, or in other suitable ways; this is not limited. The predetermined gap width between the first surface 211 of the first substrate 210 and the second surface 221 of the second substrate 220 can be set according to actual conditions and is also not limited.

[0049] In one specific embodiment, the first substrate 210 can be placed on the lower layer of the wafer basket, and the second substrate 220 can be placed on the upper layer of the wafer basket. Then, the wafer basket is fed into the machine, so that the first substrate 210 is located on the loading stage of the machine, and the second substrate 220 is located on the loading stage of the machine. The loading stage can adsorb and fix the first substrate 210 on it by electrostatic adsorption or vacuum adsorption. Based on a similar principle, the loading stage can adsorb and fix the second substrate 220 on it by electrostatic adsorption or vacuum adsorption. Thus, the second substrate 220 is located above the first substrate 210, and the lower surface of the second substrate 220 is opposite to the upper surface of the first substrate 210.

[0050] Next, proceed to step two, as follows: Figure 3B As shown, the first surface 211 of the first substrate 210 is bombarded so that the sputtered particles generated are deposited on the second surface 221 of the second substrate 220 to form the bonding layer 230.

[0051] Specifically, the second substrate 220 is located above the first substrate 210. When the first surface 211 of the first substrate 210 is bombarded, the particles generated by the bombardment are sputtered upwards, thereby depositing on the second surface 221 of the second substrate 220 and forming the bonding layer 230.

[0052] In one specific embodiment, after the first substrate 210 and the second substrate 220 are respectively adsorbed onto the loading platform and the loading platform of the machine, the ion gun can be activated to bombard the first surface 211 of the first substrate 210 with ions emitted by the ion gun. The first substrate 210, as a sputtering target, generates sputtered particles under the bombardment of ions. The generated sputtered particles are deposited upward on the second surface 221 of the second substrate 220 to form the bonding layer 230.

[0053] In some embodiments, the bonding layer 230 deposited on the second surface 221 of the second substrate 220 is a disordered silicon layer. The disordered silicon layer is α-silicon characterized by short-range order and long-range disorder. Compared to crystalline silicon, it does not have a complete diamond unit cell structure, therefore its melting point, density, and hardness are significantly lower than crystalline silicon. Because disordered silicon contains many so-called "dangling bonds"—electrons that are not bonded to surrounding silicon atoms—these electrons can generate current under an electric field, making disordered silicon a direct bandgap semiconductor with the advantage of low manufacturing cost.

[0054] Next, proceed to step three, as follows: Figure 3C As shown, the bonding layer 230 is bonded to the first surface 211 of the first substrate 210 after being bombarded, so that the bonding layer 230 and the first substrate 210 of a certain thickness form an insulating trap layer 240.

[0055] Since the bonding layer 230 is formed by sputtering particles generated from the first substrate 210, the surface of the bonding layer 230 is made of the same material as the first surface 211 of the first substrate 210 after being bombarded. Because the surface of the bonding layer 230 and the first surface 211 of the first substrate 210 after being bombarded are made of the same material, when bonding the bonding layer 230 to the first surface 211 of the first substrate 210 after being bombarded, only a small amount of pressure is needed to achieve the bonding, which can greatly reduce the bonding difficulty.

[0056] Taking a first substrate 210 as a high-resistivity silicon wafer and a second substrate 220 as a structural wafer as an example, both the first surface 211 of the first substrate 210 after being bombarded and the surface of the bonding layer 230 are silicon surfaces (preferably, the surface of the bonding layer 230 is a disordered silicon surface). When bonding the bonding layer 230 to be bonded to the first surface 211 of the first substrate 210 after being bombarded using a bonding process, silicon-silicon bonding can be achieved, thereby reducing the bonding difficulty. Of course, this application does not limit the surface of the bonding layer 230 to be bonded and the first surface 211 of the first substrate 210 after being bombarded to other surfaces of the same material. For example, when the first substrate 210 is an aluminum nitride wafer, both the surface of the bonding layer 230 to be bonded and the first surface 211 of the first substrate 210 after being bombarded can be made of aluminum nitride.

[0057] In one specific embodiment, a machine can be used to press the first substrate 210 and the second substrate 220 together to bond the bonding layer 230 to the first surface 211 of the first substrate 210 after it has been bombarded. The applied pressing force is between 10 kN and 100 kN. Under the action of the pressing force, silicon-silicon bonding can be achieved between the bonding layer 230 and the first surface 211 of the first substrate 210 after it has been bombarded. Figure 4 As shown, after the high-resistivity silicon wafer and the structure wafer are laminated, a bonding interface is formed between the bonding layer on the structure wafer and the upper surface of the high-resistivity silicon wafer. The bonding layer on the structure wafer and the upper surface of the high-resistivity silicon wafer achieve silicon-silicon bonding, and the resulting insulating trap layer is about 5nm thick.

[0058] After the bonding layer 230 is bonded to the first surface 211 of the first substrate 210 after being bombarded, the bonding layer 230 and the first substrate 210 of a certain thickness can directly form an insulating trap layer 240. Compared with the related technology of forming the insulating trap layer 240 first and then bonding, this embodiment forms the insulating trap layer 240 directly in the bonding process. It is not necessary to grow the insulating trap layer 240 on the first substrate 210 first through epitaxial process, PECVD process, sputtering process or other growth processes, nor is it necessary to perform high-specification grinding and polishing on the insulating trap layer 240, thereby reducing the process complexity and cost.

[0059] Generally speaking, the manufacturing method of the semiconductor device using this embodiment reduces the cost from 1000-1200 yuan to 300-350 yuan compared to the related art method of first forming the insulating trap layer 240 and then bonding. Moreover, after testing and verification, the performance of the semiconductor device obtained by the manufacturing method of this embodiment is completely matched with the performance of the semiconductor device obtained by the related art method of first forming the insulating trap layer 240 and then bonding, and the quality factor can reach 3000-4000.

[0060] It is worth mentioning that the order of the above steps is only for example. Without conflict, the order of the above steps can be changed or performed alternately.

[0061] This concludes the introduction of the key manufacturing method of the semiconductor device of the present invention. Other preliminary, intermediate or subsequent steps are required for the complete fabrication of the device, which will not be elaborated here.

[0062] In summary, the semiconductor device manufacturing method of the present invention bombards the first surface of a first substrate to deposit sputtered particles on the second surface of a second substrate to form a bonding layer, and then bonds the bonding layer to the bombarded first surface of the first substrate to form an insulating trap layer with the bonding layer and a portion of the thickness of the first substrate. This method achieves the direct formation of an insulating trap layer in the bonding process, reducing process complexity and cost.

[0063] Example 2

[0064] The present invention also provides a semiconductor device that can be prepared by the method described in the first embodiment above.

[0065] Below, for reference Figure 3C The semiconductor device of the present invention will be described in detail. It is worth mentioning that, in order to avoid repetition, only a brief description will be given for the same components and structures as in the foregoing Embodiment 1. For specific explanations and descriptions, please refer to the description in Embodiment 1.

[0066] Specifically, such as Figure 3C As shown, the semiconductor device of the present invention includes a first substrate and a second substrate. A bonding layer is formed on the second surface of the second substrate. A partial thickness of the first substrate and the bonding layer are bonded to form an insulating trap layer. The bonding layer is formed by sputtering particles generated by bombarding the first surface of the first substrate and depositing them on the second surface of the second substrate.

[0067] In some embodiments, the first substrate includes a high-resistivity silicon wafer.

[0068] In some embodiments, the resistivity of the high-resistivity silicon wafer is greater than 5000 ohm·cm.

[0069] In some embodiments, the second substrate includes a structure wafer.

[0070] The semiconductor device according to the present invention is prepared by means of the method in Example 1. By bombarding the first surface of the first substrate, the generated sputtered particles are deposited on the second surface of the second substrate to form a bonding layer. Then the bonding layer is bonded to the first surface of the first substrate after being bombarded, so that the bonding layer and a portion of the thickness of the first substrate form an insulating trap layer. This realizes the direct formation of the insulating trap layer in the bonding process, reducing the process complexity and cost.

[0071] Example 3

[0072] In another embodiment of the present invention, an electronic device is also provided, including the aforementioned semiconductor device, which is prepared according to the aforementioned method.

[0073] The electronic device in this embodiment can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD player, DVD player, navigator, digital photo frame, camera, camcorder, voice recorder, MP3 player, MP4 player, PSP, etc., or any intermediate product including circuitry. The electronic device in this embodiment of the invention, due to the use of the aforementioned semiconductor devices, has better performance.

[0074] in, Figure 5 An example of a mobile phone is shown. The mobile phone 400 is provided with a display 402, operation buttons 403, an external connection port 404, a speaker 405, a microphone 406, etc., included in a housing 401.

[0075] The mobile phone includes the semiconductor device described in Embodiment 2. For a description of the semiconductor device, please refer to the description in Embodiment 2, which will not be repeated here.

[0076] The present invention has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, those skilled in the art will understand that the present invention is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of the present invention, all of which fall within the scope of protection claimed by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The manufacturing method includes: A first substrate and a second substrate are provided, wherein a first surface of the first substrate and a second surface of the second substrate are disposed opposite to each other and a predetermined gap width is provided between them; The first surface of the first substrate is bombarded so that the resulting sputtered particles are deposited on the second surface of the second substrate to form a bonding layer. The layer to be bonded is bonded to the first surface of the first substrate after it has been bombarded, so that the layer to be bonded and a portion of the thickness of the first substrate form an insulating trap layer.

2. The manufacturing method as described in claim 1, characterized in that, The first substrate includes a high-resistivity silicon wafer.

3. The manufacturing method as described in claim 2, characterized in that, The resistivity of the high-resistivity silicon wafer is greater than 5000 ohm·cm.

4. The manufacturing method as described in claim 1, characterized in that, The second substrate includes a structure wafer.

5. The manufacturing method as described in claim 1, characterized in that, The first surface of the first substrate after being bombarded is made of the same material as the surface of the layer to be bonded.

6. The manufacturing method as described in claim 1, characterized in that, The layer to be bonded is a disordered silicon layer.

7. The manufacturing method as described in claim 1, characterized in that, The bombardment is an ion bombardment with the first substrate as the sputtering target.

8. A semiconductor device, characterized in that, Prepared by the manufacturing method of any one of claims 1 to 7.

9. An electronic device, characterized in that, The electronic device includes the semiconductor device as described in claim 8.

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