Chip suction method

Abstract

The embodiment of the invention discloses a chip suction method, which comprises the following steps of: identifying chips in a plurality of rows which are arranged at intervals as first chips and third chips, enabling the first chips and the third chips in the same row to be alternately arranged, and enabling an interval row to be arranged between every two adjacent rows; the chips in the interval rows are identified as second chips and third chips, and the second chips and the third chips in each interval row are arranged alternately; the interlaced suction path sequentially sucks a plurality of first chips and a plurality of second chips. During identification, the first chips and the third chips are alternately arranged, the second chips and the third chips are alternately arranged, and the rows where the first chips are located are arranged at intervals of one row, so that the surrounding environment of the to-be-sucked chips has high symmetry in the process of sucking the chips, stress is uniform during sucking, and the quality and reliability of the chips are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor chip technology, and more specifically to a chip picking method. Background Technology

[0002] In semiconductor chip packaging, after the wafer is diced into individual chips, each chip remains attached to an adhesive film of similar size to the wafer. A chip pick-up device is needed to pick up each chip from the film. Current technology involves using ejector pins to initially separate the chip's sides from the adhesive film, followed by pick-up from the chip by a pick-up head. This process is repeated sequentially for multiple chips. Therefore, for each chip to be picked up, one side has already been picked up while the other side remains unpicked. Due to the inconsistent surrounding environment of the chip, the force exerted by the ejector pins on both sides of the chip is also inconsistent when it is lifted, resulting in uneven stress during pick-up. This uneven stress can easily cause cracks or microcracks, leading to chip failure. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide a chip picking method that ensures that the surrounding environment of the chip to be picked up is highly symmetrical during the chip picking process, and that the force is uniform during picking up, thereby improving the chip quality and reliability.

[0004] This invention provides a chip picking method, comprising: The chips in multiple spaced rows in the chip array are identified as first chips and third chips, wherein the first chips and the third chips in the same row are arranged alternately, and there is a spaced row between two adjacent rows containing the first chips. The chips within a row of the multiple spaced rows in the chip array are identified as the second chip and the third chip, wherein the second chip and the third chip are arranged alternately within each spaced row; Multiple first chips and multiple second chips are sequentially picked up along the interlaced picking path.

[0005] Optionally, the chip picking method further includes: It is confirmed that the top, bottom, left, and right directions of each first chip located in the inner region of the chip array are all the third chip, and the top, bottom, left, and right directions of each second chip located in the inner region of the chip array are all the third chip, and it is confirmed that the first chip or the second chip located in the edge region of the chip array is missing at least one adjacent third chip in the direction of the array boundary.

[0006] Optionally, sequentially picking up multiple first chips and multiple second chips along the interlaced picking path includes: Multiple first chips are sequentially extracted along the first path; Multiple second chips are sequentially extracted along the second path.

[0007] Optionally, the first path and the second path are S-shaped paths.

[0008] Optionally, the chip picking method further includes: confirming that there are no chips in the four directions of the top, bottom, left, and right of each of the third chips located in the internal region of the chip array.

[0009] Optionally, the chip picking method further includes: Multiple third chips are sequentially picked up along a third path, which is a path formed by sequentially picking up chips along each row.

[0010] Optionally, the third path is an S-shaped path.

[0011] Optionally, the S-shaped path is a path that moves along the row direction to the end of the row, then turns to the next row to be processed and moves in the opposite direction along the row direction until it covers the entire chip array.

[0012] Optionally, identifying chips within a plurality of spaced rows in the chip array as the first chip and the third chip, and identifying chips within a plurality of spaced rows in the chip array as the second chip and the third chip, includes: The chips arranged alternately in each odd-numbered row of the chip array are identified as the first chip and the third chip; The chips alternately arranged in each even-numbered row of the chip array are identified as the second chip and the third chip. It is confirmed that the top, bottom, left and right directions of each first chip located in the inner region of the chip array are the third chip. It is also confirmed that the top, bottom, left and right directions of each second chip located in the inner region of the chip array are the third chip. It is confirmed that the first chip or the second chip located in the edge region of the chip array is missing at least one adjacent third chip in the direction of the array boundary.

[0013] Optionally, the chip picking method further includes: It was confirmed that there were no chips in the four directions of the top, bottom, left, and right of each of the third chips located in the internal region of the chip array.

[0014] Optionally, the chip picking method further includes: The quality of the first chip, the second chip, and the third chip is tested to determine whether they are up to standard.

[0015] This invention provides a chip picking method, comprising: identifying chips in multiple spaced rows as first chips and third chips, arranging the first and third chips in the same row alternately, with an interval row between adjacent rows; identifying chips in the interval rows as second chips and third chips, arranging the second and third chips in each interval row alternately; and sequentially picking up multiple first chips and multiple second chips via an alternating picking path. By alternating the arrangement of first and third chips, and second and third chips during identification, and by setting an interval row between rows containing first chips, the surrounding environment of the chip to be picked up is highly symmetrical during the picking process, resulting in uniform force during picking and improving chip quality and reliability. Attached Figure Description

[0016] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which: Figure 1 This is a schematic diagram of the chip state extracted from existing technology; Figure 2 This is a schematic diagram of a chip array during chip extraction in existing technology; Figure 3 This is a schematic diagram of the environment surrounding the chip being absorbed in existing technology; Figure 4 This is a schematic diagram of the top mark on the adhesive film in the prior art; Figure 5 This is a schematic flowchart of a chip picking method according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the first chip and the first path according to an embodiment of the present invention; Figure 7 This is a schematic diagram of the environment surrounding the first chip to be absorbed according to an embodiment of the present invention; Figure 8 This is a schematic diagram of the second chip and the second path according to an embodiment of the present invention; Figure 9 This is a schematic diagram of the environment surrounding the second chip to be absorbed according to an embodiment of the present invention; Figure 10 This is a schematic diagram of the third chip and the third path according to an embodiment of the present invention; Figure 11 This is a schematic diagram of the environment surrounding the third chip to be absorbed according to an embodiment of the present invention.

[0017] Explanation of reference numerals in the attached figures: 1-First chip; 2-Second chip; 3-Third chip; 4-Wafer; 5-Film; 6-Stage; 61-Through hole; 62-Mold with hole; 71-Base; 72-Receiving groove; 73-Support; 74-Ejector pin; 8-Pick-up device; R1-First path; R2-Second path; R3-Third path. Detailed Implementation

[0018] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0019] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0020] Unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0021] For ease of explanation, spatially related terms such as “inside,” “outside,” “below,” “below,” “lower,” “above,” “upper,” etc., are used herein to describe the relationship between one element or feature illustrated in the figure and another. It will be understood that spatially related terms may be intended to encompass different orientations of the device in use or operation besides those depicted in the figure. For example, if the device in the figure is flipped, an element described as “below” or “below” another element or feature would then be positioned “above” that other element or feature. Thus, the exemplified term “below” can encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptive terms used herein should be interpreted accordingly.

[0022] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0023] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0024] Before wafers are diced into chips, a film typically remains on the bottom of the wafer for fixation and support; the film's size is roughly the same as the wafer's dimensions. After dicing, each chip remains attached to the film. During the Die to Reel (DTR) process, the diced chips are separated from the film, picked up, and moved into the carrier tape to provide raw material chips for subsequent processes.

[0025] Figure 1 This diagram illustrates the process of separating and picking up the chip from the adhesive film 5 in the DTR process. Only the portion of the chip removal device corresponding to the chip to be picked up is shown in the diagram. (Refer to...) Figure 1 The wafer 4 to be processed is placed on the stage 6, and the adhesive film 5 contacts the stage 6. A chip demolding device is used to lift the chip. Specifically, a through hole 61 is provided on the stage 6 corresponding to each chip position, and the chip demolding device is located below the stage 6. The chip demolding device includes a base 71, a support 73, and ejector pins 74. The base 71 has a receiving groove 72. The support 73 can move up and down and is installed in the receiving groove 72. The ejector pins 74 are connected to the top of the support 73 and can be driven by the support 73 to pass through the through hole 61 to lift the chip at the corresponding position. Depending on the actual situation, the number of ejector pins 74 is set according to the size and shape of the chip. For example, rectangular chips often use two or more ejector pins 74, while square chips may use a single ejector pin 74. Similarly, the number, size, and position of the through holes 61 also correspond to the setting of the ejector pins 74. To further guide the ejector pin 74, a perforated mold 62 is usually provided below the stage 6. When the ejector pin 74 moves upward, it passes through the mold and the through hole 61.

[0026] Reference Figure 1 When the ejector pin 74 lifts the chip, its tip contacts the adhesive film 5 and further pushes the chip upward, allowing it to be picked up by the pick-up device 8. Since the adhesive film 5 remains intact after wafer 4 is diced, when the ejector pin 74 lifts the chip to be picked up, the chips around it are also pulled up by the adhesive film 5. Specifically, when a chip needs to be picked up, the support 73 corresponding to the chip to be picked up is moved upward in a controlled manner, allowing the ejector pin 74 to pass through the through hole 61 and the mold, contact the adhesive film 5, and continue to lift it. At this time, the portion of the adhesive film 5 lifted by the ejector pin 74 protrudes above the portion that was not lifted. Due to the rigidity of the chip, the chip will not protrude, and the adhesive film 5 at the chip edge will separate from the chip. At this point, the chip to be picked up is positioned higher than other chips and partially separated from the adhesive film 5, making it easier for the pick-up device 8 to pick it up.

[0027] The commonly used chip picking method in the current technology is to pick up the chips one by one row at a time. Figure 2 A schematic diagram of the chip being picked up one by one in the prior art is given, where blue chips represent chips that have not been picked up, and white chips represent chips that have been picked up. Figure 2 As shown in the suction path, the suction device 8 starts from the first row on one side of wafer 4 and suctions sequentially from right to left. Then the second row is suctioned sequentially from left to right, then the third row is suctioned sequentially from right to left, and so on. The above steps are repeated for each row until all chips on the entire wafer 4 have been suctioned.

[0028] like Figure 3 As shown, in the prior art, for the chips being picked up, the chips on the left and top sides of the adhesive film 5 have been completely picked up, while the chips on the right and bottom sides remain on the adhesive film 5. The side of the adhesive film 5 still with chips attached is heavier. Furthermore, due to the rigidity of the chips themselves, the adhesive film 5 on the side still with chips is pulled up over a larger area, resulting in different pulling forces on both sides of the adhesive film 5 in the vertical direction and the horizontal direction. Therefore, the side with chips attached exerts additional pressure on the ejector pin 74.

[0029] Reference Figure 1 Taking a chip demolding device with double ejector pins 74 as an example, when the chip is lifted by the double ejector pins 74, in the left and right direction, the side of the film 5 still attached to the chip exerts greater pressure on the right ejector pin 74, making the pushing force of the right ejector pin 74 on the chip greater than the pushing force of the left ejector pin 74 on the chip. Figure 4 The diagram illustrates the top marks left on the adhesive film 5 when a chip is picked up using existing methods. Only the top mark corresponding to a single chip is shown. It is evident that the right-side ejector pin 74 leaves a deeper top mark on the adhesive film 5, resulting in greater force on the chip on the right side. Due to this uneven force, the chip is prone to cracking or developing hidden marks, affecting product quality and causing economic losses.

[0030] Reference Figure 5 This invention discloses a chip picking method, in which chips on wafer 4 are divided into first chip 1, second chip 2 and third chip 3 according to the picking order, and first path R1, second path R2 and third path R3 are set respectively. Picking device 8 picks up chips along different paths, so that each chip located inside the chip array has the same environment and high symmetry around it when it is picked up, and the force is uniform during picking up, thereby improving chip quality and reliability.

[0031] Reference Figure 5 The chip picking method of this invention includes the following steps: Step S1: Identify the chips in multiple spaced rows in the chip array as the first chip 1 and the third chip 3.

[0032] Specifically, to achieve rapid and efficient chip pick-up, wafer 4 is placed on stage 6, with the adhesive film 5 in contact with stage 6, at which point the chip array and support 73 array correspond one-to-one. The chip array on wafer 4 is divided into rows and columns, with one row designated as the row containing the first chip 1. Typically, the first row is selected as the row containing the first chip 1. For the row containing the first chip 1, the chips within the row are identified as first chip 1 and third chip 3, respectively. Within the same row, first chip 1 and third chip 3 are alternately arranged. For the entire chip array, there is a gap row between any two adjacent rows containing first chip 1; the gap row is the row that does not contain first chip 1. In other words, rows containing first chip 1 are spaced apart on the chip array. For example, if the first row contains first chip 1, then the third row also contains first chip 1, the second row does not contain first chip 1, and so on, with odd-numbered rows containing first chip 1 and even-numbered rows not containing first chip 1.

[0033] It should be understood that the above is merely an example and is not intended to be limiting. Rows containing the first chip 1 can also be even-numbered rows, and rows not containing the first chip 1 can also be odd-numbered rows or multiple rows. Depending on the actual situation, the chips alternating in each odd-numbered row of the chip array are usually identified as the first chip 1 and the third chip 3.

[0034] Furthermore, referring to Figure 6 Blue chips represent other chips not identified as first chip 1, and white chips represent chips identified as first chip 1. In the first row, the first chips 1 are spaced apart. The adjacent row containing first chips 1 is the third row. When it is necessary to pick up all the first chips 1 on wafer 4, in a preferred embodiment, the chips identified as first chips 1 in the third row are kept in the same column as the first chips 1 in the first row. That is, for each row containing first chips 1, each first chip 1 within that row is spaced apart by one chip; for each column containing first chips 1, each first chip 1 within that column is also spaced apart by one chip.

[0035] Reference Figure 7 After the identification of the first chip 1 is completed, for each chip not located on the edge of the chip array, each first chip 1 has chips other than the first chip 1 in its four directions (up, down, left, and right). It can be seen that the environment around the first chip 1 is highly symmetrical and consistent at this time. That is to say, when the first chip 1 needs to be picked up subsequently, the environment around the first chip 1 to be picked up, located within the chip array, is highly symmetrical and consistent.

[0036] Step S2: Identify the chips within the rows of multiple spaced rows in the chip array as the second chip 2 and the third chip 3.

[0037] Reference Figure 8 The chips within each interleaved row are identified as second chip 2 and third chip 3, respectively. The second chip 2 and third chip 3 are alternately arranged in each interleaved row. In this embodiment, the interleaved rows are even-numbered rows. It should be understood that this embodiment is merely an example and not a limitation; the interleaved rows can also be odd-numbered rows or multiple rows. Depending on the actual situation, the chips alternately arranged in each even-numbered row of the chip array are typically identified as second chip 2 and third chip 3.

[0038] Furthermore, such as Figure 8 As shown, blue chips represent other chips not identified as either chip 1 or chip 2, white chips represent chips identified as chip 1, and yellow chips represent chips identified as chip 2. In the second row, the chip 2 chips are spaced apart. The adjacent row containing chip 2 chips is the fourth row, and the chips identified as chip 2 chips in the fourth row are in the same column as those in the second row. That is, for each row containing chip 2 chips, there is a gap of one chip between each chip 2 chip within that row; similarly, for each column containing chip 2 chips, there is a gap of one chip between each chip 2 chip within that column.

[0039] At the same time, such as Figure 8 As shown, for two adjacent rows, namely rows containing the first chip 1 and the second chip 2 respectively, the positions of the first chip 1 and the second chip 2 are staggered. At this time, the blue chips are arranged in an alternating pattern both horizontally and vertically.

[0040] Reference Figure 9 After the identification of the second chip 2 is completed, for each chip not located on the array boundary, each second chip 2 has blue chips in its four directions (up, down, left, and right), i.e., chips that are neither the first chip 1 nor the second chip 2. It can be seen that the environment around the second chip 2 is highly symmetrical and consistent at this time. That is to say, when the second chip 2 needs to be picked up subsequently, since the chips that are neither the first chip 1 nor the second chip 2 have not yet been picked up, the environment around the second chip 2 to be picked up in the inner region of the chip array is highly symmetrical and consistent. In fact, Figure 8 and Figure 9 The position of the blue chip in the diagram corresponds to the position of the third chip (3). Since the third chip (3) is a chip that is not the first chip (1) in odd-numbered rows and not the second chip (2) in even-numbered rows, therefore, referring to... Figure 10 The green chip is the third chip, number 3. The green chips are arranged in an alternating pattern both horizontally and vertically.

[0041] For each chip located within the chip array, each third chip 3 has a first chip 1 or a second chip 2 positioned in its four directions (up, down, left, and right). (Refer to...) Figure 11 Taking the third chip 3, which is adjacent to the first chip 1 above and below and to the second chip 2 on the left and right, as an example, since the first chip 1 and the second chip 2 have already been absorbed before the third chip 3 is absorbed, there are actually no chips above, below, to the left and right of the third chip 3 when it is absorbed. It can be seen that the environment around the third chip 3 is highly symmetrical and consistent at this time.

[0042] It should be understood that this embodiment is only an example, and the order of identifying the first chip 1 and the second chip 2 can be either identifying the first chip 1 first and then identifying the second chip 2, or identifying the second chip 2 first and then identifying the first chip 1.

[0043] Step S3: Confirm that each first chip 1 located in the inner region of the chip array has a third chip 3 in the four directions of top, bottom, left, and right; confirm that each second chip 2 located in the inner region of the chip array has a third chip 3 in the four directions of top, bottom, left, and right; confirm that the first chip 1 or second chip 2 located in the edge region of the chip array is missing at least one adjacent third chip 3 in the direction of the array boundary.

[0044] Reference Figure 10 After identifying the first chip 1, the second chip 2, and the third chip 3, for each first chip 1 (white chip) located inside the chip array, its four directions (up, down, left, and right) are all third chip 3 (green chip); for each second chip 2 (yellow chip) located inside the chip array, its four directions (up, down, left, and right) are all third chip 3 (green chip); for each third chip 3 (green chip) located inside the chip array, its four directions (up, down, left, and right) are either first chip 1 or second chip 2. For first chip 1 or second chip 2 located at the edge of the chip array, it is often missing at least one adjacent third chip 3 in the direction of the array boundary.

[0045] In other words, such as Figure 10 As shown, regardless of whether the first chip 1 or the second chip 2 is identified first, after all chips have been identified, each first chip 1 located within the chip array has a highly symmetrical and consistent environment, and all surrounding chips are third chips 3. When picking up a first chip 1 individually, there will only be one possibility: all chips will be picked up or none will be picked up. Similarly, each second chip 2 located within the chip array has a highly symmetrical and consistent environment, and all surrounding chips are third chips 3. When picking up a second chip 2 individually, there will only be one possibility: all chips will be picked up or none will be picked up. Therefore, the order in which the first chip 1 and the second chip 2 are identified and picked up does not affect the environment surrounding any chip to be picked up within the chip array.

[0046] Meanwhile, for chips located at the edge of the chip array, when the first chip 1 or the second chip 2 is picked up first, before the third chip 3 is picked up, the environment around the first chip 1 or the second chip 2 at the edge of the chip array is inconsistent. It lacks at least one adjacent third chip 3 in the array boundary direction, but is adjacent to the third chip 3 in the array interior direction. Conversely, when the third chip 3 is picked up first, the environment around the third chip 3 at the edge of the chip array is inconsistent. It lacks an adjacent first chip 1 or the second chip 2 in the array boundary direction, but is adjacent to the first chip 1 or the second chip 2 in the array interior direction. In other words, by sacrificing chips located at the edge of the chip array, the quality and reliability of chips inside the chip array are improved.

[0047] For the extraction of the first chip 1 and the second chip 2, since each type of chip is set in a row apart when extracted individually, it is necessary to extract multiple first chips 1 and multiple second chips 2 sequentially along the alternating row extraction path.

[0048] Step S4: Sequentially pick up multiple first chips 1 along the first path R1.

[0049] Specifically, a first path R1 is formed based on the location of the first chip 1, ensuring that each first chip 1 can be picked up, and minimizing the path traveled by the picking device 8. When picking up along the first path R1, multiple first chips 1 need to be picked up sequentially for each row; for different rows, picking up is performed every other row. For each path, the picking device 8 starts picking up the chip at the starting point. Typically, the starting point is located at the outermost chip in the first row. Figure 6 As shown, for the first path R1 of the first chip 1, the starting point can be located at the rightmost chip in the first row. At this time, the chip is exactly the first chip 1, so it can be used as the starting point of the first path R1. It should be understood that this embodiment is only an example and is not a limitation. The starting point can actually be chosen as any position in any row, such as the leftmost or rightmost first chip 1 in the last row.

[0050] Furthermore, since the starting point of the first path R1 in this embodiment is located at the rightmost side of the first row, the picking device 8 will move to the left in order to pick up all the first chips 1 in this row. This facilitates picking up the first chips 1 sequentially row by row. After picking up the first row, the picking device 8 moves to the next row containing the first chips 1, which is the third row, and picks up from left to right. Depending on the actual situation, a column-by-column picking method can also be selected.

[0051] Specifically, refer to Figure 6A Cartesian coordinate system is established with the direction of movement of the picking device 8 when continuously picking up chips in a row or column as the positive x-axis, and the direction of movement of the picking device 8 to the next row or column before the next continuous chip picking as the positive y-axis. In this embodiment, the x-axis direction is used as the row and the y-axis direction is used as the column.

[0052] Reference Figure 1 , Figure 6 When picking up the first chip 1, the support 73 corresponding to the starting point of the first chip 1 is moved upward in a controlled manner, driving the ejector pin 74 upward, so that the first chip 1 is partially separated from the adhesive film 5, making it easier for the picking device 8 to pick it up. After picking up the chip at the starting point, the next first chip 1 is picked up. The support 73 corresponding to the next first chip 1 in the same row moves upward, driving the ejector pin 74 to lift the first chip 1. The picking device 8 moves along the positive x-axis to the corresponding position to pick up the chip. The above operation is repeated until the first chip 1 in this row has been picked up.

[0053] like Figure 6 As shown, the pick-up device 8 moves in the positive y-axis direction, skipping the chips in the second row, and begins picking up the first chip 1 from the third row, which is the second row containing the first chip 1. At this time, the pick-up device 8 is located at the leftmost position of the first chip 1 in the third row. Since the wafer 4 has a circular structure, the distance of movement along the x-axis can be adjusted according to the chord length of the adjacent rows. For example, if the next row has a longer chord length, the device moves a portion more along the x-axis before moving in the y-axis direction; or if the next row has a shorter chord length, after completing the movement in the y-axis direction, the device moves a further distance along the x-axis direction to align with the remaining rows. This process continues until the first chip 1 is picked up. Figure 6 The diagram shows the final first path R1. When the nozzle device picks up chips one by one, it moves along the row direction to the end of the row, then turns to the next row and moves in the opposite direction along the row direction until it covers the entire chip array, i.e., the S-shaped path.

[0054] For the first chip 1 located inside the chip array, its surrounding chip environment is the same, such as... Figure 7 As shown, there are uncollected chips in all directions. In other words, when the chip is collected, the tension in all directions is almost the same, and the lifted film 5 and chip will not tilt significantly. This avoids the problem of uneven force on the chip and cracking caused by different ejector pins 74 on the same support 73 exerting different pushing forces on the film 5.

[0055] It should be understood that this embodiment is merely an example. The order in which the first chip 1, the second chip 2, and the third chip 3 are absorbed can be as follows: absorb the first chip 1 first, then absorb the second chip 2, and then absorb the third chip 3; absorb the second chip 2 first, then absorb the first chip 1, and then absorb the third chip 3; absorb the third chip 3 first, then absorb the second chip 2, and then absorb the first chip 1; or absorb the third chip 3 first, then absorb the first chip 1, and then absorb the second chip 2. In other words, the absorption of the third chip 3 should be performed after the first chip 1 and the second chip 2 have been absorbed or before either has been absorbed. The absorption order of the first chip 1 and the second chip 2 can be interchanged to ensure that each chip located inside the chip array has a highly symmetrical and consistent surrounding environment during absorption, and that the force applied during absorption is uniform.

[0056] Step S5: Sequentially pick up multiple second chips 2 along the second path R2.

[0057] Specifically, a second path R2 is formed based on the location of the second chip 2, ensuring that each second chip 2 can be picked up, and minimizing the path traveled by the picking device 8. When picking up along the second path R2, multiple second chips 2 need to be picked up sequentially for each row; for different rows, picking up should be done every other row. Figure 8 As shown, for the second path R2 of the second chip 2, the starting point is located at the rightmost chip in the second row. At this time, the rightmost chip is not the second chip 2; the second-to-last chip adjacent to it is the second chip 2. Using this second chip 2 as the starting point of the second path R2, the second chips 2 are picked up one by one in the same way as the first chip 1. Depending on the actual situation, the path for picking up the second chip 2 may be the same as the path for picking up the first chip 1, or it may be perpendicular to it. Similarly, it should be understood that this embodiment is only an example and is not limiting; the starting point can actually be any position in any row, such as the leftmost or rightmost second chip 2 in the last row, etc. Figure 8 A schematic diagram of the final formed second path R2 is shown, which is an S-shaped path.

[0058] For a chip located inside a chip array, the surrounding chip environment is the same, such as... Figure 9 As shown, for the second chip 2 to be picked up, there are unpicked chips on all four sides. That is to say, when the chip is picked up, the tension it experiences in all directions is almost the same, avoiding the problem of uneven stress on the chip and cracking caused by different ejector pins 74 on the adhesive film 5 under the same support 73.

[0059] Step S6: Confirm that there are no chips in the four directions of the top, bottom, left and right of each third chip 3 located in the inner area of ​​the chip array.

[0060] Specifically, refer to Figure 10 After the first chip 1 and the second chip 2 are absorbed, only the third chip 3 remains on the wafer 4. For each third chip 3 located in the inner region of the chip array, there are no chips around it. That is to say, each third chip 3 has a highly symmetrical and consistent surrounding environment, and the force is uniform during absorption.

[0061] According to the actual situation, in another embodiment, when the third chip 3 is first absorbed, since the first chip 1 and the second chip 2 have not yet been absorbed, the third chip 3 located in the inner region of the chip array is surrounded by chips. That is to say, each third chip 3 still has a highly symmetrical and consistent surrounding environment, and the force is uniform when it is absorbed.

[0062] Step S7: Sequentially pick up multiple third chips 3 along the third path R3.

[0063] Specifically, a third path R3 is formed based on the location of the third chip 3, ensuring that each third chip 3 can be picked up, and minimizing the path traveled by the picking device 8. The third chips 3 are interspersed in each row of the chip array; therefore, the third path R3 is formed by sequentially picking up chips along each row. Figure 10 As shown, for the third path R3 of the third chip 3, the starting point is located at the rightmost chip in the first row. Since the first chip 1 and the second chip 2 have already been acquired in the previous steps, Figure 10 The white and yellow chips in the image are no longer present; therefore, the rightmost chip in the first row must be the third chip 3. Using this chip as the starting point for the third path R3, the third chips 3 are extracted one by one in the same manner as the first chip 1. Similarly, it should be understood that this embodiment is merely an example and is not intended to limit the process. The starting point can actually be any position in any row, such as the leftmost or rightmost third chip 3 in the last row.

[0064] Since the third chip 3 is distributed in each row, the distribution of the third path R3 is different from that of the first path R1 and the second path R2. After the first row is picked up, the picking device 8 moves to the next row containing the third chip 3, which is the second row, and picks up from left to right. At this time, the length of movement of the picking device 8 on the y-axis is shorter, forming a shape as shown in the image. Figure 10 The third path R3 is shown. The third path R3 forms an S-shaped path.

[0065] For a chip located inside a chip array, the surrounding chip environment is the same, such as... Figure 11As shown, for the third chip 3 to be picked up, its up, down, left and right positions correspond to the first chip 1 and the second chip 2 that were picked up in the aforementioned steps. That is to say, there are no chips around each third chip 3. When the chip is picked up, the pulling force in each direction is almost the same, which avoids the problem of uneven force on the chip and cracking caused by different ejector pins 74 on the adhesive film 5 of the same support 73.

[0066] Reference Figure 10 Because chips located at the array edge are missing in the direction of the array boundary, and because the first chip 1 and the second chip 2 require chips on all four sides to ensure a highly symmetrical and consistent surrounding environment during pick-up, the chip quality is often affected when either the first chip 1 or the second chip 2 is present in that location. To avoid the inclusion of high-quality chips, each chip is typically inspected after pick-up. The first chip 1, the second chip 2, and the third chip 3 are inspected separately to determine if they meet quality standards, and any defective chips are discarded to ensure the quality of the final product.

[0067] This application provides a chip picking method, including identifying chips in multiple spaced rows as first chips and third chips, arranging the first and third chips in the same row alternately, with an interval row between adjacent rows; identifying chips in the interval rows as second chips and third chips, arranging the second and third chips in each interval row alternately; and sequentially picking up multiple first chips and multiple second chips via an alternating picking path. By alternating the arrangement of first and third chips, and second and third chips during identification, and by setting an interval row between rows containing first chips, the surrounding environment of the chip to be picked up is highly symmetrical during the picking process, resulting in uniform force during picking and improving chip quality and reliability.

[0068] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A chip picking method, characterized in that, The chip pickup method includes: The chips in multiple spaced rows in the chip array are identified as first chips and third chips, wherein the first chips and the third chips in the same row are arranged alternately, and there is a spaced row between two adjacent rows containing the first chips. The chips within a row of the multiple spaced rows in the chip array are identified as the second chip and the third chip, wherein the second chip and the third chip are arranged alternately within each spaced row; Multiple first chips and multiple second chips are sequentially picked up along the interlaced picking path.

2. The chip picking method according to claim 1, characterized in that, The chip pickup method further includes: It is confirmed that the top, bottom, left, and right directions of each first chip located in the inner region of the chip array are all the third chip, and the top, bottom, left, and right directions of each second chip located in the inner region of the chip array are all the third chip, and it is confirmed that the first chip or the second chip located in the edge region of the chip array is missing at least one adjacent third chip in the direction of the array boundary.

3. The chip picking method according to claim 1, characterized in that, The step of sequentially picking up multiple first chips and multiple second chips along the interlaced picking path includes: Multiple first chips are sequentially extracted along the first path; Multiple second chips are sequentially extracted along the second path.

4. The chip picking method according to claim 3, characterized in that, The first path and the second path are S-shaped paths.

5. The chip picking method according to claim 2, characterized in that, The chip extraction method further includes: confirming that there are no chips in the four directions of the top, bottom, left, and right of each of the third chips located in the internal region of the chip array.

6. The chip picking method according to claim 5, characterized in that, The chip pickup method further includes: Multiple third chips are sequentially picked up along a third path, which is a path formed by sequentially picking up chips along each row.

7. The chip picking method according to claim 6, characterized in that, The third path is an S-shaped path.

8. The chip picking method according to claim 4 or 7, characterized in that, The S-shaped path is a path that moves along the row direction to the end of the row, then turns to the next row to be processed and moves in the opposite direction along the row direction until it covers the entire chip array.

9. The chip picking method according to claim 1, characterized in that, The step of identifying chips within multiple spaced rows in a chip array as first chips and third chips, and the step of identifying chips within multiple spaced rows in the chip array as second chips and the third chips, includes: The chips arranged alternately in each odd-numbered row of the chip array are identified as the first chip and the third chip; The chips arranged alternately in each even-numbered row of the chip array are identified as the second chip and the third chip. It is confirmed that the top, bottom, left and right directions of each first chip located in the inner region of the chip array are the third chip. It is also confirmed that the top, bottom, left and right directions of each second chip located in the inner region of the chip array are the third chip. It is confirmed that the first chip or the second chip located in the edge region of the chip array is missing at least one adjacent third chip in the direction of the array boundary.

10. The chip picking method according to claim 9, characterized in that, The chip extraction method further includes: confirming that there are no chips in the four directions of the top, bottom, left, and right of each of the third chips located in the internal region of the chip array.

11. The chip pick-up method according to claim 1 or 9, characterized in that, The chip pickup method further includes: The quality of the first chip, the second chip, and the third chip is tested to determine whether they are up to standard.

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