TVS (Transient Voltage Suppressor) protection device based on Trench grooved isolation structure and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor device manufacturing and process, in particular to a TVS protection device based on a Trench grooving isolation structure and a preparation method of the TVS protection device. Comprising the following steps: S1, photoetching on the surface of a silicon substrate to prepare a mask, and exposing an etching region; s2, preparing a high aspect ratio Trench structure with high perpendicularity and smooth side wall by utilizing ICP (Inductively Coupled Plasma) equipment and through a circulating etching and passivation process of millisecond pulse switching; s3, performing multi-stage cleaning and impurity removal on the groove, and performing gradient heating annealing to repair lattice damage; and S4, epitaxial growth or void-free compact filling of an insulating medium is carried out to form a TVS device isolation structure. According to the invention, dangling bonds and defect levels introduced due to rough interfaces are reduced, and local electric field concentration is prevented.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing and process technology, specifically to a TVS protection device based on a Trench isolation structure and its fabrication method. Background Technology

[0002] In the development of transient voltage suppression (TVS) protection devices towards higher power density and miniaturization, deep trench isolation structures are often used to achieve electrical isolation between cells. However, there are many process challenges in fabricating deep trenches with high aspect ratios. Traditional deep silicon etching processes often have difficulty balancing the etching rates at the top and bottom of the trench due to constant gas flow and lack of pulse modulation. This results in severe scalloped effects on the trench sidewalls and grass-like defects at the bottom. This roughness in the microstructure not only introduces a large number of interface states and dangling bonds, causing an abnormally high reverse leakage current, but also reduces the breakdown voltage and isolation withstand voltage performance of the device due to local electric field concentration caused by uneven sidewalls. Furthermore, as the trench depth increases, the mass transfer limitation within the deep hole makes it difficult to remove etching byproducts and clean polymer residues. Conventional chemical vapor deposition filling processes are prone to premature closure at the top of the trench, resulting in voids and stacking faults inside the isolation structure. In addition, conventional isothermal annealing processes cannot completely repair the deep lattice damage induced by etching, ultimately leading to a decrease in the insulation performance of the device. Under surge impact, it is prone to internal cracking or sidewall thermal breakdown, making it difficult to meet the circuit protection requirements of high reliability and harsh industrial environments. Summary of the Invention

[0003] The purpose of this invention is to provide a TVS protection device based on a trench isolation structure and its fabrication method. By employing a process combining pulse-modulated etching and dynamic gas flow regulation, the invention overcomes the shortcomings of existing deep trench fabrication methods, such as severe sidewall scalloping effect, easy formation of grass-like defects at the bottom, and easy formation of voids in deep hole filling. Furthermore, it achieves excellent interface lattice repair and electrical isolation performance, thereby effectively reducing reverse leakage current and improving surge withstand capability while meeting the requirements of device miniaturization and high power density. Specifically, the technical solution of this invention is as follows:

[0004] A method for fabricating a TVS protection device based on a Trench-groove isolation structure includes the following steps:

[0005] Step S1: Prepare a photolithographically defined mask on the surface of a semiconductor silicon substrate to expose the area to be etched;

[0006] Step S2: Place the silicon substrate with a mask in the reaction chamber, introduce etching gas to carry out deep silicon etching reaction, and fabricate a Trench structure with a high aspect ratio on the silicon substrate through alternating etching and passivation processes.

[0007] Step S3: Multi-stage cleaning of the Trench structure, using ultrasonic oscillation to disperse and remove polymer residues and micro-impurities generated during etching, followed by gradient temperature annealing to repair lattice damage and reduce interface state density;

[0008] Step S4: Epitaxial growth or insulating medium filling in the Trench structure, by controlling the kinetic parameters of chemical vapor deposition to achieve dense and void-free filling, forming the isolation structure of the TVS protection device;

[0009] In the step S2, the preparation of the Trench structure specifically comprises:

[0010] In the inductively coupled plasma device, the radio frequency bias power and the chamber pressure are controlled to make the etching gas dissociate to form a high-density plasma; the silicon substrate is cut down using anisotropic etching, and the deposition of sidewall passivation gas is assisted; the bias power is periodically changed by using millisecond-level gas pulse switching and power synchronous pulse modulation mode; and the flow ratio of the etching gas and the sidewall passivation gas is dynamically adjusted according to the trench depth to balance the downward etching rate and the sidewall protection effect, so as to finally obtain a deep trench with high verticality and smooth sidewall.

[0011] Preferably, in the step S2, the etching gas comprises fluorine-based gas and fluorocarbon-based passivation gas; the fluorine-based gas is SF6, and the fluorocarbon-based passivation gas is C4F8; and the dynamic adjustment specifically comprises: increasing the flow ratio of the fluorocarbon-based passivation gas as the trench depth increases according to a preset etching time table or real-time depth monitoring data, so as to suppress sidewall roughness and scallop effect.

[0012] Preferably, the depth of the Trench structure prepared in the step S2 ranges from 10 to 20 μm; and the bottom morphology of the Trench structure is formed into a flat bottom or a rounded corner structure by controlling the etching parameters, so as to avoid grass-like defects caused by micro-shielding.

[0013] Preferably, the multi-stage cleaning process in the step S3 uses a chemical cleaning solution with high permeability and low surface tension, which enters the bottom of the Trench structure by using its high permeability, and dissolves and carries away the polymer residues by using its chemical dissolution properties; the polymer residues are mainly a mixture of etching by-products, silicon halide and fluorocarbon polymer.

[0014] Preferably, the annealing process in the step S3 comprises standing and heat preservation in an inert atmosphere, and the temperature control interval is set to 950-1050℃, so as to ensure that the leakage current index of the TVS device meets the qualified standard of engineering batch parameter test.

[0015] Preferably, the epitaxial growth or insulating medium filling in step S4 adopts a chemical vapor deposition process, and the ordered arrangement of the deposited material on the inner wall of the Trench structure is controlled by adjusting the precursor flow rate and the growth temperature or the deposition / etching time ratio; in the epitaxial growth or insulating medium filling process, a step-by-step deposition or deposition-etching-back mode is adopted to prevent the generation of stacking faults, polycrystalline nucleation or top-closed cavities in the deep trench.

[0016] Preferably, the isolation structure is used to realize electrical isolation between TVS device units; the TVS device units are blocked from the current path by the adjacent units through the isolation structure, and the interface chemical integrity of the isolation structure supports the device to withstand high voltage impact.

[0017] The application also provides a TVS protection device based on a Trench trench isolation structure, which is prepared by a preparation method of a TVS protection device based on a Trench trench isolation structure; the Trench structure has a vertical smooth sidewall, the sidewall scallop roughness is less than 20 nm, and there is no cavity and stacking fault in the epitaxial layer or the dielectric layer; the interface state density is low, and the device has a low reverse leakage current characteristic.

[0018] Compared with the prior art, the application has the following beneficial effects:

[0019] 1. The application effectively solves the micro-morphology control problem of high aspect ratio trenches through a deep silicon etching process combining power synchronous pulse modulation mode and dynamic adjustment of gas flow ratio. Through millisecond-level gas pulse switching and dynamic adjustment of the flow ratio of fluorine-based gas and fluorocarbon-based passivation gas according to the trench depth, the downward etching rate and sidewall protection effect can be balanced, and the mass transfer limitation in deep holes can be overcome. This not only significantly suppresses the sidewall scallop effect commonly seen in traditional processes, controls the sidewall roughness at a low level, but also avoids the grass-like defects at the bottom caused by volatile by-products micro-masking. The Trench structure obtained in this way has very high verticality and smooth sidewall, reduces the dangling bonds and defect energy levels introduced by interface roughness, and prevents local electric field concentration.

[0020] 2. The application introduces a post-processing process of multi-stage cleaning and gradient temperature annealing, which significantly improves the interface quality and electrical performance of the device; the chemical cleaning solution with high permeability and low surface tension is combined with ultrasonic / megasonic oscillation, which can deeply clean the etching by-products at the bottom of the high aspect ratio trench; combined with gradient temperature annealing in an inert atmosphere, the lattice is given sufficient relaxation time, which effectively eliminates the deep lattice damage induced by etching and greatly reduces the interface state density; test results show that this process keeps the reverse leakage current of the device at the level of nanoamperes, and the breakdown voltage consistency is excellent, better than the conventional constant temperature annealing process.

[0021] 3. The application solves the problem of cavity in deep trench filling by using step-by-step deposition or multi-cycle deposition-etching process mode in the isolation structure filling step. By fine control of the kinetic parameters of chemical vapor deposition, the ordered conformal growth of silicon atoms on the inner wall of the trench is controlled, effectively preventing the cavity formed by the premature closure of the precursor on the top of the deep trench, and eliminating the internal stacking faults; this cavity-free dense filling ensures the mechanical strength and chemical integrity of the isolation structure, eliminates the thermal resistance and stress concentration points under surge impact, and avoids internal burst or sidewall thermal breakdown of the device in harsh environments;

[0022] 4. The prepared TVS protection device has excellent surge protection capability and process robustness. Benefiting from the optimized trench morphology and dense isolation structure, the device can withstand extremely high peak pulse power, has low clamping voltage and safe failure mode; the preparation method can adapt to the manufacturing requirements from small size to enhanced high-power size and different depths, meeting the application requirements of miniaturization, high reliability and high power density of TVS devices in consumer electronics and automotive electronics fields. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings;

[0024] Figure 1 The preparation process flow chart of the present application is shown in the following figure:

[0025] Figure 2 The trench filling integrity SEM cross-section comparison figure of Example 5 and Comparative Example 2 at the limit depth is shown in the following figure: DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0027] Example 1:

[0028] Please refer to Figure 1The embodiment provides a preparation method of a TVS protection device based on a Trench trench isolation structure, and the method specifically comprises the following steps: mask preparation is performed on a semiconductor silicon substrate surface through photolithography definition, and a region to be etched is exposed; then, the silicon substrate with the mask is placed in a reaction chamber, in an inductively coupled plasma device, a radio frequency bias power and a chamber pressure are controlled, a fluorine-based gas selected from SF6 and a fluorocarbon-based passivation gas selected from C4F8 are input as etching gas, a gas flow ratio of the two is dynamically adjusted according to a preset etching time table or real-time depth monitoring data according to the trench depth, the C4F8 flow is linearly increased from 60 sccm to 100 sccm with the increase of the depth, the SF6 gas flow is set to be kept at 120 sccm, the current trench depth is determined through an end point detection system or a pre-tested etching rate time table, and the C4F8 gas flow is linearly increased from 60 sccm to 90 sccm with the increase of the depth, that is, the bias power is periodically changed in a power synchronous pulse modulation mode in the whole etching process, and a fast response mass flow controller with a response time less than 10 ms is matched with a high-speed gas switching valve, the radio frequency power pulse frequency is specifically set to be 12.5 Hz, the duty cycle is 40%, and the gas switching cycle is set as follows: the SF6 gas is input for 50 ms, and then the C4F8 gas is input for 30 ms, through the cyclic alternating etching and passivation process synchronous with the gas component switching, the silicon substrate is cut down through anisotropic etching, and finally, the Trench structure with a depth of 10 um and applied in a standard size of 0.50 mm TVS device unit is prepared on the silicon substrate, and the bottom morphology of the Trench structure is adjusted to be a flat bottom structure through etching parameter debugging.

[0029] Then, the Trench structure is subjected to multi-stage cleaning, the Trench structure bottom is infiltrated by using the capillary action of a low surface tension cleaning liquid, and main polymer residues and micro impurities, which are mainly etching by-products, silicon halide and fluorocarbon polymer mixture, are removed through megasonic oscillation, then gradient temperature annealing treatment is performed, and the specific procedure is as follows: the temperature is increased from room temperature to 600 DEG C at a rate of 5 DEG C / min and is kept for 30 min, then the temperature is increased to a target annealing temperature at a rate of 10 DEG C / min, and the temperature is kept in an inert atmosphere, and the temperature control interval is set to be 950 DEG C-1050 DEG C; finally, epitaxial growth or insulating medium filling is performed in the Trench structure by using a chemical vapor deposition process, in the embodiment, TEOS is selected as a precursor to deposit a silicon oxide medium layer, the precursor flow rate and the growth temperature are adjusted, and a step-by-step deposition mode is adopted, for example, the deposition is suspended and 80 sccm of C4F8 etching gas is input for 5 seconds for back-etching every 200 nm of thickness, and the cycle is continued until the filling is completed, so that the dense filling without cavity is realized, the isolation structure for realizing electrical isolation between TVS device units is formed, and thus the TVS protection device is prepared.

[0030] The TVS protection device prepared in the embodiment has a Trench structure with high verticality and smooth sidewall, and the interface state density is reduced, which can effectively inhibit the sidewall roughness and fan-shaped effect. The TVS device unit is blocked from the current path by the isolation structure and the adjacent unit, the device leakage current index meets the qualified standard of engineering batch parameter test, and is suitable for consumer electronic circuit protection scenarios with certain requirements for low power consumption.

[0031] Embodiment 2

[0032] The embodiment provides a preparation method of a TVS protection device based on a Trench trench isolation structure. The method adjusts the process parameter interval on the basis of embodiment 1, and specifically comprises the following steps: after completing mask preparation on the surface of a semiconductor silicon substrate, deep silicon etching reaction is performed by using an inductively coupled plasma device, wherein the etching gas is dissociated into high-density plasma under synchronous pulse modulation mode of a power supply, the downward etching rate and the sidewall protection effect are balanced through millisecond-level gas pulse switching, a Trench structure with a depth of 12 μm and applied in a TVS device unit with a standard size of 0.50 mm is prepared on the silicon substrate; the Trench structure is treated by a multi-stage cleaning process of a chemical cleaning solution with high permeability and low surface tension, polymer residues in the deep hole are effectively removed, and lattice damage is repaired through gradient annealing treatment; finally, epitaxial growth is performed in the Trench structure, the reaction is controlled in a surface reaction limiting region by controlling the kinetic parameters of chemical vapor deposition, the ordered conformal growth of silicon atoms on the inner wall of the Trench structure is controlled, and a dense isolation structure is formed.

[0033] The embodiment overcomes the mass transfer limitation in the deep hole by optimizing the preparation process of the Trench structure, so that the prepared TVS protection device can maintain a small size while the interface chemical integrity of the isolation structure supports the device to withstand a higher voltage impact, and the grass-like defects caused by micro-shielding are avoided, and the yield is improved.

[0034] Embodiment 3

[0035] The embodiment provides a preparation method of a TVS protection device based on a Trench groove isolation structure, parameters of the method are set for medium-depth isolation requirements, and the method specifically comprises the following steps: exposing a region through photolithography on a semiconductor silicon substrate, introducing SF6 and C4F8 into a reaction chamber, discharging volatile by-products by using a gas pulse interval, and enhancing ion bombardment energy on a bottom of a groove, so that a Trench structure with a high aspect ratio and a depth of 15 microns and applied to a standard size of 0.50 mm of a TVS device unit is prepared on the silicon substrate, and a bottom morphology of the Trench structure is adjusted to a round corner structure; then, the Trench structure is subjected to multistage cleaning and gradient temperature annealing treatment, so that etching by-products are dissolved and removed, and an interface state density is reduced; finally, epitaxial growth filling is completed in the Trench structure by a step-by-step deposition mode, so that stacking faults or polycrystal nucleation in the deep groove are prevented, and an isolation structure is formed.

[0036] The TVS protection device prepared in the embodiment has a smooth Trench structure sidewall, the isolation structure is combined with the silicon substrate closely, a device leakage current is in a preset low-power consumption range, and the stability requirement of an electrical isolation performance of the TVS device unit in the field of automobile electronics and the like can be met.

[0037] Embodiment 4

[0038] The embodiment provides a preparation method of a TVS protection device based on a Trench groove isolation structure, the method focuses on the challenge of a deeper groove and a high-power device, and specifically comprises the following steps: mask preparation is performed on a semiconductor silicon substrate surface, in an etching step, radio frequency bias power and chamber pressure are accurately controlled, a flow ratio of fluorine-based gas and fluorocarbon-based passivation gas is dynamically adjusted, and a power synchronous pulse modulation mode is matched, so that a Trench structure with a depth of 18 microns and applied to a TVS device unit with an enhanced size of 0.80 mm (note: the size is increased to adapt to high-power heat dissipation requirements) is prepared on the silicon substrate; the Trench structure is then cleaned by using a chemical cleaning solution in a vacuum-assisted immersion state and is subjected to static heat preservation annealing treatment at 1050 DEG C; finally, an insulating medium is filled in the Trench structure or epitaxial growth is performed, so that an isolation structure of the TVS protection device is formed.

[0039] The TVS protection device prepared in the embodiment still has good verticality at a depth close to 20 microns, the Trench structure effectively inhibits morphological distortion commonly occurring in deep hole etching, the isolation structure ensures current blocking of adjacent units, and the TVS protection device is suitable for high-density circuit protection applications.

[0040] Embodiment 5

[0041] The embodiment provides a preparation method of a TVS protection device based on a Trench trench isolation structure, which challenges the boundary value of a process parameter and specifically comprises the following steps: mask preparation is performed on a semiconductor silicon substrate surface through photolithography definition; in step S2, in order to overcome the mass transfer limitation in a deep hole, an optimized power synchronous pulse modulation mode and a gas flow ratio are used to prepare a Trench structure with a depth of 20 μm on the silicon substrate, and the Trench structure is applied to a TVS device unit with an enhanced size of 0.80 mm, and the bottom morphology of the Trench structure is a flat bottom structure; after the Trench structure is subjected to megasonic cavitation cleaning of a high-permeability cleaning liquid and gradient temperature annealing treatment, lattice damage is repaired; in step S4, through fine adjustment of a precursor flow rate and using a multi-cycle deposition-etching process mode, a non-cavity epitaxial growth filling is realized in the Trench structure, and an isolation structure is formed;

[0042] The TVS protection device prepared in the embodiment successfully realizes preparation of a Trench structure with a high aspect ratio, has low interface state density and strong ability to resist high-voltage impact, proves process robustness of the preparation method under an extreme depth, and can meet the demand of high-performance industrial-grade protection devices.

[0043] Comparative example 1

[0044] The comparative example provides a preparation method of a TVS protection device, which is different from the embodiment 3 only in that: in the step of preparing the Trench structure, the power synchronous pulse modulation mode is not used, and the flow ratio of etching gas to passivation gas is kept constant and is not dynamically adjusted according to the trench depth; the other steps such as photolithography, cleaning, annealing and epitaxial filling process are consistent with the embodiment 3, and finally a trench structure with a depth of 15 μm is prepared; because of the lack of dynamic adjustment and pulse modulation, the Trench structure prepared in the comparative example has obvious scallop effects on the sidewall, and a small amount of grass-like defects exist at the bottom of the trench, so that micro gaps exist at the interface of the isolation structure filled subsequently, and finally the device leakage current is higher than that of the embodiment 3, which indicates that the constant parameter etching alone cannot meet the micro-morphology requirements of the high-aspect-ratio trench.

[0045] Comparative example 2

[0046] Please refer to Figure 2The preparation method of the TVS protection device provided by the present comparative example is different from that of Example 5 only in that, in the step S3 of post-processing the Trench structure, gradient temperature annealing is not used, but conventional constant temperature annealing is used; in the epitaxial growth process of step S4, step-by-step deposition or deposition-etching is not used, but one-time continuous deposition is used; the rest of the parameters such as the trench depth of 20 μm and the device size of 0.80 mm are consistent with those of Example 5; due to the difference in annealing process and deposition method, the lattice damage repair in the inner wall of the Trench structure prepared in the present comparative example is not complete, and the epitaxial layer appears local stacking faults and holes caused by top clamping in the deep trench, which leads to the decline of the insulation performance of the isolation structure, and the performance of the device in the high voltage impact test is weaker than that of Example 5, and the device cannot completely meet the qualified standard of the engineering batch parameter test.

[0047] In Examples 1-5 and Comparative Examples 1-2, the semiconductor silicon substrate (N-type single crystal silicon wafer) is from Tianjin Zhonghuan Semiconductor Co., Ltd., the crystal direction is <111>, the resistivity is 0.001-0.005 Ω·cm, and the thickness is 200 μm; the etching gas sulfur hexafluoride (SF6) is from Guangdong Huate Gas Co., Ltd., electronic grade, purity ≥ 99.999%, CAS number: 2551-62-4; the passivation gas octafluorocyclobutane (C4F8) is from Guangdong Huate Gas Co., Ltd., electronic grade, purity ≥ 99.999%, CAS number: 115-25-3; the low surface tension cleaning solution (MOS grade isopropyl alcohol) is from Sinopharm Chemical Reagent Co., Ltd., MOS grade, purity ≥ 99.9%, CAS number: 67-63-0; the photoresist is from Suzhou Ruihong Electronic Chemicals Co., Ltd., model RZJ-304, viscosity 18-22 cP; the chemical vapor deposition precursor tetraethyl orthosilicate (TEOS) is from Shanghai Aladdin Biochemical Technology Co., Ltd., ACS grade, CAS number: 78-10-4; and the others are commercially available products.

[0048] The TVS protection devices prepared in Examples 1-5 and Comparative Examples 1-2 are tested, and the test results are as follows:

[0049] (1) Micro-morphology and structural integrity test

[0050] Test method explanation:

[0051] The cross-sectional morphology of the Trench structure prepared in Examples 1-5 and Comparative Examples 1-2 was observed using a field emission scanning electron microscope (FESEM, Model: Hitachi SU8010, Hitachi, Ltd., Japan); the prepared wafer sample was cut and prepared for sample, and the sidewall flatness, bottom morphology and internal structure after filling of the trench were observed in a vacuum environment; the sidewall roughness and whether there were voids in the internal filling were evaluated; 5 points in the center and at the edge of each sample were observed, and the average value was recorded;

[0052] Table 1

[0053] Result analysis:

[0054] As shown in Table 1, the Trench structure of the TVS protection device prepared by the application has excellent morphology characteristics, and the sidewall is smooth and has high perpendicularity; as the design depth increases (from 10 in Example 1 to 20 in Example 5), although the sidewall roughness slightly increases due to the mass transfer limitation in the deep hole, it is controlled within 20 nm, and no obvious morphological distortion occurs;

[0055] The comparative analysis of Example 3 and Comparative Example 1 shows that although Comparative Example 1 reaches a depth of 15 , due to the non-use of power synchronous pulse modulation mode and constant gas flow ratio, the sidewall roughness is as high as 125.60 nm, and obvious scallop effect occurs; this is because in deep silicon etching, the constant gas flow cannot balance the etching / passivation rate at the top and bottom of the trench, resulting in excessive erosion of the sidewall; and by dynamically adjusting the flow ratio of SF6 and C4F8 and cooperating with pulse modulation, Example 3 effectively inhibits the lateral etching of the sidewall and realizes high perpendicularity; in addition, the grass-like defects at the bottom of Comparative Example 1 are caused by the micro-shielding effect due to the volatilization of the by-products;

[0056] The comparative analysis of Example 5 and Comparative Example 2 shows that at the limit depth of 20 , due to the one-time continuous deposition in the epitaxial growth process in step S4, the reaction precursor is deposited too fast at the top of the trench and closes the opening, and the internal gas cannot be discharged, thereby forming a top closed void; in contrast, Example 5 adopts a multi-cycle deposition-etching process mode, effectively prevents the premature closure of the neck of the trench, realizes the dense filling without voids in the deep and large trench, and ensures the mechanical and chemical integrity of the isolation structure.

[0057] (2) Electrical performance test

[0058] Test method description:

[0059] The electrical performance of the packaged TVS protection device was tested using a semiconductor parameter analyzer (Keithley 4200-SCS, Tektronix, USA); the reverse leakage current and breakdown voltage of the device were tested at room temperature (25°C); wherein the test voltage was scanned step by step, and the leakage current value of the device when reaching the specified reverse working voltage was recorded; 20 device units were randomly selected for testing for each group of examples and comparative examples, and the average value was taken after removing bad points, and the test results are shown in Table 2;

[0060] Table 2

[0061] Result analysis:

[0062] As can be seen from Table 2, the devices prepared in Examples 1-5 exhibit extremely low reverse leakage current and excellent breakdown voltage consistency; with the increase of the trench depth, the leakage current increases slightly, which is due to the increase of the total number of surface states caused by the increase of the surface area of the deep trench, but the overall is still in the nanampere (nA) level, which meets the standard of high-performance low-power consumption application;

[0063] The leakage current of Comparative Example 1 is abnormally increased to 158.42 nA compared with Example 3; from the mechanism, the serious fan-shaped effect in Comparative Example 1 leads to a sharp increase in the surface area of the trench sidewall, and the rough interface introduces a large number of lattice defects and dangling bonds, which become the recombination center and generation center of carriers, thereby significantly increasing the surface leakage current; in addition, the unevenness of the sidewall will cause local electric field concentration, reducing the overall voltage withstand performance of the device;

[0064] Although the trench depth of Comparative Example 2 is the same as that of Example 5, the leakage current reaches 89.75 nA, and the isolation voltage withstand performance decreases; this is because Comparative Example 2 does not use gradient temperature annealing treatment in the post-processing step, but uses conventional constant temperature annealing; gradient temperature annealing can give the lattice sufficient relaxation time, effectively eliminating the etching-induced deep lattice damage; while the conventional annealing repair is not complete, resulting in a still high interface state density; at the same time, the existence of small cavities (see Table 1 results) in Comparative Example 2 leads to a decrease in the dielectric strength of the isolation structure, which is easily locally broken down under high voltage, and cannot meet the demand of high-voltage isolation.

[0065] (3) Reliability and surge resistance test

[0066] Test method explanation:

[0067] According to the standard IEC61000-4-5 "Electromagnetic compatibility tests and measurement techniques Surge (impulse) immunity test", a lightning surge generator (ESS-2000, NoiseKen, Japan) was used to test the surge resistance of the device; the applied waveform is 8 / 20 The pulse current is gradually increased, and the peak pulse current is gradually increased. Until the device fails (a sudden change in leakage current or a short circuit is detected at both ends); record the maximum peak pulse power that the device can withstand. ) and clamping voltage ( Repeat the test 3 times and take the average value.

[0068] Table 3

[0069] Results analysis:

[0070] As shown in Table 3, the TVS protection devices of Examples 1-5 have excellent surge protection capabilities, and their power tolerance is significantly improved with the optimization of device size and trench depth. Example 5 achieved a peak pulse power of 650W, proving that the deep trench isolation structure not only achieves electrical isolation, but also assists in heat dissipation through good interface contact.

[0071] Compared with Example 3, Comparative Example 1 shows a decrease in peak pulse power and an increase in clamping voltage. This is because the grass-like defects and micro-roughness of the sidewalls of Comparative Example 1 cause local hot spots on the current path. Under high current impact, the electric field at these tip positions is extremely concentrated, leading to local overheating and premature thermal breakdown, which limits the current carrying capacity of the device.

[0072] Compared with Example 5, Comparative Example 2 exhibits an internal burst failure mode. The root cause lies in the stacking faults and voids within the isolation structure of Comparative Example 2. During the surge impact, the gas inside the void expands due to heat, generating enormous mechanical stress. In addition, the abnormal resistivity at the stacking faults leads to uneven heating, ultimately resulting in the destruction of the device's physical structure. Example 5, on the other hand, benefits from the dense filling achieved by the deposition-etch-back process, eliminating internal thermal resistance and stress concentration points, thus exhibiting stronger robustness and meeting the circuit protection requirements of harsh industrial environments.

[0073] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments that can be applied to other fields. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A method for fabricating a TVS protection device based on a Trench-groove isolation structure, characterized in that, The method comprises the following steps: Step S1: performing mask preparation on the surface of a semiconductor silicon substrate to expose the area to be etched; Step S2: placing the silicon substrate with the mask in a reaction chamber, introducing etching gas to perform deep silicon etching reaction, and preparing a Trench structure with high aspect ratio on the silicon substrate through cyclic and alternating etching and passivation processes; Step S3: performing multi-stage cleaning on the Trench structure, dispersing and removing polymer residues and micro impurities generated in the etching process through ultrasonic oscillation, and then performing gradient annealing treatment to repair lattice damage and reduce interface state density; Step S4: performing epitaxial growth or insulating medium filling in the Trench structure, realizing dense filling without cavity through control of the kinetic parameters of chemical vapor deposition, and forming an isolation structure of a TVS protection device; In the step S2, the preparation of the Trench structure specifically comprises: In an inductively coupled plasma device, the radio frequency bias power and the chamber pressure are controlled to make the etching gas dissociate to form a high-density plasma; the silicon substrate is cut down by anisotropic etching, and the deposition of the sidewall passivation gas is cooperated to periodically change the bias power by using a power synchronous pulse modulation mode through millisecond-level gas pulse switching, and the flow ratio of the etching gas and the sidewall passivation gas is dynamically adjusted according to the trench depth to balance the downward etching rate and the sidewall protection effect, so that a deep trench with high verticality and smooth sidewall is finally obtained.

2. The method for fabricating a TVS protection device based on a Trench-groove isolation structure according to claim 1, characterized in that, In the step S2, the etching gas comprises fluorine-based gas and fluorocarbon-based passivation gas; the fluorine-based gas is SF6, and the fluorocarbon-based passivation gas is C4F8; the dynamic adjustment specifically comprises: increasing the flow ratio of the fluorocarbon-based passivation gas with the increase of the trench depth according to a preset etching time table or real-time depth monitoring data to inhibit the sidewall roughness and scallop effect.

3. The method for fabricating a TVS protection device based on a Trench-groove isolation structure according to claim 1, characterized in that, The depth of the Trench structure prepared in the step S2 ranges from 10 to 20 μm; the bottom morphology of the Trench structure is formed into a flat bottom or a rounded corner structure by controlling the etching parameters to avoid grass-like defects caused by micro-shielding.

4. The method for fabricating a TVS protection device based on a Trench-groove isolation structure according to claim 1, characterized in that, The multi-stage cleaning process in the step S3 uses a chemical cleaning solution with high permeability and low surface tension to enter the bottom of the Trench structure by using its high permeability and to dissolve and carry away the polymer residues by using its chemical dissolution properties; the polymer residues are mainly a mixture of etching by-products, silicon halides and fluorocarbon polymers.

5. The method for fabricating a TVS protection device based on a Trench-groove isolation structure according to claim 1, characterized in that, The annealing process in the step S3 comprises standing and heat preservation in an inert atmosphere, and the temperature control interval is set to 950-1050℃ to ensure that the leakage current index of the TVS device meets the qualified standard of the engineering batch parameter test.

6. The method for fabricating a TVS protection device based on a Trench-groove isolation structure according to claim 1, characterized in that, The epitaxial growth or insulating medium filling in the step S4 adopts a chemical vapor deposition process to control the ordered arrangement of the deposited material on the inner wall of the Trench structure by adjusting the precursor flow rate, growth temperature or deposition / etching time ratio; in the epitaxial growth or insulating medium filling process, a step-by-step deposition or deposition-etching mode is adopted to prevent the generation of stacking faults, polycrystalline nucleation or top closed cavity in the deep trench.

7. The method for fabricating a TVS protection device based on a Trench-groove isolation structure according to claim 1, characterized in that, The isolation structure is used for realizing electrical isolation between TVS device units; the TVS device units block current paths with adjacent units through the isolation structure, and interface chemical integrity of the isolation structure supports that the device can withstand high voltage impact.

8. A TVS protection device based on a Trench-groove isolation structure, characterized in that, The application relates to a silicon substrate, a Trench structure formed in the silicon substrate, and an epitaxial layer or a dielectric layer filled in the Trench structure; the Trench structure is prepared by the preparation method in any one of claims 1 to 7; the Trench structure has a vertical smooth sidewall, the sidewall fan-shaped shell roughness is in a nanometer level, and the epitaxial layer or the dielectric layer is free of internal cavities and stacking faults; interface state density is low, and the device has a low reverse leakage current characteristic.

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