Semiconductor device and method of manufacturing the same

Abstract

The semiconductor device includes: a substrate; a gallium nitride layer provided on the non-polar surface of the substrate, the gallium nitride layer having a plurality of fins positioned apart from each other in a first direction parallel to the c-axis direction and extending in a second direction orthogonal to the first direction; the electron supply layer is arranged on the Ga surface of the fin part; a base electrode located between the source interdigital portion and the drain interdigital portion in the second direction and facing the electron supply layer in the first direction; and a first insulating film provided between the gate electrode and the electron supply layer.

Description

TECHNICAL FIELD

[0001] Embodiments relate to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] In a lateral GaN-HEMT (High Electron Mobility Transistor), since a GaN layer is generally grown on a c-plane of a substrate, a two-dimensional structure is mainstream, and freedom for device configuration is small.

[0003] PRIOR ART DOCUMENT PATENT DOCUMENT Patent Document 1: Japanese Patent Application Laid-Open No. 2023-502631 Patent Document 2: Japanese Patent Application Laid-Open No. 2022-29220 SUMMARY

[0004] PROBLEMS TO BE SOLVED BY THE INVENTION Embodiments provide a semiconductor device capable of reducing a specific on-resistance RonA and improving a withstand voltage, and a manufacturing method thereof.

[0005] MEANS FOR SOLVING THE PROBLEMS According to an embodiment, a semiconductor device includes: a substrate; a gallium nitride layer provided on a non-polar plane of the substrate, having a plurality of fin portions located at mutually separate positions in a first direction parallel to a c-axis direction and extending in a second direction orthogonal to the first direction; an electron supply layer provided on a Ga plane of the fin portions; a source interdigital portion extending in the first direction and in contact with the electron supply layer; a drain interdigital portion extending in the first direction, located at a position separate from the source interdigital portion in the second direction, and in contact with the electron supply layer; a gate electrode located between the source interdigital portion and the drain interdigital portion in the second direction and opposite the electron supply layer in the first direction; and a first insulating film provided between the gate electrode and the electron supply layer. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 is a schematic plan view of a semiconductor device of an embodiment.

[0007] Figure 2 is Figure 1 is a cross-sectional view taken along line A-A in

[0008] Figure 3 is Figure 1 is a cross-sectional view taken along line B-B in

[0009] Figure 4(a) and (b) are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment.

[0010] Figure 5 (a) and (b) are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment.

[0011] Figure 6 (a) and (b) are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment.

[0012] Figure 7 (a) and (b) are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment.

[0013] Figure 8 (a) and (b) are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment.

[0014] Figure 9 (a) and (b) are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0015] Embodiments will be described below with reference to the accompanying drawings. Note that the same portions in different drawings are denoted with the same reference numerals, and repeated explanation of these portions is omitted.

[0016] Reference Figures 1-3 A semiconductor device 1 according to an embodiment will be described.

[0017] The semiconductor device 1 according to an embodiment includes a substrate 10 and a gallium nitride layer 20. In this specification, a direction parallel to a c-axis direction of a c-plane which is a polar plane of the gallium nitride layer 20 is referred to as a first direction Y. A direction orthogonal to the first direction Y is referred to as a second direction X. A direction orthogonal to the first direction Y and the second direction X is referred to as a third direction Z. The third direction Z is a direction parallel to an m-axis direction or an a-axis direction of the gallium nitride layer 20. Note that the gallium nitride layer 20 is also referred to as a GaN layer 20. The gallium nitride layer (GaN layer) 20 includes nitrogen (N) and gallium (Ga) and can include an additive other than nitrogen and gallium. The composition ratio of the additive in the gallium nitride layer 20 is lower than the composition ratio of nitrogen and the composition ratio of gallium.

[0018] The substrate 10 is, for example, a gallium nitride substrate. As Figure 2 and Figure 3 indicated in FIGS. 1A and IB, the GaN layer 20 is provided over a non-polar plane (an m-plane or an a-plane) 10A of the substrate 10. As the substrate 10, a sapphire substrate or a silicon substrate whose off angle is controlled can be used.

[0019] As Figure 2 indicated in FIGS. 2A and 2B, the GaN layer 20 has a plurality of fin portions 21 which are provided in a convex shape in cross section. AsFigure 1 As shown, multiple fins 21 are positioned separately in the first direction Y and extend in the second direction X. Of the two sides of the fins 21 extending in the second direction X, the side facing the +c axis is Ga surface 21A with Ga as its end, and the side facing the -c axis is N surface 21B with N as its end.

[0020] like Figure 2 As shown, the semiconductor device 1 includes an electron supply layer 30 disposed on the Ga surface 21A of the fin 21. The electron supply layer 30 extends along the fin 21 in the second direction X. The band gap of the electron supply layer 30 is wider than the band gap of the GaN layer 20. The electron supply layer 30 is, for example, an aluminum gallium nitride (AlGaN) layer. The electron supply layer 30 may also be an aluminum nitride (AlN) layer. A two-dimensional electron gas 40 is distributed in the vicinity of the interface (Ga surface 21A) with the electron supply layer 30 in the GaN layer 20 by piezoelectric polarization effect. The two-dimensional electron gas 40 is distributed along the third direction Z and extends along the second direction X.

[0021] like Figure 1 As shown, semiconductor device 1 includes a source electrode 100, a drain electrode 200, and a gate electrode 50. In semiconductor device 1, Figure 1 The construction shown is repeated multiple times in the second direction x.

[0022] The source electrode 100 has a source pad portion 101 extending in a second direction X and a plurality of source interdigitated portions 102 arranged separately from each other in the second direction X. The plurality of source interdigitated portions 102 extend from the source pad portion 101 in a first direction Y.

[0023] The drain electrode 200 has a drain pad portion 201 extending in the second direction X and a plurality of drain interdigitated portions 202 arranged separately from each other in the second direction X. The drain interdigitated portions 202 are located in the second direction X at a position separate from the source interdigitated portions 102. The plurality of drain interdigitated portions 202 extend from the drain pad portion 201 toward the source pad portion 101 in the first direction Y.

[0024] The source interdigitated portion 102 and the drain interdigitated portion 202 are connected to, for example, the upper end of the electron supply layer 30 and are in electrical contact with the electron supply layer 30. The source interdigitated portion 102 and the drain interdigitated portion 202 may also be connected to the GaN layer 20. Current flows between the drain electrode 200 and the source electrode 100 through the two-dimensional electron gas 40.

[0025] A gate electrode 50 is located between adjacent source interdigitates 102 and drain interdigitates 202 in the second direction X. Multiple gate electrodes 50 are arranged separately in the first direction Y. Each gate electrode 50 is located between adjacent fins 21 in the first direction Y. The multiple gate electrodes 50 are connected to a first gate wiring 51 extending in the first direction Y. The first gate wiring 51 is connected to a second gate wiring 52 extending in the second direction X. A gate voltage is applied to the gate electrode 50 via the second gate wiring 52 and the first gate wiring 51. Multiple first gate wirings 51 extend from the second gate wiring 52 in the first direction Y. Multiple gate electrodes 50 arranged in the first direction Y are respectively connected to the multiple first gate wirings 51. A source interdigitate 102 is located between adjacent gate electrodes 50 in the second direction X and between adjacent first gate wirings 51 in the second direction X. The distance (drift length) in the second direction X between the drain interdigitate 202 and the gate electrode 50 is longer than the distance in the second direction X between the source interdigitate 102 and the gate electrode 50. This improves the withstand voltage.

[0026] like Figure 2 As shown, the semiconductor device 1 further includes a first insulating film 61 disposed between the gate electrode 50 and the electron supply layer 30. The gate electrode 50 is positioned opposite the electron supply layer 30 in the first direction Y, separated by the first insulating film 61.

[0027] According to this embodiment, a two-dimensional electron gas 40 distributed in the height direction (third direction Z) of a plurality of fins 21 disposed on the gallium nitride layer 20 can be formed, thereby reducing the characteristic on-resistance RonA. The characteristic on-resistance RonA represents the product of the on-resistance Ron and the effective area A related to the conduction of current.

[0028] The higher the aspect ratio (height to width ratio) of the fin 21 and the narrower the spacing between multiple fins 21, the lower RonA. Therefore, if the width of the fin 21 in the first direction Y is set as A, the distance (or spacing) between adjacent fins 21 in the first direction Y is set as B, and the height of the fin 21 in the third direction Z is set as C, then it is preferable to set C > A + B. For example, A and B can be around 100 nm, and C can be greater than A + B and less than 1 μm.

[0029] Furthermore, as a comparative example, consider a configuration in which the gate electrode is disposed opposite to the side of the fin, the source electrode is disposed at the bottom of the recess between adjacent fins, and the drain electrode is disposed on the upper surface of the fin. According to this comparative example, in order to extend the distance between the gate electrode and the drain interdigitation, the height of the fin needs to be increased. According to this embodiment, it is possible to increase the distance regardless of the height of the fin 21. Figure 1The distance (drift length) between the gate electrode 50 and the drain interdigitation portion 202 is extended as shown. This improves the withstand voltage.

[0030] like Figure 2 As shown, the semiconductor device 1 may also include a p-type layer 70 disposed on the N-side 21B of the fin 21. The p-type layer 70 may be, for example, a p-type GaN layer containing magnesium (Mg). The p-type layer 70 may be connected to the gate electrode 50, for example. Alternatively, an insulating film may be disposed between the p-type layer 70 and the gate electrode 50, and the p-type layer 70 may not be connected to the gate electrode 50.

[0031] The potential of the gate electrode 50 can be supplied to the fin 21 from the N-side 21B via the p-type layer 70. Through this back-gate effect, the concentration of the two-dimensional electron gas 40 can be controlled. Thus, the threshold voltage can be controlled, and normally off operation can also be achieved.

[0032] Not limited to the gate potential, the p-type layer 70 can also be given any potential through a separate electrode. Alternatively, the p-type layer 70 can also be given a source potential (e.g., ground potential).

[0033] The semiconductor device 1 may further include a second insulating film 62. The second insulating film 62 is disposed between the lower end of the electron supply layer 30 and the GaN layer 20, between the lower end of the gate electrode 50 and the GaN layer 20, between the lower end of the p-type layer 70 and the GaN layer 20, and between the lower end of the first insulating film 61 and the GaN layer 20. Additionally, the second insulating film 62 is disposed on the upper surface of the fin 21.

[0034] The semiconductor device 1 may also include a third insulating film 63. The third insulating film 63 covers the second insulating film 62, the upper end of the electron supply layer 30, the upper end of the gate electrode 50, the upper end of the p-type layer 70 and the upper end of the first insulating film 61 disposed on the upper surface of the fin 21.

[0035] The source interdigitated portion 102 and the drain interdigitated portion 202 can, for example, be connected to the upper end of the electron supply layer 30 through an opening formed in the third insulating film 63. In addition, the source interdigitated portion 102 and the drain interdigitated portion 202 can, for example, be connected to the upper surface of the fin portion 21 through an opening formed in the third insulating film 63 and the second insulating film 62.

[0036] like Figure 1 and Figure 3As shown, the semiconductor device 1 may also include field plate electrodes 80. The field plate electrodes 80 are located between the gate electrode 50 and the drain interdigitation 202 in the second direction X, and between adjacent fins 21 in the first direction Y. A plurality of field plate electrodes 80 are arranged separately from each other in the first direction Y. The plurality of field plate electrodes 80 are connected to a first wiring 81 extending in the first direction Y. The first wiring 81 is electrically connected to the source interdigitation 102 via a second wiring 82 extending in the second direction X. A source potential is applied to the field plate electrodes 80 via the second wiring 82 and the first wiring 81. The source potential is, for example, a ground potential. This mitigates the electric field applied to the GaN layer 20 between the drain interdigitation 202 and the gate electrode 50, thereby improving the breakdown voltage.

[0037] The following is for reference Figure 4 (a) ~ Figure 9 (b) describes the manufacturing method of the semiconductor device according to the embodiment.

[0038] like Figure 4 As shown in (a), the semiconductor device manufacturing method of the embodiment includes a step of forming a gallium nitride layer (GaN layer) 20 on the non-polar surface 10A of the substrate 10. For example, the GaN layer 20 is grown on the m-surface or a-surface of the gallium nitride substrate by MOCVD (metal-organic chemical vapor deposition).

[0039] like Figure 5 As shown in (b), the method for manufacturing a semiconductor device according to the embodiment includes a step of forming a plurality of fins 21 and recesses 22 located between the plurality of fins 21 in a GaN layer 20. For example, as Figure 4 As shown in (b), a mask 91 is formed on the upper surface of the GaN layer 20. For example, a silicon oxide film can be used as the mask 91. With the mask 91 formed, GaN is grown on the upper surface of the GaN layer 20 exposed from the mask 91 using MOCVD. Figure 5 (a)). Then, for example, the mask 91 is removed by wet etching.

[0040] like Figure 5 As shown in (b), a plurality of fins 21 are positioned separately in a first direction Y parallel to the c-axis. Recesses 22 are located between adjacent fins 21 in the first direction Y. The plurality of fins 21 and the plurality of recesses 22 are arranged alternately in the first direction Y. The fins 21 and the recesses 22 extend in the second direction X.

[0041] like Figure 6As shown in (a), an insulating film 60 is embedded in the recess 22. Furthermore, the insulating film 60 covers the upper surface of the fin 21. The insulating film 60 can be, for example, a silicon nitride film formed by plasma CVD (Chemical Vapor Deposition).

[0042] In the case of manufacturing a semiconductor device having a p-type layer 70, such as Figure 6 As shown in (b), a first opening 60a is formed in the insulating film 60. The first opening 60a includes a portion of a recess 22 adjacent to the N-surface 21B of the fin 21. The N-surface 21B of the fin 21 is exposed in the first opening 60a. The first opening 60a can be formed, for example, by a RIE (Reactive Ion Etching) method.

[0043] like Figure 7 As shown in (a), after forming a second mask 92 on the upper surface of the insulating film 60, a p-type layer (e.g., a p-type GaN layer) 70 is grown from the N-side 21B exposed at the first opening 60a using MOCVD. The p-type layer 70 is formed within the first opening 60a. Alternatively, after growing the GaN layer from the N-side 21B, a p-type impurity (e.g., Mg) may be ion-implanted into the GaN layer, and activated by heat treatment to form the p-type layer 70. For example, a silicon oxide film can be used as the second mask 92.

[0044] After forming the p-type layer 70, the second mask 92 is removed and / or the upper surface of the p-type layer 70 and the upper surface of the insulating film 60 are planarized by CMP (Chemical Mechanical Polishing). Figure 7 (b)

[0045] Subsequently, the method for manufacturing the semiconductor device according to the embodiment includes a step of forming an electron supply layer 30 on the Ga surface 21A of the fin 21.

[0046] For example, through the RIE method, such as Figure 8 As shown in (a), a second opening 60b is formed in the insulating film 60. The second opening 60b includes a portion of a recess 22 adjacent to the Ga surface 21A of the fin 21. The Ga surface 21A of the fin 21 is exposed in the second opening 60b. At this time, the insulating film 60 remaining on the bottom surface of the recess 22 and the upper surface of the fin 21 becomes the aforementioned second insulating film 62.

[0047] like Figure 8As shown in (b), a third mask 93 is formed within the second opening 60b. For example, a silicon oxide film can be used as the third mask 93. The Ga surface 21A is not covered by the third mask 93 and is exposed in the second opening 60b. With the third mask 93 formed, an electron supply layer 30 is grown on the exposed Ga surface 21A, for example, by MOCVD or ALD (Atomic Layer Deposition). For example, an aluminum gallium nitride (AlGaN) layer or an aluminum nitride (AlN) layer is grown as the electron supply layer 30. Through piezoelectric polarization, a two-dimensional electron gas 40 is distributed near the interface (Ga surface 21A) with the electron supply layer 30 in the GaN layer 20.

[0048] After forming the electron supply layer 30, the third mask 93 is removed, and / or the upper surface of the second insulating film 62, the upper surface of the p-type layer 70, and the upper surface of the electron supply layer 30 are planarized by CMP. Figure 9 (a)).

[0049] Subsequently, the method for manufacturing the semiconductor device according to the embodiment is as follows: Figure 9 As shown in (b), the process includes forming a gate electrode 50 in the second opening 60b, which is opposed to the electron supply layer 30 through the first insulating film 61.

[0050] First, a first insulating film 61 is formed on the surface of the electron supply layer 30 opposite to the surface that is in contact with the Ga surface 21A. For example, a silicon nitride film can be formed as the first insulating film 61 using a CVD method.

[0051] After the first insulating film 61 is formed, a gate electrode 50 is formed in the second opening 60b in contact with the p-type layer 70 and the first insulating film 61. The gate electrode 50 may be formed, for example, a conductive film comprising at least one material selected from the group consisting of TiN, TiW, and polysilicon. The TiN and TiW films may be formed, for example, by sputtering. The polysilicon film may be formed, for example, by CVD. After the conductive film is formed, the conductive film formed on the upper surface of the second insulating film 62, the upper surface of the p-type layer 70, the upper surface of the first insulating film 61, and the upper surface of the electron supply layer 30 is removed, for example, by CMP (Chemical Mechanical Polishing).

[0052] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0053] Explanation of reference numerals in the attached figures: 1……Semiconductor device, 10……Substrate, 10A……Non-polar surface, 20……Gallium nitride layer, 21……Fin, 21A……Ga surface, 21B……N surface, 22……Recess, 30……Electron supply layer, 40……Two-dimensional electron gas, 50……Gate electrode, 51……First gate wiring, 52……Second gate wiring, 70……P-type layer, 80……Field plate electrode, 100……Source electrode, 101……Source pad portion, 102……Source interdigitated portion, 200……Drain electrode, 201……Drain pad portion, 202……Drain interdigitated portion.

Claims

1. A semiconductor device, wherein, have: substrate; A gallium nitride layer is disposed on the non-polar surface of the substrate and has a plurality of fins located at mutually separated positions in a first direction parallel to the c-axis and extending in a second direction orthogonal to the first direction. An electron supply layer is disposed on the Ga surface of the fin; The source interdigitates extend in the first direction and are in contact with the electron supply layer; The drain interdigitates extend in the first direction and are located in the second direction at a position separate from the source interdigitates, and are in contact with the electron supply layer; The gate electrode is located between the source interdigitate and the drain interdigitate in the second direction, and is opposite to the electron supply layer in the first direction; as well as A first insulating film is disposed between the gate electrode and the electron supply layer.

2. The semiconductor device according to claim 1, wherein, It also has a p-type layer disposed on the N-side of the fin.

3. The semiconductor device according to claim 2, wherein, The p-type layer is connected to the gate electrode.

4. The semiconductor device according to claim 2 or 3, wherein, The p-type layer is a p-type GaN layer.

5. The semiconductor device according to any one of claims 1 to 3, wherein, It also includes a field plate electrode, which is located between the gate electrode and the drain interdigitated portion in the second direction, and between adjacent fins in the first direction.

6. The semiconductor device according to claim 5, wherein, The field plate electrode is electrically connected to the source interdigitated portion.

7. The semiconductor device according to any one of claims 1 to 3, wherein, When the width of the fin in the first direction is set to A, the distance between adjacent fins in the first direction is set to B, and the height of the fin is set to C, then C > A + B.

8. The semiconductor device according to any one of claims 1 to 3, wherein, The electron supply layer is an aluminum gallium nitride layer or an aluminum nitride layer.

9. The semiconductor device according to any one of claims 1 to 3, wherein, The distance in the second direction between the drain interdigitate and the gate electrode is longer than the distance in the second direction between the source interdigitate and the gate electrode.

10. A method for manufacturing a semiconductor device, wherein, It has the following processes: The process of forming a gallium nitride layer on the non-polar surface of a substrate; In the process of forming a plurality of fins and recesses between the plurality of fins in the gallium nitride layer, the plurality of fins are located at mutually separated positions in a first direction parallel to the c-axis direction and extend in a second direction orthogonal to the first direction; The process of forming an electron supply layer on the Ga surface of the fin; as well as The process of forming a gate electrode in the recess that is opposed to the electron supply layer through a first insulating film.

11. The method of manufacturing a semiconductor device according to claim 10, wherein, It also includes a process for forming a p-type layer on the N-side of the fin.

12. The method of manufacturing a semiconductor device according to claim 11, wherein, After the p-type layer is formed, the gate electrode is formed in the recess in a manner that connects to the p-type layer and the first insulating film.

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