A memory control method, a storage device, a medium and an apparatus

Abstract

The application belongs to the technical field of cache prefetch optimization of the firmware layer of a computer storage system, and specifically provides a memory control method, a storage device, a medium and equipment, through a three-layer structure of a primary hot spot filtering module combined with a window cache, an apprentice queue and a protection queue, transient traffic is effectively filtered, and persistent hot spot data is accurately identified; a secondary continuous access filtering module uses mean-variance statistics of a ring buffer to dynamically determine a continuous access mode, and avoids accidental continuous triggering of prefetch; a tertiary random access judgment module prohibits invalid prefetch, and effectively distinguishes access modes. The application limits prefetch bandwidth through a token bucket algorithm, and combines a skip list global priority queue to ensure that the priority of a write task is higher than that of a prefetch task, so that resources of prefetch and foreground I / O are isolated, when full-load prefetch is performed, foreground critical I / O delay jitter can be controlled, and the problem of delay soaring caused by resource preemption of prefetch is avoided.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of cache prefetch optimization of the firmware layer of a computer storage system, and provides a memory control method, a storage device, a medium and equipment, which are particularly suitable for GaussDB database storage engine, OceanStor Dorado distributed storage firmware layer, Atlas AI training platform data preprocessing pipeline firmware and the like, and are used for improving data access efficiency and deterministic delay guarantee under mixed I / O load. BACKGROUND

[0002] The cache prefetch technology belongs to the field of kernel optimization and firmware design of a computer storage system, and specifically focuses on the cache management subsystem of the storage setting firmware layer. The core goal of the cache prefetch technology is to load data in a slow storage such as an SSD into a high-speed cache such as a DRAM in advance to hide access delay and improve I / O throughput before the data is explicitly requested.

[0003] The current mainstream cache prefetch technology relies on access pattern detection, such as sequential read triggered prefetch, and access frequency statistical decision, such as the LFU statistical method. Such cache prefetch technology exposes the following problems in actual use environment:

[0004] Under mixed I / O load, the intermingling of sequential scanning and random query can cause a large number of misjudgments of the prefetch logic. Specifically, when GaussDB executes a large analysis query of sequential scanning, if a small number of transaction point queries showing random read are inserted in the middle, the continuous access counter of the hcache will be reset, the prefetch needs to be relearned, the prefetch is interrupted, and performance jitter is shown. Random point queries accidentally trigger prefetch, useless data occupies the real hot index node in the cache, and invalid prefetch occurs, resulting in low cache utilization.

[0005] Therefore, the existing computer storage system under mixed load scenarios faces the industry pain points of frequent performance jitter under mixed load, lack of deterministic guarantee for key business, and insufficient adaptive ability of the firmware layer, and the existing technology needs to be improved to solve the problem.

[0006] SUMMARY

[0007] Based on this, in order to solve the problems of invalid prefetch and low cache utilization rate mentioned in the existing technology, the application provides a memory control method, a storage device, a medium and equipment, which can control the front-end key I / O delay jitter and avoid the problem of delay soaring caused by resource preemption of prefetch.

[0008] In a first aspect, the application provides a memory control method applied to the firmware layer of a computer storage system under I / O mixed load, and the method comprises:

[0009] A three-level filtering decision pipeline is constructed, which includes a first-level hot spot filtering module, a second-level continuous access filtering module and a third-level random access judgment module.

[0010] The obtained I / O access request is input into the first-level hot spot filtering module for hot spot data judgment, and if the judgment is yes, a hot spot prefetch strategy is triggered to pre-store data associated with the I / O access request.

[0011] If the judgment is no, the I / O access request is input into the second-level continuous access filtering module for continuous access mode judgment, and if the judgment is yes, a continuous prefetch strategy is triggered to prefetch the next or multiple continuous logical block addresses of the I / O access request.

[0012] If the judgment is no, the I / O access request is input into the third-level random access judgment module, which judges that the access mode is random, and a random processing strategy is triggered to prohibit the prefetch operation.

[0013] After the I / O tasks generated by the hot spot prefetch strategy and the continuous prefetch strategy are controlled in bandwidth by the token bucket algorithm, a global priority queue is constructed by the skip list to realize that the priority of the write task is higher than that of the prefetch task.

[0014] Further, the first-level hot spot filtering module adopts a W-Tiny LFU structure, which includes:

[0015] A window cache, which is a small-capacity LRU queue, is used to record the recently accessed I / O access request entries.

[0016] An apprentice queue and a protection queue are used to form a main cache, and the main cache is used to filter the persistent hot spot data.

[0017] A Count-Min Sketch probability data structure is used to count the access frequency of all I / O access request entries.

[0018] Further, the Count-Min Sketch probability data structure further includes a structure optimization step:

[0019] Four hardware-accelerated CRC32C hash functions are used to calculate hash values, and different initial polynomials are used in each hash function to reduce the hash collision probability.

[0020] The hash bucket counter adopts 4-bit saturated counting, and when the count reaches the maximum value, it remains unchanged, and at the same time, the counter automatically has a shift operation to decay 1 bit every 1000 accesses to adapt to the change of access frequency.

[0021] The Count-Min Sketch is divided into multiple copies according to the number of CPU cores, each copy is bound to a corresponding local cache line to reduce cross-core delay, and the state is updated by atomic operation between the copies to avoid invalid synchronization.

[0022] A low-priority background thread is started, and the counter values of all Count-Min Sketch copies are merged into a global Count-Min Sketch every 10 ms, and a weighted average is used to ensure statistical accuracy.

[0023] Further, the step of judging hot data by the first hot spot filtering module comprises:

[0024] The unique logical block address identifier of the target data is extracted from the I / O access request;

[0025] The unique logical block address identifier and the access timestamp are encapsulated into an entry structure of the window cache;

[0026] The new entry is inserted into the head of the LRU queue of the window cache, and if the logical block address identifier of the new entry already exists in the window cache, the position of the existing entry is updated to the head;

[0027] When the window cache is full, the frequency of the new entry and the old entry at the tail of the queue is compared;

[0028] The logical block address identifier of the new entry is applied to all hash functions of the Count-Min Sketch to obtain multiple counter positions, the counter values of the counter positions are read, and the minimum value is taken as the approximate access frequency freq_X of the new entry, and the logical block address identifier of the old entry at the tail is applied to all hash functions of the Count-Min Sketch to calculate, the corresponding counter values are read, and the minimum value is taken as the approximate range frequency freq_Y of the old entry;

[0029] If freq_X>freq_Y: the new entry is retained and inserted into the probation queue;

[0030] If freq_X≤freq_Y: the new entry is discarded, and the old entry is retained;

[0031] If the entry in the probation queue is accessed again, it is promoted to the protection queue, and the I / O access request corresponding to the entry in the protection queue is determined as hot data.

[0032] Further, the data associated with the I / O access request includes:

[0033] The logical block address itself corresponding to the I / O access request is prefetched, and the aligned memory page and / or adjacent logical associated data block where the logical block address of the I / O access request is located are also prefetched.

[0034] Further, the secondary continuous access filtering module comprises a ring buffer, a size N of the ring buffer is a power of 2, and logical block address difference values ΔLBA of nearly N times of I / O access requests are stored through the ring buffer.

[0035] Further, the optimization step of the ring buffer comprises:

[0036] Read-write index updating of the ring buffer is implemented through a double Compare-And-Swap atomic operation, a current value of the index is checked to see whether it is as expected, and then the index is updated to a new value, if the check fails, an index backoff retry is triggered to reduce a race condition;

[0037] Through a multi-producer single-consumer lock-free queue architecture, each producer maintains an independent temporary write buffer, and after the buffer is full, the atomic operation is used to batch submit to the ring buffer to reduce the conflict between the producers;

[0038] The size of the ring buffer is dynamically adjusted according to the foreground I / O utilization of the system, when the utilization is lower than 20%, the size is expanded to 256 entries, when the utilization is higher than 80%, the size is reduced to 64 entries, when the adjustment is performed, the atomic operation is used to switch the buffer pointer to ensure seamless transition of read-write operations;

[0039] The read operation on the ring buffer adopts a snapshot mechanism, when reading, a snapshot of the current write index is obtained first, and then data is read based on the snapshot range to avoid interference, and at the same time, the read operation preferentially uses a cache copy of a local core to reduce global memory access.

[0040] Further, the step of the secondary continuous access filtering module for judging the continuous access mode comprises:

[0041] A logical block address difference value ΔLBA of a current I / O access request and a last I / O access request is calculated: ΔLBA = current LBA - last LBA;

[0042] ΔLBA is written into the ring buffer to overwrite the oldest ΔLBA data;

[0043] A mean value μ and a variance σ² of all ΔLBA in the ring buffer are calculated in real time;

[0044] If σ² < a preset threshold value and μ > 0, the continuous access mode is determined.

[0045] Further, the step of the triggered continuous prefetch strategy comprises:

[0046] The prefetch depth = 2 + (μ / 4KB);

[0047] The prefetch depth does not exceed a prefetch upper limit configured by firmware through a register;

[0048] prefetch next or more consecutive logical block address.

[0049] Further, the step of triggering the random processing strategy to prohibit the prefetch operation when the three-level random access judgment module judges that the I / O request is in the random access mode includes:

[0050] stopping all prefetch operations;

[0051] starting a local learner to record the LBA access distribution in a short time;

[0052] if there is a small cluster in the LBA access distribution, triggering a limited depth exploratory prefetch.

[0053] Further, the three-level random access judgment module starts a low-priority background calibration task while judging that the I / O request is in the random access mode, and the execution steps of the low-priority background calibration task include:

[0054] obtaining the system foreground I / O utilization rate to adjust the sampling period, if the current utilization rate is lower than 20%, the sampling period is 1 second, if the current utilization rate is higher than 80%, the sampling period is 10 seconds, the foreground I / O utilization rate is obtained by reading the active period counter of the built-in DMA engine of the storage controller or the non-empty period counter of the I / O queue and dividing by the total time period;

[0055] In each sampling period, the logical block address sequence corresponding to all I / O access requests in a time period equal to the cycle length is collected, and the logical block address sequence is stored in a ring buffer statically allocated by the firmware;

[0056] The LBA sequence obtained by sampling is divided into LBA intervals of a fixed size, the number of accesses to each interval is counted, the access frequency of each interval is calculated, and the Shannon entropy value of the LBA sequence is calculated;

[0057] If the Shannon entropy value is continuously higher than a preset threshold value, and the number of random IOs per million IOs counted by the system is continuously higher than a preset value, the variance threshold value of the secondary continuous access filtering module is raised by a rule fence.

[0058] Further, the steps of generating I / O tasks by the hot spot prefetch strategy and the continuous prefetch strategy include:

[0059] The logical block address, aligned memory page, and adjacent logical associated data block corresponding to the I / O request pre-stored by the prefetch strategy form a hot spot prefetch LBA list;

[0060] If the continuous prefetch strategy is triggered, the logical block address pre-fetched by the continuous prefetch strategy forms a continuous prefetch LBA list;

[0061] Convert each LBA in the hot spot prefetch LBA list and / or the continuous prefetch LBA list into a background I / O task, mark the type of each task as "prefetch", and record the prefetch source.

[0062] Further, the step of controlling bandwidth by the token bucket algorithm comprises:

[0063] Set an independent token bucket for the generated I / O task, with a bucket depth of 1000 tokens, each token representing a prefetch authority of 4kb;

[0064] The token generation rate = reference rate x (1 - foreground I / O utilization rate), wherein the foreground I / O utilization rate is obtained in real time by a hardware counter;

[0065] I / O tasks consume tokens to execute, and if there are no available tokens, they wait until tokens are generated.

[0066] Further, the step of constructing a global priority queue by a skip list to achieve the priority of write tasks higher than that of prefetch tasks comprises:

[0067] Assign a 64-bit composite key value to each I / O task, with the structure of: [8-bit type priority] [32-bit monotonically increasing sequence number] [24-bit timeout time];

[0068] The type priority is defined as: synchronous write (0xF0) > asynchronous write (0xE0) > read (0xC0) > prefetch (0x00);

[0069] The skip list is sorted in descending order according to the composite key value, and the scheduler takes out tasks from the head of the skip list to execute, ensuring that the priority of write tasks is higher than that of prefetch tasks.

[0070] Further, the three-level filtering decision pipeline further comprises a rule fence, and the implementation steps of the rule fence comprise:

[0071] Predefined IF<condition>THEN<action> business rules:

[0072] Rule 1: If <prefetch hit rate 40% for 60 seconds> THEN <raise the preset threshold T_VAR of the variance σ² of the secondary continuous access filtering module to 1.1 x T_VAR>;

[0073] Rule 2: If <cache hit rate > 90% and system memory water level enters high water level marking state> THEN <lower the upper limit of continuous prefetch depth to 50% of the original upper limit>;

[0074] The rule check is performed by a low-priority background task periodically;

[0075] The rule enters a critical section, and I / O processing is stopped to ensure the atomicity of parameter adjustment.

[0076] In a second aspect, the present application provides a storage device, comprising:

[0077] a three-level filtering decision pipeline module is constructed to construct a three-level filtering decision pipeline, which comprises a first hot data filtering module, a second continuous access filtering module and a third random access judgment module;

[0078] a hot data judgment module is configured to input the obtained I / O access request into the first hot data filtering module for hot data judgment, and if the judgment is yes, trigger a hot prefetch strategy, and pre-store data associated with the I / O access request;

[0079] if the judgment is no, input the I / O access request into the second continuous access filtering module for continuous access mode judgment, and if the judgment is yes, trigger a continuous prefetch strategy, and prefetch the next or multiple continuous logical block addresses of the I / O access request;

[0080] if the judgment is no, input the I / O access request into the third random access judgment module, judge it as a random access mode through the third random access judgment module, and trigger a random processing strategy to prohibit the prefetch operation;

[0081] a global priority queue module is constructed, and after the I / O tasks generated by the hot prefetch strategy and the continuous prefetch strategy are controlled in bandwidth through a token bucket algorithm, a global priority queue is constructed through a skip list to realize that the priority of a write task is higher than the priority of a prefetch task.

[0082] In a third aspect, the present application provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to make the processor execute the steps of the method according to any one of the first aspect.

[0083] In a fourth aspect, the present application provides a computer device, which comprises a memory and a processor, and the memory stores a computer program, and the computer program is executed by the processor to make the processor execute the steps of the method according to any one of the first aspect.

[0084] According to the scheme provided in the application, the beneficial effect is that: by constructing a three-level filtering decision pipeline including a first-level hot spot filtering module, a second-level continuous access filtering module and a third-level random access judgment module; the obtained I / O access request is input into the first-level hot spot filtering module for hot spot data judgment, if it is judged to be yes, the hot spot prefetch strategy is triggered, and the data associated with the I / O access request is pre-stored; if it is judged to be no, the I / O access request is input into the second-level continuous access filtering module for continuous access mode judgment, if it is judged to be yes, the continuous prefetch strategy is triggered, and the next or multiple continuous logical block addresses of the I / O access request are prefetched; if it is judged to be no, the I / O access request is input into the third-level random access judgment module, and it is judged to be a random access mode by the third-level random access judgment module, and the random processing strategy is triggered to prohibit the prefetch operation; the I / O tasks generated by the hot spot prefetch strategy and the continuous prefetch strategy are controlled by the token bucket algorithm, and then the global priority queue is constructed by the skip list to realize that the priority of the write task is higher than the priority of the prefetch task. First, the first-level hot spot filtering module combines the three-layer structure of the window cache, the probation queue and the protection queue to effectively filter the transient traffic and accurately identify the persistent hot spot data; the second-level continuous access filtering module dynamically judges the continuous access mode by using the mean-variance statistics of the ring buffer to avoid accidental continuous triggering of the prefetch; the third-level random access judgment module prohibits invalid prefetch and effectively distinguishes the access mode. Secondly, the application limits the prefetch bandwidth by the token bucket algorithm, combines the global priority queue of the skip list, ensures that the priority of the write task is higher than the priority of the prefetch task, and isolates the resources of the prefetch and the foreground I / O, so that when the full-load prefetch is performed, the foreground key I / O delay jitter can be controlled, and the problem of delay soaring caused by the resource preemption of the prefetch is avoided. Finally, the application dynamically adjusts the prefetch threshold, the depth and the window cache ratio, and can adapt to the business switching mode without restarting. BRIEF DESCRIPTION OF DRAWINGS

[0085] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0086] Figure 1 A flowchart of a memory control method in an embodiment;

[0087] Figure 2 A block diagram of a storage module in an embodiment;

[0088] Figure 3 A structural block diagram of a computer device in an embodiment. DETAILED DESCRIPTION

[0089] In order for those skilled in the art to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0090] Embodiment one

[0091] When the existing GaussDB performs sequential scanning of a large analysis query, if a small amount of transaction point query showing random reading is inserted in the middle, the continuous access counter of the hcache will be reset, the prefetch needs to be relearned, the prefetch is interrupted, and performance jitter is shown. Random point query accidentally triggers prefetch, useless data occupies the real hot index node in the cache, invalid prefetch occurs, and the cache utilization rate is low. Therefore, the existing computer storage system faces the industry pain points of frequent performance jitter under mixed load, lack of deterministic guarantee for key business, and insufficient adaptive ability at the firmware layer under mixed load, and the existing technology needs to be improved to solve the problem.

[0092] Referring to Figure 1 The embodiment provides a memory control method, which is applied to a firmware layer of a computer storage system under I / O mixed load, and the method comprises the following steps:

[0093] S101, a three-level filtering decision pipeline is constructed, the three-level filtering decision pipeline comprises a first-level hot spot filtering module, a second-level continuous access filtering module and a third-level random access judgment module;

[0094] S102, the obtained I / O access request is input into the first-level hot spot filtering module for hot spot data judgment, if the judgment is yes, a hot spot prefetch strategy is triggered, and data associated with the I / O access request is pre-stored;

[0095] S103, if the judgment is no, the I / O access request is input into the second-level continuous access filtering module for continuous access mode judgment, if the judgment is yes, a continuous prefetch strategy is triggered, and the next or multiple continuous logical block addresses of the I / O access request are prefetched;

[0096] S104, if the judgment is no, the I / O access request is input into the third-level random access judgment module, the third-level random access judgment module judges that the access mode is random, and a random processing strategy is triggered to prohibit the prefetch operation;

[0097] S105, the I / O tasks generated by the hot spot prefetch strategy and the continuous prefetch strategy are controlled by the token bucket algorithm to control the bandwidth, and then a global priority queue is constructed by a skip list to realize that the priority of a write task is higher than that of a prefetch task.

[0098] It should be noted that the three-level filtering decision pipeline includes a first-level hot spot filtering module, a second-level continuous access filtering module, and a third-level random access judgment module. The first-level hot spot filtering module adopts a W-Tiny LFU structure, a window cache filters transient traffic, an apprentice queue and a protection queue screen persistent hot spots, and the access frequency of all I / O access request entries is counted by a Count-Min Sketch. In the second-level continuous access filtering module, the LBA difference is recorded by a ring buffer, the mean and variance are calculated in real time, and the prefetch is disabled when the mean and variance reach the preset value to determine the continuous access mode. In the third-level random access judgment module, if the first two levels are not hit, it is determined as random access by default, and the prefetch is disabled. Through token bucket bandwidth control, the token generation rate is negatively related to the foreground I / O utilization rate, the busier the system is, the slower the prefetch is, and resource preemption is avoided. Through skip list priority scheduling, the composite key value sorting ensures that the write task is prior to the prefetch task. Through three-level filtering, the mode misjudgment rate is reduced, and cache pollution caused by random access prefetch is avoided. Especially in the GaussDB mixed load scenario, the hot spot index node hit rate is improved, and the squeezing of useless data on the cache is reduced. Token bucket dynamically limits the prefetch bandwidth, and skip list priority scheduling ensures that the write task is executed first. When the full load prefetch is executed, the foreground key I / O delay jitter is controlled within a certain range, solving the problem of delay soaring caused by resource preemption in the prior art. The rule fence automatically adjusts the prefetch parameters, which can adapt to mode switching without manual intervention. The W-Tiny LFU structure and the ring buffer and other core logic are deployed in the firmware layer, the TCM / SRAM static allocation memory is used, the system call overhead is reduced, the prefetch decision delay is reduced, and the execution efficiency and reliability are improved.

[0099] Specifically, the first-level hot spot filtering module adopts a W-Tiny LFU structure, and the W-Tiny LFU structure includes:

[0100] a window cache, which is a small-capacity LRU queue, used to record the recently accessed I / O access request entries;

[0101] an apprentice queue and a protection queue, used to form a main cache, and the main cache is used to screen persistent hot spot data;

[0102] a Count-Min Sketch probability data structure, used to count the access frequency of all I / O access request entries.

[0103] It should be noted that regarding the deployment of the W-Tiny LFU structure: the window cache can be an LRU queue with a size of 128 KB, used to filter transient traffic, such as burst transactional point queries; the probation queue can be a queue with a size of 512 KB, receiving entries evicted from the window cache; the protection queue can be a queue with a size of 4 MB, receiving only entries in the probation queue that are accessed again, determined to be persistent hot data; the Count-Min Sketch uses 4 hardware-accelerated CRC32C hash functions, and the hash bucket counter is a 4-bit saturated counter, with a sketch copy maintained per CPU core (8 cores).

[0104] Specifically, the Count-Min Sketch probabilistic data structure further includes a structure optimization step:

[0105] 4 hardware-accelerated CRC32C hash functions are used to calculate hash values, and each hash function uses a different initial polynomial to reduce the probability of hash collision;

[0106] The hash bucket counter uses a 4-bit saturated counter, which remains unchanged when the count reaches the maximum value, and at the same time, the counter automatically decays 1 bit every 1000 accesses to adapt to the change in access frequency;

[0107] Independent Count-Min Sketch copies are divided according to the number of CPU cores, and each Count-Min Sketch copy is bound to the corresponding local cache line to reduce cross-core delay, and the state is updated through atomic operation between copies to avoid invalid synchronization;

[0108] Start a low-priority background thread, merge the counter values of all Count-Min Sketch copies into a global Count-Min Sketch every 10 ms, and use weighted average during merging to ensure statistical accuracy.

[0109] It needs to be explained that 4 hardware accelerated CRC32C hash functions are adopted, each hash function uses a different initial polynomial, such as 0x04C11DB7, 0x1EDC6F41, 0x85EBCA6B, 0x76DC4190, to reduce the probability of hash collision; the hash bucket counter is a 4-bit saturated counter, such as the maximum value 15, which remains unchanged when the counter reaches 15; every 1000 accesses automatically right shift operation attenuates 1 bit, such as from 15→7→3→1, to adapt to the change of access frequency; then, independent Count-Min Sketch copies are divided according to the number of CPU cores, each copy is bound to the corresponding local cache line, the copies are updated through atomic operations such as CAS instructions to avoid invalid synchronization; finally, a low-priority background thread is started, and the counter values of all Count-Min Sketch copies are merged into the global Count-Min Sketch every 10 ms, and the statistical accuracy is ensured through weighted average during merging.

[0110] Specifically, the steps of judging hot data by the first hot spot filtering module include:

[0111] extracting a unique logical block address identifier of target data from the I / O access request;

[0112] encapsulating the unique logical block address identifier and an access timestamp into an entry structure of the window cache;

[0113] inserting the new entry into the head of the LRU queue of the window cache, and if the logical block address identifier of the new entry already exists in the window cache, updating the position of the existing entry to the head;

[0114] when the window cache is full, comparing the frequency of the new entry and the old entry at the tail of the queue;

[0115] applying the logical block address identifier of the new entry to all hash functions of the Count-Min Sketch to obtain a plurality of counter positions, reading the counter values of the counter positions, and taking the minimum value as the approximate access frequency freq_X of the new entry, and applying the logical block address identifier of the old entry at the tail to all hash functions of the Count-Min Sketch to calculate, reading the corresponding counter values and taking the minimum value as the approximate range frequency freq_Y of the old entry;

[0116] if freq_X>freq_Y: keep the new entry and insert it into the probation queue;

[0117] if freq_X≤freq_Y: discard the new entry and keep the old entry;

[0118] if the entry in the probation queue is accessed again, it is promoted to the protection queue, and the I / O access request corresponding to the entry in the protection queue is determined as hot data.

[0119] It should be noted that the window cache is initialized as an LRU queue of 128 KB, with an initial ratio of 1:99, i.e., window cache: main cache; hot data is determined by the first level hot spot filtering module: after executing an OLTP transaction, accessing LBA 0x1000, extracting the LBA as a unique logical block address identifier, and encapsulating it with the access timestamp as a window cache entry; inserting the new entry into the head of the window cache LRU queue, if LBA 0x1000 already exists in the window cache, updating its position to the head, when the window cache is full, evicting the tail entry 0x2000, comparing the frequency of the new entry 0x1000 and the old entry 0x2000; applying 4 CRC32C hash functions to 0x1000, reading the corresponding counter value, taking the minimum value as freq_X (set to 5); applying 4 CRC32C hash functions to 0x2000, reading the corresponding counter value, taking the minimum value as freq_Y (set to 2); since freq_X>freq_Y, the new entry 0x1000 is retained and inserted into the probation queue. When the user queries 0x1000 again, 0x1000 in the probation queue is promoted to the protection queue, and is determined as hot data.

[0120] It is worth noting that the hardware accelerated hash function is enabled by reading and writing the CRC32C control register of the storage controller; the pointer update of the window cache, probation queue and protection queue is realized by atomic operation to ensure concurrent safety; the rule fence module dynamically adjusts the window cache ratio according to the burst IOPS change rate, for example, expanding to 2~5:95~98 when detecting burst traffic. Through the three-level queue hierarchical filtering, the accuracy of persistent hot spot recognition is improved, the cache pollution caused by random access triggering prefetch is avoided, the hot index node hit rate is improved, and the squeezing of useless data on the cache is reduced.

[0121] Specifically, the pre-stored data associated with the I / O access request includes:

[0122] The logical block address corresponding to the I / O access request is prefetched, and the aligned memory large page and / or adjacent logical associated data block where the logical block address is located are prefetched.

[0123] It should be noted that by prefetching the logical block address of the hot data itself, the aligned memory large and the adjacent logical associated data block, the delay of subsequent access can be reduced from the disk level to the cache level, from milliseconds to microseconds, and the prefetching of associated data blocks can reduce multiple I / O access requests due to the lack of locality; through the three-level filtering mechanism of W-TinyLFU, the pre-fetched associated data are all verified persistent hot spots, avoiding the flushing of burst one-time data to the cache; prefetching adjacent logical associated data blocks can adapt to complex scenarios such as databases and distributed storage.

[0124] Specifically, the secondary continuous access filtering module includes a ring buffer, the size N of the ring buffer is a power of 2, and the logical block address difference ΔLBA of nearly N times of I / O access requests is stored through the ring buffer.

[0125] It should be noted that the logical block address difference ΔLBA of nearly N times of I / O access requests is stored through the ring buffer, and the mean value and the variance are calculated in real time, so that the stable continuous access and the accidental continuous access can be accurately distinguished. The sliding window of the ring buffer can filter transient fluctuations, and the robustness of the continuous access detection is ensured.

[0126] Specifically, the optimization step of the ring buffer includes:

[0127] The read-write index update of the ring buffer is realized through double Compare-And-Swap atomic operations, the current value of the index is checked to see whether it meets the expectation, the index is updated to a new value, if the check fails, an exponential backoff retry is triggered to reduce the race conflict;

[0128] Through the multi-producer single-consumer lock-free queue architecture, each producer maintains an independent temporary write buffer, and after the buffer is full, the atomic operation is used to batch submit to the ring buffer to reduce the conflict between the producers;

[0129] According to the system foreground I / O utilization rate, the size of the ring buffer is dynamically adjusted, when the utilization rate is lower than 20%, the size is expanded to 256 entries, and when the utilization rate is higher than 80%, the size is reduced to 64 entries, when adjusting, the buffer pointer is switched through the atomic operation, and the read-write operation is seamlessly transitioned;

[0130] The read operation on the ring buffer adopts a snapshot mechanism, when reading, the snapshot of the current write index is first obtained, and then the data is read based on the snapshot range to avoid interference, and at the same time, the read operation preferentially uses the cache copy of the local core to reduce global memory access.

[0131] It should be noted that the ring buffer is initialized, the initial size of the ring buffer is 128 entries, the read and write indexes are maintained through 64-bit atomic variables, each CPU core is bound to a temporary write buffer, the ring buffer is statically allocated from the firmware-managed TCM / SRAM, the memory layout is aligned with the cache line to avoid cross-core access conflicts. Further optimization steps are deployed, the atomic update of the read and write indexes is checked first, if the current write index value is equal to the preset value, it is updated, if it is not matched, the exponential backoff retry is triggered; each CPU core maintains an independent temporary write buffer, when the buffer is full, it is submitted to the ring buffer in batches through atomic operations to reduce conflicts; the buffer size can be dynamically adjusted, the foreground I / O utilization rate of the storage controller is read in real time, when the utilization rate is lower than the preset value, such as lower than 20%, the ring buffer pointer is switched to a 256-entry copy through atomic operations; when the utilization rate is higher than the preset value, such as higher than 80%, it is switched to a 64-entry copy, ensuring seamless transition of read and write operations. When reading the ring buffer, the snapshot of the current write index is obtained through atomic operation first, and then the data is read based on the snapshot range, while the cache copy of the local core is preferentially used to reduce global memory access. Retry delay is implemented by right shift to avoid exacerbating race conditions.

[0132] Specifically, the step of judging the continuous access mode by the two-level continuous access filtering module includes:

[0133] Calculate the logical block address difference value of the current I / O access request and the last I / O access request: ΔLBA = current LBA - last LBA;

[0134] Write ΔLBA into the ring buffer, covering the oldest ΔLBA data;

[0135] Real-time calculation of the mean μ and variance σ² of all ΔLBA in the ring buffer;

[0136] If σ² < preset threshold and μ > 0, it is determined as continuous access mode.

[0137] It should be noted that the two-level continuous access filtering module uses a ring buffer with a size of 128 to record the LBA difference value of the last 128 times, and real-time calculates the mean μ and variance σ², and determines the continuous access mode when σ² < 0.5 and μ > 0.

[0138] Specifically, the steps of the triggered continuous prefetch strategy include:

[0139] Prefetch depth = 2 + (μ / 4KB);

[0140] The prefetch depth does not exceed the prefetch upper limit configured by the firmware through the register;

[0141] Prefetch the next one or more consecutive logical block addresses.

[0142] It should be noted that by dynamically calculating the prefetch depth, the system can adaptively adjust the amount of prefetch data according to the actual access mode, avoid insufficient or excessive prefetching caused by fixed depth, and effectively solve the performance jitter problem caused by fixed prefetch depth mentioned in the prior art.

[0143] Specifically, the step of the three-level random access judgment module judging that the I / O request is in a random access mode and triggering a random processing strategy to disable the prefetch operation includes:

[0144] stopping all prefetch operations;

[0145] starting a local learner to record the LBA access distribution in a short time;

[0146] if the LBA access distribution has a small cluster, triggering a limited-depth exploratory prefetch.

[0147] It should be noted that when the three-level random access judgment module determines that the I / O request is in a random access mode, all prefetch operations are immediately stopped, effectively avoiding that random data once squeezes out the real hot data in the cache. By starting a local learner to record the LBA access distribution in a short time, small clusters in random access can be captured, and a limited-depth exploratory prefetch is triggered. The exploratory prefetch mechanism of the local learner can be dynamically adjusted according to the actual access mode, avoiding the limitations of fixed strategies.

[0148] Embodiment Two

[0149] On the basis of Embodiment One, this embodiment provides further solutions to further technical problems. When the sampling period is fixed, it can cause resource waste or high delay. A fixed sampling period can occupy too many CPU resources under high load, causing the foreground I / O delay to rise. Under low load, the sampling frequency is low, and the access mode change cannot be captured in time. Moreover, the LBA sequence is stored in dynamically allocated memory, which is prone to compete with the host operating system for memory, causing high acquisition delay and affecting the real-time performance of Shannon entropy calculation.

[0150] Specifically, the three-level random access judgment module starts a low-priority background calibration task while judging that the I / O request is in a random access mode. The execution steps of the low-priority background calibration task include:

[0151] obtaining the system foreground I / O utilization rate to adjust the sampling period. If the current utilization rate is lower than 20%, the sampling period is 1 second. If the current utilization rate is higher than 80%, the sampling period is 10 seconds. The foreground I / O utilization rate is obtained by reading the active period counter of the DMA engine or the non-empty period counter of the I / O queue built in the storage controller and dividing the total time period.

[0152] In each sampling period, a sequence of logical block addresses corresponding to all I / O access requests in a time period equal to the length of the period is collected, and the sequence of logical block addresses is stored in a ring buffer statically allocated by firmware;

[0153] The sampled LBA sequence is divided into LBA intervals of a fixed size, the number of accesses in each interval is counted, the access frequency of each interval is calculated, and the Shannon entropy value of the LBA sequence is calculated.

[0154] If the Shannon entropy value is continuously higher than a preset threshold value, and the number of random IOs per million IOs counted by the system is continuously higher than a preset value, the variance threshold value of the secondary continuous access filtering module is raised by the rule fence.

[0155] It should be noted that, in the embodiment, the sampling period is adjusted dynamically to adapt to the load, the sampling period is adjusted dynamically according to the foreground I / O utilization rate, the sampling period is lengthened to reduce resource occupation in high load, and the sampling period is shortened to improve response speed in low load, so as to balance resource utilization rate and sampling real-time performance, and avoid the problems of resource waste or delay caused by fixed sampling period. The LBA sequence interval division and Shannon entropy calculation are performed, the sampled LBA sequence is divided into intervals of a fixed size, the number of accesses and the frequency of each interval are counted, the entropy value is calculated by the Shannon entropy formula, the higher the entropy value, the more random the access mode, and the randomness of the access mode is accurately reflected. According to the feedback of the rule fence, if the Shannon entropy value is continuously higher than a preset threshold value and the number of random IOs is continuously higher than a preset value, the variance threshold value of the secondary continuous access filtering module is raised by the rule fence, so that the continuous access mode recognition is more strict, the misjudgment is reduced, the adaptive adjustment of the access mode recognition is realized, and the accuracy of the continuous access mode recognition is improved.

[0156] Specifically, the steps of generating I / O tasks by the hot spot prefetch strategy and the continuous prefetch strategy include:

[0157] The logical block addresses corresponding to the I / O requests pre-stored by the prefetch strategy, the aligned memory huge pages, and the adjacent logically associated data blocks form a hot spot prefetch LBA list;

[0158] If the continuous prefetch strategy is triggered, the logical block addresses pre-prefetched by the continuous prefetch strategy form a continuous prefetch LBA list;

[0159] Each LBA in the hot spot prefetch LBA list and / or the continuous prefetch LBA list is converted into a background I / O task, each task is marked as “prefetch”, and the prefetch source is recorded.

[0160] It should be noted that the hot spot prefetch LBA list is formed by pre-storing the logical block address, aligning the memory large page and the adjacent logical associated data block through the hot spot prefetch strategy, which can effectively cover the potential access range of the hot spot data. Each LBA in the hot spot prefetch LBA list and the continuous prefetch LBA list is converted into a background I / O task, and is marked as “prefetch”, records the prefetch source, and provides a basis for subsequent resource scheduling.

[0161] Specifically, the step of controlling bandwidth by the token bucket algorithm includes:

[0162] An independent token bucket is set for the generated I / O task, and the bucket depth is 1000 tokens, each token representing a prefetch authority of 4kb;

[0163] The token generation rate = reference rate x (1-foreground I / O utilization rate), wherein the foreground I / O utilization rate is obtained in real time through a hardware counter;

[0164] The I / O task can be executed only by consuming tokens, and if there is no available token, it waits until the token is generated.

[0165] It should be noted that in the present embodiment, an independent token bucket is set for the prefetch I / O task, the bucket depth is 1000 tokens, and the reference rate is initialized to 1000 tokens / second. The foreground I / O utilization rate is calculated by reading the active period counter and total time period of the built-in DMA engine of the storage controller. When the prefetch task is generated, tokens need to be applied from the token bucket, if there is no available token in the token bucket, the task enters the waiting queue until the token is generated. Through the dynamic token generation rate and token consumption mechanism, the prefetch bandwidth can be adjusted in real time according to the system load, avoiding excessive resource occupation by prefetch.

[0166] Specifically, the step of constructing a global priority queue by a skip list to realize that the priority of the write task is higher than the priority of the prefetch task includes:

[0167] A 64-bit composite key value is allocated to each I / O task, and the structure is: [8-bit type priority] [32-bit monotonically increasing serial number] [24-bit timeout time];

[0168] The type priority is defined as: synchronous write (0xF0) > asynchronous write (0xE0) > read (0xC0) > prefetch (0x00);

[0169] The skip list is sorted in descending order according to the composite key value, and the scheduler takes out the tasks from the head of the skip list in turn to execute, ensuring that the priority of the write task is higher than the priority of the prefetch task.

[0170] It should be noted that by assigning a 64-bit composite key value to the I / O task and arranging in descending order based on the skip list, it is ensured that the write task priority is higher than the prefetch task. The average O(log n) insertion, deletion and query complexity of the skip list significantly improves the scheduling efficiency of the global priority queue. The type priority field of the composite key value supports flexible expansion, and the priority can be dynamically adjusted according to business needs.

[0171] Specifically, the three-level filtering decision pipeline further includes a rule fence, and the implementation steps of the rule fence include:

[0172] Predefined IF<condition> THEN<action> business rules:

[0173] Rule 1: If <cache hit rate 40% for 60 seconds> THEN <increase the preset threshold T_VAR of the variance σ² of the secondary continuous access filtering module to 1.1×T_VAR>;

[0174] Rule 2: If <cache hit rate> 90% and system memory water level enters high water level marking state> THEN <decrease the upper limit of continuous prefetch depth to 50% of the original upper limit>;

[0175] The rule check is performed by a low-priority background task periodically;

[0176] The rule enters a critical section, and the I / O processing is stopped to ensure the atomicity of parameter adjustment.

[0177] It should be noted that in the embodiment, when the prefetch hit rate is less than 40% for 60 seconds, the variance threshold of the secondary continuous access filtering module is increased, the judgment condition of the continuous access mode is relaxed, and the prefetch coverage range is increased. When the cache hit rate is greater than 90% and the system memory water level enters the high water level marking state, the upper limit of the continuous prefetch depth is decreased to 50% of the original upper limit, and the occupation of the memory by the prefetch data is reduced.

[0178] Embodiment three

[0179] Referring to Figure 2 The embodiment provides a storage device, and the device includes:

[0180] A three-level filtering decision pipeline module 100 is constructed for constructing a three-level filtering decision pipeline, and the three-level filtering decision pipeline includes a first hot spot filtering module, a second continuous access filtering module and a third random access judgment module;

[0181] A hot spot data judgment module 200 is used for inputting an obtained I / O access request into the first hot spot filtering module for hot spot data judgment, triggering a hot spot prefetch strategy if the judgment is yes, and pre-storing data associated with the I / O access request;

[0182] If the judgment is no, the I / O access request is input to the second-level continuous access filtering module for continuous access mode judgment, and if the judgment is yes, a continuous prefetch strategy is triggered to prefetch the next or multiple continuous logical block addresses of the I / O access request.

[0183] If the judgment is no, the I / O access request is input to the third-level random access judgment module, the third-level random access judgment module judges that the access mode is random access mode, and a random processing strategy is triggered to prohibit the prefetch operation.

[0184] The global priority queue module 300 is constructed, the I / O tasks generated by the hot spot prefetch strategy and the continuous prefetch strategy are controlled in bandwidth through the token bucket algorithm, and the global priority queue is constructed through the skip list to realize that the priority of the write task is higher than the priority of the prefetch task.

[0185] Embodiment Four

[0186] The embodiment provides a computer readable storage medium, which stores a computer program. The computer program is executed by a processor to make the processor execute the following method: constructing a three-level filtering decision pipeline, the three-level filtering decision pipeline comprising a first-level hot spot filtering module, a second-level continuous access filtering module and a third-level random access judgment module; inputting an obtained I / O access request to the first-level hot spot filtering module for hot spot data judgment, triggering a hot spot prefetch strategy if the judgment is yes, and pre-storing data associated with the I / O access request; if the judgment is no, inputting the I / O access request to the second-level continuous access filtering module for continuous access mode judgment, triggering a continuous prefetch strategy if the judgment is yes, and prefetching the next or multiple continuous logical block addresses of the I / O access request; if the judgment is no, inputting the I / O access request to the third-level random access judgment module, judging that the access mode is random access mode through the third-level random access judgment module, and triggering a random processing strategy to prohibit the prefetch operation; and constructing a global priority queue through a skip list after the I / O tasks generated by the hot spot prefetch strategy and the continuous prefetch strategy are controlled in bandwidth by a token bucket algorithm, so that the priority of the write task is higher than the priority of the prefetch task.

[0187] Embodiment Five

[0188] Reference is made to Figure 1 , Figure 2 and Figure 3As shown, the embodiment provides a computer device, comprising a memory and a processor, the memory stores a computer program, the computer program is executed by the processor to make the processor execute the following method: constructing a three-level filtering decision pipeline, the three-level filtering decision pipeline comprises a first hot spot filtering module, a second continuous access filtering module and a third random access judgment module; input the obtained I / O access request into the first hot spot filtering module for hot spot data judgment, if it is judged to be, trigger the hot spot prefetch strategy, prestore the data associated with the I / O access request; if it is judged to be not, input the I / O access request into the second continuous access filtering module for continuous access mode judgment, if it is judged to be, trigger the continuous prefetch strategy, prefetch the next or more continuous logical block addresses of the I / O access request; if it is judged to be not, input the I / O access request into the third random access judgment module, judge it to be a random access mode through the third random access judgment module, trigger the random processing strategy to prohibit the prefetch operation; generate the I / O tasks of the hot spot prefetch strategy and the continuous prefetch strategy, control the bandwidth through the token bucket algorithm, then construct a global priority queue through the skip list to realize that the priority of the write task is higher than the priority of the prefetch task.

[0189] It should be noted that the terms "first", "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple", "several" is two or more, unless otherwise explicitly specified.

[0190] It should be understood that the structures, proportions, sizes, etc. shown in the drawings of the present application are only used to cooperate with the disclosed content of the present application, to enable those skilled in the art to understand and read, and are not used to limit the implementation conditions of the present application, so they do not have technical significance. Any modification of structure, change of proportion relationship or adjustment of size, which does not affect the effect and purpose that can be achieved by the present application, should still fall within the scope of the technical content disclosed by the present application.

[0191] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The program can be stored in a non-volatile computer readable storage medium, and when the program is executed, the processes of the above-mentioned embodiment methods can be included. Any reference to memory, storage, database, or other medium used in the embodiments provided in the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0192] Any combination of the technical features of the above embodiments can be made. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combination of the technical features does not exist, it should be considered as the scope of the present application.

[0193] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent of the present application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A memory control method applied to a computer storage system firmware layer under an I / O mixed load, characterized in that, The method comprises: constructing a three-level filtering decision pipeline, which comprises a first-level hot spot filtering module, a second-level continuous access filtering module, and a third-level random access judgment module; inputting the obtained I / O access request into the first-level hot spot filtering module for hot spot data judgment, triggering a hot spot prefetch strategy if the judgment is yes, and pre-storing data associated with the I / O access request; if the judgment is no, inputting the I / O access request into the second-level continuous access filtering module for continuous access mode judgment, triggering a continuous prefetch strategy if the judgment is yes, and prefetching the next or multiple continuous logical block addresses of the I / O access request; if the judgment is no, inputting the I / O access request into the third-level random access judgment module, judging as a random access mode through the third-level random access judgment module, and triggering a random processing strategy to prohibit the prefetch operation; generating I / O tasks of the hot spot prefetch strategy and the continuous prefetch strategy, controlling the bandwidth through a token bucket algorithm, and constructing a global priority queue through a skip list to realize that the priority of a write task is higher than that of a prefetch task; wherein the first-level hot spot filtering module adopts a W-Tiny LFU structure, and the W-Tiny LFU structure comprises: a window cache, which is a small-capacity LRU queue, and is used for recording recently accessed I / O access request entries; a probation queue and a protection queue, which are used to form a main cache, and filter persistent hot spot data through the main cache; a Count-Min Sketch probability data structure, which is used to count the access frequency of all I / O access request entries; wherein the hot spot data judgment through the first-level hot spot filtering module comprises: extracting a unique logical block address identifier of target data from the I / O access request; encapsulating the unique logical block address identifier and an access timestamp as an entry structure of the window cache; inserting a new entry into the head of the LRU queue of the window cache, and updating the position of an existing entry to the head if the logical block address identifier of the new entry already exists in the window cache; when the window cache is full, comparing the frequency of the new entry and an old entry at the tail of the queue; applying the logical block address identifier of the new entry to all hash functions of the Count-Min Sketch to obtain multiple counter positions, reading the counter values of the counter positions, taking the minimum value as the approximate access frequency freq_X of the new entry, applying the logical block address identifier of the old entry at the tail to all hash functions of the Count-Min Sketch to calculate, reading the corresponding counter values, and taking the minimum value as the approximate range frequency freq_Y of the old entry; if freq_X>freq_Y: retaining the new entry and inserting it into the probation queue; if freq_X≤freq_Y: discarding the new entry and retaining the old entry; if the entry in the probation queue is accessed again, it is promoted to the protection queue, and the I / O access request corresponding to the entry in the protection queue is determined as hot spot data; wherein the second-level continuous access filtering module comprises a ring buffer, the size N of the ring buffer is a power of 2, and the ring buffer stores the logical block address difference ΔLBA of nearly N times of I / O access requests. The step of the secondary continuous access filtering module judging the continuous access mode includes: calculating the logical block address difference value of the current I / O access request and the last I / O access request: ΔLBA = current LBA - last LBA; writing ΔLBA into the ring buffer to overwrite the oldest ΔLBA data; calculating the mean μ and variance σ 2 of all ΔLBA in the ring buffer in real time; if σ 2 < preset threshold and μ > 0, it is determined that the continuous access mode is adopted.

2. The memory control method according to claim 1, wherein, The Count-Min Sketch probability data structure further includes a structure optimization step: four hardware-accelerated CRC32C hash functions are used to calculate hash values, and each hash function uses a different initial polynomial to reduce the probability of hash collision; the hash bucket counter uses 4-bit saturated counting, and remains unchanged when the count reaches the maximum value, and the counter is automatically shifted by 1 bit every 1000 accesses to adapt to the change in access frequency; independent Count-Min Sketch copies are divided according to the number of CPU cores, each Count-Min Sketch copy is bound to a corresponding cache line to reduce cross-core delay, and the copies are updated by atomic operation to avoid invalid synchronization; start a low-priority background thread, and merge the counter values of all Count-Min Sketch copies into a global Count-Min Sketch every 10 ms, and use weighted average during merging to ensure statistical accuracy.

3. The memory control method of claim 1, wherein, The pre-stored data associated with the I / O access request includes: prefetching the logical block address itself corresponding to the I / O access request, and prefetching the aligned memory huge page and / or adjacent logical associated data block where the logical block address of the I / O access request is located.

4. The memory control method of claim 1, wherein, The optimization step of the ring buffer includes: the read-write index update of the ring buffer is realized through double Compare-And-Swap atomic operation, which checks whether the current index value is as expected, and then updates it to a new value, if the check fails, an exponential backoff retry is triggered to reduce the race condition; through a multi-producer single-consumer lock-free queue architecture, each producer maintains an independent temporary write buffer, and after the buffer is full, it is submitted to the ring buffer in batches through atomic operation to reduce the conflict between producers; adjust the size of the ring buffer dynamically according to the front-end I / O utilization rate of the system, expand it to 256 entries when the utilization rate is less than 20%, and reduce it to 64 entries when the utilization rate is higher than 80%, and when adjusting, switch the buffer pointer through atomic operation to ensure seamless transition of read-write operations; the read operation of the ring buffer adopts a snapshot mechanism, when reading, first get the snapshot of the current write index, and then read the data based on the snapshot range to avoid interference, and at the same time, the read operation preferentially uses the cache copy of the local core to reduce global memory access.

5. The memory control method of claim 1, wherein, The steps of the triggered continuous prefetch strategy include: prefetch depth = 2 + (μ / 4KB); the prefetch depth does not exceed the prefetch upper limit configured by the firmware through the register; prefetch the next or multiple consecutive logical block addresses.

6. The memory control method of claim 1, wherein, The steps of the tertiary random access judgment module judging the random access mode and triggering the random processing strategy to prohibit the prefetch operation include: Stop all prefetch operations; Start local learner, record LBA access distribution in short time; If there is a small cluster in LBA access distribution, trigger limited depth exploratory prefetch.

7. The memory control method of claim 1, wherein, The three-level random access judgment module starts a low-priority background calibration task when judging that the I / O request is in a random access mode, and the execution steps of the low-priority background calibration task include: Obtaining the system foreground I / O utilization rate to adjust the sampling period, if the current utilization rate is lower than 20%, the sampling period is 1 second, if the current utilization rate is higher than 80%, the sampling period is 10 seconds, the foreground I / O utilization rate is obtained by reading the active period counter of the built-in DMA engine of the storage controller or the non-empty period counter of the I / O queue, and then dividing by the total time period; In each sampling period, the logical block address sequence corresponding to all I / O access requests in the past time period equal to the cycle length is collected, and the logical block address sequence is stored in the ring buffer statically allocated by the firmware; The LBA sequence obtained by sampling is divided into LBA intervals of a fixed size, the number of accesses to each interval is counted, the access frequency of each interval is calculated, and the Shannon entropy value of the LBA sequence is calculated; If the Shannon entropy value is continuously higher than the preset threshold value, and the number of random IOs per million IOs calculated by the system is continuously higher than the preset value, the variance threshold value of the second continuous access filtering module is raised by a rule fence.

8. The memory control method of claim 1, wherein, The steps of the I / O tasks generated by the hot spot prefetch strategy and the continuous prefetch strategy include: The logical block address, aligned memory large page, and adjacent logical associated data block corresponding to the I / O request pre-stored by the prefetch strategy form a hot spot prefetch LBA list; If the continuous prefetch strategy is triggered, the logical block address pre-fetched by the continuous prefetch strategy forms a continuous prefetch LBA list; Each LBA in the hot spot prefetch LBA list and / or the continuous prefetch LBA list is converted into a background I / O task, each task is marked as "prefetch", and the prefetch source is recorded.

9. The memory control method of claim 1, wherein, The steps of controlling the bandwidth by the token bucket algorithm include: An independent token bucket is set for the generated I / O task, the bucket depth is 1000 tokens, and each token represents a prefetch authority of 4kb; The token generation rate = reference rate x (1-foreground I / O utilization rate), wherein the foreground I / O utilization rate is obtained in real time by a hardware counter; The I / O task can be executed only by consuming tokens, and if there is no available token, it will wait until a token is generated.

10. The memory control method of claim 1, wherein, The steps of constructing a global priority queue by a skip list to realize that the priority of a write task is higher than that of a prefetch task include: A 64-bit composite key value is allocated to each I / O task, and the structure is: [8-bit type priority] [32-bit monotonically increasing sequence number] [24-bit timeout time]; The type priority is defined as: synchronous write > asynchronous write > read > prefetch; The skip list is sorted in descending order according to the composite key value, and the scheduler takes out the tasks from the head of the skip list in turn to execute, ensuring that the priority of a write task is higher than that of a prefetch task.

11. The memory control method of claim 1, wherein, The three-level filtering decision pipeline further includes a rule fence, and the implementation steps of the rule fence include: Predefining IF<condition> THEN<action> business rules: Rule 1: If <Prefetch Hit Ratio 40% for 60 seconds> THEN <Increase the default threshold T_VAR of variance σ² of the secondary sequential access filter module to 1.1×T_VAR>; Rule 2: If <Cache Hit Ratio >90% and system memory water level enters high water level mark state> THEN <Decrease the upper limit of sequential prefetch depth to 50% of the original upper limit>; The rule check is performed by a low-priority background task periodically; The rule is executed into a critical section, and I / O processing is stopped to ensure the atomicity of parameter adjustment.

12. A memory device, comprising: The apparatus is applied to the memory control method in any one of claims 1 to 10, and the apparatus comprises: A three-level filter decision pipeline module is constructed to construct a three-level filter decision pipeline, and the three-level filter decision pipeline comprises a first hot spot filter module, a second sequential access filter module, and a third random access judgment module. A hot spot data judgment module is configured to input the obtained I / O access request into the first hot spot filter module to perform hot spot data judgment, and if the judgment result is yes, a hot spot prefetch strategy is triggered to pre-store data associated with the I / O access request. If the judgment result is no, the I / O access request is input into the second sequential access filter module to perform sequential access mode judgment, and if the judgment result is yes, a sequential prefetch strategy is triggered to prefetch the next or multiple continuous logical block addresses of the I / O access request. If the judgment result is no, the I / O access request is input into the third random access judgment module, and the third random access judgment module judges that the access mode is random access mode, and a random processing strategy is triggered to prohibit the prefetch operation. A global priority queue module is constructed, and after the I / O tasks generated by the hot spot prefetch strategy and the sequential prefetch strategy are controlled in bandwidth by a token bucket algorithm, a global priority queue is constructed by a skip list to realize that the priority of a write task is higher than the priority of a prefetch task.

13. A computer-readable storage medium, characterized in that, A computer program is stored, and the computer program is executed by a processor to enable the processor to perform the steps of the method in any one of claims 1 to 10.

14. A computer device, comprising: A memory and a processor are included, the memory stores a computer program, and the computer program is executed by the processor to enable the processor to perform the steps of the method in any one of claims 1 to 10.

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