A method and system for improving the reliability of operational data from electricity meters and terminals.
By selecting anti-mechanical stress chip capacitors, optimizing PCB layout, and configuring high-performance power chips, combined with multi-factor fault tolerance judgment and self-diagnosis, the mechanical stress and voltage instability problems of the electricity meter were solved, improving the operational reliability and data integrity of the electricity meter.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN YINJUN TECH
- Filing Date
- 2025-12-26
- Publication Date
- 2026-05-26
AI Technical Summary
Existing electricity meters have weak resistance to mechanical stress, are prone to micro-cracks, have excessively small pad spacing leading to leakage or short circuit risks, are easily damaged by filters, and lack fault tolerance in software logic, making it impossible to compensate for hardware failures in real time, resulting in metering errors and data loss.
It adopts chip capacitors with strong resistance to mechanical stress and thermal shock, optimizes PCB layout, configures high-performance power chips and voltage detection circuits to dynamically monitor voltage stability, connects energy storage capacitors in parallel, constructs multi-factor collaborative fault-tolerant judgment logic, inserts delay and high fault-tolerant coding, and performs periodic self-diagnosis and early warning.
It improves the stability of electricity meter and terminal operation, reduces the incidence of data loss and metering errors, and ensures the integrity of electricity data and the reliability of the system.
Smart Images
Figure CN121413552B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electricity meter data operation technology, and in particular to a method and system for improving the reliability of electricity meter and terminal operation data. Background Technology
[0002] Electricity meters are typically used to measure electricity consumption data in power systems and monitor the operating status of electricity. The accuracy of their measurement and the stability of their data storage determine the fairness between electricity supply and demand. In the internal circuit design of smart electricity meters, filter capacitors are usually configured to provide a stable operating voltage for key functional chips such as EEPROM. As a core storage component, EEPROM stores important information such as the first power-on identifier, which has a critical impact on the security of electricity data.
[0003] Existing electricity meters have the following shortcomings: First, conventional capacitors have weak resistance to mechanical stress and are prone to micro-cracks during production or assembly. After the subsequent board washing process, moisture or residual washing water from the environment can seep into the dielectric layer inside the capacitor through these micro-cracks, causing the capacitor's equivalent series resistance to rise sharply and ultimately resulting in the loss of its filtering and voltage regulation function. Second, to achieve miniaturization of electricity meters, the spacing between the pads of the filter capacitors is designed to be too small, and there is no copper-free zone set in the PCB for this area. This leads to a compression of the creepage distance between the pads after subsequent copper-laying processes, increasing the risk of leakage or direct short circuits between pads due to contaminants. In addition, if the electrolytic capacitors are placed near relays, etc., it is easy to cause... Devices subjected to vibration or heat radiation will continuously endure mechanical compression or thermal stress during operation, leading to damage to the capacitor sealing structure and ultimately capacitor failure. Thirdly, the software logic lacks the ability to perceive and tolerate hardware faults. When the filter capacitor fails, causing the EEPROM power supply voltage to become unstable, resulting in the failure to read the identifier, the system will mistakenly identify it as the device's first power-on and trigger a power reset operation. At the same time, the coding design of the program branch conditions is not fault-tolerant enough and is easily affected by power supply voltage fluctuations, causing the program to jump to an incorrect execution flow. Furthermore, the existing fault diagnosis system for electricity meters focuses on post-event analysis and compensation, and cannot perform compensation operations during the event, which has limitations. Summary of the Invention
[0004] The purpose of this invention is to provide a method and system for improving the reliability of operational data from electricity meters and terminals, in order to solve the problems mentioned in the background art.
[0005] To achieve the above objectives, the present invention provides the following technical solution: a method and system for improving the reliability of operational data from electricity meters and terminals, comprising:
[0006] S1. Select capacitors and improve processes. Select chip capacitors with strong resistance to mechanical stress and thermal shock as key filter capacitors. Introduce non-destructive testing for internal cracks of capacitors and strengthen drying processes in the production process.
[0007] S2, PCB anti-contamination layout and stress resistance enhancement: In the PCB layout, a no-copper-pour-area area is set between the pads of the filter capacitor, and mechanical buffering and thermal isolation measures are applied to the electrolytic capacitor.
[0008] S3. Configure and dynamically monitor the chip, configure the power chip with load capacity and transient response characteristics for the EEPROM, and dynamically monitor its voltage stability during power-on and read / write operations.
[0009] S4. Power failure data writing: An energy storage capacitor is connected in parallel at the input of the power chip to provide sufficient energy when the main power supply fails, ensuring that the EEPROM completes the last data writing operation.
[0010] S5. Multi-factor collaborative fault-tolerant judgment: Construct and execute collaborative judgment logic, and allow the clearing operation only when all multi-factor conditions meet the preset threshold.
[0011] S6. Delay insertion and encoding scheme definition: Insert a preset delay before nodes involving critical branch judgments in the program execution path to allow power and signal stabilization; and define a highly fault-tolerant encoding scheme for the branch judgment conditions.
[0012] S7. Monitor and issue early warnings, and periodically perform self-diagnosis on the system. When an anomaly is detected, record the fault, restrict non-core functions, and attempt to maintain basic metering, while generating and reporting fault warning information.
[0013] Preferably, in step S1, the chip capacitor is an X7R multilayer ceramic chip capacitor.
[0014] Preferably, in step S1, the capacitors after mounting are sampled and inspected using an acoustic scanning microscope, and a vacuum drying and stepped temperature baking process is added after the circuit board cleaning process.
[0015] Preferably, in step S2, a copper-free zone with a width of not less than 0.5 mm is set between the two pads of the filter capacitor, the minimum distance between the electrolytic capacitor and components that are prone to vibration and heat is not less than 3 mm, and flexible silicone pads are added between the electrolytic capacitor and the vibrating components for mechanical buffering, and heat insulation pads are added between the electrolytic capacitor and the heat-generating components for physical heat insulation.
[0016] Preferably, in step S2, electrolytic capacitors are avoided within 5mm of the PCB edge. For capacitors that must be placed on the board edge, a half-hole process is used for metal edging.
[0017] Preferably, the power chip used in step S3 is a voltage chip, and a voltage detection circuit is integrated on the energy meter. The voltage detection circuit is electrically connected to the voltage chip and is used to monitor the voltage of the EEPROM.
[0018] Preferably, in step S5, the multi-factor conditions include the reading status of the first power-on identifier, the cumulative running time recorded by the real-time clock, and the consistency of the historical power data stored in the EEPROM. The zeroing operation is only allowed when all multi-factor conditions meet the preset threshold.
[0019] Preferably, in step S6, the preset delay is 10-100ms; the high-fault-tolerant encoding scheme is Gray code.
[0020] Preferably, in step S7, the self-test types include voltage monitoring and data integrity verification.
[0021] Preferably, the system includes:
[0022] High-reliability hardware module: This module uses surface-mount capacitors that are resistant to mechanical stress and thermal shock, optimizes the PCB layout, and adds buffering and heat insulation measures for electrolytic capacitors;
[0023] Optimized power management module: This module ensures a stable and sufficient operating voltage for the EEPROM by configuring a high-performance voltage chip power supply chip and connecting an energy storage capacitor in parallel at its input, and provides backup energy when the main power supply fails.
[0024] Dynamic voltage monitoring module: This module is used to periodically monitor the power supply voltage to the EEPROM and other key chips;
[0025] Multi-factor collaborative judgment module: This module runs in the MCU and its function is to make a comprehensive logical judgment based on multi-dimensional information to determine whether to perform the zeroing operation;
[0026] Program flow fault tolerance control module: This module runs in the MCU. Its function is to insert a delay before the critical branch judgment to wait for the signal to stabilize, and to define the branch judgment conditions using a highly fault-tolerant coding scheme.
[0027] Self-diagnosis and early warning management module: This module runs in the MCU and its function is to periodically perform system self-checks and automatically trigger corresponding measures when an anomaly is detected.
[0028] The technical effects and advantages of this invention are as follows:
[0029] 1. This invention combines hardware and software to form a complete protection system that includes hardware anti-interference, power supply stability, software fault tolerance, and fault early warning. This system improves the operational stability of electricity meters and terminals, reduces the incidence of data loss and metering errors, and meets the needs of users.
[0030] 2. By selecting X7R multilayer ceramic chip capacitors with strong resistance to mechanical stress and thermal shock, and introducing non-destructive testing with acoustic scanning microscope and enhanced drying process, this invention can reduce the probability of micro-cracks in the capacitor during the production and assembly process, while removing residual washing water and moisture, preventing the capacitor dielectric layer from being damaged by moisture, and reducing the risk of abnormal increase in the capacitor's equivalent series resistance.
[0031] 3. This invention ensures sufficient creepage distance by setting a no-copper zone between solder pads, thus preventing leakage or short circuits between solder pads caused by contaminants; and by using flexible silicone pads and heat insulation pads to buffer the impact of mechanical vibration and heat radiation on electrolytic capacitors, preventing damage to the capacitor sealing structure, extending the capacitor's service life, and ensuring the stability of the hardware system.
[0032] 4. By configuring a high-performance voltage chip power supply chip and voltage detection circuit, this invention can dynamically monitor the voltage stability of the EEPROM during power-on and read / write operations, and can promptly detect hardware-related faults such as voltage anomalies and data corruption. Furthermore, through the energy storage capacitor, it ensures that data will not be lost due to voltage fluctuations and power outages when the main power supply fails. Moreover, through multi-factor collaborative fault tolerance judgment, it avoids erroneous zeroing operations caused by failure to read the identifier due to voltage instability, thus ensuring the integrity of power data and meeting user needs. Attached Figure Description
[0033] Figure 1 This is a schematic diagram of the overall process of the present invention;
[0034] Figure 2 This is a flowchart illustrating the hardware hardening implementation of the present invention;
[0035] Figure 3 This is a flowchart illustrating the power management and data protection process of this invention.
[0036] Figure 4 This is a flowchart of the multi-factor fault tolerance judgment process of the present invention;
[0037] Figure 5 This is a flowchart illustrating the fault tolerance and self-diagnosis process of the present invention.
[0038] Figure 6 This is a system module architecture diagram of the present invention. Detailed Implementation
[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0040] This invention provides, for example Figure 1 The method and system thereof for improving the reliability of operating data of electricity meters and terminals, as shown, include:
[0041] S1. Select capacitors and improve processes. Select chip capacitors with strong resistance to mechanical stress and thermal shock as key filter capacitors. Introduce non-destructive testing for internal cracks of capacitors and strengthen drying processes in the production process.
[0042] S2, PCB anti-contamination layout and stress resistance enhancement: In the PCB layout, a no-copper-pour-area area is set between the pads of the filter capacitor, and mechanical buffering and thermal isolation measures are applied to the electrolytic capacitor.
[0043] S3. Configure and dynamically monitor the chip, configure the power chip with load capacity and transient response characteristics for the EEPROM, and dynamically monitor its voltage stability during power-on and read / write operations.
[0044] S4. Power failure data writing: An energy storage capacitor is connected in parallel at the input of the power chip to provide sufficient energy when the main power supply fails, ensuring that the EEPROM completes the last data writing operation.
[0045] S5. Multi-factor collaborative fault-tolerant judgment: Construct and execute collaborative judgment logic, and allow the clearing operation only when all multi-factor conditions meet the preset threshold.
[0046] S6. Delay insertion and encoding scheme definition: Insert a preset delay before nodes involving critical branch judgments in the program execution path to allow power and signal stabilization; and define a highly fault-tolerant encoding scheme for the branch judgment conditions.
[0047] S7. Monitor and issue early warnings, and periodically perform self-diagnosis on the system. When an anomaly is detected, record the fault, restrict non-core functions, and attempt to maintain basic metering, while generating and reporting fault warning information.
[0048] Example 1: In this example, firstly, capacitor selection and process improvement are implemented, using X7R or X8R multilayer ceramic chip capacitors as the main capacitors, and introducing non-destructive testing and enhanced drying processes; secondly, the PCB layout is optimized, setting a copper-free area for filter capacitors, and stress-resistant measures are taken for electrolytic capacitors; next, a voltage chip power supply chip is configured to power the EEPROM, which can accurately match the voltage, while the integrated voltage detection circuit dynamically monitors the voltage; then, an energy storage capacitor is connected in parallel at the input of the voltage chip power supply chip to ensure that the EEPROM can complete the last data write when the main power supply fails; then, a multi-factor collaborative judgment logic is used to control the clearing operation to avoid the system misjudging the first power-on and performing the clearing operation when the power supply is unstable due to capacitor failure, causing the flag to fail to read, thus preventing the system from performing the clearing operation; then, a 10-100ms delay is inserted before the critical branches of the program, and Gray code is used to define the judgment conditions; finally, the system self-diagnosis is performed periodically, and when abnormalities occur, faults are recorded, functions are restricted, and warnings are reported.
[0049] like Figures 2 to 3 The method and system thereof for improving the reliability of operating data of electricity meters and terminals, as shown, include:
[0050] S1. Select capacitors and improve processes. Select chip capacitors with strong resistance to mechanical stress and thermal shock as key filter capacitors. Introduce non-destructive testing for internal cracks of capacitors and strengthen drying processes in the production process.
[0051] S2, PCB anti-contamination layout and stress resistance enhancement: In the PCB layout, a no-copper-pour-area area is set between the pads of the filter capacitor, and mechanical buffering and thermal isolation measures are applied to the electrolytic capacitor.
[0052] S3. Configure and dynamically monitor the chip, configure the power chip with load capacity and transient response characteristics for the EEPROM, and dynamically monitor its voltage stability during power-on and read / write operations.
[0053] S4. Power failure data writing: An energy storage capacitor is connected in parallel at the input of the power chip to provide sufficient energy when the main power supply fails, ensuring that the EEPROM completes the last data writing operation.
[0054] S5. Multi-factor collaborative fault-tolerant judgment: Construct and execute collaborative judgment logic, and allow the clearing operation only when all multi-factor conditions meet the preset threshold.
[0055] S6. Delay insertion and encoding scheme definition: Insert a preset delay before nodes involving critical branch judgments in the program execution path to allow power and signal stabilization; and define a highly fault-tolerant encoding scheme for the branch judgment conditions.
[0056] S7. Monitor and issue early warnings, and periodically perform self-diagnosis on the system. When an anomaly is detected, record the fault, restrict non-core functions, and attempt to maintain basic metering, while generating and reporting fault warning information.
[0057] In step S1, the chip capacitor is an X7R multilayer ceramic chip capacitor.
[0058] In step S1, the capacitors after being mounted are sampled and inspected using an acoustic scanning microscope. After the circuit board cleaning process, a vacuum drying and stepped temperature baking process is added.
[0059] In step S2, a copper-free zone with a width of not less than 0.5mm is set between the two pads of the filter capacitor. The minimum distance between the electrolytic capacitor and components that are prone to vibration and heat is not less than 3mm. Flexible silicone pads are added between the electrolytic capacitor and the vibrating components for mechanical buffering, and heat insulation pads are added between the electrolytic capacitor and the heat-generating components for physical heat insulation.
[0060] In step S2, avoid placing electrolytic capacitors within 5mm of the PCB edge. For capacitors that must be placed on the board edge, use a half-hole process for metal edging.
[0061] The power chip used in step S3 is a voltage chip. A voltage detection circuit is integrated on the energy meter. The voltage detection circuit is electrically connected to the voltage chip and is used to monitor the voltage of the EEPROM.
[0062] The system includes:
[0063] High-reliability hardware module: This module uses surface-mount capacitors that are resistant to mechanical stress and thermal shock, optimizes the PCB layout, and adds buffering and heat insulation measures for electrolytic capacitors;
[0064] Optimized power management module: This module ensures a stable and sufficient operating voltage for the EEPROM by configuring a high-performance voltage chip power supply chip and connecting an energy storage capacitor in parallel at its input, and provides backup energy when the main power supply fails.
[0065] Dynamic voltage monitoring module: This module is used to periodically monitor the power supply voltage to the EEPROM and other key chips;
[0066] Multi-factor collaborative judgment module: This module runs in the MCU and its function is to make a comprehensive logical judgment based on multi-dimensional information to determine whether to perform the zeroing operation;
[0067] Program flow fault tolerance control module: This module runs in the MCU. Its function is to insert a delay before the critical branch judgment to wait for the signal to stabilize, and to define the branch judgment conditions using a highly fault-tolerant coding scheme.
[0068] Self-diagnosis and early warning management module: This module runs in the MCU and its function is to periodically perform system self-checks and automatically trigger corresponding measures when an anomaly is detected.
[0069] Example 2: In this example, X7R multilayer ceramic chip capacitors are used as the key filter capacitors. Non-destructive testing for internal cracks and enhanced drying processes are introduced into the production process. Specifically, the non-destructive testing involves sampling the surface-mounted capacitors using an acoustic scanning microscope. Internal microcracks are identified by analyzing ultrasonic echo signals, allowing for the timely removal of defective products. After the circuit board cleaning process, a vacuum drying and stepped temperature baking process is added. The temperature curve for the stepped temperature baking needs precise control, increasing the temperature from room temperature to 125°C at a rate not exceeding 3°C / minute and holding for 2 hours to ensure the removal of moisture and cleaning agents within the capacitor's dielectric layer. All residual solder paste must be completely evaporated and discharged to prevent crack propagation due to vaporization and expansion during subsequent use. For all filter capacitors, a no-copper zone with a width of not less than 0.5mm should be set between their two pads to increase the creepage distance and reduce the risk of leakage or short circuits caused by solder paste residue, dust, and other contaminants. Filter capacitors should maintain a distance of at least 3mm from relays, transformers, and other components that are prone to vibration or heat. If the distance cannot be met, a flexible silicone pad should be added between the capacitor and the vibration source for mechanical buffering. Electrolytic capacitors and heat-generating components should be physically insulated with thermal pads made of ceramic fiber, which can achieve both buffering and heat insulation effects. Avoid placing electrolytic capacitors within 5mm of the PCB edge. For capacitors that must be placed on the board edge, use a half-hole process for metal edging or locally thicken the solder resist ink to enhance their resistance to mechanical impact.
[0070] The selection of voltage chips to power EEPROM should not only be based on the datasheet, but also require the use of an oscilloscope to measure the voltage drop of the EEPROM power pins during power-on and read / write operations under actual load circuit conditions. This ensures that the selected voltage chip maintains a stable output voltage at the EEPROM operating voltage under maximum dynamic load.
[0071] like Figures 4 to 6 The method and system thereof for improving the reliability of operating data of electricity meters and terminals, as shown, include:
[0072] S1. Select capacitors and improve processes. Select chip capacitors with strong resistance to mechanical stress and thermal shock as key filter capacitors. Introduce non-destructive testing for internal cracks of capacitors and strengthen drying processes in the production process.
[0073] S2, PCB anti-contamination layout and stress resistance enhancement: In the PCB layout, a no-copper-pour-area area is set between the pads of the filter capacitor, and mechanical buffering and thermal isolation measures are applied to the electrolytic capacitor.
[0074] S3. Configure and dynamically monitor the chip, configure the power chip with load capacity and transient response characteristics for the EEPROM, and dynamically monitor its voltage stability during power-on and read / write operations.
[0075] S4. Power failure data writing: An energy storage capacitor is connected in parallel at the input of the power chip to provide sufficient energy when the main power supply fails, ensuring that the EEPROM completes the last data writing operation.
[0076] S5. Multi-factor collaborative fault-tolerant judgment: Construct and execute collaborative judgment logic, and allow the clearing operation only when all multi-factor conditions meet the preset threshold.
[0077] S6. Delay insertion and encoding scheme definition: Insert a preset delay before nodes involving critical branch judgments in the program execution path to allow power and signal stabilization; and define a highly fault-tolerant encoding scheme for the branch judgment conditions.
[0078] S7. Monitor and issue early warnings, and periodically perform self-diagnosis on the system. When an anomaly is detected, record the fault, restrict non-core functions, and attempt to maintain basic metering, while generating and reporting fault warning information.
[0079] In step S5, the multi-factor conditions include the reading status of the first power-on identifier, the cumulative running time recorded by the real-time clock, and the consistency of the historical power data stored in the EEPROM. The zeroing operation is only allowed when all multi-factor conditions meet the preset threshold. In step S6, the preset delay is 10-100ms; the high-fault-tolerant encoding scheme is Gray code. In step S7, the self-test types include voltage monitoring and data integrity verification.
[0080] Example 3: This method, by configuring a high-performance voltage chip power supply chip and voltage detection circuit, can dynamically monitor the voltage stability of the EEPROM during power-on and read / write operations, and can detect faults in a timely manner. Furthermore, through the energy storage capacitor, it ensures that data will not be lost due to voltage fluctuations and power outages when the main power supply fails. Moreover, through multi-factor collaborative fault tolerance judgment, it avoids erroneous zeroing operations caused by failure to read the identifier due to voltage instability, thus ensuring the integrity of power data and meeting user needs.
[0081] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A method for improving the reliability of operational data from electricity meters and terminals, characterized in that, include: S1. Select capacitors and improve processes. Select chip capacitors with strong resistance to mechanical stress and thermal shock as key filter capacitors. Introduce non-destructive testing for internal cracks of capacitors and strengthen drying processes in the production process. S2, PCB anti-contamination layout and stress resistance enhancement: In the PCB layout, a no-copper-pour-area area is set between the pads of the filter capacitor, and mechanical buffering and thermal isolation measures are applied to the electrolytic capacitor. S3. Configure and dynamically monitor the chip, configure the power chip with load capacity and transient response characteristics for the EEPROM, and dynamically monitor its voltage stability during power-on and read / write operations. S4. Power failure data writing: An energy storage capacitor is connected in parallel at the input of the power chip to provide sufficient energy when the main power supply fails, ensuring that the EEPROM completes the last data writing operation. S5. Multi-factor collaborative fault-tolerant judgment: Construct and execute collaborative judgment logic, and allow the clearing operation only when all multi-factor conditions meet the preset threshold. S6. Delay insertion and encoding scheme definition: Insert a preset delay before nodes involving critical branch judgments in the program execution path to allow power and signal stabilization; and define a highly fault-tolerant encoding scheme for the branch judgment conditions. S7. Monitor and issue early warnings, and periodically perform self-diagnosis of the system; When an anomaly is diagnosed, the fault is recorded, non-core functions are restricted and an attempt is made to maintain basic metering, while fault warning information is generated and reported. In step S1, the chip capacitor is an X7R multilayer ceramic chip capacitor; In step S2, a copper-free zone with a width of not less than 0.5mm is set between the two pads of the filter capacitor. The minimum distance between the electrolytic capacitor and components that are prone to vibration and heat is not less than 3mm. Flexible silicone pads are added between the electrolytic capacitor and the vibrating components for mechanical buffering, and heat insulation pads are added between the electrolytic capacitor and the heat-generating components for physical heat insulation. In step S5, the multi-factor conditions include the reading status of the first power-on identifier, the cumulative running time recorded by the real-time clock, and the consistency of the historical power data stored in the EEPROM. The zeroing operation is only allowed when all multi-factor conditions meet the preset threshold.
2. The method for improving the reliability of electricity meter and terminal operation data according to claim 1, characterized in that, In step S1, the capacitors after being mounted are sampled and inspected using an acoustic scanning microscope. After the circuit board cleaning process, a vacuum drying and stepped temperature baking process is added.
3. The method for improving the reliability of electricity meter and terminal operation data according to claim 1, characterized in that, In step S2, avoid placing electrolytic capacitors within 5mm of the PCB edge. For capacitors that must be placed on the board edge, use a half-hole process for metal edging.
4. The method for improving the reliability of electricity meter and terminal operation data according to claim 1, characterized in that, The power chip used in step S3 is a voltage chip. A voltage detection circuit is integrated on the energy meter. The voltage detection circuit is electrically connected to the voltage chip and is used to monitor the voltage of the EEPROM.
5. The method for improving the reliability of electricity meter and terminal operation data according to claim 1, characterized in that, In step S6, the preset delay is 10-100ms; the high-fault-tolerant encoding scheme is Gray code.
6. The method for improving the reliability of electricity meter and terminal operation data according to claim 1, characterized in that, In step S7, the types of self-tests include voltage monitoring and data integrity verification.
7. A system for improving the reliability of operational data from electricity meters and terminals, used to execute the method for improving the reliability of operational data from electricity meters and terminals as described in any one of claims 1-6, characterized in that, include: High-reliability hardware module: This module uses surface-mount capacitors that are resistant to mechanical stress and thermal shock, optimizes the PCB layout, and adds buffering and heat insulation measures for electrolytic capacitors; Optimized power management module: This module ensures a stable and sufficient operating voltage for the EEPROM by configuring a high-performance voltage chip power supply chip and connecting an energy storage capacitor in parallel at its input, and provides backup energy when the main power supply fails. Dynamic voltage monitoring module: This module is used to periodically monitor the power supply voltage to the EEPROM and other key chips; Multi-factor collaborative judgment module: This module runs in the MCU and its function is to make a comprehensive logical judgment based on multi-dimensional information to determine whether to perform the zeroing operation; Program flow fault tolerance control module: This module runs in the MCU. Its function is to insert a delay before the critical branch judgment to wait for the signal to stabilize, and to define the branch judgment conditions using a coding scheme with high fault tolerance. Self-diagnosis and early warning management module: This module runs in the MCU and its function is to periodically perform system self-checks and automatically trigger corresponding measures when an anomaly is detected.