Cache lock group, memory and electronic equipment

Abstract

The invention relates to a cache lock group, a memory and electronic equipment, the cache lock group is applied to a flash memory array, each bit line in the flash memory array is connected with one cache lock group, a cache lock group circuit comprises at least five latch circuits, a first transistor and a second transistor, and each latch circuit comprises a cross-coupled inverter; the first end of the cross-coupled inverter of one latch circuit is connected with the first end of the first transistor, the second end of the first transistor is connected with the first end of the second transistor, the second end of the second transistor is grounded, and the control end of the first transistor is connected with the first end of the cross-coupled inverter of the other latch circuit. The control end of the second transistor receives an XOR control signal, and the XOR control signal is used for activating XOR operation. According to the cache lock group disclosed by the embodiment of the invention, the data calculation can be unloaded into the flash memory chip, the transmission quantity of the data from the storage chip to a flash memory device processor and a host is reduced, and the system performance is improved.

Description

Technical Field

[0001] This disclosure relates to the field of storage technology, and in particular to a cache lock group, a memory, and an electronic device. Background Technology

[0002] Flash memory is an electronically erasable programmable memory. Compared to traditional hard disk media, flash memory features high read / write bandwidth, low access latency, low power consumption, and high stability, and is now widely used in data centers, personal computers, and mobile devices. The high bandwidth and low latency of flash memory devices are due to the parallel operation of numerous flash memory chips and a multi-channel architecture. This means that a flash memory device has multiple channels connecting to the storage medium, with multiple flash memory chips connected to each channel. This design allows multiple flash memory chips to process data transmission simultaneously, significantly improving parallel processing capabilities. Combined with efficient controller optimization and caching mechanisms, flash memory devices can read and write data at faster speeds, reduce access latency, and exhibit higher performance.

[0003] Each flash memory chip consists of multiple flash planes, each containing a flash array with numerous bit lines (e.g., 32K to 128K bit lines) and word lines (e.g., more than 2K word lines). The flash planes connect to peripheral circuitry, including address unlocking units and cache lock arrays. Each bit line of the flash array is connected to a set of latch circuits in the cache lock array. Its function in flash read and write operations is as follows: when reading, data is stored from the flash cell to the latch circuit and then sent to the flash device controller; when writing, data is stored from the flash device controller to the latch circuit, and the data is stored in the memory cell according to the circuit state. Due to write, buffer, and parallel operations, currently common three-level cell (TLC) flash memory can contain four to six latch circuits in the cache lock of each bit line.

[0004] To further improve the performance of storage devices, in-memory computing methods in related technologies offload computing tasks to the controller of the storage device or to the storage medium chip.

[0005] One method to offload computing tasks to the storage device controller is to add additional computing processors or computing units to the controller, allowing data to be read from the storage medium and transferred to the computing unit for processing. However, for flash memory devices with multi-channel architectures and multiple flash chips operating in parallel, this method still incurs significant data migration overhead from the storage medium to the storage device processor.

[0006] Another method for offloading computational tasks to the storage medium chip involves adding extra computing units or hardware devices, significantly increasing chip area and power consumption, making it difficult to implement and widely adopted. Other technologies utilize the storage medium's own operations for computation offloading. For example, binary gate operations are implemented based on multiple flash reads and cache lock control. However, various types of gate operations require numerous read operations, severely increasing computational latency and making it difficult to further extend these gate operations.

[0007] The methods in related technologies are still limited to binary gate operations, and applying such operations to more advanced data processing requires a significant amount of time. Summary of the Invention

[0008] In view of this, the present disclosure proposes a cache lock group, a memory, and an electronic device.

[0009] According to one aspect of this disclosure, a cache latch group is provided, the cache latch group being applied to a flash memory array, wherein each bit line in the flash memory array is connected to a cache latch group, the cache latch group circuit including at least five latch circuits, a first transistor, and a second transistor, each latch circuit including a cross-coupled inverter; wherein, a first terminal of the cross-coupled inverter of one latch circuit is connected to a first terminal of the first transistor, a second terminal of the first transistor is connected to a first terminal of the second transistor, a second terminal of the second transistor is grounded, a control terminal of the first transistor is connected to a first terminal of the cross-coupled inverter of another latch circuit, and a control terminal of the second transistor receives an XOR control signal, the XOR control signal being used to activate an XOR operation.

[0010] In one possible implementation, each latch circuit further includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; wherein, the first terminal of the cross-coupled inverter is connected to the first terminal of the fifth transistor, the second terminal of the cross-coupled inverter is connected to the control terminal of the seventh transistor and the first terminal of the fourth transistor, the first terminal of the seventh transistor is connected to the second terminal of the third transistor, the second terminal of the seventh transistor is grounded, the second terminals of the fourth transistor and the fifth transistor are connected to the first terminal of the sixth transistor, the second terminal of the sixth transistor is grounded, the first terminal of the third transistor and the control terminal of the sixth transistor are connected to a bit line, the control terminal of the third transistor receives an output control signal, the output control signal is used to output the current data latched by the latch circuit, the control terminal of the fourth transistor receives a first control signal, the first control signal is used to store data when reading data, and the control terminal of the fifth transistor receives a second control signal, the second control signal is used to store the toggled data when reading data.

[0011] In one possible implementation, the cache lock group performs at least one of the following bit operations according to the instruction of the control signal from the controller: reading data from the bit line and storing it in at least one latch circuit; transferring data from one latch circuit to at least another latch circuit; performing binary gate operations on the data stored in the two latch circuits and storing the gate operation result in at least one latch circuit, the binary gate operations including AND, OR, and XOR.

[0012] In one possible implementation, with the first terminal of the first transistor connected to the first terminal of the cross-coupled inverter of the second latch circuit, and the control terminal of the first transistor connected to the first terminal of the cross-coupled inverter of the third latch circuit, the third latch circuit is used to perform an XOR operation on the first data stored in the first latch circuit and the second data stored in the second latch circuit, and the result of the XOR operation is stored in the third latch circuit.

[0013] In one possible implementation, the third latch circuit is used to perform an XOR operation on the first data stored in the first latch circuit and the second data stored in the second latch circuit, and the XOR result is stored in the second latch circuit. This includes: turning on the third transistor in the first latch circuit, the third transistor in the second latch circuit, and the fourth transistor in the third latch circuit; performing an AND operation on the first data stored in the first latch circuit and the second data stored in the second latch circuit; and storing the AND result in the third latch circuit. Then, turning on the third transistor in the first latch circuit and the fourth transistor in the second latch circuit; performing an OR operation on the first data stored in the first latch circuit and the second data stored in the second latch circuit; and storing the OR result in the second latch circuit. Finally, turning on the second transistor; performing an AND operation on the flipped data of the AND operation result stored in the third latch circuit and the OR operation result stored in the second latch circuit to obtain an XOR result; and storing the XOR result in the second latch circuit.

[0014] In one possible implementation, a transmission circuit connects buffer lock groups x and x+1 corresponding to every two adjacent bit lines, where x is a positive integer. The transmission circuit is used to implement multi-bit operations and includes an eighth transistor and a ninth transistor. The second terminal of the cross-coupled inverter of the first latch circuit in buffer lock group x is connected to the first terminal of the eighth transistor, the second terminal of the eighth transistor is connected to the first terminal of the ninth transistor, the second terminal of the ninth transistor is grounded, the control terminal of the eighth transistor is connected to the first terminal of the cross-coupled inverter of the latch circuit in buffer lock group x+1 used for caching carry data, and the control terminal of the ninth transistor receives a transmission control signal for activating multi-bit operations.

[0015] In one possible implementation, the control terminal of the ninth transistor of each adjacent 4N bit line shares the same transmission control signal to support 4N bit data types, where N is a positive integer.

[0016] In one possible implementation, the cache lock group performs an addition operation by combining bitwise operations to obtain the addition result.

[0017] According to another aspect of this disclosure, a memory is provided that includes a cache lock group as described above.

[0018] According to another aspect of this disclosure, an electronic device is provided, the electronic device including the cache lock group as described above.

[0019] The cache latch group of this disclosure can be applied to a flash memory array. Each bit line in the flash memory array is connected to a cache latch group. The cache latch group circuit includes at least five latch circuits, a first transistor, and a second transistor. Each latch circuit includes a cross-coupled inverter. The first terminal of the cross-coupled inverter of one latch circuit is connected to the first terminal of the first transistor, the second terminal of the first transistor is connected to the first terminal of the second transistor, the second terminal of the second transistor is grounded, the control terminal of the first transistor is connected to the first terminal of the cross-coupled inverter of another latch circuit, and the control terminal of the second transistor receives an XOR control signal, which is used to activate the XOR operation.

[0020] According to the cache lock group disclosed herein, data computation can be offloaded to the flash memory chip, reducing the amount of data transfer between the memory chip and the flash memory device processor and host, thereby improving system performance. Specifically, by further configuring a first transistor and a second transistor in the cache lock group, the XOR operation can be performed with fewer transistor activations, increasing the computation speed of the cache lock group performing the XOR operation.

[0021] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0022] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0023] Figure 1 A circuit diagram of a cache lock group according to an embodiment of the present disclosure is shown.

[0024] Figure 2 A circuit diagram of a cache lock group according to another embodiment of the present disclosure is shown.

[0025] Figure 3A schematic diagram of an adder implemented in a cache lock according to an embodiment of the present disclosure is shown.

[0026] Figure 4 A schematic diagram of a transmission circuit according to an embodiment of the present disclosure is shown.

[0027] Figure 5 A schematic diagram of a transmission circuit control method according to an embodiment of the present disclosure is shown.

[0028] Figure 6 A schematic diagram showing a controller sending commands according to an embodiment of the present disclosure is provided. Detailed Implementation

[0029] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0030] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0031] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0032] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0033] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0034] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0035] It should be noted that the transistors used in all embodiments of this disclosure can be metal-oxide-semiconductor field-effect transistors (MOSFETs), thin-film transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in the embodiments of this disclosure are switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their sources and drains can be interchanged. The source is referred to as the first terminal, and the drain as the second terminal, or vice versa. For example, the control terminal is the gate, the signal input terminal is the source, and the signal output terminal is the drain. Furthermore, the switching transistors used in the embodiments of this disclosure can include any one or a combination of P-type and N-type transistors. Specifically, the P-type transistor conducts when the gate voltage is low and turns off when the gate voltage is high, while the N-type transistor conducts when the gate voltage is high and turns off when the gate voltage is low. It should be understood that, for ease of description, the following description uses a transistor that is turned on when its gate is at a high voltage as an example to describe the cache lock group of the embodiments of this disclosure, and this disclosure does not limit it.

[0036] Figure 1 A circuit diagram of a cache lock group according to an embodiment of the present disclosure is shown. Figure 1 As shown, the cache lock group is applied to the flash memory array. Each bit line BL in the flash memory array is connected to a cache lock group. The cache lock group circuit includes at least five latch circuits (e.g., the first latch circuit L1 to the Nth latch circuit LN, where N is an integer greater than or equal to 5) and a first transistor M. xor1 Second transistor M xor2 .

[0037] Each latch circuit includes a cross-coupled inverter. For example, the first latch circuit L1 includes a cross-coupled inverter 2_1, the second latch circuit L2 includes a cross-coupled inverter 2_2, and so on, with the Nth latch circuit LN including a cross-coupled inverter 2_N. In this example, the cross-coupled inverter is composed of two inverters connected end-to-end, where the input of one inverter is the output of the other. Assuming the cross-coupled inverter is composed of a first inverter and a second inverter connected end-to-end, if the output of the first inverter is initially 1, then the input of the second inverter is 1, and its output is 0. This feedback to the input of the first inverter causes its output to be 1, thus stabilizing the output state of the first inverter at 1 and the output state of the second inverter at 0. Alternatively, if the output of the first inverter is initially 0, then the input of the second inverter is 0 and its output is 1. This feedback to the input of the first inverter causes its output to become 0, thus stabilizing the output state of the first inverter at 0 and the output state of the second inverter at 1. Therefore, the cross-coupled inverter, as a bistable device, has two stable states, 1 and 0, and can store 1 bit of data information. Here, 1 represents high voltage and 0 represents low voltage. It should be understood that, since the cross-coupled inverter is symmetrical, the first and second terminals of the cross-coupled inverter are interchangeable. For example, the output terminal of the first inverter can be used as the first terminal and the output terminal of the second inverter as the second terminal; alternatively, the output terminal of the first inverter can be used as the second terminal and the output terminal of the second inverter as the first terminal. The embodiments of this disclosure do not limit this.

[0038] By setting up cache lock groups for the connection bit lines of the flash memory chip, most data computation can be offloaded to the flash memory chip itself, reducing the amount of data transfer between the storage chip and the flash device processor and host, thereby improving system performance.

[0039] In this circuit, the first terminal of the cross-coupled inverter is connected to the first transistor M. xor1 The first terminal, the first transistor M xor1 The second terminal is connected to the second transistor M xor2 The first terminal, the second transistor M xor2 The second terminal is grounded, and the first transistor M xor1 The control terminal is connected to the first terminal of the cross-coupled inverter of another latching circuit, and the second transistor M xor2 The control terminal receives an XOR control signal, which is used to activate the XOR operation. It should be understood that a latch circuit can be any one of multiple latch circuits, and the embodiments of this disclosure do not limit this.

[0040] For example, such as Figure 1As shown, assuming one latch circuit is the second latch circuit L2 and the other latch circuit is the third latch circuit L3, the first terminal of the cross-coupled inverter 2_2 of the second latch circuit L2 is connected to the first transistor M. xor1 The first terminal, the first transistor M xor1 The second terminal is connected to the second transistor M xor2 The first terminal, the second transistor M xor2 The second terminal is grounded, and the first transistor M xor1 The control terminal is connected to the first terminal of the cross-coupled inverter 2_3 of the third latch circuit L3, and the second transistor M xor2 The control terminal receives an XOR control signal, which is used to activate the XOR operation. For example, if the XOR control signal is high, the second transistor M is turned on. xor2 This enables the cache lock group to perform XOR operations.

[0041] By setting the first transistor M in the cache lock group xor1 Second transistor M xor2 It can complete the XOR operation with fewer transistor activations, thus improving the computation speed of the cache lock group in performing the XOR operation.

[0042] It should be understood that the embodiments of this disclosure only use the first transistor M xor1 The first terminal is connected to the second latch circuit L2, and the first transistor M xor1 Taking the control terminal connected to the third latch circuit L3 as an example, the first transistor M xor1 The first terminal and the control terminal can be connected to any two different latch circuits from the first latch circuit L1 to the Nth latch circuit LN, and the embodiments of this disclosure do not limit this.

[0043] It should be noted that, although... Figure 1 The cache lock group described above is an example, but those skilled in the art will understand that this disclosure is not limited thereto. In fact, users can flexibly modify the circuitry of the cache lock group according to their personal preferences and / or actual application scenarios.

[0044] In one possible implementation, each latch circuit further includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; wherein, the first terminal of the cross-coupled inverter is connected to the first terminal of the fifth transistor, the second terminal of the cross-coupled inverter is connected to the control terminal of the seventh transistor and the first terminal of the fourth transistor, the first terminal of the seventh transistor is connected to the second terminal of the third transistor, the second terminal of the seventh transistor is grounded, the second terminals of the fourth transistor and the fifth transistor are connected to the first terminal of the sixth transistor, the second terminal of the sixth transistor is grounded, the first terminal of the third transistor and the control terminal of the sixth transistor are connected to a bit line, the control terminal of the third transistor receives an output control signal, the output control signal is used to output the current data latched by the latch circuit, the control terminal of the fourth transistor receives a first control signal, the first control signal is used to store data when reading data, and the control terminal of the fifth transistor receives a second control signal, the second control signal is used to store the toggled data when reading data.

[0045] The latch circuit of this disclosure has a simple structure, high applicability, and can be integrated into area-sensitive flash memory chips.

[0046] In this system, the signal sources for the first control signal, the second control signal, and the output control signal are all the same. This signal source, connected to a bit line, can receive data stored in the flash memory medium, and it has an independent voltage control switch to regulate its voltage value. For example, the signal source could originate from the flash memory chip's controller, which could apply voltage to the transistors of the first, second, and output control signals to change their states. When the first or second control signal is activated, the data stored in its corresponding latch circuit changes according to the signal source; when the output control signal is activated, the voltage at the signal output changes according to the data stored in the latch circuit.

[0047] For example, Figure 2 A circuit diagram of a buffer lock group according to another embodiment of the present disclosure is shown, such as Figure 2 As shown, a bit line BL in the flash memory array is connected to a cache latch group, which can consist of at least five latch circuits, such as a first latch circuit L1, a second latch circuit L2, a third latch circuit L3, etc. The first terminal B of the cross-coupled inverter of the second latch circuit L2 is connected to the first transistor M. xor1 The first terminal, the first transistor M xor1 The second terminal is connected to the second transistor M xor2 The first terminal, the second transistor M xor2 The second terminal is grounded, and the first transistor M xor1The control terminal is connected to the first terminal C of the cross-coupled inverter of the third latch circuit L3, and the second transistor M xor2 The control terminal receives the XOR control signal.

[0048] For example, such as Figure 2 As shown, the first latch circuit L1 includes a cross-coupled inverter, a third transistor M1, a fourth transistor M2, a fifth transistor M3, a sixth transistor ML1, and a seventh transistor M4; wherein, the first terminal A of the cross-coupled inverter is connected to the first terminal of the fifth transistor M3, and the second terminal of the cross-coupled inverter... The control terminal of the seventh transistor M4 and the first terminal of the fourth transistor M2 are connected. The first terminal of the seventh transistor M4 is connected to the second terminal of the third transistor M1, and the second terminal of the seventh transistor M4 is grounded. The second terminal of the fourth transistor M2 and the second terminal of the fifth transistor M3 are connected to the first terminal of the sixth transistor ML1, and the second terminal of the sixth transistor ML1 is grounded. The first terminal of the third transistor M1 and the control terminal of the sixth transistor ML1 are connected to the bit line BL. The control terminal of the third transistor M1 receives an output control signal, which is used to output the current data latched by the first latch circuit L1. The control terminal of the fourth transistor M2 receives a first control signal, which is used to store data when reading data. The control terminal of the fifth transistor M3 receives a second control signal, which is used to store the flipped data of the data when reading data.

[0049] For example, such as Figure 2 As shown, the second latch circuit L2 includes a cross-coupled inverter, a third transistor M5, a fourth transistor M6, a fifth transistor M7, a sixth transistor ML2, and a seventh transistor M8; wherein, the first terminal B of the cross-coupled inverter is connected to the first terminal of the fifth transistor M7, and the second terminal of the cross-coupled inverter... The control terminal of the seventh transistor M8 and the first terminal of the fourth transistor M6 are connected. The first terminal of the seventh transistor M8 is connected to the second terminal of the third transistor M5, and the second terminal of the seventh transistor M8 is grounded. The second terminal of the fourth transistor M6 and the second terminal of the fifth transistor M7 are connected to the first terminal of the sixth transistor ML2, and the second terminal of the sixth transistor ML2 is grounded. The first terminal of the third transistor M5 and the control terminal of the sixth transistor ML2 are connected to the bit line BL. The control terminal of the third transistor M5 receives an output control signal, which is used to output the current data latched by the second latch circuit L2. The control terminal of the fourth transistor M6 receives a first control signal, which is used to store data when reading data. The control terminal of the fifth transistor M7 receives a second control signal, which is used to store the flipped data of the data when reading data.

[0050] For example, such as Figure 2 As shown, the third latch circuit L3 includes a cross-coupled inverter, a third transistor M9, and a fourth transistor M1. 10 Fifth transistor M 11 The sixth transistor ML3, the seventh transistor M 12 The first terminal C of the cross-coupled inverter is connected to the fifth transistor M. 11 The first end, the second end of the cross-coupled inverter With the seventh transistor M 12 The control terminal, the fourth transistor M 10 The first terminal is connected, the seventh transistor M 12 The first terminal is connected to the second terminal of the third transistor M9, and the seventh transistor M 12 The second terminal is grounded, and the fourth transistor M 10 The second terminal, the fifth transistor M 11 The second terminal of the third transistor M9 is connected to the first terminal of the sixth transistor ML3, and the second terminal of the sixth transistor ML3 is grounded. The first terminal of the third transistor M9 and the control terminal of the sixth transistor ML3 are connected to the bit line BL. The control terminal of the third transistor M9 receives the output control signal, which is used to output the current data latched by the third latch circuit L3. The fourth transistor M... 10 The control terminal receives a first control signal, which is used to store data when reading data. The fifth transistor M 11 The control terminal receives a second control signal, which is used to flip the stored data when reading data.

[0051] Each bit line BL can also be connected to the controller of the flash memory chip and the switching transistor M.pre The second terminal, the switching transistor M pre The first terminal is used to receive power signals, switching transistor M pre The controller can accept signals from the controller, and the switching transistor M pre Used to initialize the SO value of bit line BL to 1. The inputs and outputs of each latch circuit in the buffer latch group can be connected to bit line BL. When a latch circuit reads data, it can obtain the data by connecting to the bit line; when a latch circuit outputs data to the bit line, it can first activate the switching transistor M. pre Initialize the bit line SO value to 1.

[0052] It should be understood that the cache lock group may include N latch circuits (N is an integer greater than or equal to 5). The circuit structure of the fourth latch circuit L4 to the Nth latch circuit LN is similar to that of the first latch circuit L1 to the third latch circuit L3, and will not be described again here.

[0053] After the data in the flash memory is read into the cache lock group, it can repeatedly participate in bit operations in the cache lock group through the orderly control of the control signals of multiple latching circuits in the cache lock group.

[0054] In one possible implementation, the cache lock group performs at least one of the following bit operations according to the instruction of the control signal from the controller:

[0055] Data is read from the bit line and stored in at least one latch circuit, for example, it may be stored in one or more buffer locks;

[0056] Transferring data from one latch circuit to at least one other latch circuit;

[0057] Binary gate operations are performed on the data stored in two latch circuits, and the results of the gate operations are stored in at least one latch circuit. The binary gate operations include AND, OR, and XOR.

[0058] The following is based on Figure 2 Taking the three latch circuits in the demonstrated cache lock group as examples, we will introduce their corresponding voltage control operations. Specifically, before controlling any operations (such as arbitrary bit operations), the switching transistor M is activated first. pre The SO value of bit line BL is initialized to 1.

[0059] For example, when reading data from bit line BL to the first latch circuit L1, the controller can set the first control signal at the control terminal of the fourth transistor M2 to a high level, turning on the fourth transistor M2 and storing the SO value of bit line BL into the first latch circuit L1; for example, if the SO value of bit line BL is 1, the sixth transistor ML1 is turned on, and the second terminal of the cross-coupled inverter of the first latch circuit L1... Grounding can set the value in the first latch circuit L1 to 1; when you want to read the flipped data from the bit line BL to the first latch circuit L1, you can set the second control signal at the control terminal of the fifth transistor M3 to a high level through the controller, turn on the fifth transistor M3, and store the inverted bit data of the SO value of the bit line BL into the first latch circuit L1.

[0060] Similarly, when reading data from bit line BL to the second latch circuit L2, the controller can set the first control signal at the control terminal of the fourth transistor M6 to a high level, turn on the fourth transistor M6, and store the SO value of bit line BL into the second latch circuit L2; when reading the flipped data from bit line BL to the second latch circuit L2, the controller can set the second control signal at the control terminal of the fifth transistor M7 to a high level, turn on the fifth transistor M7, and store the inverted bit data of the SO value of bit line BL into the second latch circuit L2.

[0061] Similarly, when you want to read data from bit line BL to the third latch circuit L3, you can use the controller to activate the fourth transistor M. 10 The first control signal at the control terminal is set to a high level, turning on the fourth transistor M. 10 The SO value of bit line BL is stored in the third latch circuit L3; when you want to read the flipped data from bit line BL to the third latch circuit L3, the controller can activate the fifth transistor M. 11 The second control signal at the control terminal is set to a high level, turning on the fifth transistor M. 11 The inverted bit data of the SO value of bit line BL is stored in the third latch circuit L3.

[0062] For example, when data DA wants to be transmitted from the first latch circuit L1 to the second latch circuit L2, the controller can set the second control signal at the control terminal of the fifth transistor M7 to a high level, turn on the fifth transistor M7, and make the value stored in the second latch circuit L2 grounded to 0.

[0063] The controller then sets the output control signal at the control terminal of the third transistor M1 to a high level, turning on the third transistor M1. Thus, if the value of the data DA stored in the first latch circuit L1 is 1, the second terminal of the cross-coupled inverter of the first latch circuit L1... If the value of the data DA stored in the first latch circuit L1 is 0, thus turning off the seventh transistor M4, the conduction of the third transistor M1 will not change the SO value of the bit line BL; if the value of the data DA stored in the first latch circuit L1 is 0, the second terminal of the cross-coupled inverter of the first latch circuit L1... When the value is 1, the seventh transistor M4 is turned on. Then the third transistor M1, which is turned on, will ground the bit line BL. The SO value of the bit line BL will become 0, that is, the SO value is equal to the value of data DA.

[0064] Finally, the controller sets the first control signal at the control terminal of the fourth transistor M6 to a high level, turning on the fourth transistor M6. If the value of data DA in the first latch circuit L1 is 1, then the second terminal of the cross-coupled inverter in the second latch circuit L2... When grounded, the data stored in the second latch circuit L2 becomes 1; if the value of data DA in the first latch circuit L1 is 0, then the data stored in the second latch circuit L2 remains unchanged, that is, the second latch circuit L2 stores data DA.

[0065] For example, assuming the first latch circuit L1 stores data DA and the second latch circuit L2 stores data DB, when you want to perform a binary AND gate on data DA and data DB and store the result in the third latch circuit L3, you can first initialize the value of the third latch circuit L3 to 0; then, the controller sets the output control signals at the control terminals of the third transistor M1 and the third transistor M5 to high level, turning on the third transistors M1 and M5. Thus, if both data DA and data DB are 1, the second terminal of the cross-coupled inverter in the first latch circuit L1... The value is 0, and the second terminal of the cross-coupled inverter in the second latch circuit L2 is 0. The value is 0, thus turning off the seventh transistors M4 and M8, and keeping the SO value of bit line BL high. Otherwise, if data DA and / or data DB are 0, the third transistor M1 and / or the third transistor M5 grounds bit line BL, and the SO value of bit line BL becomes 0. Then, the fourth transistor M can be turned on by the controller. 10 The first control signal at the control terminal is set to a high level, turning on the fourth transistor M. 10 The SO value of the current bit line BL, that is, the result of the operation between data DA and data DB, is stored in the third latch circuit L3.

[0066] For example, assuming the first latch circuit L1 stores data DA and the second latch circuit L2 stores data DB, when you want to perform a binary OR gate on data DA and data DB and store the result in the second latch circuit L2 instead of data DB, you can sequentially set the output control signal at the control terminal of the third transistor M1 and the first control signal at the control terminal of the fourth transistor M6 to a high level through the controller, thereby sequentially turning on the third transistor M1 and the fourth transistor M6. When the third transistor M1 is turned on, the SO value of the bit line BL is equal to the value of data DA. After turning on the fourth transistor M6, if data DA is 1, the sixth transistor ML2 can be turned on, and the second terminal of the cross-coupled inverter of the second latch circuit L2 can be turned on. If the data DA is grounded, the value in the second latch circuit L2 can be set to 1; if the data DA is 0, the sixth transistor ML2 is turned off, and the value of DB in the second latch circuit L2 can be retained. In this way, the result of the binary OR gate operation between the data DA and the data DB can replace the data DB and be stored in the second latch circuit L2.

[0067] For example, in the first transistor M xor1 The first terminal is connected to the first terminal B of the cross-coupled inverter of the second latch circuit L2, and the first transistor M xor1 When the control terminal is connected to the first terminal C of the cross-coupled inverter of the third latch circuit L3, the third latch circuit L3 can be used to perform an XOR operation on the first data (e.g., data DA) stored in the first latch circuit L1 and the second data (e.g., data DB) stored in the second latch circuit L2, and the result of the XOR operation is stored in the third latch circuit L3.

[0068] If the first latch circuit L1 stores data DA and the second latch circuit L2 stores data DB, when data DA and data DB are XORed, since DA⊕DB can be represented as ( ) ∧ (DA ∨ DB), where ⊕ is the XOR operator, ∧ is the AND operator, and ∨ is the OR operator. This can be achieved using the third latch circuit L3, through the bitwise AND and bitwise OR operations described above, and the first transistor M. xor1 Second transistor M xor2 It performs a binary XOR operation between data DA and data DB, and stores the result of the XOR operation in the third latch circuit L3.

[0069] In one possible implementation, the controller can sequentially set the output control signals at the control terminals of the third transistor M1 and the third transistor M5 to high level, thereby turning on the third transistor M1 in the first latch circuit L1, the third transistor M5 in the second latch circuit L2, and the fourth transistor M in the third latch circuit L3. 10 The first data (e.g., data DA) stored in the first latch circuit L1 and the second data (e.g., data DB) stored in the second latch circuit L2 are ANDed, and the result of the AND operation is stored in the third latch circuit L3.

[0070] The controller can sequentially set the output control signal at the control terminal of the third transistor M1 and the first control signal at the control terminal of the fourth transistor M6 to a high level, thereby turning on the third transistor M1 in the first latch circuit L1 and the fourth transistor M6 in the second latch circuit L2. This allows the controller to perform an OR operation on the first data (e.g., data DA) stored in the first latch circuit L1 and the second data (e.g., data DB) stored in the second latch circuit L2, and store the OR result in the second latch circuit L2, replacing the original second data (e.g., data DB).

[0071] It should be understood that the AND and OR operations of the first and second data can be referred to above, and will not be repeated here.

[0072] The second transistor M can be controlled by the controller xor2 The XOR control signal at the control terminal is set to a high level, turning on the second transistor M. xor2 The reversed data of the AND operation result stored in the third latch circuit L3 and the OR operation result stored in the second latch circuit L2 are ANDed to obtain the XOR operation result, and the XOR operation result is stored in the second latch circuit L2.

[0073] For example, suppose the first data stored in the cross-coupled inverter in the first latch circuit L1 is "1", and the second data stored in the cross-coupled inverter in the second latch circuit L2 is "0", then the third transistor M1 in the first latch circuit L1, the third transistor M5 in the second latch circuit L2, and the fourth transistor M in the third latch circuit L3 are turned on. 10 The first data "1" and the second data "0" are ANDed together to obtain the result "0", which is stored in the third latch circuit L3. The third transistor M1 in the first latch circuit L1 and the fourth transistor M6 in the second latch circuit L2 are turned on, and the OR operation result "1" of the first data "1" and the second data "0" is stored in the cross-coupled inverter in the second latch circuit L2, replacing the original "0". Since the AND operation result stored in the cross-coupled inverter in the third latch circuit L3 is "0", the first transistor M1 is turned off. xor1 In the second latch circuit L2, the cross-coupled inverter keeps the OR operation result "1" unchanged, that is, the XOR result of the first data "1" and the second data "0" is "1".

[0074] For example, suppose the first data stored in the cross-coupled inverter in the first latch circuit L1 is "0", and the second data stored in the cross-coupled inverter in the second latch circuit L2 is "1", then the third transistor M1 in the first latch circuit L1, the third transistor M5 in the second latch circuit L2, and the fourth transistor M in the third latch circuit L3 are turned on. 10The first data "0" and the second data "1" are ANDed together to obtain a result of "0", which is stored in the third latch circuit L3. The third transistor M1 in the first latch circuit L1 and the fourth transistor M6 in the second latch circuit L2 are turned on, and the OR operation result of the first data "0" and the second data "1" is stored in the cross-coupled inverter in the second latch circuit L2, ensuring that the cross-coupled inverter in the second latch circuit L2 retains the stored value "1". Since the AND operation result stored in the cross-coupled inverter in the third latch circuit L3 is "0", the first transistor M1 is turned off. xor1 In the second latch circuit L2, the cross-coupled inverter keeps the OR operation result "1" unchanged, that is, the XOR result of the first data "0" and the second data "1" is "1".

[0075] For example, assuming the first data stored in the cross-coupled inverter of the first latch circuit L1 is "0" and the second data stored in the cross-coupled inverter of the second latch circuit L2 is "0", the third transistor M1 in the first latch circuit L1, the third transistor M5 in the second latch circuit L2, and the fourth transistor M6 in the third latch circuit L3 are turned on. 10 The AND operation result "0" of the first data "0" and the second data "0" is stored in the third latch circuit L3; the third transistor M1 in the first latch circuit L1 and the fourth transistor M6 in the second latch circuit L2 are turned on, and the OR operation result "0" of the first data "0" and the second data "0" is stored in the cross-coupled inverter in the second latch circuit L2, so that the cross-coupled inverter in the second latch circuit L2 keeps the stored value "0" unchanged; since the AND operation result stored in the cross-coupled inverter in the third latch circuit L3 is "0", the first transistor M1 is turned off. xor1 In the second latch circuit L2, the cross-coupled inverter keeps the OR operation result "0" unchanged, that is, the XOR result of the first data "0" and the second data "0" is "0".

[0076] For example, assuming the first data stored in the cross-coupled inverter in the first latch circuit L1 is "1", and the second data stored in the cross-coupled inverter in the second latch circuit L2 is "1", the third transistor M1 in the first latch circuit L1, the third transistor M5 in the second latch circuit L2, and the fourth transistor M6 in the third latch circuit L3 are turned on. 10 The AND operation result "1" of the first data "1" and the second data "1" is stored in the third latch circuit L3; the third transistor M1 in the first latch circuit L1 and the fourth transistor M6 in the second latch circuit L2 are turned on, and the OR operation result "1" of the first data "1" and the second data "1" is stored in the cross-coupled inverter in the second latch circuit L2, so that the cross-coupled inverter in the second latch circuit L2 keeps the stored value "1" unchanged; the second transistor M1 is turned on. xor2Since the AND operation result stored in the cross-coupled inverter in the third latch circuit L3 is "1", the first transistor M is turned on. xor1 The first terminal B of the cross-coupled inverter in the second latch circuit L2 is grounded, thereby changing the data stored in the cross-coupled inverter in the second latch circuit L2 from "1" to "0", that is, the XOR result of the first data "1" and the second data "1" is "0".

[0077] It should be understood that when the second latch circuit L2 stores the OR operation result of the first data and the second data, and the third latch circuit L3 stores the AND operation result of the first data and the second data, the relevant technology requires the controller to continue to sequentially turn on the third transistor M9 and the fifth transistor M7 in order to realize the OR operation result of the first data and the second data. In the embodiments of this disclosure, the first transistor M9... xor1 The on / off state of the second transistor M is determined by the stored value of the cross-coupled inverter in the third latch circuit L3, without receiving instructions from the controller. xor2 This reduces the number of transistors activated by the controller in the XOR operation, which can further improve the calculation speed of the XOR operation.

[0078] In one possible implementation, the cache lock group performs an addition operation by combining bitwise operations to obtain the addition result.

[0079] Figure 3 A schematic diagram illustrating the implementation of an adder in a cache lock according to an embodiment of the present disclosure is shown. Figure 3 As shown, the adder can be composed of AND gates, OR gates, and XOR gates. x and y are two input data, and z is the carry input. Assume that x is stored in the first latch circuit L1, and y is stored in the second latch circuit L2.

[0080] The first step is to perform a binary AND operation on x and y, and store the result t1 in the third latch circuit L3.

[0081] The second step is to use the value of the AND operation result t1 to store the XOR result t2 of x and y in the second latch circuit L2.

[0082] Before the third step begins, the carry value z is stored in the first latch circuit L1.

[0083] In the third step, the result t3 of the binary AND operation of z and t2 is stored in the fourth latch circuit L4.

[0084] The fourth step is to use the value of t3 to store the XOR result of z and t2 in the second latch circuit L2, which is the sum of x and y, S.

[0085] The fifth step is to store the binary AND gate result of t1 and t3 in the fourth latch circuit L4, which is the final output carry C.

[0086] The adder implemented using the buffer lock group in the embodiments of this disclosure is a full adder with three bits as input, and can output a sum and carry signal based on the three input data.

[0087] It should be understood that when calculating multi-bit addition, all buffer locks can first perform the first and second steps to obtain results t1 and t2, which are then stored in the third latch circuit L3 and the second latch circuit L2, respectively. The calculation steps of the third and fifth steps are then repeated, with the carry transferred from the lower-order buffer lock to the first latch circuit L1 in the higher-order buffer lock. During this process, the fourth step is not performed to ensure that the values ​​of the third latch circuit L3 and the second latch circuit L2 do not change. Finally, until all bits have received the correct carry, the fourth step can be performed to obtain the final result.

[0088] By performing the following steps on the cache lock group: Figure 3 The sequence control shown allows for low-latency binary bitwise operations on two bits of data stored in a buffer latch group, and can selectively store the intermediate value in one or more target latch circuits. Furthermore, by combining binary bitwise operations on the two bits of data, adder operations are performed with minimal operational latency, even with limited latch circuitry.

[0089] The cache lock groups of this disclosure can achieve a high-efficiency adder array through bitwise combination operations and circuit control of the cache lock groups. For example, for the controller of the cache lock groups of all bit lines on the flash memory chip, the same sequence signal control is applied simultaneously (see...). Figure 3 (Signal control logic) to achieve the purpose of concurrent adder array, the input data can be two bits of data from the same bit line stored in the same cache lock group.

[0090] Figure 4 A schematic diagram of a transmission circuit according to an embodiment of the present disclosure is shown, such as Figure 4 As shown, a transmission circuit connects buffer lock groups x and x+1 corresponding to every two adjacent bit lines, where x is a positive integer. This transmission circuit is used to implement multi-bit operations and includes an eighth transistor M1. x Ninth transistor M2 x The second terminal of the cross-coupled inverter of the first latch circuit (e.g., the first latch circuit L1) in cache lock group x is connected to the eighth transistor M1. x The first terminal, the eighth transistor M1 x The second terminal is connected to the ninth transistor M2 x The first terminal, the ninth transistor M2 xThe second terminal is grounded, and the eighth transistor M1 x The control terminal is connected to the first terminal of the cross-coupled inverter in the latch circuit (e.g., the fourth latch circuit L4) used for caching carry data in the cache latch group x+1, and the ninth transistor M2 x The control terminal receives the transmission control signal used to activate multi-bit operations.

[0091] For example, the transmission circuit between buffer lock group x-1 and buffer lock group x may include an eighth transistor M1. x-1 Ninth transistor M2 x-1 The second terminal of the cross-coupled inverter of the first latch circuit (e.g., the first latch circuit L1) in cache lock group x-1 Connect the eighth transistor M1 x-1 The first terminal, the eighth transistor M1 x-1 The second terminal is connected to the ninth transistor M2 x-1 The first terminal, the ninth transistor M2 x-1 The second terminal is grounded, and the eighth transistor M1 x-1 The control terminal is connected to the first terminal E of the cross-coupled inverter in the cache latch circuit (e.g., the fourth latch circuit L4) used for caching carry data in the cache latch group x, and the ninth transistor M2 x-1 The control terminal receives the transmission control signal used to activate multi-bit operations.

[0092] The transmission circuit connects to and controls the output of the latch circuit storing the carry signal in the buffer lock group that stores the lower bit, as well as the latch circuit storing the input data in the buffer lock group that stores the adjacent higher bit.

[0093] The transmission circuit is used for unidirectional transmission of the dependent data between two adjacent bits in multi-bit data calculations. It can be combined with the control signals of the adder to form multi-bit data addition. The dependent data between two adjacent bits refers to the carry generated when the lower bit is calculated and then carried over to the higher bit during multi-bit data calculation. Multi-bit data calculations can be completed by continuously activating the adder control logic and the transmission circuit.

[0094] It should be understood that cache lock group x refers to the cache lock group connected to the xth bit line, and the fourth latch circuit L4 of cache lock group x is connected to the eighth transistor M1. x-1 The first latch circuit L1 of cache lock group x-1 is controlled; simultaneously, the first latch circuit L1 of cache lock group x can also be controlled by the fourth latch circuit L4 of cache lock group x+1. Here, the fourth latch circuit L4 refers to the latch circuit for storing carry. If other latch circuits are selected to store carry, the fourth latch circuit L4 can be replaced with the corresponding latch circuit. The embodiments of this disclosure do not limit this.

[0095] In this way, for each pair of adjacent bit lines corresponding to a buffer lock group, by adding a set of transmission transistors (e.g., the eighth transistor, the ninth transistor) and wires, data can be unidirectionally transmitted to the adjacent buffer lock group via the transmission circuit. Buffer lock group x+1, buffer lock group x, and buffer lock group x-1 can store the low-order to high-order bits of the data, respectively. For example, the number of bits stored in buffer lock group x+1 is one bit lower than that in group x, and the number of bits stored in buffer lock group x-1 is one bit higher than that in group x. Multi-bit data computation can be realized through the transmission circuit, and dependent data between different bit numbers can be transmitted on-chip. Among them, multi-bit data computation refers to integer operations involving 4, 8, 16, 32, or 64 bits.

[0096] To meet the computational needs of different types of integer data, the transmission circuit can be configured with different transmission control signals for different data types, ensuring that the multi-bit data computation process is not interfered with by data stored in adjacent locations.

[0097] In one possible implementation, the control terminal of the ninth transistor of each adjacent 4N bit line shares the same transmission control signal to support 4N bit data types, where N is a positive integer.

[0098] Figure 5 A schematic diagram of a transmission circuit control method according to an embodiment of the present disclosure is shown. Figure 5 As shown, every four bit lines (see...) Figure 5 (int_4 part), every eight bit lines (see) Figure 5 (int_8 part), every sixteen bit lines (see) Figure 5 (int_16 part) and every thirty-two bit lines (see Figure 5 The int_32 part can have a separate transmission control signal to prevent data contamination between different groups of data calculations. Transmission control signal EN_8 is activated when the data type is greater than or equal to eight bits; transmission control signal EN_16 is activated when the data type is greater than or equal to sixteen bits; transmission control signal EN_32 is activated when the data type is greater than or equal to thirty-two bits; similarly, even larger data types such as sixty-four bits can be used, and the embodiments of this disclosure are not limited in this regard. Transmission control signal shf is activated when all data types are calculated.

[0099] In this way, starting from the first bit line, every four, eight, sixteen, thirty-two, sixty-four or more adjacent bit lines of the ninth transistor correspond to the same transmission control signal, and the remaining additional ninth transistors share a single transmission control signal, which can respectively support multiple data types from four bits to sixty-four bits.

[0100] Figure 6A schematic diagram illustrating the sending of commands by a controller according to an embodiment of the present disclosure is shown. Figure 6 As shown, the controller can send corresponding commands to the flash memory chip, which contains a cache lock group. The controller's commands may include: a start command; a read address command; an add command; a shift command; a shift-plus command; and a stop command. Specifically, the start command puts the flash memory chip into in-memory computing mode; the read address command allows the flash memory chip to read data according to row and column addresses; the add command allows two data items to be added according to their data type within the flash memory chip's cache lock group; the shift and shift-plus commands can be used in multiplication to transfer data to the next bit or to add data and then transfer it to the next bit; and the stop command puts the flash memory chip into storage mode, and the calculation result can be output upon completion of the calculation.

[0101] In one possible implementation, the controller sends corresponding commands to the flash memory chip according to the computing requirements. After reading the data from the flash memory chip into the cache lock group, the flash memory chip runs preset logic code (e.g., code composed of corresponding commands) to control the cache lock group and the peripheral transmission circuit to perform complex arithmetic calculations on the data.

[0102] For example, based on computational needs, the controller can send flash memory commands to the flash memory chip. Upon receiving the commands, the flash memory chip can sequentially control the ninth transistor in the peripheral circuitry with voltage signals to complete the computational task. These computational needs may include addition, multiplication, and combinations of arbitrary multiplication and addition operations on shaped data. Multiplication involves performing a bitwise multiplication / bitwise AND operation between the shift of one multiplier and another multiplier, and then summing the results.

[0103] In multiplication operations, one multiplier can be stored in the controller of the flash memory chip, while the other multiplier is stored in the fifth latch circuit L5 in the cache lock group of the flash memory chip. During the calculation, the original data can be shifted and is not altered by other calculation processes. The controller of the flash memory chip can send commands, such as shift commands and shift-plus commands, based on one of the currently stored multipliers. If the current bit stored in the controller is 0, it means that multiplying with the current bit results in zero, and the controller can send a shift command to shift the other multiplier. If the current bit stored in the controller is 1, the controller can send a shift-plus command to add the result of the current shift of the other multiplier to the current calculated value, and then shift the current multiplier.

[0104] In one possible implementation, the initial calculated value is 0 during the multiplication process.

[0105] In one possible implementation, during multiplication, shifting refers to shifting each bit of the computational input data stored in the cache controller to a higher bit. When shifting, the computational input data currently stored in the fifth latch circuit L5 can be transferred to the fourth latch circuit L4 for shifting. During computation, the input data can be transferred back to the fifth latch circuit L5 to ensure data correctness. Similarly, when shifting the computational input data, the same method is used to ensure the correctness of the current calculated cumulative value.

[0106] In one possible implementation, when addition is involved, the two data involved in the addition are already stored in consecutively adjacent cache lock sets. The data may come from different flash memory pages or be loaded by the controller; multi-bit addition can be completed by continuously starting the adder and transmission circuit.

[0107] In one possible implementation, the data stored in the flash memory chip controller during multiplication can come from upper-layer input or be read from the flash memory medium. During computation, for a multiplier stored in the controller, the controller can send commands to the flash memory chip in a corresponding sequence of signals based on each bit of the multiplier data, from the least significant bit to the most significant bit. For example, the flash memory chip controller can send commands starting from the least significant bit of the data and ending with the most significant bit.

[0108] In one possible implementation, after the current calculation is completed, the calculation result is stored in a latch circuit connected to the controller and awaits output, while the next calculation request or read / write request is calculated synchronously and in parallel.

[0109] After the calculation is completed, the calculation result can be sent to the upper-layer data. In most computing scenarios, the calculation can be offloaded to the lower-layer flash memory medium, thereby achieving the computing purpose with extremely high concurrency, effectively reducing data transmission, improving the overall computing performance of the flash memory chip, and effectively reducing the energy consumption of the overall system during calculation. For example, all multiplication-accumulation based operations can be offloaded to the flash memory chip, while taking advantage of the high concurrency of flash memory to improve computing efficiency. It can be seen that the cache lock group of this disclosure embodiment effectively reduces the data migration requirements from the flash memory medium to the controller of the flash memory device and even the upper-layer host, reduces the task load on the host side, effectively improves the overall computing performance, and reduces the energy consumption required for calculation.

[0110] In summary, the cache latch group of this disclosure can be applied to a flash memory array. Each bit line in the flash memory array is connected to a cache latch group. The cache latch group circuit includes at least five latch circuits, a first transistor, and a second transistor. Each latch circuit includes a cross-coupled inverter. The first terminal of the cross-coupled inverter of one latch circuit is connected to the first terminal of the first transistor, the second terminal of the first transistor is connected to the first terminal of the second transistor, the second terminal of the second transistor is grounded, the control terminal of the first transistor is connected to the first terminal of the cross-coupled inverter of another latch circuit, and the control terminal of the second transistor receives an XOR control signal, which is used to activate the XOR operation.

[0111] According to the cache lock group disclosed herein, data computation can be offloaded to the flash memory chip, reducing the amount of data transfer between the memory chip and the flash memory device processor and host, thereby improving system performance. Specifically, by further configuring a first transistor and a second transistor in the cache lock group, the XOR operation can be performed with fewer transistor activations, increasing the computation speed of the cache lock group performing the XOR operation.

[0112] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0113] This disclosure also provides a memory that includes a cache lock group as described above. For example, a flash memory chip may include a cache lock group.

[0114] This disclosure also provides an electronic device, which includes the buffer lock group described above. The electronic device can be a server, user equipment (UE), mobile device, user terminal, terminal, cellular phone, cordless phone, personal digital assistant (PDA), handheld device, computing device, vehicle-mounted device, wearable device, etc., and this disclosure does not limit the scope of the application.

[0115] This disclosure also provides a computer program product, including a computer program or a non-volatile computer-readable storage medium carrying the computer program, wherein the computer program, when executed by a processor, implements the steps of the above method.

[0116] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0117] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A cache lock group, characterized in that, The cache lock group is applied to the flash memory array, and each bit line in the flash memory array is connected to a cache lock group. The cache lock group circuit includes at least five latch circuits, a first transistor, a second transistor, and each latch circuit includes a cross-coupled inverter. In this circuit, the first terminal of the cross-coupled inverter of a latching circuit is connected to the first terminal of the first transistor, the second terminal of the first transistor is connected to the first terminal of the second transistor, the second terminal of the second transistor is grounded, the control terminal of the first transistor is connected to the first terminal of the cross-coupled inverter of another latching circuit, and the control terminal of the second transistor receives an XOR control signal, which is used to activate the XOR operation.

2. The cache lock group according to claim 1, characterized in that, Each latch circuit also includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; In this configuration, the first terminal of the cross-coupled inverter is connected to the first terminal of the fifth transistor; the second terminal of the cross-coupled inverter is connected to the control terminal of the seventh transistor and the first terminal of the fourth transistor; the first terminal of the seventh transistor is connected to the second terminal of the third transistor and is grounded; the second terminals of the fourth transistor and the fifth transistor are connected to the first terminal of the sixth transistor and are grounded; and the first terminal of the third transistor and the control terminal of the sixth transistor are connected to a bit line. The control terminal of the third transistor receives an output control signal, which is used to output the current data latched by the latch circuit. The control terminal of the fourth transistor receives a first control signal, which is used to store data when reading data. The control terminal of the fifth transistor receives a second control signal, which is used to store the flipped data of the data when reading data.

3. The cache lock group according to claim 1 or 2, characterized in that, The buffer lock group performs at least one of the following bit operations according to the instruction from the control signal from the controller: Data is read from the bit line and stored in at least one latch circuit; Transferring data from one latch circuit to at least one other latch circuit; Binary gate operations are performed on the data stored in two latch circuits, and the results of the gate operations are stored in at least one latch circuit. The binary gate operations include AND, OR, and XOR.

4. The cache lock group according to claim 3, characterized in that, When the first terminal of the first transistor is connected to the first terminal of the cross-coupled inverter of the second latch circuit, and the control terminal of the first transistor is connected to the first terminal of the cross-coupled inverter of the third latch circuit, the third latch circuit is used to perform an XOR operation on the first data stored in the first latch circuit and the second data stored in the second latch circuit, and the result of the XOR operation is stored in the third latch circuit.

5. The cache lock group according to claim 4, characterized in that, Using the third latch circuit, an XOR operation is performed on the first data stored in the first latch circuit and the second data stored in the second latch circuit, and the XOR result is stored in the second latch circuit, including: The third transistor in the first latch circuit, the third transistor in the second latch circuit, and the fourth transistor in the third latch circuit are turned on to perform a bitwise AND operation on the first data stored in the first latch circuit and the second data stored in the second latch circuit, and the result of the bitwise AND operation is stored in the third latch circuit. The third transistor in the first latch circuit and the fourth transistor in the second latch circuit are turned on to perform an OR operation on the first data stored in the first latch circuit and the second data stored in the second latch circuit, and the OR operation result is stored in the second latch circuit. The second transistor is turned on, and the flipped data of the AND operation result stored in the third latch circuit and the OR operation result stored in the second latch circuit are ANDed to obtain the XOR operation result, and the XOR operation result is stored in the second latch circuit.

6. The cache lock group according to claim 4, characterized in that, The transmission circuit connects the buffer lock group x and buffer lock group x+1 corresponding to each two adjacent bit lines, where x is a positive integer. The transmission circuit is used to implement multi-bit operations and includes: an eighth transistor and a ninth transistor. The second terminal of the cross-coupled inverter of the first latch circuit in cache lock group x is connected to the first terminal of the eighth transistor, the second terminal of the eighth transistor is connected to the first terminal of the ninth transistor, the second terminal of the ninth transistor is grounded, the control terminal of the eighth transistor is connected to the first terminal of the cross-coupled inverter of the latch circuit used for caching carry data in cache lock group x+1, and the control terminal of the ninth transistor receives the transmission control signal used to activate multi-bit operation.

7. The cache lock group according to claim 6, characterized in that, The control terminals of the ninth transistors of each adjacent 4N bit lines share the same transmission control signal to support 4N bit data types, where N is a positive integer.

8. The cache lock group according to claim 3, characterized in that, The cache lock group performs addition operations through bitwise operations to obtain the addition result.

9. A memory, characterized in that, The memory includes a cache lock group as described in any one of claims 1 to 8.

10. An electronic device, characterized in that, The electronic device includes a cache lock group as described in any one of claims 1 to 8.

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