Display device

Abstract

A display device according to an embodiment of the present disclosure includes: a substrate; the driving chip is arranged on the substrate; a plurality of banks disposed on the driving chip; a plurality of first electrodes, at least one of the plurality of first electrodes disposed on the plurality of banks and electrically connected to the driving chip; a plurality of solder patterns disposed on the plurality of first electrodes, respectively; a plurality of light emitting elements respectively disposed on some of the plurality of solder patterns; a first optical layer disposed around the plurality of banks and the plurality of light emitting elements, and having at least one recess exposing at least one solder pattern on which the light emitting elements are not disposed; and an insulating pattern disposed on the solder pattern in the recess of the first optical layer.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a display device. BACKGROUND

[0002] Display devices are applied to various electronic devices such as TVs, mobile phones, notebook computers, and tablet computers.

[0003] Examples of display devices include organic light emitting display (OLED) devices having self-emission of light, liquid crystal display (LCD) devices requiring a separate light source, and the like.

[0004] Recently, display devices including light emitting diodes (LEDs) are attracting attention as next-generation display devices. Since light emitting diodes are formed of inorganic materials rather than organic materials, display devices including LEDs have faster lightening speed, better light emitting efficiency, and higher brightness images than LCD or OLED devices. SUMMARY

[0005] The disclosure aims to provide a display device capable of preventing short circuit between a first electrode and a second electrode for driving a light emitting element in a sub-pixel in which the light emitting element is omitted.

[0006] The objects of the disclosure are not limited to the above-mentioned objects, and other objects not mentioned will be clearly understood by those skilled in the art based on the following description.

[0007] According to an embodiment of the disclosure, there is provided a display device including a substrate, a driving chip disposed on the substrate, a plurality of bank portions disposed on the driving chip, a plurality of first electrodes of which at least one is disposed on each of the plurality of bank portions and electrically connected to the driving chip, a plurality of solder patterns respectively disposed on the plurality of first electrodes, a plurality of light emitting elements respectively disposed on some of the plurality of solder patterns, a first optical layer disposed around the plurality of bank portions and the plurality of light emitting elements and having at least one recess exposing at least one solder pattern on which the light emitting element is not disposed, and an insulating pattern disposed on the solder pattern in the recess of the first optical layer.

[0008] According to an embodiment of the present disclosure, there is provided a display device including a substrate; a signal line disposed on the substrate; a plurality of first electrodes connected to the signal line; a plurality of solder patterns respectively disposed on the plurality of first electrodes; a plurality of light emitting elements respectively disposed on some of the plurality of solder patterns; a first optical layer disposed around the plurality of light emitting elements and having at least one recess exposing at least one solder pattern on which the light emitting element is not disposed; and an insulating pattern disposed on the solder pattern in the recess of the first optical layer. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is an exploded perspective view of a display device according to an embodiment of the present disclosure.

[0010] Figure 2 is a plan view of a display device according to an embodiment of the present disclosure.

[0011] Figure 3 is an enlarged view of a display device according to an embodiment of the present disclosure.

[0012] Figure 4 is a diagram illustrating a circuit structure according to an embodiment of the present disclosure.

[0013] Figure 5 is a plan view of a display device according to an embodiment of the present disclosure.

[0014] Figure 6 is a plan view of a display device according to an embodiment of the present disclosure.

[0015] Figure 7 is a plan view of a display device according to an embodiment of the present disclosure.

[0016] Figure 8 is a sectional view of a display device according to an embodiment of the present disclosure.

[0017] Figure 9 is a sectional view of a display device according to an embodiment of the present disclosure.

[0018] Figures 10 to 13 is a diagram illustrating a device to which a display device according to an embodiment of the present disclosure is applied.

[0019] Figure 14 is a plan view of a display panel according to an embodiment of the present disclosure.

[0020] Figure 15 is a diagram illustrating a device to which a display device according to an embodiment of the present disclosure is applied. Figure 14a plan view of a region of one of the plurality of drive chips of the display device.

[0021] Figure 16 is a diagram illustrating a touch operation of a display device according to an embodiment of the present disclosure.

[0022] Figure 17 is an example diagram illustrating a signal waveform diagram when driving a display device according to an embodiment of the present disclosure.

[0023] Figure 18 is a cross-sectional view along line XVIII-XVIII of the display device of Figure 14

[0024] Figure 19 is an enlarged plan view of a display region including one pixel of a display device according to an embodiment of the present disclosure.

[0025] Figure 20 is a cross-sectional view along line XX-XX of the display device of Figure 19

[0026] Figures 21 to 23 is a cross-sectional view of a display device according to an embodiment of the present disclosure and is a cross-sectional view corresponding to Figure 20

[0027] Figures 24A to 24C is a cross-sectional view for describing a method of manufacturing an insulating pattern shown in Figure 20 DETAILED DESCRIPTION

[0028] The advantages and features of the present disclosure and a method of achieving the advantages and features will become apparent from the embodiments described below in detail with reference to the accompanying drawings. The present disclosure, however, is not limited to the embodiments disclosed below and can be implemented in various different forms, and the embodiments are provided only to make the disclosure complete and to fully convey the scope of the present disclosure to those skilled in the art.

[0029] Since shapes, sizes, ratios, angles, numbers, and the like disclosed in the accompanying drawings for describing the embodiments of the present disclosure are illustrative, the present disclosure is not limited to the stated matters. Throughout the disclosure, the same reference numerals refer to the same components. Also, in describing the present disclosure, when it is determined that a detailed description of the related known technology can unnecessarily obscure the gist of the present disclosure, the detailed description thereof will be omitted. When the terms "include", "have", "comprise", and the like are used in the present disclosure, other parts can be added unless "only" is used. When a component is expressed in a singular form, unless there is a specific expression, it can include a case in which the component is provided as a plurality of components.

[0030] ​​​​In explaining components, the components are explained as including an error margin, even if there is no separate explicit description related to the error margin.

[0031] When describing positional relationships, for example, when describing the positional relationship between two components using "upper", "above", "below", "next to", etc., one or more other components can be disposed between the two components, unless "immediately", "directly", or "closely" is used.

[0032] When describing temporal relationships, for example, when describing the temporal relationship using "after", "later", "next", "before", etc., it can also include a discontinuous case, unless "immediately" or "directly" is used.

[0033] Although terms such as first and second are used to describe various components, the components should not be limited by these terms. These terms are used only to distinguish one component from another component. Therefore, the first component described below can be a second component within the scope of the technical spirit of the disclosure.

[0034] In describing the components of the disclosure, terms such as first, second, A, B, (a), and (b) can be used. These terms are only for the purpose of distinguishing one component from another component, and the nature, order, sequence, etc. of the corresponding components are not limited by these terms.

[0035] When a certain component is described as being "connected", "joined", "engaged", or "attached" to another component, the certain component can be directly connected, joined, engaged, or attached to the other component, but it should be understood that unless specifically set forth, they can be indirectly connected, joined, engaged, or attached to each other with another component interposed therebetween.

[0036] When a component or layer is described as being "in contact" or "overlapping" with another component or layer, a component or layer can be in direct contact or overlapping with another component or layer, but it should be understood that unless specifically set forth, they can also be indirectly in contact or overlapping with each other with another component or layer interposed therebetween.

[0037] It should be understood that the term "at least one" includes any combination of one or more related components. For example, the meaning of the term "at least one of the first component, the second component, and the third component" can include not only the first component, the second component, or the third component, but also any combination of two or more of the first component, the second component, and the third component.

[0038] The terms "first direction", "second direction", "third direction", "X-axis direction", "Y-axis direction", and "Z-axis direction" should not be interpreted as a geometric relationship in which they are perpendicular to each other only, but can represent a wider directionality within a range in which the configuration of the present disclosure can functionally work.

[0039] Features of various embodiments of the present disclosure can be partially or wholly combined or integrated, can be variously inter-operable and drivable, and embodiments can be implemented independently of or in association with each other.

[0040] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0041] Figure 1 is an exploded perspective view of a display device according to an embodiment of the present disclosure. Figure 2 is a plan view of a display device according to an embodiment of the present disclosure. Figure 3 is an enlarged view of a display device according to an embodiment of the present disclosure.

[0042] Referring to Figures 1 to 3 The display device 1000 according to an embodiment of the present disclosure can include a display panel 100, a polarizing layer 293, an adhesive layer 295, a cover member 155, a support substrate 145, a flexible circuit board 157, and a printed circuit board 160.

[0043] For example, the display device 1000 can include a substrate 110. The substrate 110 can be a member that supports other components of the display device 1000. The substrate 110 can be made of an insulating material. For example, the substrate 110 can be made of glass or resin. Alternatively, the substrate 110 can be made of a material having flexibility. For example, the substrate 110 can be made of a plastic material having flexibility such as polyimide (PI). However, embodiments of the present disclosure are not limited thereto.

[0044] The display panel 100 can implement information, a video, and / or an image to be provided to a user. For example, the display panel 100 can include a display area AA and a non-display area NA. For example, the substrate 110 can include the display area AA and the non-display area NA. The distinction between the display area AA and the non-display area NA is applicable not only to the substrate 110 but also to the entire display device 1000.

[0045] The display area AA can be an area in which an image is displayed. The display area AA can include a plurality of pixels PX. Each of the plurality of pixels PX can be composed of a plurality of sub-pixels. A plurality of light emitting elements can be provided at each of the plurality of sub-pixels. The plurality of light emitting elements can be variously configured according to the kind of the display device 1000. For example, in the case where the display device 1000 is an inorganic light emitting display device, the light emitting elements can be light emitting diodes (LEDs), micro LEDs, or mini LEDs. However, embodiments of the present disclosure are not limited thereto.

[0046] The non-display area NA can be an area in which an image is not displayed. In the non-display area NA, various kinds of wiring and circuitry for driving the plurality of pixels PX in the display area AA can be provided. For example, various kinds of wiring and driving circuitry can be mounted in the non-display area NA, and a pad portion PAD connected to an integrated circuit and a printed circuit can be provided in the non-display area NA. However, embodiments of the present disclosure are not limited thereto.

[0047] For example, the driving circuitry can be data driving circuitry and / or gate driving circuitry. However, embodiments of the present disclosure are not limited thereto. In the non-display area NA, wiring through which a control signal for controlling the driving circuitry is provided can be provided. For example, the control signal can include various kinds of timing signals including a synchronization signal, an input data enable signal, and a clock signal. However, embodiments of the present disclosure are not limited thereto. The control signal can be received through the pad portion PAD. For example, in the non-display area NA, a wire LL for transmitting a signal can be provided. For example, a driving component such as a flexible circuit board 157 and a printed circuit board 160 can be connected to the pad portion PAD.

[0048] According to the present disclosure, the non-display area NA can include a first non-display area NA1, a bending area BA, and a second non-display area NA2. For example, the first non-display area NA1 can be an area surrounding at least a portion of the display area AA. The bending area BA can be an area that is bendable and extends from at least one of a plurality of edges of the first non-display area NA1. The second non-display area NA2 can be an area extending from the bending area BA, and the pad portion PAD can be provided therein. For example, the bending area BA can be in a bent state, and the remaining area of the substrate 110 other than the bending area BA can be in a flat state. In this case, when the bending area BA is bent, the second non-display area NA2 can be located on the rear surface of the display area AA. However, embodiments of the present disclosure are not limited thereto.

[0049] The substrate 110 or the display area AA of the display device 1000 can be configured in various shapes according to the design of the display device 1000. For example, the display area AA can be configured in a rectangular shape having four rounded corners. However, embodiments of the present disclosure are not limited thereto. For example, the display area AA can be configured in a rectangular shape having four right-angled corners, a circular shape, or the like. However, embodiments of the present disclosure are not limited thereto.

[0050] According to the present disclosure, the width of the second non-display area NA2 in which the plurality of pad electrodes PE are disposed can be greater than the width of the bending area BA in which only the plurality of connection lines LL are disposed. Further, the width of the display area AA in which the plurality of sub-pixels are disposed can be greater than the width of the bending area BA in which only the plurality of connection lines LL are disposed. Although the width of the bending area BA is depicted as being smaller than the width of other areas of the substrate 110 in the drawing, the shape of the substrate 110 including such a bending area BA is merely an example, and embodiments of the present disclosure are not limited thereto.

[0051] Referring to Figure 3 A plurality of pixel driving circuits PD can be disposed in the display area AA. The plurality of pixel driving circuits PD can be circuits for driving light emitting elements of the plurality of sub-pixels. Each of the plurality of pixel driving circuits PD can include a plurality of transistors including a driving transistor, a storage capacitor, or the like, and can control the light emitting operation of the plurality of light emitting elements by providing a control signal, power, and a driving current to the light emitting elements of the plurality of sub-pixels. For example, the pixel driving circuit PD can include a power line and a signal line for controlling the on / off and / or light emitting time of the light emitting element. For example, the plurality of pixel driving circuits PD can be a driving chip manufactured on a semiconductor substrate using a metal oxide silicon field effect transistor (MOSFET) manufacturing process. However, embodiments of the present disclosure are not limited thereto. The driving chip can include the plurality of pixel driving circuits PD, and can drive the plurality of sub-pixels. For example, the plurality of pixel driving circuits PD can belong to a micro driver, which is a kind of driving chip having a size of tens of μm to hundreds of μm. However, embodiments of the present disclosure are not limited thereto.

[0052] Referring to Figure 1 A flexible circuit board 157 and a printed circuit board 160 can be disposed on the lower side of the display panel 100. The flexible circuit board 157 and the printed circuit board 160 can be disposed on at least one edge of the display panel 100. However, embodiments of the present disclosure are not limited thereto. One side of the flexible circuit board 157 can be attached to the display panel 100, and the other side of the flexible circuit board 157 can be attached to the printed circuit board 160. However, embodiments of the present disclosure are not limited thereto. The flexible circuit board 157 can be made of a flexible film. However, embodiments of the present disclosure are not limited thereto.

[0053] In the second non-display area NA2, a pad portion PAD including a plurality of pad electrodes PE can be disposed. A driving part including one or more flexible circuit boards (or flexible films) 157 and a printed circuit board 160 can be attached or bonded to the pad portion PAD. The plurality of pad electrodes PE of the pad portion PAD can be electrically connected to the one or more flexible circuit boards (or flexible films) 157 to transmit various signals or power from the printed circuit board 160 and the flexible circuit board (or flexible film) 157 to the plurality of pixel driving circuits PD in the display area AA.

[0054] The flexible circuit board (or flexible film) 157 can be a film in which various components are disposed on a flexible base film. For example, a driving IC such as a gate driver IC or a data driver IC can be disposed on the flexible circuit board (or flexible film) 157. However, embodiments of the present disclosure are not limited thereto. The driving IC can be a component that processes data and driving signals for displaying an image. According to a mounting method, the driving IC can be disposed in a manner such as chip on glass (COG), chip on film (COF), or tape carrier package (TCP). However, embodiments of the present disclosure are not limited thereto. The flexible circuit board (or flexible film) 157 can be attached or bonded to the plurality of pad electrodes PE via a conductive adhesive layer. However, embodiments of the present disclosure are not limited thereto.

[0055] The printed circuit board 160 can be a component electrically connected to the one or more flexible circuit boards (or flexible films) 157 to provide signals to the driving IC. The printed circuit board 160 can be disposed on one side of the flexible circuit board (or flexible film) 157 to be electrically connected to the flexible circuit board (or flexible film) 157. Various components for providing various signals to the driving IC can be disposed on the printed circuit board 160. For example, various components including a timing controller, a power supply, a memory, a processor, etc. can be disposed on the printed circuit board 160. For example, the printed circuit board 160 can be provided with a power management integrated circuit (PMIC). However, embodiments of the present disclosure are not limited thereto.

[0056] The printed circuit board 160 can include at least one hole 180. However, embodiments of the present disclosure are not limited thereto. In an area corresponding to the at least one hole 180, an internal component that detects ambient light, temperature, etc. can be disposed. The internal component can include a plurality of sensors. For example, the internal component can include an ambient light sensor (ALS) or a temperature sensor. However, embodiments of the present disclosure are not limited thereto. For example, the hole 180 can be a through-hole. However, embodiments of the present disclosure are not limited thereto.

[0057] Referring to Figure 1A polarizing layer 293 can be disposed on the display panel 100. The polarizing layer 293 can prevent or reduce a phenomenon in which light generated by an external light source enters the display panel 100 and affects the light emitting element or the like. The polarizing layer 293 can prevent or reduce reflection of external light due to components of the display panel 100.

[0058] A cover member 155 can be disposed on the polarizing layer 293. The cover member 155 can be a member for protecting the display panel 100. An adhesive layer 295 can be disposed between the polarizing layer 293 and the cover member 155. The cover member 155 can be attached to the polarizing layer 293 by the adhesive layer 295. The adhesive layer 295 can include an optical clear adhesive (OCA), an optical clear resin (OCR), a pressure sensitive adhesive (PSA), or the like. However, embodiments of the present disclosure are not limited thereto.

[0059] A support substrate 145 can be disposed between the display panel 100 and the printed circuit board 160. The support substrate 145 can strengthen the rigidity of the display panel 100. The support substrate 145 can be a back plate. However, embodiments of the present disclosure are not limited thereto.

[0060] Referring to Figures 1 to 3 A plurality of lines LL can be disposed in the non-display area NA. The plurality of lines LL can be wiring for transmitting various signals from the one or more flexible circuit boards (or flexible films) 157 and the printed circuit board 160 to the display area AA. The plurality of lines LL can extend from the plurality of pad electrodes PE in the second non-display area NA2 toward the bending area BA and the first non-display area NA1 to be electrically connected to the plurality of drive lines VL in the display area AA. The plurality of pixel driving circuits PD can be driven by receiving signals from the one or more flexible circuit boards (or flexible films) 157 and the printed circuit board 160 through the drive lines VL in the display area AA and the lines LL in the non-display area NA.

[0061] For example, the plurality of drive lines VL can be wiring for transmitting signals output from the flexible circuit board (or flexible film) 157 and the printed circuit board 160 to the plurality of pixel driving circuits PD together with the plurality of lines LL. The plurality of drive lines VL can be disposed in the display area AA to be electrically connected to each of the plurality of pixel driving circuits PD. The plurality of drive lines VL can extend from the display area AA toward the non-display area NA to be electrically connected to the plurality of lines LL. Accordingly, the signals output from the flexible circuit board (or flexible film) 157 and the printed circuit board 160 can be transmitted to each of the plurality of pixel driving circuits PD through the plurality of lines LL and the plurality of drive lines VL.

[0062] When the bending region BA is bent, a part of the plurality of lines LL also bends together. Stress can concentrate on the part of the lines LL that is bent, which can cause a crack to occur in the lines LL. Thus, the plurality of lines LL can be made of a conductive material having excellent ductility to reduce a crack when the bending region BA is bent. For example, the plurality of lines LL can be configured of a conductive material having excellent ductility such as gold (Au), silver (Ag), aluminum (Al), or the like. However, embodiments of the present disclosure are not limited thereto. Alternatively, the plurality of lines LL can be configured of one of various conductive materials used in the display region AA. For example, the plurality of lines LL can be configured of an alloy of molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), silver (Ag), and magnesium (Mg), or any alloy thereof. However, embodiments of the present disclosure are not limited thereto. The plurality of lines LL can be configured of a multi-layer structure including various conductive materials. For example, the plurality of lines LL can be configured of a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti). However, embodiments of the present disclosure are not limited thereto.

[0063] The plurality of lines LL can be configured in various shapes to reduce stress. At least a part of the plurality of lines LL provided on the bending region BA can extend in the same direction as the extension direction of the bending region BA, or can extend in a direction different from the extension direction of the bending region BA to reduce stress. For example, in the case where the bending region BA extends in one direction from the first non-display region NA1 toward the second non-display region NA2, at least a part of the lines LL provided on the bending region BA can extend in a direction inclined with respect to the one direction. In another example, at least a part of the plurality of lines LL can be configured in a pattern of various shapes. For example, at least a part of the plurality of lines LL provided on the bending region BA can have a shape in which a conductive pattern having at least one of a diamond shape, a lozenge shape, a trapezoidal wave shape, a triangular wave shape, a sawtooth wave shape, a sinusoidal wave shape, a circle, and an omega (Ω) shape can be repeatedly provided. However, embodiments of the present disclosure are not limited thereto. Thus, in order to minimize stress concentrated on the plurality of lines LL and a crack generated, the shape of the plurality of lines LL can be formed in various shapes including the above-described shapes. However, embodiments of the present disclosure are not limited thereto.

[0064] Figure 4 FIG. 1 is a diagram illustrating a circuit structure according to an embodiment of the present disclosure.

[0065] In Figure 4In the present embodiment, as an example, one light emitting element ED is connected to one micro driver μDriver. However, embodiments of the present disclosure are not limited thereto. For example, eight light emitting elements (LEDs) can be connected to one micro driver. In another example, sixteen light emitting elements ED can be connected to one micro driver, or thirty-two light emitting elements ED or sixty-four light emitting elements ED can be connected to one micro driver at the same time. The light emitting element ED can be a micro light emitting element (micro LED).

[0066] One micro driver can include at least one drive transistor T DR and at least one light emitting transistor T EM . However, embodiments of the present disclosure are not limited thereto.

[0067] For example, the drive transistor T DR may have a first electrode to which a high potential power voltage VDD is applied, a second electrode connected to a first electrode of the light emitting transistor T EM , and a gate electrode to which a scan signal SC is applied. The scan signal SC applied to the gate electrode of the drive transistor T DR may be a direct current (DC) power, and a fixed reference voltage Vref can be applied per frame. However, embodiments of the present disclosure are not limited thereto.

[0068] The light emitting transistor T EM may have a first electrode connected to the second electrode of the drive transistor T DR , a second electrode connected to the light emitting element ED, and a gate electrode to which a light emitting signal EM is applied. The light emitting signal EM applied to the gate electrode of the light emitting transistor T EM may be a pulse width modulation (PWM) signal that varies per frame. However, embodiments of the present disclosure are not limited thereto.

[0069] The light emitting element ED can have a first electrode connected to the second electrode of the light emitting transistor T EM , and a second electrode connected to the ground. For example, the first electrode can be an anode electrode, and the second electrode can be a cathode electrode. However, embodiments of the present disclosure are not limited thereto.

[0070] Each of the drive transistor T DR and the light emitting transistor T EM may be an n-type or a p-type transistor.

[0071] In the micro driver, the drive transistor T DR may be turned on by a scan signal SC applied from a timing controller (T-CON), and the light emitting transistor T EM may be turned on by a light emitting signal EM. By doing so, a voltage Vdata applied to the drive transistor T DRThe high potential power supply voltage VDD of the first electrode can be driven by transistor T DR and light-emitting transistor T EM A driving current is applied to the light-emitting element (ED), causing the ED to emit light.

[0072] Figures 5 to 7 This is a plan view of a display device according to an embodiment of the present disclosure. Figure 8 and Figure 9 This is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0073] For example, Figure 5 It is a magnified planar view of a display area that includes multiple pixels. For example, Figure 6 It is a magnified planar view of a display area including one pixel. For example, Figure 7 It is a magnified planar view of a display area that includes multiple pixels. For example, Figure 8 This is a cross-sectional view of the display area AA, the first non-display area NA, the curved area BA, and the second non-display area NA2. For example, Figure 9 It is a cross-sectional view of the display area including a sub-pixel SP1.

[0074] exist Figure 5 and Figure 6 The diagram only shows multiple signal lines TL, multiple communication lines NL, multiple first electrodes CE1, multiple embankments BNK, and multiple light-emitting elements ED. However, embodiments of this disclosure are not limited to this. Figure 7 It is one of the gifts Figure 5 An enlarged planar view showing the additional setup of multiple second electrodes CE2.

[0075] Reference Figure 5 , Figure 6 and Figure 9 Multiple pixels PX, configured as multiple subpixels, can be set in the display area AA. Each of the multiple subpixels may include a light-emitting element ED and can emit light independently. The multiple subpixels can be arranged in multiple rows and multiple columns, and therefore can be arranged in a matrix form. However, the embodiments of this disclosure are not limited thereto.

[0076] Multiple sub-pixels may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. For example, one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be a red sub-pixel, another may be a green sub-pixel, and the remaining one may be a blue sub-pixel. The types of multiple sub-pixels are given by way of example only, and the implementation of this disclosure is not limited thereto.

[0077] Each of the plurality of pixels PX can include one or more first sub-pixels SP1, one or more second sub-pixels SP2, and one or more third sub-pixels SP3. For example, one pixel PX can include a pair of first sub-pixels SP1, a pair of second sub-pixels SP2, and a pair of third sub-pixels SP3. The pair of first sub-pixels SP1 can include a 1-1 sub-pixel SP1a and a 1-2 sub-pixel SP1b. The pair of second sub-pixels SP2 can include a 2-1 sub-pixel SP2a and a 2-2 sub-pixel SP2b. The pair of third sub-pixels SP3 can include a 3-1 sub-pixel SP3a and a 3-2 sub-pixel SP3b. For example, one pixel PX can include a 1-1 sub-pixel SP1a and a 1-2 sub-pixel SP1b, a 2-1 sub-pixel SP2a and a 2-2 sub-pixel SP2b, and a 3-1 sub-pixel SP3a and a 3-2 sub-pixel SP3b. However, embodiments of the present disclosure are not limited thereto.

[0078] The plurality of sub-pixels constituting one pixel PX can be arranged in various ways. For example, in one pixel PX, the pair of first sub-pixels SP1 can be disposed in the same column, the pair of second sub-pixels SP2 can be disposed in the same column, and the pair of third sub-pixels SP3 can be disposed in the same column. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be disposed in the same row. The number and arrangement of the plurality of sub-pixels constituting one pixel PX are given by way of example only, and embodiments of the present disclosure are not limited thereto.

[0079] The plurality of signal lines TL can be disposed in regions between the plurality of sub-pixels. The plurality of signal lines TL can extend in the column direction while being disposed between adjacent sub-pixels among the plurality of sub-pixels. The plurality of signal lines TL can be wiring lines that transmit an anode voltage from the pixel driving circuit PD to the plurality of sub-pixels. For example, the plurality of signal lines TL can be electrically connected to the plurality of pixel driving circuits PD and the first electrodes CE1 of the plurality of sub-pixels. The anode voltage output from the pixel driving circuit PD can be transmitted to the first electrodes CE1 of the plurality of sub-pixels through the plurality of signal lines TL. For example, the first electrode CE1 can be an electrode electrically connected to the anode electrode 134 of the light emitting element ED. Thereby, the anode voltage from the signal line TL can be transmitted to the anode electrode 134 of the light emitting element ED through the first electrode CE1.

[0080] Accordingly, instead of forming a plurality of transistors and storage capacitors in each of the plurality of sub-pixels, by using the pixel driving circuit PD in which a plurality of pixel circuits are integrated, the structure of the display device 1000 can be simplified. Further, since the circuit disposed in each of the plurality of sub-pixels is integrated into one pixel driving circuit PD, high efficiency and low power driving can be achieved.

[0081] The plurality of signal lines TL can include a first signal line TL1, a second signal line TL2, a third signal line TL3, a fourth signal line TL4, a fifth signal line TL5, and a sixth signal line TL6. Each of the first signal line TL1 and the second signal line TL2 can be electrically connected to a pair of first sub-pixels SP1. Each of the third signal line TL3 and the fourth signal line TL4 can be electrically connected to a pair of second sub-pixels SP2. Each of the fifth signal line TL5 and the sixth signal line TL6 can be electrically connected to a pair of third sub-pixels SP3.

[0082] The first signal line TL1 can be disposed at one side of the pair of first sub-pixels SP1, and the second signal line TL2 can be disposed at the other side of the pair of first sub-pixels SP1. The first signal line TL1 can be electrically connected to a first electrode CE1 of one first sub-pixel SP1 (e.g., 1-1 sub-pixel SP1a) of the pair of first sub-pixels SP1. The second signal line TL2 can be electrically connected to first electrodes CE1 of the remaining first sub-pixels SP1 (e.g., 1-2 sub-pixel SP1b) of the pair of first sub-pixels SP1.

[0083] The third signal line TL3 can be disposed at one side of the pair of second sub-pixels SP2, and the fourth signal line TL4 can be disposed at the other side of the pair of second sub-pixels SP2. For example, the third signal line TL3 can be disposed adjacent to the second signal line TL2. The third signal line TL3 can be electrically connected to a first electrode CE1 of one second sub-pixel SP2 (e.g., 2-1 sub-pixel SP2a) of the pair of second sub-pixels SP2. The fourth signal line TL4 can be electrically connected to first electrodes CE1 of the remaining second sub-pixels SP2 (e.g., 2-2 sub-pixel SP2b) of the pair of second sub-pixels SP2.

[0084] The fifth signal line TL5 can be disposed at one side of the pair of third sub-pixels SP3, and the sixth signal line TL6 can be disposed at the other side of the pair of third sub-pixels SP3. For example, the fifth signal line TL5 can be disposed adjacent to the fourth signal line TL4. The sixth signal line TL6 can be disposed adjacent to the first signal line TL1 connected to an adjacent pixel PX. The fifth signal line TL5 can be electrically connected to a first electrode CE1 of one third sub-pixel SP3 (e.g., 3-1 sub-pixel SP3a) of the pair of third sub-pixels SP3. The sixth signal line TL6 can be electrically connected to first electrodes CE1 of the remaining third sub-pixels SP3 (e.g., 3-2 sub-pixel SP3b) of the pair of third sub-pixels SP3.

[0085] The plurality of signal lines TL can be made of an electrically conductive material. For example, the plurality of signal lines TL can be made of an electrically conductive material such as titanium (Ti), aluminum (Al), copper (Cu), molybdenum (Mo), nickel (Ni), chromium (Cr), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), or the like. However, embodiments of the present disclosure are not limited thereto. In another example, the plurality of signal lines TL can be formed of a multi-layer structure of an electrically conductive material. For example, the plurality of signal lines TL can be configured as a multi-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti) / indium tin oxide (ITO). However, embodiments of the present disclosure are not limited thereto.

[0086] The plurality of communication lines NL can be provided in a region between the plurality of pixels PX. The plurality of communication lines NL can be provided to extend in the row direction in a region between adjacent pixels in the plurality of pixels PX. The plurality of communication lines NL can be provided in a region between adjacent second electrodes CE2 in the plurality of second electrodes CE2, and can not overlap the plurality of second electrodes CE2. For example, the plurality of communication lines NL can be wiring for short distance communication such as near field communication (NFC). The plurality of communication lines NL can function as an antenna. For example, the plurality of communication lines NL can be a plurality of connection lines, or the like. However, embodiments of the present disclosure are not limited thereto.

[0087] According to the present disclosure, the bank BNK can be provided in each of the plurality of sub-pixels. The plurality of banks BNK can be a structure on which the plurality of light emitting elements ED are mounted. The plurality of banks BNK can guide the positions of the plurality of light emitting elements ED in a transfer process of transferring the plurality of light emitting elements ED to the display device 1000. In the transfer process of the plurality of light emitting elements ED, the plurality of light emitting elements ED can be transferred onto the plurality of banks BNK. The plurality of banks BNK can be a bank pattern or a bank structure. However, embodiments of the present disclosure are not limited thereto.

[0088] The bank BNK of the first sub-pixel SP1, the bank BNK of the second sub-pixel SP2, and the bank BNK of the third sub-pixel SP3 can be provided to be separated from each other. The bank BNK of the first sub-pixel SP1, the bank BNK of the second sub-pixel SP2, and the bank BNK of the third sub-pixel SP3 can be configured to be separated from each other. Accordingly, it is possible to easily recognize the banks BNK of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 to which light emitting elements ED of different types are transferred.

[0089] The bank BNK of the 1st-1 sub-pixel SP1a and the bank BNK of the 1st-2 sub-pixel SP1b can be connected to each other, or can be formed to be separated or isolated from each other. For example, the bank BNK of the 1st-1 sub-pixel SP1a and the bank BNK of the 1st-2 sub-pixel SP1b, which are provided with the same type of light emitting element ED, can be connected to each other, or can be separated or isolated from each other in consideration of design requirements of a transfer process or the like. Further, the bank BNK of the 2nd-1 sub-pixel SP2a and the bank BNK of the 2nd-2 sub-pixel SP2b can be connected to each other, or can be formed to be separated or isolated from each other. The bank BNK of the 3rd-1 sub-pixel SP3a and the bank BNK of the 3rd-2 sub-pixel SP3b can be connected to each other, or can be formed to be separated or isolated from each other. Thus, the banks BNK of the pair of first sub-pixels SP1, the pair of second sub-pixels SP2, and the pair of third sub-pixels SP3 can be formed in various ways, and thus embodiments of the present disclosure are not limited thereto.

[0090] For example, the plurality of banks BNK can be made of an organic insulating material. The plurality of banks BNK can be configured in a single layer or a multi-layer structure of an organic insulating material. For example, the plurality of banks BNK can be made of a photoresist, a polyimide (PI), or an acrylic material, or the like. However, embodiments of the present disclosure are not limited thereto.

[0091] A first electrode CE1 can be provided on each of the plurality of sub-pixels. The first electrode CE1 can be provided on the bank BNK. The first electrode CE1 can be electrically connected to one of the plurality of signal lines TL. At least a portion of the first electrode CE1 can extend outside the bank BNK to be electrically connected to the signal line TL closest to the first electrode CE1. For example, a portion of the first electrode CE1 of the 1st-1 sub-pixel SP1a can extend to one side region of the 1st-1 sub-pixel SP1a to be electrically connected to the first signal line TL1, and a portion of the first electrode CE1 of the 1st-2 sub-pixel SP1b can extend to the other side region of the 1st-2 sub-pixel SP1b to be electrically connected to the second signal line TL2. A portion of the first electrode CE1 of the 2nd-1 sub-pixel SP2a can extend to one side region of the 2nd-1 sub-pixel SP2a to be electrically connected to the third signal line TL3, and a portion of the first electrode CE1 of the 2nd-2 sub-pixel SP2b can extend to the other side region of the 2nd-2 sub-pixel SP2b to be electrically connected to the fourth signal line TL4. A portion of the first electrode CE1 of the 3rd-1 sub-pixel SP3a can extend to one side region of the 3rd-1 sub-pixel SP3a to be electrically connected to the fifth signal line TL5, and a portion of the first electrode CE1 of the 3rd-2 sub-pixel SP3b can extend to the other side region of the 3rd-2 sub-pixel SP3b to be electrically connected to the sixth signal line TL6.

[0092] The first electrode CE1 can be electrically connected to the anode electrode 134 of the light emitting element ED to transmit an anode voltage from the pixel driving circuit PD to the light emitting element ED through the signal line TL. Different voltages can be applied to the first electrode CE1 of each of the plurality of sub-pixels according to an image to be displayed. For example, different voltages can be applied to the first electrode CE1 of each of the plurality of sub-pixels. The first electrode CE1 can be a pixel electrode, and embodiments of the present disclosure are not limited thereto.

[0093] The first electrode CE1 can be made of a conductive material. For example, the first electrode CE1 can be integrally constituted with the plurality of signal lines TL. For example, the first electrode CE1 can be made of the same conductive material as the plurality of signal lines TL. However, embodiments of the present disclosure are not limited thereto. For example, the first electrode CE1 can be made of a conductive material such as titanium (Ti), aluminum (Al), copper (Cu), molybdenum (Mo), nickel (Ni), chromium (Cr), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), or the like. However, embodiments of the present disclosure are not limited thereto. In another example, the first electrode CE1 can be constituted as a multi-layer structure of a conductive material. For example, the plurality of first electrodes CE1 can be constituted as a multi-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti) / indium tin oxide (ITO). However, embodiments of the present disclosure are not limited thereto.

[0094] The light emitting element ED can be provided in each of the plurality of sub-pixels. The plurality of light emitting elements ED can be any one of a light emitting diode (LED) and a micro light emitting diode (Micro LED). However, embodiments of the present disclosure are not limited thereto. The plurality of light emitting elements ED can be provided on the bank BNK and the first electrode CE1. Each of the plurality of light emitting elements ED can be provided on the first electrode CE1 to be electrically connected to the first electrode CE1. Thus, the light emitting element ED can emit light by receiving an anode voltage from the pixel driving circuit PD through the signal line TL and the first electrode CE1.

[0095] Each of the plurality of light emitting elements ED can include a first light emitting element 130, a second light emitting element 140, and a third light emitting element 150. The first light emitting element 130 can be disposed in the first sub-pixel SP1. The second light emitting element 140 can be disposed in the second sub-pixel SP2. The third light emitting element 150 can be disposed in the third sub-pixel SP3. For example, one of the first light emitting element 130, the second light emitting element 140, and the third light emitting element 150 can be a red light emitting element, another can be a green light emitting element, and the remaining one can be a blue light emitting element. However, embodiments of the present disclosure are not limited thereto. Thus, by combining red light, green light, and blue light emitted from the plurality of light emitting elements ED, light of various colors including white can be implemented. The types of the plurality of light emitting elements ED are given only as an example, and embodiments of the present disclosure are not limited thereto.

[0096] The first light emitting element 130 can include a first-1 light emitting element 130a disposed in a first-1 sub-pixel SP1a and a first-2 light emitting element 130b disposed in a first-2 sub-pixel SP1b. The second light emitting element 140 can include a second-1 light emitting element 140a disposed in a second-1 sub-pixel SP2a and a second-2 light emitting element 140b disposed in a second-2 sub-pixel SP2b. The third light emitting element 150 can include a third-1 light emitting element 150a disposed in a third-1 sub-pixel SP3a and a third-2 light emitting element 150b disposed in a third-2 sub-pixel SP3b.

[0097] Referring to FIGS. 1A and 1B together, Figure 5 , Figure 6 , Figure 7 and Figure 9 A second electrode CE2 can be disposed on each of the plurality of sub-pixels. The second electrode CE2 can be disposed on the light emitting element ED. The second electrode CE2 can be electrically connected to the pixel driving circuit PD through the plurality of contact electrodes CCE.

[0098] For example, the second electrode CE2 can be electrically connected to the cathode electrode 135 of the light emitting element ED to transmit a cathode voltage from the pixel driving circuit PD to the light emitting element ED. The same cathode voltage can be applied to the second electrode CE2 of each of the plurality of sub-pixels. For example, the same voltage can be applied to the second electrode CE2 of each of the plurality of sub-pixels and the cathode electrode 135 of the light emitting element ED. The second electrode CE2 can be a common electrode. However, embodiments of the present disclosure are not limited thereto.

[0099] At least some of the plurality of sub-pixels can share the second electrode CE2 with each other. At least some of the second electrodes CE2 of the plurality of respective sub-pixels can be electrically connected to each other. The second electrodes CE2 can be shared for at least some of the sub-pixels when the same voltage is applied to the second electrodes CE2. For example, the second electrodes CE2 of at least some of the pixels PX among the plurality of pixels PX provided in the same row can be connected to each other. For example, one second electrode CE2 can be provided over the plurality of pixels PX. For example, one second electrode CE2 can be provided for every n sub-pixels.

[0100] For example, some of the second electrodes CE2 of the plurality of respective sub-pixels can be provided to be separated or isolated from each other. For example, the second electrode CE2 connected to the pixels PX of the nth row and the second electrode CE2 connected to the pixels PX of the (n+1)th row can be provided to be separated or isolated from each other. For example, the plurality of second electrodes CE2 can be provided to be separated from each other with the communication lines NL interposed therebetween and extended in the row direction. Accordingly, the number of the plurality of sub-pixels can be greater than the number of the plurality of second electrodes CE2. In another example, all of the second electrodes CE2 of the plurality of sub-pixels can be connected to each other so that only one second electrode CE2 is provided on the substrate 110. However, embodiments of the present disclosure are not limited thereto.

[0101] The plurality of second electrodes CE2 can be made of a transparent conductive material. However, embodiments of the present disclosure are not limited thereto. The plurality of second electrodes CE2 can be made of a transparent conductive material so that light emitted from the light emitting element ED can be directed upward beyond the second electrode CE2. For example, the second electrode CE2 can be made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), or the like. However, embodiments of the present disclosure are not limited thereto. The second electrode CE2 can be a transparent electrode.

[0102] A plurality of contact electrodes CCE can be provided on the substrate 110. For example, the plurality of contact electrodes CCE can be provided to be separated from the plurality of bank portions BNK and the plurality of signal lines TL. Each of the plurality of second electrodes CE2 can overlap at least one contact electrode CCE. For example, one second electrode CE2 can overlap the plurality of contact electrodes CCE.

[0103] For example, the plurality of contact electrodes CCE can be electrically connected to the plurality of second electrodes CE2. The plurality of contact electrodes CCE can be provided between the substrate 110 and the plurality of second electrodes CE2 to transmit a cathode voltage from the pixel driving circuit PD to the second electrode CE2.

[0104] For example, in the case of using micro-LEDs as the light emitting elements ED, a plurality of micro-LEDs can be formed on a wafer, and the micro-LEDs can be transferred to the substrate 110 of the display device 1000 to manufacture the display device 1000. In a process of transferring a plurality of light emitting elements ED having a microscopic size from a wafer to a substrate 110, various defects can be formed. For example, in some sub-pixels, a non-transfer defect in which a light emitting element ED is not transferred can occur, and in some other sub-pixels, a defect in which a light emitting element ED is transferred outside a predetermined position due to an alignment error can occur. Also, although the transfer process has been normally performed, the transferred light emitting element ED itself can be defective. Accordingly, in consideration of defects generated during a transfer process of a plurality of light emitting elements ED, a plurality of light emitting elements ED of the same type can be transferred to one sub-pixel. A burn-in test can be performed on the plurality of light emitting elements ED, and only one light emitting element ED that is finally judged to be normal can be used.

[0105] For example, the 1-1 light emitting element 130a and the 1-2 light emitting element 130b can be transferred together to one pixel PX, and can be tested to find out whether they are defective. If it is determined that both the 1-1 light emitting element 130a and the 1-2 light emitting element 130b are normal, only the 1-1 light emitting element 130a can be used, and the 1-2 light emitting element 130b can not be used. In another example, if only the 1-2 light emitting element 130b among the 1-1 light emitting element 130a and the 1-2 light emitting element 130b is judged to be normal, the 1-1 light emitting element 130a can not be used, and the 1-2 light emitting element 130b can be used. Accordingly, even if a plurality of light emitting elements ED of the same type are transferred to one pixel PX, only one light emitting element ED can be finally used.

[0106] Accordingly, one light emitting element ED of a pair of light emitting elements ED can be a main light emitting element ED or a primary light emitting element ED, and the other light emitting element ED can be a redundant light emitting element ED. The redundant light emitting element ED can be a spare light emitting element ED that has been transferred in preparation for a failure of the main light emitting element ED. In the case where the main light emitting element ED fails, the redundant light emitting element ED can be used as a replacement therefor. Accordingly, by transferring the main light emitting element ED and the redundant light emitting element ED together to one pixel PX, degradation in display quality due to defects in the light emitting elements ED themselves can be minimized.

[0107] For example, the 1-1 light emitting element 130a, the 2-1 light emitting element 140a, and the 3-1 light emitting element 150a transferred to one pixel PX can be used as main light emitting elements ED, and the 1-2 light emitting element 130b, the 2-2 light emitting element 140b, and the 3-2 light emitting element 150b can be used as redundant light emitting elements ED.

[0108] Figure 8 is a cross-sectional view of a display device according to an embodiment of the disclosure. Figure 9 is a cross-sectional view of a display device according to an embodiment of the disclosure. For example, Figure 8 is a cross-sectional view of a display region AA, a first non-display region NA1, a bending region BA, and a second non-display region NA2. For example, Figure 9 is a cross-sectional view of a display region including one sub-pixel SP1.

[0109] Referring to Figure 8 The first buffer layer 111a and the second buffer layer 111b can be disposed in the remaining regions of the substrate 110 except for the bending region BA.

[0110] The first buffer layer 111a and the second buffer layer 111b can be disposed in the display region AA, the first non-display region NA1, and the second non-display region NA2. The first buffer layer 111a and the second buffer layer 111b can reduce penetration of moisture or impurities through the substrate 110. The first buffer layer 111a and the second buffer layer 111b can be made of an inorganic insulating material. For example, the first buffer layer 111a and the second buffer layer 111b can be configured as a single layer or a multi-layer structure of silicon oxide (SiOx) or silicon nitride (SiNx). However, embodiments of the disclosure are not limited thereto.

[0111] For example, portions of the first buffer layer 111a and the second buffer layer 111b in the bending region BA can be removed. The upper surface of the substrate 110 located in the bending region BA can be exposed from the first buffer layer 111a and the second buffer layer 111b. By removing the first buffer layer 111a and the second buffer layer 111b made of an inorganic insulating material from the bending region BA, cracks that can occur in the first buffer layer 111a and the second buffer layer 111b when bent can be minimized.

[0112] A plurality of alignment keys MK can be disposed between the first buffer layer 111a and the second buffer layer 111b. The plurality of alignment keys MK can be configured to identify the positions of the pixel driving circuit PD during a manufacturing process of the display device 1000. For example, the plurality of alignment keys MK can be configured to align the positions of the pixel driving circuit PD transferred on the adhesive layer 112. In another example, the plurality of alignment keys MK can be omitted.

[0113] An adhesive layer 112 can be provided on the second buffer layer 111b. The adhesive layer 112 can be provided in the display area AA, the first non-display area NA1, the bending area BA, and the second non-display area NA2. In another example, at least a portion of the adhesive layer 112 can be removed from the non-display area NA including the bending area BA. For example, the adhesive layer 112 can be made of any one of an adhesive polymer, an epoxy resin, a UV curable resin, a polyimide resin, an acrylate resin, a polyurethane resin, and a polydimethylsiloxane (PDMS). However, embodiments of the present disclosure are not limited thereto.

[0114] A pixel driving circuit PD can be provided on the adhesive layer 112 in the display area AA. In a case where the pixel driving circuit PD is implemented as a driving chip (hereinafter, the pixel driving circuit PD can also be referred to as a driving chip PD), the driving chip can be mounted on the adhesive layer 112 through a transfer process. However, embodiments of the present disclosure are not limited thereto.

[0115] A first protective layer 113a and a second protective layer 113b can be provided on the adhesive layer 112. The first protective layer 113a and the second protective layer 113b can be provided to surround side surfaces of the pixel driving circuit PD. However, embodiments of the present disclosure are not limited thereto. For example, the second protective layer 113b can be provided to cover at least a portion of an upper surface of the pixel driving circuit PD. For example, at least one of the first protective layer 113a and the second protective layer 113b provided on the bending area BA can be omitted. For example, the first protective layer 113a can be entirely provided in the display area AA and the non-display area NA, and the second protective layer 113b can be partially provided in the display area AA, the first non-display area NA1, and the second non-display area NA2. For example, a portion of the second protective layer 113b in the bending area BA can be removed. However, embodiments of the present disclosure are not limited thereto.

[0116] The first protective layer 113a and the second protective layer 113b can be made of an organic insulating material. However, embodiments of the present disclosure are not limited thereto. For example, the first protective layer 113a and the second protective layer 113b can be made of a photoresist, a polyimide (PI), or a photoacryl material, etc. However, embodiments of the present disclosure are not limited thereto. For example, the first protective layer 113a and the second protective layer 113b can be a coating layer or an insulating layer. However, embodiments of the present disclosure are not limited thereto.

[0117] According to the present disclosure, a plurality of first connection lines 121 can be provided over the second protective layer 113b in the display region AA. The plurality of first connection lines 121 can be a wiring for electrically connecting the pixel driving circuit PD to another component. For example, the pixel driving circuit PD can be electrically connected to the plurality of signal lines TL, the plurality of contact electrodes CCE, and the like through the plurality of first connection lines 121. For example, the plurality of first connection lines 121 can include a 1-1st connection line 121a, a 1-2nd connection line 121b, a 1-3rd connection line 121c, and a 1-4th connection line 121d. However, embodiments of the present disclosure are not limited thereto.

[0118] For example, the plurality of 1-1st connection lines 121a can be provided over the second protective layer 113b. The plurality of 1-1st connection lines 121a can be electrically connected to the pixel driving circuit PD. The plurality of 1-1st connection lines 121a can transmit a voltage output from the pixel driving circuit PD to the first electrode CE1 or the second electrode CE2.

[0119] For example, a third protective layer 114 can be provided over the second protective layer 113b. The third protective layer 114 can be provided in the display region AA and the non-display region NA as a whole. In the bending region BA, the third protective layer 114 can cover the side surface of the second protective layer 113b and the upper surface of the first protective layer 113a. The third protective layer 114 can be made of an organic insulating material. For example, the third protective layer 114 can be made of a photoresist, a polyimide (PI), or a photoacryl material, and the like. However, embodiments of the present disclosure are not limited thereto. For example, the first protective layer 113a, the second protective layer 113b, and the third protective layer 114 can be made of the same material. However, embodiments of the present disclosure are not limited thereto.

[0120] The plurality of 1-2nd connection lines 121b can be provided over the third protective layer 114. The plurality of 1-2nd connection lines 121b can be connected or directly connected to the pixel driving circuit PD. For example, a portion of the 1-2nd connection line 121b can be directly connected to the pixel driving circuit PD through a contact hole in the third protective layer 114. Another portion of the 1-2nd connection line 121b can be electrically connected to the 1-1st connection line 121a through a contact hole in the third protective layer 114. However, embodiments of the present disclosure are not limited thereto. A voltage output from the pixel driving circuit PD can be transmitted to the first electrode CE1 or the second electrode CE2 through a connection line different from the plurality of 1-2nd connection lines 121b.

[0121] The first insulating layer 115a can be provided on the plurality of first-2 connection lines 121b. The first insulating layer 115a can be provided in the display region AA and the non-display region NA as a whole. However, embodiments of the present disclosure are not limited thereto. The first insulating layer 115a can be made of an organic insulating material. However, embodiments of the present disclosure are not limited thereto. For example, the first insulating layer 115a can be made of a photoresist, polyimide (PI), or a photoacryl material, etc. However, embodiments of the present disclosure are not limited thereto.

[0122] The plurality of first-3 connection lines 121c can be provided on the first insulating layer 115a. The plurality of first-3 connection lines 121c can be electrically connected to the plurality of first-2 connection lines 121b. For example, the first-3 connection lines 121c can be electrically connected to the first-2 connection lines 121b through contact holes in the first insulating layer 115a.

[0123] The second insulating layer 115b can be provided on the plurality of first-3 connection lines 121c. The second insulating layer 115b can be provided in the remaining regions except for the bending region BA. However, embodiments of the present disclosure are not limited thereto. The second insulating layer 115b can be provided in the display region AA, the first non-display region NA1, and the second non-display region NA2. However, embodiments of the present disclosure are not limited thereto. For example, a portion of the second insulating layer 115b provided in the bending region BA can be removed. The second insulating layer 115b can be made of an organic insulating material. However, embodiments of the present disclosure are not limited thereto. For example, the second insulating layer 115b can be made of a photoresist, polyimide (PI), or a photoacryl material, etc. However, embodiments of the present disclosure are not limited thereto.

[0124] The plurality of first-4 connection lines 121d can be provided on the second insulating layer 115b. The plurality of first-4 connection lines 121d can be electrically connected to the plurality of first-3 connection lines 121c. For example, the first-4 connection lines 121d can be electrically connected to the first-3 connection lines 121c through contact holes in the second insulating layer 115b.

[0125] According to the present disclosure, the plurality of second connection lines 122 can be provided on the second protective layer 113b in the non-display region NA. The plurality of second connection lines 122 can be wirings for transmitting signals transmitted from the flexible circuit board (or flexible film) 157 and the printed circuit board 160 (see Figure 1 ) to the pad portion PAD to the pixel driving circuit PD in the display region AA. For example, the plurality of second connection lines 122 can be electrically connected to the plurality of pad electrodes PE to receive signals from the flexible circuit board (or flexible film) 157 and the printed circuit board 160.

[0126] For example, a plurality of second connection lines 122 can extend from the pad portion PAD toward the display area AA to transmit a signal to a wiring of the display area AA. In this case, the plurality of second connection lines 122 can function as the connection line LL. The plurality of second connection lines 122 can include a 2-1 connection line 122a, a 2-2 connection line 122b, a 2-3 connection line 122c, and a 2-4 connection line 122d.

[0127] The plurality of 2-1 connection lines 122a can be disposed on the second protection layer 113b. The plurality of 2-1 connection lines 122a can extend from the second non-display area NA2 to the bend area BA and the first non-display area NA1. The plurality of 2-1 connection lines 122a can transmit a signal, which is transmitted from the flexible circuit board (or flexible film) 157 and the printed circuit board 160 to the pad portion PAD, to the pixel driving circuit PD of the display area AA.

[0128] The plurality of 2-2 connection lines 122b can be disposed on the third protection layer 114. The plurality of 2-2 connection lines 122b can be disposed in the second non-display area NA2. The 2-2 connection line 122b can be electrically connected to the 2-1 connection line 122a through a contact hole in the third protection layer 114. Accordingly, a signal from the flexible circuit board (or flexible film) 157 and the printed circuit board 160 can be transmitted to the 2-1 connection line 122a through the 2-2 connection line 122b.

[0129] The 2-3 connection line 122c can be disposed on the first insulating layer 115a. The 2-3 connection line 122c can be disposed in the second non-display area NA2. The 2-3 connection line 122c can be electrically connected to the 2-2 connection line 122b through a contact hole in the first insulating layer 115a. Accordingly, a signal from the flexible circuit board (or flexible film) 157 and the printed circuit board 160 can be transmitted to the 2-1 connection line 122a through the 2-3 connection line 122c and the 2-2 connection line 122b.

[0130] The 2-4 connection line 122d can be disposed on the second insulating layer 115b. The 2-4 connection line 122d can be disposed in the second non-display area NA2. The 2-4 connection line 122d can be electrically connected to the 2-3 connection line 122c through a contact hole in the second insulating layer 115b. Accordingly, a signal from the flexible film 157 and the printed circuit board 160 can be transmitted to the 2-1 connection line 122a through the 2-4 connection line 122d, the 2-3 connection line 122c, and the 2-2 connection line 122b.

[0131] The plurality of first connection lines 121 and the plurality of second connection lines 122 can be made of any of various conductive materials used in the display region AA or a conductive material having excellent ductility. For example, the second connection lines 122, part of which is provided in the bend region, can be made of a conductive material having excellent ductility, such as gold (Au), silver (Ag), aluminum (Al), or the like. However, embodiments of the present disclosure are not limited thereto. In another example, the plurality of first connection lines 121 and the plurality of second connection lines 122 can be made of an alloy of molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), silver (Ag), and magnesium (Mg), or any alloy thereof. However, embodiments of the present disclosure are not limited thereto.

[0132] A third insulating layer 115c can be provided on the plurality of first connection lines 121 and the plurality of second connection lines 122. The third insulating layer 115c can be provided in the remaining regions except for the bend region BA. However, embodiments of the present disclosure are not limited thereto. The third insulating layer 115c can be provided in the display region AA, the first non-display region NA1, and the second non-display region NA2. Part of the third insulating layer 115c in the bend region BA can be removed. The third insulating layer 115c can be made of an organic insulating material. However, embodiments of the present disclosure are not limited thereto. For example, the third insulating layer 115c can be made of a photoresist, polyimide (PI), or a photoacryl material, or the like. However, embodiments of the present disclosure are not limited thereto.

[0133] A plurality of banks BNK can be provided on the third insulating layer 115c in the display region AA. The plurality of banks BNK can be provided so as to overlap the plurality of sub-pixels, respectively. One or more light emitting elements ED of the same kind can be provided on the upper side of each of the plurality of banks BNK. The bank BNK can be made of an organic insulating material. However, embodiments of the present disclosure are not limited thereto. For example, the bank BNK can be made of a photoresist, polyimide (PI), or a photoacryl material, or the like. However, embodiments of the present disclosure are not limited thereto.

[0134] A plurality of signal lines TL can be provided on the third insulating layer 115c in the display region AA. The plurality of signal lines TL can be provided in a region between the plurality of banks BNK. For example, the plurality of signal lines TL can be provided so as to be adjacent to any one of the plurality of banks BNK.

[0135] A plurality of contact electrodes CCE can be provided on the third insulating layer 115c in the display region AA. The plurality of contact electrodes CCE can supply a cathode voltage from the pixel driving circuit PD to the second electrode CE2.

[0136] The first electrode CE1 can be provided on the bank BNK. For example, the first electrode CE1 can be provided to extend from the adjacent signal line TL toward the upper surface of the bank BNK. The first electrode CE1 can be provided on the upper surface of the bank BNK and on the side surface of the bank BNK. For example, the first electrode CE1 can be provided to extend from the signal line TL on the upper surface of the third insulating layer 115c to the side surface of the bank BNK and to the upper surface of the bank BNK.

[0137] Referring to Figure 9 The first electrode CE1 can be made of a plurality of conductive layers. For example, the first electrode CE1 can include a first conductive layer CE1a, a second conductive layer CE1b, a third conductive layer CE1c, and a fourth conductive layer CE1d. However, embodiments of the present disclosure are not limited thereto.

[0138] The first conductive layer CE1a can be provided on the bank BNK. The second conductive layer CE1b can be provided on the first conductive layer CE1a. The third conductive layer CE1c can be provided on the second conductive layer CE1b. The fourth conductive layer CE1d can be provided on the third conductive layer CE1c. For example, each of the first conductive layer CE1a, the second conductive layer CE1b, the third conductive layer CE1c, and the fourth conductive layer CE1d can be made of titanium (Ti), molybdenum (Mo), aluminum (Al), or indium tin oxide (ITO). However, embodiments of the present disclosure are not limited thereto.

[0139] According to the present disclosure, some of the plurality of conductive layers constituting the first electrode CE1 having good reflection efficiency can be used as an alignment key for aligning the light emitting element ED and / or a reflection plate. For example, the second conductive layer CE1b of the plurality of conductive layers of the first electrode CE1 can include a reflection material. For example, the second conductive layer CE1b can include aluminum (Al). However, embodiments of the present disclosure are not limited thereto. Thus, the second conductive layer CE1b can be used as a reflection plate. Further, since the second conductive layer CE1b is easily recognized in a manufacturing process due to its high reflection efficiency, the position or transfer position of the light emitting element ED can be aligned based on the second conductive layer CE1b.

[0140] For example, to form the second conductive layer CE1b as a reflection plate, the third conductive layer CE1c and the fourth conductive layer CE1d covering the second conductive layer CE1b can be partially removed or etched. For example, a portion of the third conductive layer CE1c and the fourth conductive layer CE1d disposed on the bank BNK can be removed or etched to expose the upper surface of the second conductive layer CE1b. For example, a central portion and a boundary portion or an edge portion of the third conductive layer CE1c and the fourth conductive layer CE1d can be left, and the remaining portions can be removed, in which the solder pattern SDP is placed on the central portion. For example, the boundary portion or the edge portion of each of the third conductive layer CE1c made of titanium (Ti) and the fourth conductive layer CE1d made of indium tin oxide (ITO) can not be etched. Accordingly, the other conductive layers of the first electrode CE1 can be prevented from being corroded by a tetramethylammonium hydroxide (TMAH) solution used in a mask process of the first electrode CE1.

[0141] According to the present disclosure, the first conductive layer CE1a and the third conductive layer CE1c can include titanium (Ti) or molybdenum (Mo). The second conductive layer CE1b can include aluminum (Al). The fourth conductive layer CE1d can include a transparent conductive oxide layer, such as indium tin oxide (ITO) or indium zinc oxide (IZO), which has good adhesion to the solder pattern SDP and has corrosion resistance and acid resistance. However, embodiments of the present disclosure are not limited thereto.

[0142] The first conductive layer CE1a, the second conductive layer CE1b, the third conductive layer CE1c, and the fourth conductive layer CE1d can be sequentially deposited and then patterned by performing a photolithography process and an etching process. However, embodiments of the present disclosure are not limited thereto.

[0143] According to the present disclosure, the signal line TL, the contact electrode CCE, and the pad electrode PE, which are disposed on the same layer as the first electrode CE1, can be configured as a multi-layer structure of conductive materials. However, embodiments of the present disclosure are not limited thereto. For example, the signal line TL, the contact electrode CCE, and the pad electrode PE can be formed as a multi-layer structure of indium tin oxide (ITO) / titanium (Ti) / aluminum (Al) / titanium (Ti). However, embodiments of the present disclosure are not limited thereto.

[0144] According to the present disclosure, a solder pattern SDP can be provided on the first electrode CE1 in each of the plurality of sub-pixels. The solder pattern SDP can join the light emitting element ED to the first electrode CE1. The first electrode CE1 and the light emitting element ED can be electrically connected by eutectic bonding with the solder pattern SDP. However, embodiments of the present disclosure are not limited thereto. For example, in a case where the solder pattern SDP is made of indium (In) and the anode electrode 134 of the light emitting element ED is made of gold (Au), the solder pattern SDP and the anode electrode 134 can be joined by applying heat and pressure during a transfer process of the light emitting element ED. By eutectic bonding, the light emitting element ED can be joined to the solder pattern SDP and the first electrode CE1 without a separate adhesive material. For example, the solder pattern SDP can be made of indium (In), tin (Sn), or an alloy thereof. However, embodiments of the present disclosure are not limited thereto. For example, the solder pattern SDP can be a joining pad or a bonding pad. However, embodiments of the present disclosure are not limited thereto.

[0145] According to the present disclosure, a passivation layer 116 can be provided on the plurality of signal lines TL, the plurality of first electrodes CE1, the plurality of contact electrodes CCE, and the third insulating layer 115c. For example, the passivation layer 116 can be provided in the display area AA, the first non-display area NA1, and the second non-display area NA2. A portion of the passivation layer 116 in the bending area BA can be removed. A portion of the passivation layer 116 covering the plurality of pad electrodes PE in the second non-display area NA2 can be removed. Since the passivation layer 116 is provided to cover the remaining area except for the bending area BA, the plurality of pad electrodes PE, and an area where the solder pattern SDP is provided, penetration of moisture or impurities into the light emitting element ED can be reduced. For example, the passivation layer 116 can be configured as a single layer or a multi-layer structure of silicon oxide (SiOx) or silicon nitride (SiNx). However, embodiments of the present disclosure are not limited thereto. For example, the passivation layer 116 can be a protective layer or an insulating layer. However, embodiments of the present disclosure are not limited thereto. For example, the passivation layer 116 can include a hole through which the solder pattern SDP is exposed.

[0146] In each of the plurality of sub-pixels, a light emitting element ED can be provided on the solder pattern SDP. A first light emitting element 130 can be provided in the first sub-pixel SP1. A second light emitting element 140 can be provided in the second sub-pixel SP2. A third light emitting element 150 can be provided in the third sub-pixel SP3.

[0147] The light emitting element ED can be formed on a silicon wafer by a method such as metal organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), sputtering, or the like. However, embodiments of the present disclosure are not limited thereto.

[0148] Referring to Figure 9 The first light emitting element 130 can include an anode electrode 134, a first semiconductor layer 131, an active layer 132, a second semiconductor layer 133, a cathode electrode 135, and an encapsulation film 136. However, embodiments of the present disclosure are not limited thereto. For example, the first light emitting element 130 can not include the encapsulation film 136.

[0149] The first semiconductor layer 131 can be disposed on the solder pattern SDP. The second semiconductor layer 133 can be disposed on the first semiconductor layer 131.

[0150] For example, one of the first semiconductor layer 131 and the second semiconductor layer 133 can be made of a compound semiconductor of Group III-V, Group II-VI, or the like, and can be doped with an impurity or a dopant. For example, one of the first semiconductor layer 131 and the second semiconductor layer 133 can be a semiconductor layer doped with an n-type impurity, and the other can be a semiconductor layer doped with a p-type impurity. However, embodiments of the present disclosure are not limited thereto. For example, one of the first semiconductor layer 131 and the second semiconductor layer 133 can be a layer in which an n-type or p-type impurity is doped in a material such as gallium nitride (GaN), gallium phosphide (GaP), gallium arsenide phosphide (GaAsP), aluminum gallium indium phosphide (AlGaInP), indium aluminum phosphide (InAlP), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlInGaN), aluminum gallium arsenide (AlGaAs), or gallium arsenide (GaAs). However, embodiments of the present disclosure are not limited thereto. For example, the n-type impurity can be silicon (Si), germanium (Ge), selenium (Se), carbon (C), tellurium (Te), tin (Sn), or the like. However, embodiments of the present disclosure are not limited thereto. For example, the p-type impurity can be magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), beryllium (Be), or the like. However, embodiments of the present disclosure are not limited thereto.

[0151] For example, the first semiconductor layer 131 and the second semiconductor layer 133 can be a nitride semiconductor containing an n-type impurity and a nitride semiconductor containing a p-type impurity, respectively. However, embodiments of the present disclosure are not limited thereto. For example, the first semiconductor layer 131 can be a nitride semiconductor containing a p-type impurity, and the second semiconductor layer 133 can be a nitride semiconductor containing an n-type impurity. However, embodiments of the present disclosure are not limited thereto.

[0152] The active layer 132 can be disposed between the first semiconductor layer 131 and the second semiconductor layer 133. The active layer 132 can receive holes and electrons from the first semiconductor layer 131 and the second semiconductor layer 133 to emit light. For example, the active layer 132 can be constituted of one of a single-well structure, a multi-well structure, a single-quantum well structure, a multi-quantum well (MQW) structure, a quantum dot structure, and a quantum wire structure. However, embodiments of the present disclosure are not limited thereto. For example, the active layer 132 can be made of indium gallium nitride (InGaN) or gallium nitride (GaN). However, embodiments of the present disclosure are not limited thereto.

[0153] In another example, the active layer 132 can include a multi-quantum well (MQW) structure having a well layer and a barrier layer having a higher band gap than the well layer. For example, the active layer 132 can include an InGaN layer as the well layer and an AlGaN layer as the barrier layer. However, embodiments of the present disclosure are not limited thereto.

[0154] The anode electrode 134 can be disposed between the first semiconductor layer 131 and the solder pattern SDP. For example, the anode electrode 134 can electrically connect the first semiconductor layer 131 with the first electrode CE1. An anode voltage output from the pixel driving circuit PD can be applied to the first semiconductor layer 131 through the signal line TL, the first electrode CE1, and the anode electrode 134. For example, the anode electrode 134 can be made of a conductive material capable of being eutectically bonded with the solder pattern SDP. However, embodiments of the present disclosure are not limited thereto. For example, the anode electrode 134 can be made of gold (Au), tin (Sn), tungsten (W), silicon (Si), silver (Ag), titanium (Ti), iridium (Ir), chromium (Cr), indium (In), zinc (Zn), lead (Pb), nickel (Ni), platinum (Pt), copper (Cu), or any alloy thereof. However, embodiments of the present disclosure are not limited thereto.

[0155] The cathode electrode 135 can be disposed on the second semiconductor layer 133. For example, the cathode electrode 135 can electrically connect the second semiconductor layer 133 with the second electrode CE2. A cathode voltage output from the pixel driving circuit PD can be applied to the second semiconductor layer 133 through the contact electrode CCE, the second electrode CE2, and the cathode electrode 135. The cathode electrode 135 can be made of a transparent conductive material so that light emitted from the light emitting element ED can be guided upward from the light emitting element ED. However, embodiments of the present disclosure are not limited thereto. For example, the cathode electrode 135 can be made of a material such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), or the like. However, embodiments of the present disclosure are not limited thereto.

[0156] The encapsulation film 136 can be disposed on at least a portion of the first semiconductor layer 131, the active layer 132, the second semiconductor layer 133, the anode electrode 134, and the cathode electrode 135. For example, the encapsulation film 136 can surround at least a portion of the first semiconductor layer 131, the active layer 132, the second semiconductor layer 133, the anode electrode 134, and the cathode electrode 135.

[0157] For example, the encapsulation film 136 can protect the first semiconductor layer 131, the active layer 132, and the second semiconductor layer 133. For example, the encapsulation film 136 can be disposed on a side surface of the first semiconductor layer 131, a side surface of the active layer 132, and a side surface of the second semiconductor layer 133.

[0158] For example, the encapsulation film 136 can be disposed on at least a portion of the anode electrode 134 and the cathode electrode 135, for example, on an edge portion or a boundary portion or one side of the anode electrode 134 and an edge portion or a boundary portion or one side of the cathode electrode 135. At least a portion of the anode electrode 134 can be exposed from the encapsulation film 136 so that the anode electrode 134 and the solder pattern SDP can be connected to each other. For example, at least a portion of the cathode electrode 135 can be exposed from the encapsulation film 136 so that the cathode electrode 135 and the second electrode CE2 can be connected to each other. For example, the encapsulation film 136 can be made of an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). However, embodiments of the present disclosure are not limited thereto.

[0159] In another example, the encapsulation film 136 can be made of a resin layer in which a reflective material is dispersed. However, embodiments of the present disclosure are not limited thereto. For example, the encapsulation film 136 can be manufactured as a reflector having various structures. However, embodiments of the present disclosure are not limited thereto. Light emitted from the active layer 132 can be reflected upward by the encapsulation film 136, and thus light extraction efficiency can be improved. For example, the encapsulation film 136 can be a reflective layer. However, embodiments of the present disclosure are not limited thereto.

[0160] According to the present disclosure, the light emitting element ED is described as having a vertical structure. However, embodiments of the present disclosure are not limited thereto. For example, the light emitting element ED can have a lateral structure or a flip chip structure.

[0161] Although the first light emitting element 130 has been described with reference to Figure 9 The second light emitting element 140 and the third light emitting element 150 can have substantially the same or similar structures as those of the first light emitting element 130. For example, the second light emitting element 140 and the third light emitting element 150 can include substantially the same or similar layers as the first semiconductor layer 131, the active layer 132, the second semiconductor layer 133, the anode electrode 134, the cathode electrode 135, and the encapsulation film 136 of the first light emitting element 130.

[0162] According to the present disclosure, a first optical layer 117a surrounding the plurality of light emitting elements ED can be provided in the display area AA. For example, the first optical layer 117a can be provided to cover the plurality of light emitting elements ED and the bank BNK in the area of the plurality of sub-pixels. For example, the first optical layer 117a can cover the bank BNK, a portion of the passivation layer 116, and side surfaces of the plurality of light emitting elements ED. The first optical layer 117a can cover or be provided in an area between the plurality of light emitting elements ED included in one pixel PX and between the plurality of banks BNK. For example, the first optical layer 117a can extend in the first direction and be spaced apart from each other in the second direction. For example, the first optical layer 117a can be provided between the passivation layer 116 and the second electrode CE2 to surround the side of the light emitting element ED and the bank BNK. However, embodiments of the present disclosure are not limited thereto. For example, the first optical layer 117a can be a diffusion layer or a sidewall diffusion layer. However, embodiments of the present disclosure are not limited thereto.

[0163] The first optical layer 117a can include an organic insulating material in which fine particles are dispersed. However, embodiments of the present disclosure are not limited thereto. For example, the first optical layer 117a can be made of silicone in which fine particles such as titanium dioxide (TiO2) particles are dispersed. However, embodiments of the present disclosure are not limited thereto. Light from the plurality of light emitting elements ED can be scattered by the fine particles dispersed in the first optical layer 117a and emitted to the outside of the display device 1000. Accordingly, the first optical layer 117a can improve the extraction efficiency of light emitted from the plurality of light emitting elements ED.

[0164] For example, the first optical layer 117a can be provided in each of the plurality of pixels PX, or can be commonly provided in some pixels PX provided in the same row. However, embodiments of the present disclosure are not limited thereto. For example, the first optical layer 117a can be provided in each of the plurality of pixels PX, or the plurality of pixels PX can share one first optical layer 117a. In another example, each of the plurality of sub-pixels can individually include the first optical layer 117a. However, embodiments of the present disclosure are not limited thereto.

[0165] According to the present disclosure, a second optical layer 117b can be provided on the passivation layer 116 in the display area AA. For example, the second optical layer 117b can be provided to surround the first optical layer 117a. For example, the second optical layer 117b can be in contact with a side surface of the first optical layer 117a. For example, the second optical layer 117b can be provided in an area between adjacent pixels in the plurality of pixels PX. However, embodiments of the present disclosure are not limited thereto. For example, the second optical layer 117b can be a diffusion layer, a diffusion layer window, a window diffusion layer, or the like. However, embodiments of the present disclosure are not limited thereto.

[0166] The second optical layer 117b can be made of an organic insulating material. However, embodiments of the present disclosure are not limited thereto. The second optical layer 117b can be made of the same material as the first optical layer 117a. However, embodiments of the present disclosure are not limited thereto. For example, the first optical layer 117a can include fine particles, and the second optical layer 117b can not include fine particles. For example, the second optical layer 117b can be made of silicone. However, embodiments of the present disclosure are not limited thereto.

[0167] For example, the thickness of the first optical layer 117a can be less than the thickness of the second optical layer 117b. However, embodiments of the present disclosure are not limited thereto. Thus, when viewed in a cross-sectional view of the display device 1000, the first optical layer 117a can include a concave portion that is concave inwardly than the upper surface of the second optical layer 117b.

[0168] According to the present disclosure, a second electrode CE2 can be provided on the first optical layer 117a and the second optical layer 117b. For example, the second electrode CE2 can be electrically connected to the plurality of contact electrodes CCE through a contact hole in the second optical layer 117b. For example, the second electrode CE2 can be provided on the plurality of light emitting elements ED. For example, the second electrode CE2 can include a transparent conductive oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO). However, embodiments of the present disclosure are not limited thereto. For example, the second electrode CE2 can be provided to be in contact with the cathode electrode 135. For example, the second electrode CE2 can overlap the first optical layer 117a. For example, the second electrode CE2 can cover the upper surface of the first optical layer 117a.

[0169] The second electrode CE2 can continuously extend in the first direction of the substrate 110. Thus, it can be commonly connected to the plurality of pixels PX arranged in the first direction of the substrate 110. For example, the second electrode CE2 can be commonly connected to the plurality of pixels PX.

[0170] According to the disclosure, the second electrode CE2 can continuously extend over the first optical layer 117a, the second optical layer 117b, and the light emitting elements ED. The first optical layer 117a can include a concave portion that is recessed inwardly than an upper surface of the second optical layer 117b. Accordingly, a first portion of the second electrode CE2 disposed on the first optical layer 117a is disposed along the concave portion, and thus can be disposed at a lower position than a second portion of the second electrode CE2 disposed on the second optical layer 117b.

[0171] A third optical layer 117c can be disposed on the second electrode CE2. The third optical layer 117c can be disposed to overlap the plurality of light emitting elements ED and the first optical layer 117a. Since the third optical layer 117c is disposed on the second electrode CE2 and the plurality of light emitting elements ED, mura that can occur on some of the plurality of light emitting elements ED can be mitigated. For example, when the plurality of light emitting elements ED are transferred onto the substrate 110 of the display device 1000, process deviation, etc. can cause a region in which a pitch between the plurality of light emitting elements ED is not uniform to occur. If the pitch between the plurality of light emitting elements ED is not uniform, light emitting regions of the plurality of corresponding light emitting elements ED are disposed non-uniformly, which can cause mura to be visible to a user. Accordingly, since the third optical layer 117c configured to uniformly diffuse light is disposed on top of the plurality of light emitting elements ED, a phenomenon in which light emitted from some of the light emitting elements ED appears like mura can be mitigated. Accordingly, since light emitted from the plurality of light emitting elements ED is uniformly diffused by the third optical layer 117c and extracted to the outside of the display device 1000, brightness uniformity of the display device 1000 can be improved.

[0172] The third optical layer 117c can be made of an organic insulating material in which fine particles are dispersed. However, embodiments of the disclosure are not limited thereto. For example, the third optical layer 117c can be made of silicone in which fine particles such as titanium dioxide (TiO2) particles are dispersed. However, embodiments of the disclosure are not limited thereto. For example, the third optical layer 117c can be made of the same material as the first optical layer 117a. However, embodiments of the disclosure are not limited thereto. For example, the third optical layer 117c can be a diffusion layer or an upper surface diffusion layer. However, embodiments of the disclosure are not limited thereto.

[0173] According to the disclosure, light from the plurality of light emitting elements ED can be scattered by the fine particles dispersed in the third optical layer 117c and emitted to the outside of the display device 1000. The third optical layer 117c can uniformly mix light emitted from the plurality of light emitting elements ED to further improve brightness uniformity of the display device 1000. In addition, light extraction efficiency of the display device 1000 can be improved by light scattered by the plurality of fine particles, thereby enabling the display device 1000 to be driven at low power.

[0174] A black matrix BM can be disposed on the second electrode CE2, the first optical layer 117a, the second optical layer 117b, and the third optical layer 117c in the display area AA. For example, the black matrix BM can fill the contact hole in the second optical layer 117b. The black matrix BM can be disposed to cover the display area AA, so that color mixing of light from the plurality of sub-pixels and external light reflection can be reduced. For example, since the black matrix BM can be disposed in the contact hole in which the second electrode CE2 and the contact electrode CCE are connected to each other, light leakage between adjacent sub-pixels can be prevented.

[0175] For example, the black matrix BM can be made of an opaque material. However, embodiments of the present disclosure are not limited thereto. For example, the black matrix BM can be made of an organic insulating material to which a black pigment or a black dye is added. However, embodiments of the present disclosure are not limited thereto.

[0176] A cover layer 118 can be disposed on the black matrix BM in the display area AA. The cover layer 118 can protect components under the cover layer 118. For example, the cover layer 118 can be made of an organic insulating material. However, embodiments of the present disclosure are not limited thereto. For example, the cover layer 118 can be made of a photoresist, a polyimide (PI), or a photoacryl material, etc. However, embodiments of the present disclosure are not limited thereto. For example, the cover layer 118 can be a coating layer or an insulating layer. However, embodiments of the present disclosure are not limited thereto.

[0177] A polarizing layer 293 can be disposed on the cover layer 118 via a first adhesive layer 291. A cover member 155 can be disposed on the polarizing layer 293 via an adhesive layer 295 (hereinafter, which can also be referred to as a second adhesive layer 295). For example, the first adhesive layer 291 and the second adhesive layer 295 can include an optical clear adhesive (OCA), an optical clear resin (OCR), or a pressure sensitive adhesive (PSA). However, embodiments of the present disclosure are not limited thereto.

[0178] According to the present disclosure, a plurality of pad electrodes PE can be disposed on the third insulating layer 115c in the second non-display area NA2. For example, at least a portion of the plurality of pad electrodes PE can be exposed from the passivation layer 116. For example, the plurality of pad electrodes PE can be electrically connected to the 2-4th connection line 122d through a contact hole in the third insulating layer 115c.

[0179] An adhesive layer ACF can be disposed on the plurality of pad electrodes PE. The adhesive layer ACF can be an adhesive layer in which conductive balls are dispersed in an insulating material. However, embodiments of the present disclosure are not limited thereto. In a case in which heat or pressure is applied to the adhesive layer ACF, the conductive balls can be electrically connected in a portion to which the heat or pressure is applied, thereby providing an electrically conductive characteristic. By placing the adhesive layer ACF between the plurality of pad electrodes PE and the flexible circuit board (or flexible film) 157, the flexible circuit board (or flexible film) 157 can be attached or bonded to the plurality of pad electrodes PE. For example, the adhesive layer ACF can be an anisotropic conductive film. However, embodiments of the present disclosure are not limited thereto.

[0180] The flexible circuit board (or flexible film) 157 can be disposed on the adhesive layer ACF. The flexible circuit board (or flexible film) 157 can be electrically connected to the plurality of pad electrodes PE through the adhesive layer ACF. Accordingly, signals output from the flexible circuit board (or flexible film) 157 and the printed circuit board can be transmitted to the pixel driving circuit PD in the display area AA through the plurality of pad electrodes PE, the 2-4 connection line 122d, the 2-3 connection line 122c, the 2-2 connection line 122b, and the 2-1 connection line 122a.

[0181] Figures 10 to 13 is a diagram illustrating a device to which a display device according to an embodiment of the present disclosure is applied.

[0182] Referring to Figures 10 to 13 , the display device 1000 according to an embodiment of the present disclosure can be included in various devices or electronic devices. For example, referring to Figures 10 to 13 , various electronic devices can include a wearable device 1100, a mobile device 1200, a notebook 1300, and a display or TV 1400. However, embodiments of the present disclosure are not limited thereto.

[0183] The wearable device 1100, the mobile device 1200, the notebook 1300, and the display or TV 1400 can each include a housing 1005, 1010, 1015, 1020, and a display panel 100 (or a display device 1000) according to an embodiment of the present disclosure described with reference to Figures 1 to 9

[0184] ​For example, the display device according to an embodiment of the disclosure can be applied to a mobile device, a video phone, a smart watch, a watch phone, a wearable device, a foldable device, a rollable device, a bendable device, a flexible device, a curved device, a sliding device, a transformable device, an electronic notebook, an electronic book, a portable multimedia player (PMP), a personal digital assistant (PDA), an MP3 player, a mobile medical device, a desktop PC, a laptop PC, a netbook computer, a workstation, a navigation system, a vehicle display device, a theater display device, a television, a wallpaper device, a signage device, a game device, a notebook, a display, a camera, a camcorder, a home appliance, etc.

[0185] Figure 14 is a plan view of a display panel according to an embodiment of the disclosure.

[0186] Referring to Figure 14 The flexible circuit board 157 and the printed circuit board 160 can be connected to one side of the display panel 100. The flexible circuit board 157 and the printed circuit board 160 can be disposed on at least one side edge of the display panel 100. One side of the flexible circuit board 157 can be attached to the display panel 100, and the other side thereof can be attached to the printed circuit board 160.

[0187] The flexible circuit board 157 can supply power or signals supplied from the printed circuit board 160 to the plurality of pixel driving circuits of the display panel 100.

[0188] The flexible circuit board 157 can include a control circuit that is a timing controller 151. The printed circuit board 160 can include a power management integrated circuit 161.

[0189] The display panel 100 can include a display area AA that displays an image and a non-display area NA that does not display an image. The display panel 100 can include a trimming line TRL along an outer edge of the non-display area NA. The trimming line TRL can refer to an area that is cut by a laser during a scribing process to separate a plurality of individual units of the display panel 100 from a mother substrate. An area located outside the trimming line TRL can be removed by the scribing process.

[0190] In the display area AA, a plurality of driving chips PD and a plurality of pixels including a plurality of light emitting elements electrically connected with the plurality of driving chips PD can be arranged. Each of the driving chips PD can control light emitting operations of the plurality of light emitting elements by providing control signals and power to the plurality of light emitting elements. Each of the driving chips PD can be a micro-driver.

[0191] The display panel 100 can have a shape in which one side thereof is longer than the other side thereof. For example, the display panel 100 can include a long side and a short side that is shorter than the long side.

[0192] The display panel 100 can include one or more crack detection lines PCDL, PCDR disposed in a portion of the non-display area NA. Each of the one or more crack detection lines PCDL, PCDR can be disposed along an outer portion of the display area AA to detect a defect, such as a crack, that can occur in the outer portion of the display area AA. The one or more crack detection lines PCDL, PCDR can be disposed to surround at least a portion of two side areas, an upper area, and a lower area of the display area AA. For example, the one or more crack detection lines PCDL, PCDR can include a first crack detection line PCDL and a second crack detection line PCDR.

[0193] The first crack detection line PCDL can extend along a left long side of the display panel 100 and can extend to each of an upper left corner and a lower left corner of the display panel 100, and then can extend along a left portion of each of an upper short side and a lower short side of the display panel 100. The second crack detection line PCDR can extend along a right long side of the display panel 100 and can extend to each of an upper right corner and a lower right corner of the display panel 100, and then can extend along a right portion of each of an upper short side and a lower short side of the display panel 100. The first crack detection line PCDL and the second crack detection line PCDR can be disposed apart from each other.

[0194] The first crack detection line PCDL and the second crack detection line PCDR can be disposed to overlap some of the plurality of driving chips PD at a corner area of the display panel 100. The driving chip disposed to overlap the first crack detection line PCDL and the second crack detection line PCDR at the corner area can be an inactive driving chip PD_n.

[0195] Each driving chip PD arranged in the display area AA can be an active driving chip capable of providing a control signal and power to the plurality of light emitting elements to control light emitting operations of the plurality of light emitting elements. In order for each driving chip PD to control the plurality of light emitting elements, not only a power supply line but also a signal line for controlling the on / off or light emitting time of the light emitting elements is required.

[0196] The inactive driving chip PD_n can not be electrically connected to at least some of the power supply line or the signal line because it is disposed to overlap the first crack detection line PCDL or the second crack detection line PCDR at the corner area of the display panel 100. Accordingly, the inactive driving chip PD_n can be an unused driving chip that is not capable of controlling the plurality of light emitting elements. Eight inactive driving chips PD_n can be disposed along the corner area of the display panel 100.

[0197] In the outer side of the trimming line TRL, a plurality of alignment key patterns 101, 103 can be provided. The plurality of alignment key patterns 101, 103 can include a first alignment key pattern 101 and a second alignment key pattern 103. However, embodiments of the present disclosure are not limited thereto.

[0198] The first alignment key pattern 101 can be a pattern for alignment between the display panel 100 and the cover member 155. The plurality of first alignment key patterns 101 can be positioned in at least one of each outer side region of the trimming line TRL facing each corner region of the display panel 100. For example, the plurality of first alignment key patterns 101 can include four alignment key patterns each provided at a respective one of the four corner regions of the display panel 100. Figure 1

[0199] The second alignment key pattern 103 can include various alignment key patterns for aligning components provided in different layers, such as a plurality of signal lines, contact holes, and a plurality of driving chips provided on the display panel 100, to correct positions. The second alignment key pattern 103 can include a metal material. Accordingly, the second alignment key pattern 103 can be provided in the display region AA or the non-display region NAA, and can be formed together with the plurality of signal lines including the metal material. However, embodiments of the present disclosure are not limited thereto.

[0200] Figure 15 is a plan view illustrating a region of one of the plurality of driving chips provided in the display panel 100. Figure 14

[0201] Referring to Figure 14 , the plurality of driving chips PD can be arranged in a matrix shape in the display region AA. Referring to Figure 15 , a plurality of pixels PX1 to PX16 including a plurality of light emitting elements can be arranged in a matrix shape with respect to one driving chip PD. The plurality of pixels can be arranged to be spaced apart from each other in a first direction and a second direction intersecting the first direction. The first direction can be an X-axis direction of the display panel 100, and the second direction can be a Y-axis direction of the display panel 100. However, it is not limited thereto. For example, the first direction can be a horizontal direction or a row direction of the display panel 100, and the second direction can be a vertical direction or a column direction of the display panel 100.

[0202] ​​In the first direction of the display panel 100, sub-pixels emitting different colors of light can be alternately disposed. Also, sub-pixels emitting the same color of light can be disposed in the second direction of the display panel 100. For example, the first to sixteenth pixels PX1 to PX16 can be arranged in a row direction as the first direction. A single pixel PX can include sub-pixels of red R, green G, and blue B. Accordingly, in the first direction as the row direction, for example, sub-pixels of red R, green G, and blue B can be disposed in a repeating order.

[0203] A plurality of light emitting elements can be disposed corresponding to each sub-pixel. At least one light emitting element can be disposed in one sub-pixel. For example, two light emitting elements can be disposed in one sub-pixel. One of the two light emitting elements can be a main light emitting element, and the other can be a redundant light emitting element. The light emitting elements can be micro-LEDs.

[0204] Also, sub-pixels emitting the same color of light can be disposed in the second direction, i.e., the column direction. For example, sub-pixels of one color among red R, green G, or blue B can be disposed in the second direction, i.e., the column direction. The sub-pixels emitting the same color of light can be electrically connected to each other via one signal line TL_P or TL_R.

[0205] The signal line TL can include a main line TL_P and a redundant line TL_R. The main line TL_P and the redundant line TL_R can be disposed to be separated from each other in the first direction of the display panel 100. The main line TL_P can be connected to the main light emitting element through the first electrode CE1, and the redundant line TL_R can be connected to the redundant light emitting element through the first electrode CE1.

[0206] Each of the plurality of second electrodes CE2 can extend in the first direction. Also, each of the plurality of second electrodes CE2 can be arranged to be separated from each other in the second direction. Accordingly, each of the second electrodes CE2 can extend in the first direction to be connected to each of the first to sixteenth pixels PX1 to PX16 disposed in each of the plurality of rows Row 1, Row 2, Row 3, …, Row 16.

[0207] One driving chip PD can include a plurality of driving circuits to drive a plurality of light emitting elements. One driving chip PD can be connected to a plurality of second electrodes CE2 and a plurality of signal lines TL connected to a plurality of pixels PX1, PX2, …, PX16. For example, one driving chip PD can drive a plurality of light emitting elements arranged on the first to sixteenth rows Row 1 to Row 16. In other words, one driving chip PD can be electrically connected to a plurality of light emitting elements arranged on the first to sixteenth rows Row 1 to Row 16 through a plurality of signal lines TL and a plurality of second electrodes CE2, and can control light emitting operations of the plurality of light emitting elements by providing control signals and power to the plurality of light emitting elements through the plurality of signal lines TL and the plurality of second electrodes CE2.

[0208] The plurality of signal lines TL can be radially connected to the driving chip PD to connect the plurality of pixels PX1, PX2, …, PX16 arranged in each of the plurality of rows Row 1, Row 2, Row 3, …, Row 16 to the driving chip PD. For example, when viewed from above the display panel 100, the shape in which the plurality of signal lines TL are connected to the driving chip PD can look like a diamond shape in an area around the driving chip PD. For example, when viewed from above the display panel 100, the arrangement shape of the plurality of connection lines connecting the plurality of signal lines TL and the driving chip PD can look like a diamond shape in an area around the pixel driving circuit PD.

[0209] The display device according to the embodiment of the disclosure can have an in-cell touch structure using each of the plurality of second electrodes CE2 as a touch electrode instead of forming a separate touch panel. Accordingly, since a separate touch panel is not formed, it is possible to reduce the thickness of the display panel.

[0210] Figure 16 is a diagram illustrating a touch operation of a display device according to an embodiment of the disclosure. Referring to Figure 16 When a user's touch operation is performed on the cover member 155, a change in a first capacitance C1 between the plurality of second electrodes CE2 provided on the display panel 100 and the cover member 155 and a change in a second capacitance C2 between the plurality of second electrodes CE2 and the plurality of signal lines SL can be detected and provided to the driving chip PD. Further, the driving chip PD can function as a touch controller to provide control signals for operation to the plurality of light emitting elements according to a touch input. A ground portion GND can be provided on a side opposite to the cover member 155.

[0211] The display device 1000 according to the embodiment of the disclosure can perform touch driving and touch sensing in a self-capacitance-based touch sensing manner, or can perform touch driving and touch sensing in a mutual-capacitance-based touch sensing manner.

[0212] Figure 17 FIG. 1 is a diagram illustrating an example of a signal waveform diagram when driving a display apparatus according to an embodiment of the disclosure.

[0213] Referring to Figure 17 , the display apparatus according to an embodiment of the disclosure can perform a light emitting operation in units of one frame.

[0214] One frame can include a touch period A and a display period B.

[0215] One frame can operate at a frequency of, for example, 60 Hz. In this case, the touch period A can operate a first time period at a frequency of, for example, 60 Hz, and the display period B can operate a second time period longer than the first time period at a frequency of, for example, 60 Hz. Accordingly, the operation time of the touch period A within one frame and the operation time of the display period B can be different from each other. For example, the operation time of the touch period A can be shorter than the operation time of the display period B.

[0216] The display period B can include sixteen sub-frames.

[0217] For example, in the case where eight micro-LEDs are connected to each signal line connected to a driving chip in a display panel, one sub-frame period C can include eight pulse signals 1-Row, 2-Row, 3-Row, 4-Row, 5-Row, 6-Row, 7-Row, 8-Row. That is, in an embodiment of the disclosure, eight micro-LEDs can operate during one sub-frame.

[0218] Accordingly, in an embodiment of the disclosure, since one frame includes sixteen sub-frames and one sub-frame includes eight pulse signals, 128 micro-LEDs can operate during one frame.

[0219] Embodiments of the disclosure are not limited thereto. For example, in the case where sixteen micro-LEDs are connected to each signal line connected to a driving chip, one sub-frame period C can include sixteen pulse signals. In this case, 256 micro-LEDs can operate during one frame.

[0220] One pulse signal (for example, 5-Row) drives one micro-LED. One pulse signal period D can include a high signal period and a low signal period. In this regard, the time length of the low signal period can be greater than the time length of the high signal period.

[0221] In an embodiment of the disclosure, the driving time of the micro-LED can be controlled based on an emission signal EM applied to a gate electrode of a light emitting transistor T EM

[0222] ​The micro driver can control the application time of the light emission signal EM with a pulse width PW. For example, in the case where one pulse signal (e.g., 5-Row) having one pulse width PW is applied to the gate electrode of the light emission transistor T EM , it can be referred to as 1 Gray.

[0223] The micro driver can control the application time of the light emission signal EM by adjusting the pulse width PW of one pulse signal (e.g., 5-Row) from a minimum of 1 Gray to a maximum of 32 Gray.

[0224] The single pixel PX can include sub-pixels of red R, green G, and blue B. Each of a plurality of micro-LEDs can be disposed in each sub-pixel.

[0225] Accordingly, the micro driver can control the light emission time of the micro-LED corresponding to each sub-pixel of red R, green G, or blue B by applying a pulse signal having a pulse width PW adjusted from at least 1 Gray (Min) to at most 32 Gray (Max) to the gate electrode of the light emission transistor T EM .

[0226] Figure 18 is a cross-sectional view along the line XVIII-XVIII of Figure 14 .

[0227] In Figure 18 , components identical to those described with reference to Figures 1 to 9 will be assigned the same reference numerals used therein, and a description thereof will be simplified or omitted.

[0228] With reference to Figure 18 , the display panel can include a display area AA and a non-display area NA, and the non-display area NA can include a fan-out area FA, a bending area BA, a taper area TA, and a pad area PA.

[0229] In the display area AA, a plurality of light emission elements 130, 140, 150 and at least one driving chip PD electrically connected to the plurality of light emission elements 130, 140, 150 can be disposed.

[0230] The first protection layer 113a and the second protection layer 113b disposed on the adhesive layer 112 can be disposed to surround the side surface of the at least one driving chip PD. However, embodiments of the disclosure are not limited thereto. For example, the second protection layer 113b can be disposed to cover at least a portion of the upper surface of the driving chip PD. The protection film 214 can be disposed between the first protection layer 113a and the second protection layer 113b.

[0231] The first protective layer 113a can be disposed to cover a portion of the side surface of the driving chip PD. The protective film 214 can include a first portion disposed on the upper surface of the first protective layer 113a, a second portion disposed on the side surface of the driving chip PD, and a third portion disposed on the edge of the upper surface of the driving chip PD.

[0232] The second protective layer 113b can be disposed on the protective film 214. The second protective layer 113b can be disposed to cover the edge of the upper surface of the driving chip PD while covering the third portion of the protective film 214.

[0233] The protective film 214 can strengthen the adhesion between the driving chip PD and the second protective layer 113b to prevent a gap from being generated between the driving chip PD and the second protective layer 113b during a subsequent process. By preventing a gap from being generated between the driving chip PD and the second protective layer 113b, damage to the driving chip PD or settlement of the third protective layer 114 around the driving chip PD due to penetration of moisture, a chemical solution, or the like through the gap during a manufacturing process can be prevented. The protective film 214 can include an inorganic insulating material. For example, the protective film 214 can include silicon nitride (SiN).

[0234] To electrically connect the plurality of light emitting elements 130, 140, 150 and the plurality of driving chips PD, a plurality of first connection lines 121 can be disposed between the plurality of light emitting elements 130, 140, 150 and the plurality of driving chips PD. The plurality of driving chips PD can be electrically connected to the plurality of signal lines TL and the plurality of contact electrodes CCE through the plurality of first connection lines 121. For example, the plurality of first connection lines 121 can include a 1-1 connection line 121a, a 1-2 connection line 121b, a 1-3 connection line 121c, and a 1-4 connection line 121d. However, embodiments of the present disclosure are not limited thereto.

[0235] The side surfaces of the plurality of light emitting elements 130, 140, 150 can be covered by a first optical layer 117a. A second optical layer 117b can be disposed around the first optical layer 117a. A second electrode CE2 can be disposed on the plurality of light emitting elements 130, 140, 150, the first optical layer 117a, and the second optical layer 117b. A third optical layer 117c in which fine particles are dispersed can be disposed on the second electrode CE2.

[0236] A black matrix BM can be disposed on the third optical layer 117c. A cover layer 118 can be disposed on the black matrix BM and the third optical layer 117c.

[0237] A polarizing layer 293 can be disposed on the cover layer 118 via a first adhesive layer 291. The cover member 155 can be disposed on the polarizing layer 293 via a second adhesive layer 295.

[0238] The fan-out area FA can be an area provided with a plurality of lines LL1, LL2, LL3, LL4, LL5 to connect the plurality of connection lines 121 provided in the display area AA to the pad area PA.

[0239] The plurality of lines LL1, LL2, LL3, LL4, LL5 can include a first line LL1, a second line LL2, a third line LL3, a fourth line LL4, and a fifth line LL5. The first line LL1, the second line LL2, the third line LL3, the fourth line LL4, and the fifth line LL5 can be provided on different insulating layers from each other.

[0240] Each of the plurality of lines LL1, LL2, LL3, LL4, LL5 can be formed together with the plurality of connection lines 121 and the plurality of signal lines TL, and can be provided on the same layer. For example, the first line LL1 can be provided on the same layer as the 1-1 connection line 121a, and the second line LL2 can be provided on the same layer as the 1-2 connection line 121b. Also, the third line LL3 can be provided on the same layer as the 1-3 connection line 121c, and the fourth line LL4 can be provided on the same layer as the 1-4 connection line 121d. Also, the fifth line LL5 can be provided on the same layer as the signal line TL.

[0241] The first line LL1 can extend to the pad area PA through the bend area BA. However, embodiments of the present disclosure are not limited thereto. The portion of the first line LL1 extending to the pad area PA can be a 2-1 connection line 122a. The 2-1 connection line 122a can be a signal connection line.

[0242] A laminate structure including the adhesive layer 112, the first protective layer 113a, the 2-1 connection line 122a, the third protective layer 114, and the first insulating layer 115a can be provided on the substrate 110 in the bend area BA. The thickness of the bend area BA can be relatively smaller than the thickness of the fan-out area FA.

[0243] The pad area PA can include a 2-2 connection line 122b, a 2-3 connection line 122c, a 2-4 connection line 122d, and a pad electrode PE, all of which are electrically connected to the 2-1 connection line 122a extending from the display area AA.

[0244] The 2-2 connection line 122b, the 2-3 connection line 122c, the 2-4 connection line 122d, and the pad electrode PE can be formed together with the plurality of connection lines 121 and the plurality of signal lines TL, and disposed on the same layer. For example, the 2-2 connection line 122b can be disposed on the same layer as the 1-2 connection line 121b. Further, the 2-3 connection line 122c can be disposed on the same layer as the 1-3 connection line 121c, and the 2-4 connection line 122d can be disposed on the same layer as the 1-4 connection line 121d. Further, the pad electrode PE can be disposed on the same layer as the signal line TL.

[0245] In addition, in order to prevent the joining properties of one or more insulating layers from deteriorating and causing defects such as delamination or cracking in the bending area BA during the bending operation, the thickness of the insulating layer can gradually decrease in the tapered area TA.

[0246] As described above, the plurality of light emitting elements ED can be transferred onto the plurality of bank portions BNK by a transfer process of the plurality of light emitting elements ED. However, there can be a case in which the light emitting elements ED are not transferred into some of the plurality of bank portions BNK during the transfer process.

[0247] In this case, in the sub-pixels SP1, SP2, and SP3 in which the light emitting elements ED are omitted, a short circuit can occur between the first electrode CE1 and the second electrode CE2 for driving the light emitting elements ED. In the sub-pixels SP1, SP2, and SP3 in which the light emitting elements ED are omitted, a recess RCS of the first optical layer 117a surrounding the side surface of the plurality of light emitting elements ED can be formed, and a solder pattern SDP for joining the first electrode CE1 and the light emitting elements ED can be exposed through the recess RCS. The second electrode CE2 can be directly disposed on the exposed solder pattern SDP in the sub-pixels SP1, SP2, and SP3 in which the light emitting elements ED are omitted, thereby causing a short circuit between the first electrode CE1 and the second electrode CE2. Since the light emitting elements ED of the plurality of sub-pixels are commonly connected to one signal line, even when a short circuit occurs between the first electrode CE1 and the second electrode CE2 in one sub-pixel, all of the light emitting elements ED of the plurality of sub-pixels commonly connected to one signal line do not emit light.

[0248] Hereinafter, a display device including sub-pixels in which light emitting elements are omitted will be described.

[0249] Figure 19 is an enlarged plan view of a display area including one pixel of a display device according to an embodiment of the disclosure. Figure 20 is a cross-sectional view along Figure 19 line XX-XX in Figure 19 and Figure 20An example of a case in which at least one light emitting element ED is omitted is illustrated.

[0250] Referring to Figure 19 and Figure 20 A plurality of bank portions BNK can be provided on the third insulating layer 115c, and the first to sixth signal lines TL1, TL2, TL3, TL4, TL5, and TL6 can be provided adjacent to the plurality of bank portions BNK. The plurality of first electrodes CE1 provided on the upper surfaces of the plurality of bank portions BNK can extend along the side surfaces of the plurality of bank portions BNK, and can be connected to the first to sixth signal lines TL1, TL2, TL3, TL4, TL5, and TL6. The plurality of first electrodes CE1 can be commonly connected to each signal line. For example, eight first electrodes CE1 can be commonly connected to each signal line.

[0251] For example, one bank portion BNK can be provided on each sub-pixel SP1, SP2, or SP3, and two first electrodes CE1 can be provided to be separated from each other on one bank portion BNK.

[0252] The plurality of solder patterns SDP can be provided on the plurality of first electrodes CE1 in a one-to-one correspondence. One solder pattern SDP can be provided in each first electrode CE1.

[0253] In the present embodiment, when the first sub-pixel SP1 includes a first-1 sub-pixel SP1a and a first-2 sub-pixel SP1b, a first-1 light emitting element 130a can be provided on the solder pattern SDP of the first-1 sub-pixel SP1a, and a first-2 light emitting element 130b can be provided on the solder pattern SDP of the first-2 sub-pixel SP1b. When the second sub-pixel SP2 includes a second-1 sub-pixel SP2a and a second-2 sub-pixel SP2b, a second-1 light emitting element 140a can be provided on the solder pattern SDP of the second-1 sub-pixel SP2a, and a light emitting element can be omitted on the solder pattern SDP of the second-2 sub-pixel SP2b. When the third sub-pixel SP3 includes a third-1 sub-pixel SP3a and a third-2 sub-pixel SP3b, a third-1 light emitting element 150a can be provided on the solder pattern SDP of the third-1 sub-pixel SP3a, and a third-2 light emitting element 150b can be provided on the solder pattern SDP of the third-2 sub-pixel SP3b.

[0254] The case where the light emitting element is omitted on the solder pattern SDP of the 2-2 sub-pixel SP2b has been exemplarily described, but embodiments of the present disclosure are not limited thereto. The light emitting element can be omitted on at least one of the six solder patterns SDP provided in the pixel PX. For example, the light emitting element can be omitted on the solder pattern SDP of the 1-1 sub-pixel SP1a, the light emitting element can be omitted on the solder pattern SDP of the 3-2 sub-pixel SP3a, or the light emitting element can be omitted on the solder pattern SDP of the 2-1 sub-pixel SP2a and the solder pattern SDP of the 1-2 sub-pixel SP1b.

[0255] The first optical layer 117a can be provided around the plurality of light emitting elements ED, and the first optical layer 117a can have at least one recess RCS exposing at least one solder pattern SDP on which the light emitting element is not provided. The solder pattern SDP can be located in a lower portion of the recess RCS of the first optical layer 117a. The width of the recess RCS can be narrowed downward. The recess RCS can have a slanted sidewall. The area of the lower portion of the recess RCS can be greater than the area of the solder pattern SDP, but embodiments of the present disclosure are not limited thereto. The recess RCS can expose a portion of the solder pattern SDP. In this case, the area of the lower portion of the recess RCS can be less than the area of the solder pattern SDP.

[0256] An insulating pattern INP can be provided on the solder pattern SDP in the recess RCS of the first optical layer 117a. The insulating pattern INP can cover the entire upper surface of the solder pattern SDP. The area of the insulating pattern INP can be greater than the area of the solder pattern SDP. The insulating pattern INP can be made of an inorganic insulating material. For example, the insulating pattern INP can include silicon nitride, silicon oxide, or silicon oxynitride, but is not limited thereto.

[0257] The second electrode CE2 can be commonly provided on the 1-1 light emitting element 130a, the 1-2 light emitting element 130b, the 2-1 light emitting element 140a, the 3-1 light emitting element 150a, and the 3-2 light emitting element 150b. The second electrode CE2 can extend in a direction intersecting the first to sixth signal lines TL1, TL2, TL3, TL4, TL5, and TL6. The second electrode CE2 can be in contact with the insulating pattern INP in the recess RCS of the first optical layer 117a.

[0258] In this way, since the insulating pattern INP is provided between the second electrode CE2 and the solder pattern SDP exposed through the recess RCS of the first optical layer 117a in the sub-pixel in which the light emitting element ED is omitted, short circuit between the first electrode for driving the light emitting element and the second electrode can be prevented.

[0259] Figures 21 to 23is a sectional view of a display device according to an embodiment of the present disclosure and is a sectional view corresponding to Figure 20 .

[0260] Referring to Figure 21 , the light emitting element can be omitted on the solder pattern SDP of the 2-2nd sub-pixel SP2b, and the insulating pattern INP-1 can be disposed on the solder pattern SDP exposed through the recess RCS of the first optical layer 117a. The insulating pattern INP-1 can also be disposed on the inclined side wall of the recess RCS of the first optical layer 117a. The thickness of the portion of the insulating pattern INP-1 disposed on the side wall of the recess RCS can be less than the thickness of the portion of the insulating pattern INP-1 disposed on the solder pattern SDP.

[0261] In this way, since the insulating pattern INP-1 is disposed between the second electrode CE2 and the solder pattern SDP exposed through the recess RCS of the first optical layer 117a in the sub-pixel in which the light emitting element ED is omitted, it is possible to prevent a short circuit between the first electrode for driving the light emitting element and the second electrode.

[0262] Referring to Figure 22 , the light emitting element can be omitted on the solder pattern SDP of the 2-2nd sub-pixel SP2b, and the insulating pattern INP-2 can be disposed on the solder pattern SDP exposed through the recess RCS of the first optical layer 117a. At least a portion of the side surface of the solder pattern SDP can be exposed through the recess RCS of the first optical layer 117a, and the insulating pattern INP-2 can cover not only the upper surface of the solder pattern SDP but also at least a portion of the side surface of the solder pattern SDP.

[0263] In this way, since the insulating pattern INP-2 is disposed between the second electrode CE2 and the solder pattern SDP exposed through the recess RCS of the first optical layer 117a in the sub-pixel in which the light emitting element ED is omitted, it is possible to prevent a short circuit between the first electrode for driving the light emitting element and the second electrode.

[0264] Referring to Figure 23A light emitting element can be omitted on the solder pattern SDP of the 2-2 sub-pixel SP2b, and an insulating pattern INP-3 can be provided on the solder pattern SDP exposed by the recess RCS of the first optical layer 117a. The insulating pattern INP-3 can also be provided on the inclined side wall of the recess RCS of the first optical layer 117a. The thickness of the portion of the insulating pattern INP-3 provided on the side wall of the recess RCS can be smaller than the thickness of the portion of the insulating pattern INP-3 provided on the solder pattern SDP. At least a portion of the side surface of the solder pattern SDP can be exposed by the recess RCS of the first optical layer 117a, and the insulating pattern INP-3 can cover not only the upper surface of the solder pattern SDP but also at least a portion of the side surface of the solder pattern SDP.

[0265] In this way, since the insulating pattern INP-3 is provided between the second electrode CE2 and the solder pattern SDP exposed by the recess RCS of the first optical layer 117a in the sub-pixel in which the light emitting element ED is omitted, short-circuit between the first electrode for driving the light emitting element and the second electrode can be prevented.

[0266] Figures 24A to 24C is a cross-sectional view for describing a method of manufacturing Figure 20 the insulating pattern shown in FIG. 1.

[0267] Referring to Figure 24A A first optical layer 117a covering the side surface of the light emitting element ED including the 1-2 light emitting element 130b and the 3-2 light emitting element 150b is formed on the third insulating layer 115c. In this case, a recess RCS exposing the solder pattern SDP is formed in the second sub-pixel SP2 in which the light emitting element is omitted.

[0268] After the first optical layer 117a is coated to cover the upper surface and the side surface of the light emitting element ED, the first optical layer 117a is patterned using a half-tone mask and an exposure process, and a portion of the first optical layer 117a covering the upper surface of the light emitting element ED is removed. The first optical layer 117a includes a photosensitive organic insulating material and fine particles. In this case, in the sub-pixel in which the light emitting element ED is omitted, for example, in the 2-2 sub-pixel SP2b, the first optical layer 117a can be removed to expose the solder pattern SDP.

[0269] Referring to Figure 24BAn insulating material layer INL can be deposited on the light emitting elements ED and the first optical layer 117a by a chemical vapor deposition (CVD) method. The insulating material layer INL can be deposited thicker in the recesses RCS of the first optical layer 117a than in other areas. The thickness t2 of the insulating material layer INL deposited on the solder pattern SDP can be greater than the thickness t1 of the insulating material layer INL deposited on other surfaces of the first optical layer 117a.

[0270] Referring to Figure 24C The insulating material layer INL can be removed from the upper surfaces of the light emitting elements ED and the first optical layer 117a by an etchback process. In this case, the insulating material layer INL can remain in the recesses RCS of the first optical layer 117a to form an insulating pattern INP. Depending on the conditions of the etchback process and / or the inclination of the sidewalls of the recesses RCS of the first optical layer 117a, the insulating pattern INP can also be formed on the sidewalls of the recesses RCS of the first optical layer 117a.

[0271] Referring back to Figure 20 A second electrode CE2 can be formed on the light emitting elements ED and the first optical layer 117a. The second electrode CE2 can be electrically insulated from the solder pattern SDP by the insulating pattern INP.

[0272] A display device according to various embodiments of the present disclosure can be described as follows.

[0273] According to various embodiments of the present disclosure, a display device includes a substrate, a driving chip disposed on the substrate, a plurality of banks disposed on the driving chip, at least one of a plurality of first electrodes disposed on each of the plurality of banks and electrically connected to the driving chip, a plurality of solder patterns respectively disposed on the plurality of first electrodes, a plurality of light emitting elements respectively disposed on some of the plurality of solder patterns, a first optical layer disposed around the plurality of banks and the plurality of light emitting elements and having at least one recess exposing at least one solder pattern on which the light emitting element is not disposed, and an insulating pattern disposed on the solder pattern in the recess of the first optical layer.

[0274] According to various embodiments of the present disclosure, the recess can have an inclined sidewall, and the insulating pattern can be further disposed on the sidewall of the recess.

[0275] According to various embodiments of the present disclosure, a thickness of a portion of the insulating pattern disposed on the sidewall of the recess can be less than a thickness of a portion of the insulating pattern disposed on an upper surface of the solder pattern.

[0276] According to various embodiments of the present disclosure, an area of the insulation pattern can be greater than an area of the solder pattern.

[0277] According to various embodiments of the present disclosure, the insulation pattern can cover at least a portion of a side surface of the solder pattern.

[0278] According to various embodiments of the present disclosure, the insulation pattern can be made of an inorganic insulation material.

[0279] According to various embodiments of the present disclosure, the display device can further include a second electrode commonly disposed on the plurality of light emitting elements, and the second electrode can be in contact with the insulation pattern in the recess.

[0280] According to various embodiments of the present disclosure, the driving chip can be a micro driver, and the plurality of light emitting elements can be micro light emitting diodes (LEDs).

[0281] According to various embodiments of the present disclosure, the micro light emitting diodes can have a vertical structure.

[0282] According to various embodiments of the present disclosure, the plurality of light emitting elements can be electrically connected to the plurality of first electrodes through eutectic bonding.

[0283] According to various embodiments of the present disclosure, the solder pattern can be located in a lower portion of the recess of the first optical layer, and a width of the recess can be narrower downward

[0284] According to various embodiments of the present disclosure, an area of the lower portion of the recess can be greater than an area of the solder pattern.

[0285] According to various embodiments of the present disclosure, the insulation pattern can cover an entire upper surface of the solder pattern and at least a portion of a side surface of the solder pattern.

[0286] According to various embodiments of the present disclosure, a display device includes a substrate, a signal line disposed on the substrate, a plurality of first electrodes connected to the signal line, a plurality of solder patterns respectively disposed on the plurality of first electrodes, a plurality of light emitting elements respectively disposed on some of the plurality of solder patterns, a first optical layer disposed around the plurality of light emitting elements and having at least one recess exposing at least one solder pattern on which the light emitting element is not disposed, and an insulation pattern disposed on the solder pattern in the recess of the first optical layer.

[0287] According to various embodiments of the present disclosure, the recess can have an inclined sidewall, and the insulating pattern can be further disposed on the sidewall of the recess.

[0288] According to various embodiments of the present disclosure, a thickness of a portion of the insulating pattern disposed on the sidewall of the recess can be less than a thickness of a portion of the insulating pattern disposed on the solder pattern.

[0289] According to various embodiments of the present disclosure, an area of the insulating pattern can be greater than an area of the solder pattern.

[0290] According to various embodiments of the present disclosure, the insulating pattern can cover at least a portion of a side surface of the solder pattern.

[0291] According to various embodiments of the present disclosure, the insulating pattern can be made of an inorganic insulating material.

[0292] According to various embodiments of the present disclosure, the display device can further include a second electrode extending in a direction crossing the signal line and disposed on some of the plurality of light emitting elements, wherein the second electrode can be in contact with the insulating pattern in the recess.

[0293] According to various embodiments of the present disclosure, the plurality of light emitting elements can be micro light emitting diodes (LEDs) having a vertical structure.

[0294] According to various embodiments of the present disclosure, the plurality of light emitting elements can be electrically connected to the plurality of first electrodes by eutaxy bonding.

[0295] According to various embodiments of the present disclosure, the solder pattern can be located in a lower portion of the recess of the first optical layer, and a width of the recess can be narrower downward

[0296] According to various embodiments of the present disclosure, an area of the lower portion of the recess can be greater than an area of the solder pattern.

[0297] According to various embodiments of the present disclosure, the insulating pattern can cover an entire upper surface of the solder pattern and at least a portion of a side surface of the solder pattern.

[0298] According to embodiments of the present disclosure, in a sub-pixel in which a light emitting element is omitted due to a defect of a transfer process, by disposing an insulating pattern on a solder pattern exposed via a recess of a first optical layer, short-circuiting between a first electrode for driving the light emitting element and a second electrode can be prevented.

[0299] According to embodiments of the present disclosure, since the defect rate of the display device due to a transfer process is reduced, production energy required to manufacture the display device can be reduced.

[0300] Effects of the present disclosure are not limited to the above-mentioned effects, and those skilled in the art will be able to clearly understand other effects not mentioned in light of the above detailed description.

[0301] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not necessarily limited to the embodiments, and various modifications can be made without departing from the technical spirit of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but to describe the technical spirit of the present disclosure and the scope of the technical spirit of the present disclosure is not limited to the embodiments. Therefore, it should be understood that the above-described embodiments are illustrative rather than restrictive in all aspects.

Claims

1. A display device, comprising: substrate; A driver chip, wherein the driver chip is disposed on the substrate; Multiple dikes are disposed on the driver chip; A plurality of first electrodes, at least one of the plurality of first electrodes being disposed on each of the plurality of embankments and electrically connected to the driving chip; Multiple solder patterns are respectively disposed on the multiple first electrodes; Multiple light-emitting elements, wherein the multiple light-emitting elements are respectively disposed on some of the multiple solder patterns; A first optical layer is disposed around the plurality of embankments and the plurality of light-emitting elements, and has at least one recess exposing at least one solder pattern thereon on which at least one light-emitting element is not disposed; as well as An insulating pattern is disposed on the solder pattern in the recess of the first optical layer.

2. The display device according to claim 1, wherein the recess has inclined sidewalls, and The insulating pattern is also provided on the sidewall of the recess.

3. The display device according to claim 2, wherein the thickness of the portion of the insulating pattern disposed on the sidewall of the recess is less than the thickness of the portion of the insulating pattern disposed on the solder pattern.

4. The display device according to claim 1, wherein the area of ​​the insulating pattern is larger than the area of ​​the solder pattern.

5. The display device of claim 1, wherein the insulating pattern covers at least a portion of the side surface of the solder pattern.

6. The display device according to claim 1, wherein the insulating pattern is made of an inorganic insulating material.

7. The display device according to claim 1, further comprising a second electrode commonly disposed on the plurality of light-emitting elements, The second electrode is in contact with the insulating pattern in the recess.

8. The display device according to claim 1, wherein the driving chip is a microdriver and the plurality of light-emitting elements are micro light-emitting diodes (LEDs).

9. The display device according to claim 8, wherein the micro light-emitting diode has a vertical structure.

10. The display device according to claim 1, wherein the plurality of light-emitting elements are electrically connected to the plurality of first electrodes via eutectic bonding.

11. The display device of claim 1, wherein the solder pattern is located in the lower portion of the recess in the first optical layer, and The width of the recess narrows downwards.

12. The display device according to claim 11, wherein the area of ​​the lower portion of the recess is greater than the area of ​​the solder pattern.

13. The display device of claim 1, wherein the insulating pattern covers the entire upper surface of the solder pattern and at least a portion of the side surfaces of the solder pattern.

14. A display device, comprising: substrate; Signal lines, wherein the signal lines are disposed on the substrate; A plurality of first electrodes, the plurality of first electrodes being connected to the signal line; Multiple solder patterns are respectively disposed on the multiple first electrodes; Multiple light-emitting elements, wherein the multiple light-emitting elements are respectively disposed on some of the multiple solder patterns; A first optical layer is disposed around the plurality of light-emitting elements and has at least one recess that exposes at least one solder pattern on which at least one light-emitting element is not disposed; as well as An insulating pattern is disposed on the solder pattern in the recess of the first optical layer.

15. The display device according to claim 14, wherein the recess has inclined sidewalls, and The insulating pattern is also provided on the sidewall of the recess.

16. The display device according to claim 15, wherein the thickness of the portion of the insulating pattern disposed on the sidewall of the recess is less than the thickness of the portion of the insulating pattern disposed on the solder pattern.

17. The display device according to claim 15, wherein the area of ​​the insulating pattern is larger than the area of ​​the solder pattern.

18. The display device of claim 15, wherein the insulating pattern covers at least a portion of the side surface of the solder pattern.

19. The display device according to claim 15, wherein the insulating pattern is made of an inorganic insulating material.

20. The display device of claim 15, further comprising a second electrode extending in a direction intersecting the signal line and disposed on some of the plurality of light-emitting elements. The second electrode is in contact with the insulating pattern in the recess.

21. The display device according to claim 14, wherein the plurality of light-emitting elements are micro light-emitting diodes (LEDs) having a vertical structure.

22. The display device of claim 14, wherein the plurality of light-emitting elements are electrically connected to the plurality of first electrodes via eutectic bonding.

23. The display device of claim 14, wherein the solder pattern is located in the lower portion of the recess in the first optical layer, and The width of the recess narrows downwards.

24. The display device of claim 23, wherein the area of ​​the lower portion of the recess is greater than the area of ​​the solder pattern.

25. The display device of claim 14, wherein the insulating pattern covers the entire upper surface of the solder pattern and at least a portion of the side surfaces of the solder pattern.

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