Semiconductor device and preparation method thereof
By using liquid phase deposition and high-density plasma chemical vapor deposition processes to form fluorine-doped silicon-based precursor films and isolation material layers in semiconductor devices, the problem of void defects in shallow trench isolation structures is solved, thereby improving device performance and reliability.
Patent Information
- Application Number
- CN202511618885.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-06
- Publication Date
- 2026-01-27
AI Technical Summary
As the feature size of semiconductor devices shrinks, voids are more likely to form in shallow trench isolation structures, leading to increased leakage current and enhanced capacitive coupling, which affects device performance and reliability.
Fluorine-doped silicon-based precursor films are deposited in trenches using liquid phase deposition, combined with a backing layer and annealing, and then an isolation material layer is formed by high-density plasma chemical vapor deposition to achieve high-quality filling.
It effectively avoids void defects, improves filling quality, enhances the performance and reliability of semiconductor devices, and has a simple and low-cost process, making it suitable for mass production.
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Figure CN121419618A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for fabricating the same. Background Technology
[0002] As semiconductor manufacturing processes continue to advance towards deeper submicron and nanometer scales, isolation technology between semiconductor devices has become a key factor affecting their performance and reliability in order to achieve high-density, high-performance large-scale integrated circuits. Shallow Trench Isolation (STI), as the mainstream isolation structure in CMOS processes, is widely used in logic, memory, and RF devices. STI achieves electrical isolation between adjacent active regions by etching trenches in the substrate and filling them with an insulating dielectric, effectively suppressing leakage current, crosstalk, and latch-up effects, thus meeting the requirements of high-density integration.
[0003] In related technologies, the filling of shallow trench isolation structures typically employs high-density plasma-chemical vapor deposition (HDP-CVD). This process achieves trench filling by etching and depositing simultaneously, relying on the deposition rate exceeding the etching rate. However, as the feature size of semiconductor devices continues to shrink, the aspect ratio of trenches becomes increasingly larger. Reactive species in the HDP plasma struggle to diffuse uniformly into the trench, leading to premature closure at the trench top and the formation of voids in the STI region. These voids compromise the isolation performance of the STI, resulting in increased leakage current and enhanced capacitive coupling, ultimately impacting the performance and reliability of the semiconductor device.
[0004] Therefore, improvements are needed to at least partially address the aforementioned problems. Summary of the Invention
[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.
[0006] To address the existing problems, this application provides a method for fabricating a semiconductor device, comprising: providing a substrate, wherein a trench extending from the surface of the substrate into the substrate is formed therein; depositing a fluorine-doped silicon-based precursor film in the trench using a liquid phase deposition process, wherein the fluorine-doped silicon-based precursor film fills a portion of the depth of the trench; and forming an isolation material layer on the fluorine-doped silicon-based precursor film, wherein the isolation material layer fills the trench completely.
[0007] For example, the deposition of a fluorine-doped silicon-based precursor film in the trench via a liquid phase deposition process includes: applying a mixed solution of fluorosilicic acid and boric acid to the surface of the substrate and the trench; and, by using preset process conditions, causing the fluorosilicic acid and the boric acid to react to form the fluorine-doped silicon-based precursor film in the trench, wherein the fluorine-doped silicon-based precursor film fills a portion of the depth of the trench, and wherein the thickness of the fluorine-doped silicon-based precursor film is 500 Å to 2000 Å.
[0008] For example, the substrate is rotated during or after the application of the mixed solution, wherein the rotation speed is from 100 r / min to 500 r / min and the rotation time is from 0.5 minutes to 2 minutes.
[0009] For example, the preset process conditions include at least one of the following: the concentration of the fluorosilicic acid is 0.1 mol / L to 0.5 mol / L; the molar ratio of the boric acid to the fluorosilicic acid is 2:1 to 4:1; the pH value of the mixed solution is 2.5 to 3.5; the temperature of the liquid phase deposition process is 40 degrees to 60 degrees; and the time of the liquid phase deposition process is 5 minutes to 30 minutes.
[0010] For example, the insulating material layer is formed using a high-density plasma chemical vapor deposition process.
[0011] For example, after forming the trench and before depositing the fluorine-doped silicon-based precursor film, the method further includes the step of forming a pad layer at the bottom and sidewalls of the trench.
[0012] For example, after depositing the fluorine-doped silicon-based precursor film and before forming the isolation material layer, the fluorine-doped silicon-based precursor film is further annealed in an inert gas atmosphere.
[0013] For example, the annealing temperature is 400 to 600 degrees Celsius, and the annealing time is 1 to 2 hours.
[0014] Another aspect of this application provides a semiconductor device, comprising: a substrate having a trench formed therein extending from the surface of the substrate into the substrate; a fluorine-doped silicon-based precursor film located within the trench and filling a portion of the depth of the trench; and an isolation material layer located on the fluorine-doped silicon-based precursor film and filling the trench.
[0015] Exemplarily, it also includes a liner layer that covers the bottom and sidewalls of the trench and is located between the fluorine-doped silicon-based precursor film and the trench.
[0016] The semiconductor device and its fabrication method provided in this application form a fluorine-doped silicon-based precursor film that fills part of the depth of a trench using a liquid phase deposition process. Utilizing the excellent flowability and self-filling capability of the liquid phase deposition process, high-quality filling of high aspect ratio trenches is achieved. Then, an isolation material layer is deposited to complete the trench filling. This step-by-step filling strategy significantly reduces the aspect ratio of the subsequent isolation material layer filling, effectively avoiding void defects in trench filling, improving the overall filling quality, and offering a simple, low-cost process that enhances the performance and reliability of the semiconductor device, thus facilitating large-scale production applications. Attached Figure Description
[0017] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.
[0018] In the attached image: Figure 1 A flowchart illustrating a method for fabricating a semiconductor device according to a specific embodiment of this application is shown; Figures 2A to 2F The diagram shows a semiconductor device obtained by sequentially implementing a method for fabricating a semiconductor device according to a specific embodiment of this application. Detailed Implementation
[0019] The invention will now be described more fully with reference to the accompanying drawings, which illustrate embodiments of the invention. However, the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.
[0020] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.
[0021] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0023] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.
[0024] In related technologies, the filling of shallow trench isolation structures typically employs high-density plasma-chemical vapor deposition (HDP-CVD). This process achieves trench filling by etching and depositing simultaneously, relying on the deposition rate exceeding the etching rate. However, as the feature size of semiconductor devices continues to shrink, the aspect ratio of trenches becomes increasingly larger. Reactive species in the HDP plasma struggle to diffuse uniformly into the trench, leading to premature closure at the trench top and the formation of voids in the STI region. These voids compromise the isolation performance of the STI, resulting in increased leakage current and enhanced capacitive coupling, ultimately impacting the performance and reliability of the semiconductor device.
[0025] Therefore, in view of the aforementioned technical problems, this application proposes a method for fabricating a semiconductor device, such as... Figure 1 As shown, it mainly includes the following steps: Step S1: Provide a substrate, in which trenches extending from the surface of the substrate into the substrate are formed; Step S2: A fluorine-doped silicon-based precursor film is deposited in the trench using a liquid phase deposition process, and the fluorine-doped silicon-based precursor film fills part of the depth of the trench. Step S3: An isolation material layer is formed on the fluorine-doped silicon-based precursor film, and the isolation material layer fills the trench.
[0026] The semiconductor device and its fabrication method in this application employ a liquid phase deposition process to form a fluorine-doped silicon-based precursor film that fills a portion of the depth of a trench. Utilizing the excellent flowability and self-filling capability of the liquid phase deposition process, high-quality filling of high aspect ratio trenches is achieved. Then, an isolation material layer is deposited to complete the trench filling. This step-by-step filling strategy significantly reduces the aspect ratio of the subsequent isolation material layer filling, effectively avoiding void defects in trench filling, improving overall filling quality, and offering a simple, low-cost process that enhances the performance and reliability of the semiconductor device, thus facilitating large-scale production applications.
[0027] Example 1 Below, for reference Figure 1 as well as Figures 2A to 2F The method for fabricating the image sensor of this application is described in detail, wherein, Figure 1 A flowchart illustrating a method for fabricating a semiconductor device according to a specific embodiment of this application is shown. Figures 2A to 2F The diagram shows a semiconductor device obtained by sequentially implementing a method for fabricating a semiconductor device according to a specific embodiment of this application.
[0028] For example, the method for fabricating the semiconductor device of this application includes the following steps: First, step S1 is performed, providing a substrate in which trenches extending from the substrate surface into the substrate are formed.
[0029] In one example, such as Figure 2A As shown, a substrate 20 is provided, and the material of the substrate 20 includes, but is not limited to, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), sapphire, or other III / V compound semiconductors; or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI); or it may be a double-sided polished wafer (DSP), a ceramic substrate such as alumina, a quartz, or a glass substrate, etc. Although several examples of materials that can form a substrate have been described herein, any material that can serve as a substrate falls within the spirit and scope of the invention.
[0030] Exemplarily, a mask layer 201 is also formed on the substrate 20. The mask layer 201 includes a buffer layer 202 on the substrate 20 and a silicon nitride layer 203 on the buffer layer 202. The method for forming the buffer layer 202 includes, but is not limited to, thermal oxidation. The material of the buffer layer 202 includes, but is not limited to, silicon dioxide. The method for forming the silicon nitride layer 203 includes, but is not limited to, chemical vapor deposition (CVD). The buffer layer 202 is formed between the substrate 20 and the silicon nitride layer 203 to alleviate stress in subsequent processes and protect the substrate. In other examples, the mask layer 201 may also be a single-layer structure; this is not specifically limited.
[0031] In one example, such as Figure 2AAs shown, a trench 21 extending from the surface of the substrate 20 into the substrate 20 is formed within the substrate 20. The steps for forming the trench 21 include: forming a patterned photoresist layer on the surface of a mask layer 201, the patterned photoresist layer defining the shape and position of the trench 21; etching the mask layer 201 and the substrate 20 using the patterned photoresist layer as a mask to form the trench 21, the formed trench 21 extending from the surface of the substrate 20 into the interior of the substrate 20; and finally removing the photoresist layer. The etching of the substrate 20 can be performed using dry etching, such as reactive ion etching (RIE), ion beam etching, or plasma etching, or other conventional etching processes. The number of trenches 21 can be one or more, for example, one, two, or three, without specific limitation. The cross-sectional shape of the trench can be, but is not limited to, rectangular, inverted trapezoidal, U-shaped, or V-shaped, and the sidewalls of the trench can be vertical, inclined, or arc-shaped, without specific limitation. In some embodiments, the trench has an inverted trapezoidal cross-section or a structure that is wider at the top and narrower at the bottom, meaning that the opening width of the trench is greater than the bottom width. This structure helps to improve the step coverage of subsequent deposition processes and enhance the integrity and uniformity of the filling process.
[0032] Next, step S2 is performed, in which a fluorine-doped silicon-based precursor film is deposited in the trench using a liquid phase deposition process, and the fluorine-doped silicon-based precursor film fills part of the depth of the trench.
[0033] In one example, such as Figure 2B As shown, after forming the trench 21 and before depositing the fluorine-doped silicon-based precursor film 23, the method further includes forming a pad layer 22 on the bottom and sidewalls of the trench 21. Exemplarily, the material of the pad layer 22 includes, but is not limited to, silicon oxide or silicon nitride, and the method for forming the pad layer 22 includes, but is not limited to, chemical vapor deposition (CVD) and physical vapor deposition (PVD). The thickness of the pad layer 22 can be set according to process requirements, for example, from 200 Å to 1000 Å, and is not specifically limited thereto. The pad layer 22 is used to repair lattice damage introduced during etching, release interfacial stress, improve the adhesion of subsequently deposited films, and prevent impurity diffusion, effectively improving the interface quality and filling reliability of the shallow trench isolation structure, and enhancing the electrical performance and long-term stability of the device.
[0034] In one example, such as Figure 2CAs shown, a fluorine-doped silicon-based precursor film 23 is deposited in the trench 21 using a liquid phase deposition process, and the fluorine-doped silicon-based precursor film 23 fills a portion of the depth of the trench 21. Specifically, a liquid phase deposition (LPD) process is performed after the formation of the liner layer 22 to deposit a fluorine-doped silicon-based precursor (SiO2:F) film in the trench 21.
[0035] In one example, depositing a fluorine-doped silicon-based precursor film 23 within a trench 21 via a liquid phase deposition process includes: applying a mixed solution of fluorosilicic acid (H2SiF6) and boric acid (H3BO3) to the surface of a substrate 20 and into the trench 21; and, through preset process conditions, causing the fluorosilicic acid and boric acid to undergo a chemical reaction to form a fluorine-doped silicon-based precursor film 23 within the trench 21. Specifically, the step of depositing the fluorine-doped silicon-based precursor film 23 within the trench 21 includes: First, a mixed solution is prepared. Specifically, fluorosilicic acid (H₂SiF₆) and boric acid (H₃BO₃) are used as the main reactants and dissolved in high-purity deionized water to form a mixed solution. The preset process conditions are: the concentration of fluorosilicic acid is 0.1 mol / L to 0.5 mol / L, for example, 0.1 mol / L, 0.2 mol / L, 0.25 mol / L, 0.3 mol / L, 0.4 mol / L, or 0.5 mol / L. As the concentration of fluorosilicic acid increases, the silicon source supply in the solution increases, and the amount of fluorine-doped silicon-based precursor generated by the hydrolysis reaction increases, thereby leading to an increase in the thickness of the deposited film. By adjusting the concentration of fluorosilicic acid, the fluorine doping can be controlled. The deposition thickness of the silicon-based precursor film meets the filling depth requirements of different device structures; the molar ratio of boric acid to fluorosilicic acid is 2:1 to 4:1, such as 2:1, 3:1 or 4:1, etc., and the film deposition rate can be improved by increasing the molar ratio; the pH value of the formed mixed solution is 2.5 to 3.5, such as 2.5, 2.8, 3, 3.2, 3.4 or 3.5, etc., to ensure that the mixed solution is weakly acidic to optimize reaction kinetics and film growth rate, and to prevent the substrate from being corroded due to excessively low pH value.
[0036] Subsequently, a mixed solution of fluorosilicic acid (H2SiF6) and boric acid (H3BO3) is applied to the substrate surface, and the substrate 20 is subjected to a rotational treatment, wherein the rotational treatment is performed during or after the application of the mixed solution. Exemplarily, the mixed solution can be applied to the substrate surface in various ways, including but not limited to drop application, spraying, or spin coating. Specifically, the substrate 20 is fixed on a rotating stage, and the mixed solution is slowly applied to the surface of the substrate 20. The stage is controlled to rotate at a speed of 100 r / min to 500 r / min for 0.5 minutes to 2 minutes, thereby causing the substrate 20 to rotate. The rotational treatment can be initiated synchronously during the application of the mixed solution (e.g., rotation begins as the solution is applied to the substrate surface) or after the mixed solution is applied to the substrate surface. This rotation process helps the mixed solution flow into the trench 21 and remove the mixed solution from the substrate surface, which can maximize the formation of fluorine-doped silicon-based precursor (SiO2:F) films in the trenches rather than on the substrate surface. At the same time, moderate centrifugal force can regulate the mixed solution to make it uniformly distributed in the trench 21, thereby improving the filling efficiency of the trench 21.
[0037] In the reaction environment, the temperature of the liquid phase deposition process is controlled between 40 and 60 degrees Celsius. It should be noted that as the temperature increases, molecular thermal motion intensifies, the chemical reaction rate accelerates, and the deposition rate significantly increases. Therefore, the film growth rate can be controlled by adjusting the temperature. Simultaneously, excessively high temperatures can cause non-uniform aggregation or precipitation of fluorosilicic acid byproduct particles in the solution or on the trench surface, forming particle defects that affect film uniformity and interface quality. The liquid phase deposition process takes 5 to 30 minutes, during which the following reactions occur, as shown in the following equations: First, fluorosilicic acid (H2SiF6) undergoes a hydrolysis reaction (reaction formula (1)) to generate silicon dioxide (SiO2) precipitate and hydrogen fluoride (HF). This hydrolysis reaction is reversible, and the thermodynamic driving force for spontaneous rightward movement is weak, requiring external force to drive it. Then, hydrogen fluoride (HF) is consumed by boric acid (H3BO3), converting hydrogen fluoride (HF) into stable fluoroborate ions (BF4). - (Reaction (2)) reduces the HF concentration in the solution system, and simultaneously, according to Le Chatelier's principle, promotes the hydrolysis reaction to continue to the right, achieving continuous precipitation of silicon dioxide. Finally, through the above reaction, continuous precipitation of silicon dioxide is achieved, thereby forming a fluorine-doped silicon-based precursor (SiO2:F) film that fills part of the trench depth and covers part of the liner layer. For example, the thickness of the formed fluorine-doped silicon-based precursor film is 500 Å to 2000 Å, such as 500 Å, 800 Å, 1000 Å, 1500 Å, 1700 Å or 2000 Å.
[0038] It should be noted that the silicon source compounds used in this application to generate fluorine-doped silicon-based precursor films include, but are not limited to, fluorosilicic acid. Other compounds that can hydrolyze in aqueous solution and release hydrogen fluoride (HF) while generating silicon dioxide or silicon-based gels, such as silicon tetrafluoride (SiF4) and ammonium fluorosilicate ((NH4)2SiF6), can also be used as silicon source precursors in mixed solutions. As long as the reaction mechanism still relies on shifting the chemical equilibrium of silicon oxide deposition to the right by removing the byproduct HF, they are all equivalent alternatives to the present invention and fall within the protection scope of the present invention.
[0039] Furthermore, boric acid is used as an HF scavenger in this invention, its role being to undergo an irreversible reaction with the HF generated in the reaction to form stable fluoroborate ions (BF4). - This reduces the concentration of HF in the solution system, thereby promoting the continued progress of the main reaction according to Le Chatelier's principle. Without departing from the basic principles of this application, other compounds that can react efficiently and selectively with HF to form stable soluble complexes or gaseous products, without introducing metal impurities or particulate contamination, may also be used to replace boric acid; no specific limitations are imposed on this.
[0040] After the reaction, residual solution is drained, for example, by rinsing the substrate surface with deionized water to remove unreacted substances and byproducts. Due to the use of liquid phase deposition, the solution flows into the trench, exhibiting excellent self-filling and planarization characteristics, achieving void-free uniform filling even for shallow trench structures with high aspect ratios. By pre-filling the bottom of the trench with a fluorine-doped silicon-based precursor film 23, the aspect ratio required for subsequent HDP-CVD processes can be effectively reduced, significantly improving the filling quality and reliability of the subsequent isolation material layer 25. This method has a simple process flow, requires no expensive vacuum equipment, is low-cost, and is easily integrated into existing production lines. Furthermore, the resulting composite filling structure does not alter the overall chemical and electrical properties of the film layer, does not affect device performance, and combines process advantages with device reliability.
[0041] In one example, after depositing the fluorine-doped silicon precursor film 23 and before forming the isolation material layer 24, the fluorine-doped silicon precursor film is further annealed in an inert gas atmosphere. Exemplarily, after completing liquid phase deposition and forming the fluorine-doped silicon precursor film, to improve the film's stability, density, and interfacial compatibility with the subsequent isolation material layer, the fluorine-doped silicon precursor film 23 undergoes a post-processing step before depositing the isolation material layer 24. This post-processing includes two steps: inert gas purging and drying, and thermal annealing.
[0042] First, after the liquid phase deposition process, the fluorine-doped silicon-based precursor film 23 is purged with an inert gas, such as high-purity nitrogen (N2). This process effectively removes residual moisture and unreacted solution from the trench surface and the fluorine-doped silicon-based precursor film 23, thus curing the film. Next, the fluorine-doped silicon-based precursor film 23 is annealed in an inert gas atmosphere at temperatures ranging from 400°C to 600°C (e.g., 450°C, 500°C, 550°C, or 600°C) for 1 hour to 2 hours (e.g., 1 hour, 1.5 hours, or 2 hours). Annealing removes hydroxyl groups (-OH) and moisture from the film, increasing the density of the fluorine-doped silicon-based precursor film, enhancing its mechanical strength and chemical stability, and providing a good interface foundation for the subsequent deposition of the isolation material layer. This improves the overall filling quality and reliability of the STI structure.
[0043] Finally, step S3 is performed to form an isolation material layer on the fluorine-doped silicon-based precursor film, the isolation material layer filling the trench.
[0044] In one example, such as Figure 2D As shown, an isolation material layer 24 is formed on a fluorine-doped silicon-based precursor film 23, completely filling the trench 21. After the deposition and post-processing of the fluorine-doped silicon-based precursor film 23, the isolation material layer 24 is deposited to completely fill the remaining space of the trench 21, achieving complete filling of the shallow trench isolation structure. Specifically, chemical vapor deposition (CVD) processes, such as high-density plasma chemical vapor deposition (HDP-CVD), can be used to form the isolation material layer 24 on the fluorine-doped silicon-based precursor film 23. The material of the isolation material layer 24 includes, but is not limited to, silicon oxide. By pre-depositing the fluorine-doped silicon-based precursor film 23, the aspect ratio of the isolation material layer 24 is reduced, effectively avoiding void defects. Combined with HDP-CVD and other processes, dense filling is achieved, significantly improving the filling integrity and interface quality of the STI structure, which is beneficial for CMP planarization and improves the isolation performance and reliability of the device.
[0045] Among them, such as Figure 2E As shown, after forming the isolation material layer 24, the process further includes removing the isolation material layer 24 from the substrate 20. Specifically, a planarization process can be used to remove a portion of the isolation material layer 204, stopping at the mask layer 201. The planarization process includes, but is not limited to, chemical mechanical polishing (CMP). Through the above steps, a shallow trench isolation structure consisting of a pad layer, a fluorine-doped silicon-based precursor film 23, and an isolation material layer 24 is formed within the substrate.
[0046] Next, as Figure 2F As shown, the mask layer 201 is removed to expose the surface of the substrate 20. Specifically, the removal can be achieved by selecting an appropriate etching process (e.g., dry etching or wet etching) or cleaning process depending on the type of mask layer material, and there is no specific limitation on this.
[0047] It is worth mentioning that the above steps are only examples, and the order of the steps can be adjusted without conflict.
[0048] Thus, the process steps of the semiconductor device fabrication method according to the embodiments of this application are completed. It is understood that the semiconductor device fabrication method of this embodiment includes not only the above steps, but may also include other necessary steps before, during or after the above steps, all of which are included within the scope of the fabrication method of this embodiment.
[0049] In summary, the semiconductor device fabrication method of this application forms a fluorine-doped silicon-based precursor film that fills part of the depth of a trench using a liquid phase deposition process. Utilizing the excellent flowability and self-filling capability of the liquid phase deposition process, high-quality filling of high aspect ratio trenches is achieved. Then, an isolation material layer is deposited to complete the trench filling. This step-by-step filling strategy significantly reduces the aspect ratio of the subsequent isolation material layer filling, effectively avoiding void defects in trench filling, improving the overall filling quality, and offering a simple, low-cost process that enhances the performance and reliability of semiconductor devices, thus facilitating large-scale production applications.
[0050] Example 2 This application also provides a semiconductor device, which can be prepared by the method of the aforementioned embodiment one, or can be prepared by other suitable preparation methods.
[0051] The following reference Figure 2F The semiconductor devices in the embodiments of this application will be explained and described, wherein structures that are the same as those in the aforementioned Embodiment 1 will not be described in detail here.
[0052] Specifically, such as Figure 2F As shown, the semiconductor device of this application includes: a substrate 20, and a trench 21 extending from the surface of the substrate 20 into the substrate 20 is formed therein.
[0053] The semiconductor device of this application further includes: a fluorine-doped silicon-based precursor film 23 and an isolation material layer 24. The fluorine-doped silicon-based precursor film 23 is located within a trench 21 and fills a portion of the depth of the trench 21; the isolation material layer 24 is located on the fluorine-doped silicon-based precursor film 23 and completely fills the trench 21. By pre-filling the trench with a fluorine-doped silicon-based precursor film, the aspect ratio of the subsequent isolation material layer is reduced, significantly improving the filling quality of the isolation material layer. The process is simple, requires no expensive vacuum equipment, is low-cost, and is easy to integrate into existing production lines. Furthermore, the resulting composite filling structure does not alter the overall chemical and electrical properties of the film layer, does not affect device performance, and combines process advantages with device reliability.
[0054] Exemplarily, the semiconductor device further includes a pad layer 22, which covers the bottom and sidewalls of the trench 21 and is located between the fluorine-doped silicon-based precursor film 23 and the trench 21. Exemplarily, the material of the pad layer 22 includes, but is not limited to, silicon oxide or silicon nitride, and the method for forming the pad layer 22 includes, but is not limited to, chemical vapor deposition (CVD) and physical vapor deposition (PVD). The thickness of the pad layer 22 can be set according to process requirements, for example, from 200 Å to 1000 Å, and is not specifically limited thereto. The pad layer 22 is used to repair lattice damage introduced during etching, release interfacial stress, improve the adhesion of subsequent deposited films and prevent impurity diffusion, effectively improve the interface quality and filling reliability of the shallow trench isolation structure, and enhance the electrical performance and long-term stability of the device.
[0055] The semiconductor device of this application has essentially the same advantages as the aforementioned fabrication method.
[0056] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will be conceived by those skilled in the art, all of which will fall within the spirit and scope of the disclosed concept. More particularly, various modifications and changes can be made in terms of the arrangement and / or components of the subject matter within the scope of the disclosure, drawings, and appended claims. In addition to modifications and changes in components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.
Claims
1. A method for fabricating a semiconductor device, characterized in that, The preparation method includes: A substrate is provided, wherein a trench extending from the surface of the substrate into the substrate is formed therein; A fluorine-doped silicon-based precursor film is deposited in the trench using a liquid phase deposition process, and the fluorine-doped silicon-based precursor film fills a portion of the depth of the trench. An isolation material layer is formed on the fluorine-doped silicon-based precursor film, and the isolation material layer fills the trench.
2. The preparation method according to claim 1, characterized in that, The deposition of a fluorine-doped silicon-based precursor film in the trench via a liquid phase deposition process includes: A mixed solution of fluorosilicic acid and boric acid is applied to the surface of the substrate and the trenches; By using preset process conditions, the fluorosilicic acid and the boric acid react to form the fluorine-doped silicon-based precursor film in the trench. The fluorine-doped silicon-based precursor film fills a portion of the depth of the trench, wherein the thickness of the fluorine-doped silicon-based precursor film is 500 Å to 2000 Å.
3. The preparation method according to claim 2, characterized in that, During or after the application of the mixed solution, the substrate is rotated at a speed of 100 r / min to 500 r / min for a time of 0.5 min to 2 min.
4. The preparation method according to claim 3, characterized in that, The preset process conditions include at least one of the following conditions: The concentration of the fluorosilicic acid is from 0.1 mol / L to 0.5 mol / L; The molar ratio of boric acid to fluorosilicic acid is 2:1 to 4:1; The pH value of the mixed solution is 2.5 to 3.5; The temperature of the liquid phase deposition process is 40 to 60 degrees Celsius. The liquid phase deposition process takes 5 to 30 minutes.
5. The preparation method according to claim 1, characterized in that, The isolation material layer is formed using a high-density plasma chemical vapor deposition process.
6. The preparation method according to claim 1, characterized in that, After the trench is formed and before the fluorine-doped silicon-based precursor film is deposited, the method further includes the step of forming a liner layer at the bottom and sidewalls of the trench.
7. The preparation method according to claim 1, characterized in that, After depositing the fluorine-doped silicon-based precursor film and before forming the isolation material layer, the fluorine-doped silicon-based precursor film is further subjected to annealing in an inert gas atmosphere.
8. The preparation method according to claim 7, characterized in that, The annealing temperature is 400 to 600 degrees Celsius, and the annealing time is 1 to 2 hours.
9. A semiconductor device, characterized in that, include: A substrate, wherein a trench extending from the surface of the substrate into the substrate is formed therein; A fluorine-doped silicon-based precursor film, wherein the fluorine-doped silicon-based precursor film is located within the trench and fills a portion of the depth of the trench; An isolation material layer is located on the fluorine-doped silicon-based precursor film and fills the trench.
10. The semiconductor device as claimed in claim 9, characterized in that, It also includes a liner layer that covers the bottom and sidewalls of the trench and is located between the fluorine-doped silicon-based precursor film and the trench.