High voltage isolation with controlled discharge path

Abstract

The invention relates to high voltage isolation with a controlled discharge path. A semiconductor device (100) including a capacitive HV isolation component (102) and a method of manufacturing the same are disclosed. In one example, the semiconductor device (100) comprises: a semiconductor substrate (101); a bottom capacitor plate (104) over the semiconductor substrate (101); a top capacitor plate (105) above the bottom capacitor plate (104); and one or more conductive posts (195A to 195C) extending between the bottom plate (104) and the top plate (105).

Description

Technical Field

[0001] The disclosed embodiments generally relate to the fields of integrated circuits (ICs) and IC manufacturing. More specifically, but not exclusively, the disclosed embodiments relate to ICs that include high-voltage isolation components. Background Technology

[0002] Current isolation works on the principle of isolating functional parts of an electrical system or integrated circuit to prevent the flow of current, while energy or information can still be exchanged between these parts via other means, such as capacitors, inductors, or electromagnetic waves, or via optical, acoustic, or mechanical means. Current isolation is commonly used when two or more circuits are communicating but their ground or reference nodes may be at different potentials. This is an effective way to break a ground loop by preventing unwanted current from flowing between two units sharing a reference conductor. Current isolation is also used for safety reasons to prevent current from accidentally reaching the ground through a person's body.

[0003] An isolator is a device designed to minimize direct current (DC) and unwanted alternating current (AC) or transient current between two systems or circuits, while allowing data and power transfer between the two systems or circuits. In most applications, an isolator acts as a barrier against high voltages, in addition to allowing the system to operate properly. When capacitive elements are used as isolators, dielectric breakdown is a critical issue, especially in high-voltage (HV) applications.

[0004] As integrated circuits and semiconductor manufacturing continue to advance in design, improvements are also being made to microelectronic devices that include current isolators. Summary of the Invention

[0005] The following is a simplified overview to provide a basic understanding of some examples of this disclosure. This summary is not a broad overview of the examples, nor is it intended to identify key or essential elements of the examples, nor to define their scope. Rather, the main purpose of this summary is to present some concepts of this disclosure in a simplified form as a prelude to the detailed embodiments further presented in subsequent sections.

[0006] An example of this disclosure is directed to an IC device (also known as an electronic device, semiconductor device, etc.) that includes a capacitive HV isolation component, wherein a discharge path from the top plate of the HV isolation component can be controllably guided through a better-characterized dielectric layer, thereby facilitating more reliable prediction of the IC's time-dependent quality and performance metrics.

[0007] In one example, an IC device is disclosed, which particularly includes: a semiconductor substrate; a bottom capacitor plate above the semiconductor substrate; a top capacitor plate above the bottom capacitor plate; and one or more conductive pillars extending between the bottom plate and the top plate. In some arrangements, the conductive pillars may be configured to guide a discharge path between the top plate and the bottom plate through a dielectric stack disposed between the bottom plate and the top plate.

[0008] In one example, an IC package is disclosed, which in particular includes: a first IC die comprising: a capacitor comprising a bottom capacitor plate above a first semiconductor substrate, a top capacitor plate above the bottom capacitor plate, and a conductive post between the bottom capacitor plate and the top capacitor plate; a second IC die comprising circuitry above or extending into the second semiconductor substrate; and a wire bond connecting the top capacitor plate to the circuitry.

[0009] In one example, a method for manufacturing an IC is disclosed, which particularly includes: forming a metal base plate of a capacitor over a semiconductor substrate; forming a conductive post over the base plate; and forming a metal top plate of the capacitor over the conductive post, wherein the conductive post extends between the base plate and the top plate. Attached Figure Description

[0010] In the accompanying drawings, embodiments of the present disclosure are illustrated by way of example rather than limitation. Different references to "an" or "one" embodiments in this disclosure do not necessarily refer to the same embodiment, and such references may mean at least one. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, whether or not it is explicitly described, such feature, structure, or characteristic may be combined with other embodiments.

[0011] To illustrate one or more exemplary embodiments of this disclosure, accompanying drawings are incorporated in and form a part of the specification. Various advantages and features of this disclosure will be understood from the following detailed description, taken in conjunction with the appended claims and with reference to the accompanying drawings:

[0012] Figures 1A-1 to 1A-3 Cross-sectional views of semiconductor devices including capacitive HV isolation components and conductive pillar arrangements are shown for each of the three examples.

[0013] Figure 1B Illustrate a top plan view of a semiconductor device based on some examples;

[0014] Figures 2A to 2Q The illustration shows cross-sectional views of semiconductor devices at the incremental manufacturing stage, based on some examples; and

[0015] Figure 3A and 3B A flowchart illustrating an IC manufacturing method based on some examples;

[0016] Figure 4 This is a partial cross-sectional view of an IC package based on some examples; and

[0017] Figures 5A to 5C A plan view of a metal plate having a plurality of conductive pillars that can operate as conductors in the discharge path direction, according to some examples of this disclosure. Detailed Implementation

[0018] Examples of this disclosure are described with reference to the accompanying drawings, in which similar reference numerals are generally used to refer to similar elements. The drawings are not drawn to scale and are provided only to illustrate the examples. Numerous specific details, relationships, and methods are set forth below to provide an understanding of one or more examples. However, some examples may be practiced without such specific details. In other instances, well-known subsystems, components, structures, and techniques have not been shown in detail to avoid obscuring the understanding of the examples. Therefore, examples of this disclosure may be practiced without such specific components.

[0019] Additionally, terms such as “coupled” and “connected” and their derivatives may be used in the detailed description below, the appended claims, or both. It should be understood that these terms are not necessarily intended to be synonyms. “Coupled” can be used to indicate that two or more elements (which may or may not be in direct physical or electrical contact with each other) cooperate or interact with each other. “Connected” can be used to indicate the establishment of a connection, i.e., a connectivity, between two or more coupled elements. Furthermore, in one or more examples set forth herein, generally, if an element can be programmed to perform or otherwise structurally arranged to perform a function, then the element, component, or module can be configured to perform said function.

[0020] Without restriction, examples of high-voltage isolation components and their manufacturing methods will be described below in the context of capacitive isolation devices formed in the interconnect layer of IC devices during back-end process (BEOL) manufacturing.

[0021] Circuit isolation (also known as current isolation) prevents direct current (DC) and unwanted alternating current (AC) signals from being transmitted from one area of ​​a system or circuit to another area or circuit that needs protection, as previously mentioned. In its application, isolation maintains the signal integrity of a system or circuit by preventing the propagation of high-frequency noise, protecting sensitive circuit systems from high-voltage surges and spikes, and providing safety for human operators.

[0022] High voltages, ranging from hundreds to thousands of volts, can exist in applications such as factory automation, motor drives, power grid infrastructure, and electric vehicles (EVs). Current isolation helps address the challenges of designing safe human-machine interfaces in the presence of such high voltages.

[0023] In some exemplary embodiments, a current isolator can be generated by forming a parallel-plate capacitor using electrodes in different metallization layers of an integrated circuit (e.g., different metallization layers in a BEOL interconnect level). The dielectric layers of the BEOL level separate the electrodes to form the capacitor, where the stacking of dielectric layers forms the distance through isolation (DTI) of the capacitor. For HV applications, the thickness and / or number of BEOL dielectric layers can be increased to provide a higher DTI, thus improving the capacitor's breakdown performance (e.g., increasing the capacitor's breakdown voltage). In some instances, a composite dielectric layer comprising silicon nitride (SiN) and silicon oxynitride (SiON) can be disposed below the top electrode to improve HV isolation performance.

[0024] Despite advances in controlling the quality and / or composition of the dielectric layer of the BEOL (and thus, the DTI of the current isolator), certain types of failure modes associated with current isolators persist, leading to persistent reliability issues. For example, the maximum or inherent capacitance of a current isolation capacitor can be limited by early-life failures, which can be attributed to (but not limited to) breakdown of materials located above and / or laterally adjacent to the top plate of the capacitor in the presence of high electric fields (e.g., approximately hundreds of volts / μm or thousands of volts / μm). In exemplary embodiments, the materials above and / or laterally adjacent to the top plate typically include passivations, protective outer coatings, and / or molding compounds, which have poorer dielectric breakdown strength than materials including DTI (e.g., SiO2, etc.). For example, polyimides and molding compounds are prone to isolation degradation due to moisture absorption and are also prone to life degradation when subjected to stress at higher frequencies. Additionally, the interface between the protective outer coating and the top metal plate / molding compound is also prone to less reliable characterization.

[0025] Examples of this disclosure recognize the aforementioned challenges and provide technical solutions for controlling fault paths (also referred to herein as discharge paths) that can be induced by isolation capacitors in the presence of high electric fields. To prevent lateral and / or upward fault paths across or above the IC device, and alternatively to guide fault paths downward (e.g., through the capacitor DTI), examples herein may include one or more conductive pillars positioned relative to the top and / or bottom plate of the isolation capacitor, which may operate as “hot spots” to preferably draw in and terminate the fault path. Because the downward fault path is guided through the DTI material with higher dielectric strength, more reliable quality estimates and operating voltage predictions of the IC device are obtained. While such examples and variations are expected to increase the overall reliability and / or electrical performance of the IC device, specific results are not required unless expressly stated in the particular claims.

[0026] Turn Figures 1A-1 to 1A-3 The corresponding cross-sectional views illustrate three representative examples of a semiconductor device 100 (e.g., an IC device), wherein, according to some embodiments described herein, a capacitive HV isolation component that can operate as a discharge path component, as well as conductive pillars, may be provided. As will be further elaborated below, one or more conductive pillars may be fabricated during the BEOL process of the semiconductor device 100, wherein the conductive pillars may be formed as metal structures not electrically connected between metal interconnect layers of a multilayer metallization scheme associated with the semiconductor device 100. Furthermore, depending on the embodiment, the conductive pillars may be positioned at various levels and / or locations relative to the conductive structure (e.g., electrodes) of the HV isolation component.

[0027] For specific references Figure 1A-1 The semiconductor device 100 includes a semiconductor substrate 101, on which a capacitor 102, which can operate as a current-isolated device, and optionally a transistor 103 are formed. Depending on the application, in some instances, the semiconductor substrate 101 may primarily comprise suitably doped silicon, but other semiconductor materials such as Ge, SiGe, GaAs, SiC, GaN, and other Group III-V materials may be used in some embodiments, wherein in some arrangements, one or more epitaxial layers or single-crystal layers may be formed or provided in certain regions of the semiconductor substrate 101.

[0028] Capacitor 102 includes a first electrode 104 and a second electrode 105. Without limitation, implication, or otherwise, the first electrode 104 may be referred to as a base plate / electrode or lower plate / electrode 104, and the second electrode 105 may be referred to as a top plate / electrode or upper plate / electrode 105. In some embodiments, the top plate 105 and the base plate 104 may have similar or identical form factors, such as having the same size, thickness, and shape, but this is not necessary for the purposes of this disclosure. Additionally, in exemplary embodiments, such as where there may or may not be a varying amount of overlap between the two plates, the base plate 104 may be directly disposed between the top plate 105 and the substrate 101 along a surface normal. The top plate 105 may be connected to a high-voltage circuit node, while in some arrangements, the base plate 104 and the transistor 103 may be connected to a low-voltage circuit node.

[0029] In some instances, base plate 104 and / or top plate 105 may have a minimum length along the longest axis of approximately 30 μm. Similarly, base plate 104 and / or top plate 105 may each have a minimum length along an orthogonal shortest axis of approximately 30 μm. In some instances, each of base plate 104 and top plate 105 may have an aspect ratio in the range of approximately one to approximately five (e.g., the length of the longest axis divided by the length of the orthogonal shortest axis). Plates 104 and 105 are not limited to any particular shape that may include a variety of geometries, such as square, circular, elliptical, rectangular, oval, coiled / serpentine, racetrack-shaped, oblong, trapezoidal, rhomboid, regular or irregular polygons, etc. In some further instances, plates 104 and 105 may have a minimum lateral width (parallel to the main surface of substrate 101) sufficient to facilitate the formation of line bonds (e.g., bond 197) for top plate 105 in order to provide connectivity to external circuitry (not shown in this figure). Such a minimum width may depend on the wire bonding technique and can be approximately 80 μm without any limitations. In one non-limiting example, plates 104 and 105 each have a short axis length of approximately 120 μm and a long axis length of approximately 160 μm. In another non-limiting example, both plates 104 and 105 have a circular shape with a diameter of approximately 120 μm. In some examples, one of the base plate 104 and the top plate 105 may be implemented as multiple plates, such as two plates. Thus, in one non-limiting example, the base plate 104 may be a single continuous metal plate, while the top plate 105 may be two discontinuous metal plates. In such examples, the two or more plates do not need to be of the same shape or have the same area.

[0030] Figure 1A-1The example illustrates a five-level metal (5LM) device 100, but is not limited thereto. Therefore, device 100 comprises five metal levels, designated MET1 to MET5, Met1 to Met5, M1 to M5, or similar terms. Each metal level contains metallic features within a corresponding inter-metal / intra-metal dielectric (IMD) layer IMD1 to IMD5. Inter-level dielectric (ILD) layers are located between each IMD layer, such that... Figure 1A-1 In the illustrative example, four dielectric layers ILD1 to ILD4 are present. A metal front dielectric (PMD) layer 114, which may include one or more sub-layers, is located between the IMD1 layer and the substrate 101. In some arrangements, the PMD layer 114 may include a material that can serve as a penetration barrier for various impurities generated by one or more CMP or other processes that can be used to fabricate various MET layers, and interconnect vias that can be used to provide electrical connectivity between two or more MET layers disposed at different levels. Depending on the embodiment, exemplary PMD materials may include low-pressure tetraethyl orthosilicate glass (LP-TEOS), Si-rich (SR) oxide, plasma-enhanced (PE) oxide nitride, PE nitride, PE-TEOS film, etc., and may be doped with fluorine or phosphorus.

[0031] A passivation / protective outer coating (PO) layer 196 comprising one or more sub-layers is topped with a metal layer MET5. Depending on the implementation, the PO layer 196 may have a total thickness ranging from tens or hundreds of nanometers (nm) to several micrometers (μm). The PO layer may contain one or more layers or sub-layers of an insulating material that can be deposited as part of a BEOL process, such as silicon nitride, silicon oxide, silicon oxynitride, polyimide, etc. Generally, IC chips designed to operate at higher voltages may require thicker PO layers, for example, in the range of about 4 μm to about 10 μm.

[0032] A molding compound is provided to encapsulate the semiconductor device 100 in the form of a bare die as part of a package body. Figure 1A-1 (Not shown in the image) Covered with a PO layer 196. In some arrangements, the encapsulation body may be formed from thermosetting epoxy resin in a molding process, or formed by using epoxy resin, plastic, or a resin that is liquid at room temperature and subsequently cures.

[0033] Optional isolation structures 106, such as shallow trench isolation (STI) structures, may be disposed between the PMD layer 114 (e.g., including sub-layers 112, 115) and the substrate 101. In some instances, the isolation structure 106 may be operable to reduce capacitive coupling between the substrate 104 and the substrate 101. In other instances not shown, the isolation structure 106 (if present) may include one or more doped well regions that provide junction isolation between the substrate 104 and the substrate 101. Figure 1A-1 As depicted, the base plate 104 may be formed of a metal structure disposed in the MET2 level of the illustrated 5LM metal interconnect example, but in other examples it may be located in another metal level. The metal level in which the base plate 104 is located may be selected in part based on design considerations such as the desired isolation between the base plate 104 and the substrate 101, the expected capacitive coupling to the top plate 105, etc.

[0034] Plates 104 and 105 may comprise any suitable metal. The examples described herein may depict plates 104 and 105 as being formed of aluminum (Al), but other metal interconnect systems, such as copper (Cu) or gold (Au), may be used in additional and / or alternative arrangements without excessive experimentation. Top plate 105 may be configured to receive high-voltage signals, such as via wires ball-bonded to top plate 105. High-voltage signals may be received from a high-voltage source to which device 100 is connected (e.g., another IC, motor, etc., operating in a high-voltage domain) to provide data transmission or electronic functions, such as monitoring or control. Depending on the implementation, for the purposes of some examples herein, "high voltage" may refer to a static or RMS voltage of about 100V or greater, and "low voltage" may refer to a static or RMS voltage of about 20V or less, but is not limited thereto.

[0035] Top plate 105 includes, for example, in Figure 1A-1 The dielectric stack of the intervening dielectric layers of ILD1 to ILD4 and the corresponding IMD1 to IMD4 in the illustrated arrangement is capacitively coupled to the base plate 104. This coupling can induce a weakened electrical signal on the base plate 104 corresponding to a high-voltage signal present at the top plate 105. The weakened signal at the base plate 104 can be coupled to another electronic device on another semiconductor substrate, or can be routed to an electronic device located on the same substrate, such as transistor 103.

[0036] In some instances, plates 104 and 105 may be located between stacks or pillars connected to substrate 101, as further described below. Substrate 101 may provide a ground reference for the via stack, for example, such that the via stack may provide a guard ring 109 serving as a portion of a Faraday cage capable of terminating or otherwise containing the electric field lines associated with plates 104 and / or 105. Additionally, guard ring 109 provides an outer periphery of a DTI volume over the substrate, wherein the DTI volume comprises various levels of dielectric layers in which one or more conductive pillars may be positioned relative to bottom plate 104 and / or top plate 105. In this example, the conductive pillars may be operable to guide or otherwise realize a discharge path between top plate 105 and bottom plate 104, for example, wherein the discharge path may be from top plate 105 toward bottom plate 104, or vice versa, rather than laterally across the polyimide / molded material overlying and / or laterally adjacent to the isolation capacitor 102. Although protective rings such as protective ring 109 are described in Figure 1A-1 The examples shown are not essential for the purposes of this disclosure. In some arrangements, the guard ring 109 (if provided) may be spaced from plates 104 and 105 by a distance greater than the DTI thickness between plates 104 and 105 or a multiple of the DTI thickness, in order to reduce or eliminate the risk of limiting the expected life of the component.

[0037] Generally, conductive pillars can be positioned anywhere within the BEOL stack between a bottom horizontal plane (e.g., a first XY plane) passing through the base plate 104 and a top horizontal plane (e.g., a second XY plane) passing through the top plate 105. This facilitates a discharge path between the top plate 105 and the base plate 104 when the isolation capacitor 102 encounters a high electric field (e.g., caused by an out-of-specification voltage spike). As will be further explained below, according to some examples, conductive pillars can be fabricated using existing via forming stages in the BEOL process, thus avoiding additional mask layers and associated manufacturing costs. Although via forming stages can be advantageously used to fabricate conductive pillars that can operate as a discharge path direction mechanism for the isolation capacitor 102, conductive pillars do not possess the characteristics of an interconnect level (e.g., a metal interconnect structure, such as a horizontal routing level, etc.) and multilayer metallization schemes (e.g., Figure 1A-1 Electrical connections between features of another interconnect layer (e.g., a metal interconnect structure, such as a horizontal routing layer, etc.) of the 5LM scheme described herein.

[0038] For the purposes of some examples of this disclosure, three types of silica dielectric materials are described. Two types can be produced by a plasma-enhanced chemical vapor deposition (PECVD) process in a capacitively coupled plasma reactor using tetraethoxysilane (TEOS) feedstock. These dielectrics are referred to herein as “PE-TEOS,” wherein the first type of PE-TEOS is “high-stress” PE-TEOS, and the second type of PE-TEOS is “low-stress” PE-TEOS, but is not limited thereto. In a non-limiting example, the “high-stress” PE-TEOS process can be configured to produce a SiO2 layer with a compressive stress of about 120 megapascals (MPa), while the “low-stress” PE-TEOS process can be configured to produce a SiO2 layer with a compressive stress of about 20 MPa. A third type of silica can be produced using high-density plasma in an inductively coupled reactor and is referred to as “HDP oxide,” but is not limited thereto. In some arrangements, HDP oxide and / or high-stress PE-TEOS may be used as dielectrics very close to or in contact with plates 104 and 105, while one or more of the dielectric layers between plates 104 and 105 contain low-stress PE-TEOS to reduce the effect / degree of wafer bowing. Additional details regarding the formation of PE-TEOS and HDP oxide layers that may be implemented in some embodiments of this disclosure can be found in U.S. Patent No. 11,495,658, which is incorporated herein by reference for all purposes.

[0039] Continue to refer to Figure 1A-1 For example, PMD layer 114 is illustrated as a composite layer comprising layers 112 and 115, wherein phosphorus-doped silicate glass (PSG) material is used to form layer 112 and high-stress PE-TEOS material is used to form layer 115, each having a suitable thickness depending on the embodiment. In some other embodiments, PMD layer 114 may be undoped and formed from a single dielectric type. The specific selection of PMD layer materials may depend, for example, on the type and functionality of the transistors included in device 100. In some arrangements, IMD1 layer may comprise an HDP oxide sublayer 121 and a high-stress PE-TEOS sublayer 127. Such a configuration may be produced by first depositing HDP oxide sublayer 121 over a MET1 feature, wherein the MET1 feature creates a surface shape in HDP oxide sublayer 121. As used herein, the term "surface shape" may be defined as a deviation of the top surface of a material layer from flatness of at least 10% of the layer thickness over a lateral distance three times the layer thickness. A high-stress PE-TEOS sublayer 127 of IMD1 is formed on top of the HDP oxide sublayer 121 and planarized to produce a suitable surface for subsequent processing, as will be further described below. Subsequently, a high-stress PE-TEOS layer 130 is formed on top of the planarized surface of the high-stress PE-TEOS sublayer 127 as part of IMD1.

[0040] In the illustrated example, the base plate 104 is formed in a MET2 layer formed over a high-stress PE-TEOS sublayer 130, wherein the HDP oxide layer 139 is formed as a portion of the IMD2 layer above the base plate 104. Therefore, the base plate 104 is defined by the HDP oxide on the top and side surfaces and by the high-stress PE-TEOS on the bottom surface. The base plate 104 and the top plate 105 are spaced apart by a dielectric stack structure (e.g., forming a DTI structure), which includes portions of or is formed of various ILD and IMD layers, which may include PE-TEOS and / or HDP oxide materials. In some instances, a silicon nitride (SiN) layer forming part of the DTI structure may be formed directly beneath the top plate 105 to provide additional HV robustness, but this is not required for the purposes of this disclosure.

[0041] In the illustrated example, portions of ILD2, IMD3, ILD3, IMD4, and ILD4 layers can be used as portions of a vertically stacked structure of dielectrics respectively disposed between the base plate 104 and the top plate 105 (not shown in the example). Figure 1A-1 The figures are labeled in the attached diagram.

[0042] (Specifically marked). In some arrangements, IMD2, IMD3, and IMD4 layers or levels may each contain corresponding PE-TEOS.

[0043] Layers 141, 156, and 171. A top plate 105 may be at least partially located within an IMD5 layer comprising an HDP oxide layer 190, wherein the HDP oxide layer 190 covers or touches a portion of the sidewalls and top surface of the top plate 105, such that only the openings 199 formed for wire bonding are exposed. Similarly, a TEOS layer 193 with openings corresponding to the wire bonding openings of the HDP oxide layer 190 may be formed over the top plate. A suitable PO layer (e.g., PO layer 196) may be formed to cover the remaining portion of the TEOS layer 193 at the IMD5 level. Additionally, in some instances, the PE-TEOS layer 171 of the IMD4 may be covered by SiN layers 177 and SiON layers 174 to enhance the HV breakdown performance of the electronic device 100. In yet other instances, the SiN layer 177 may include SiN sublayers 177A and 177B with different properties (e.g., refractive indices), but this is not required.

[0044] In some arrangements, PE-TEOS layers 141, 156, and 171 may be provided as low-stress layers, which may be encapsulated by other dielectric layers that effectively prevent moisture from diffusing into the dielectric stack and / or prevent moisture incorporated into the PE-TEOS layers during manufacturing from diffusing significantly outward. In other, unshown instances configured to operate in relatively low-voltage applications where the risk of dielectric breakdown near the corners of the top plate 105 is reduced, the low-stress PE-TEOS layers may be replaced, respectively, by high-stress PE-TEOS layers of similar thickness.

[0045] exist Figure 1A-1 In some examples, the oxide layer may be positioned in direct contact with one or more adjacent oxide layers. In other examples, a thin layer of dissimilar dielectric may be placed between some adjacent oxide layers. For example, a nitrogen-containing dielectric such as SiN or SiON may be placed between a low-stress PE-TEOS layer and a high-stress PE-TEOS layer, or between a low-stress PE-TEOS layer and an HDP oxide layer. The dissimilar dielectric (if used) may be a thin layer, for example, from 30 nm to 300 nm, to minimize its contribution to the cumulative stress of the dielectric stack in some additional, alternative, and / or optional arrangements. Regarding Figure 1A-1 The specific 5LM device 100 shown herein is described as follows: IMD1 is defined as layers 121 and 127; ILD1 as layer 130; IMD2 as layers 139 and 141; ILD2 as layer 144; IMD3 as layers 153 and 156; ILD3 as layer 159; IMD4 as layers 168 and 171; ILD4 as SiN layer 177 and SiON layer 174; and IMD5 as layers 190 and 193. In some instances, optional isolation breaks or notches 180 in the SiON / SiN composite layers 174 / 177 may be provided to enhance the lateral breakdown performance of device 100, particularly in applications involving 1000V or higher, as set forth in U.S. Patent No. 9,299,697, which is incorporated herein by reference for all purposes. Additionally, reference numerals 124, 136, 150, 165, and 187 in the attached drawings refer to various metal structures at MET1 to MET5 levels, respectively. Furthermore, in Figure 1A-1 The example illustrates the contact via 118 through PMD 114 and the interlayer vias 133, 147, 162 and 183 through the corresponding ILD1 to ILD4 layers.

[0046] exist Figure 1A-1In the example shown, the conductive post 195A may be formed during the fabrication of an interlayer via 147 connecting a metal structure 136 of a second metallization layer (e.g., MET2) and a metal structure 150 of a third metallization layer (e.g., MET3), wherein the conductive post 195A touches or directly contacts the top surface 191 of the base plate 104. Although only one conductive post 195A is shown positioned at or near the center of the base plate 104, multiple such conductive posts 195A may be present and arranged in a grid, wherein the post grid may have a center aligned with or laterally translated away from the center of the base plate 104 (e.g., the geometric center or centroid of the flat geometry of the grid). In some instances, multiple conductive posts 195A may be arranged in a 2×2 grid, a 4×4 grid, or more generally, an N×M grid constructed from repeating unit cells with minimal dimensions, but are not limited thereto. In some instances, the conductive posts 195A may be arranged in a configuration different from a grid, array, or matrix (e.g., a single-line construction such as rows or columns of variable length), arranged in straight or curved shapes, or arranged as circles, triangles, regular or irregular polygons, etc., which may be placed anywhere on the top surface 191 of the base plate 104. In some additional and / or alternative embodiments, the conductive posts 195A (whether configured as an array or a single curve) may be arranged closer to the edge of the plate 105, as will be seen further below.

[0047] In some instances, post 195A may have a shape factor similar to that of inter-level via 147, but this is not required. Depending on the implementation, the mask layer used to fabricate inter-level via 147 may be appropriately modified to accommodate similar or different sizes of post 195A. In one exemplary arrangement, conductive post 195A may comprise a metal post (e.g., tungsten) having a height of 194A and a width of 198A, the height being in the range of about 2 μm to about 4 μm, and the width being in the range of about 0.5 μm to about 1.5 μm.

[0048] Similar to the arrangement of conductive post 195A contacting the top surface 191 of the base plate 104 described above, one or more conductive posts 195B may be provided in some additional and / or alternative arrangements to contact the bottom surface 192 of the top plate 105. Figure 1A-2 The cross-sectional view shows a representative form of this example. Except for the placement of conductive post 195B, Figure 1A-2 The cross-sectional view of the semiconductor device 100 depicted in the figure and Figure 1A-1 The cross-sectional view depicted above is the same. Therefore, the above description... Figure 1A-1 The description also applies to Figure 1A-2 And unless otherwise mentioned, it will not be repeated here.

[0049] In some instances, the conductive post 195B may be formed during the fabrication of an inter-layer via 183 connecting a metal structure 165 of a fourth metallization layer (e.g., MET4) and a metal structure 187 of a fifth metallization layer (e.g., MET5), wherein the conductive post 195B is configured to contact the bottom surface 192 of the top plate 105. Additionally, the conductive post 195B may extend downwards to the interface of layers 171 and 168. Depending on the via etching process implemented, and because there is no drop-down metal structure such as a stop-etch structure 165, in some forms of this example, the conductive post 195B may extend through the interface of layers 171 and 168, but... Figure 1A-2 Not specifically shown. Similar to conductive post 195A, conductive post 195B may include any number and / or configuration and may be placed anywhere on the bottom surface 192 of top plate 105. In addition, conductive post 195B may have a height 194B and a width 198B similar to the height 194A and width 198A of conductive post 195A, but this is not required.

[0050] In some instances, one or more conductive pillars may be formed during the fabrication of interlayer vias not associated with the metal layers of the base plate 104 and / or top plate 105 corresponding to the isolation capacitor 102. In such arrangements, the conductive pillars are electrically isolated from both the base plate 104 and the top plate 105, and may be formed as “floating” pillars in any intervening dielectric layer. As an illustration, this can be achieved during the fabrication of... Figure 1A-3 During the inter-layer via 162 shown, one or more conductive pillars 195C are formed in ILD3, wherein the inter-layer via 162 connects the metal structure 150 of the third metallization layer (e.g., MET3) and the metal structure 165 of the fourth metallization layer (e.g., MET4). Similar to the bottom of the conductive pillar 195B, in some instances, the bottom of the conductive pillar 195C may extend through the interface of layers 156 and 153, due to the absence of a drop metal structure for stopping the via etching process. In addition to the placement of the conductive pillars 195C, Figure 1A-3 The cross-sectional view of the semiconductor device 100 depicted in the figure and Figure 1A-1 and 1A-2 The cross-sectional view depicted above is the same. Therefore, the above description... Figure 1A-1 The description also applies to Figure 1A-3 And unless otherwise specified where applicable, it will not be repeated here.

[0051] Similar to conductive posts 195A and 195C, conductive post 195C may include any number and / or configuration. Additionally, conductive post 195C may be formed anywhere within the ILD3, for example, within a boundary defined by a grounding ring (if provided, e.g., guard ring 109). In some arrangements, conductive post 195C may have a height 194C and width 198C similar to conductive posts 195A and 195B, but this is not required.

[0052] exist Figures 1A-1 to 1A-3 In some examples, conductive posts 195A, 195B, and / or 195C (collectively, “conductive posts 195”) are connected to another metallic feature, such as capacitor plates 104, 105, at no more than one surface, or are not connected to another metallic feature at all (e.g., “floating”). Therefore, conductive posts 195 may not carry current except in the event of breakdown of one or more of the dielectric layers between plates 104, 105. Specifically, although conductive posts 195 may be formed by processes that produce vias (e.g., vias 133, 147, 162, and 183), conductive posts 195 do not carry current between interconnect layers and do not conduct current in any circuit node except during discharge events.

[0053] In some additional and / or alternative instances, more than one configuration of conductive pillars can be provided, for example, by using different combinations of plate-connected pillars such as pillars 195A and 195B and floating pillars such as pillar 195C. In yet another arrangement, conductive pillars 195A and / or conductive pillars 195B can be “decoupled” from the corresponding plates 104, 105, wherein pillars 195A and 195B can be manufactured as floating pillars anywhere in ILD2 and ILD4, respectively, but demarcated by guard ring 109 (if provided). Thus, the examples herein can be combined in a variety of arrangements and combinations, taking into account different choices of the number of conductive pillars, form factors, and / or grid configurations, to achieve a highly customizable discharge path orientation mechanism for current isolation components, depending on the HV application environment.

[0054] Turn Figure 1B The device 100 described in this article is along Figures 1A-1 to 1A-3 The image shows a top view of plane X'-X" in the MET5 level. For illustration, it indicates that individual conductive pillars 195A to 195C are in... Figure 1BThe conductive post 195 is typically shown positioned internally relative to plates 104 and / or 105, but examples of this disclosure are not limited thereto. Depending on design considerations, the placement of the conductive post 195 may be determined based on its location relative to the high field region experienced and / or expected in the application environment relative to the HV isolation capacitor 102. In some examples, the higher field region may be more dominant closer to the edges of plates 104 and / or 105 of the HV isolation capacitor 102. Therefore, in some examples, the conductive post 195 may be positioned close to the edges of plates 104 and / or 105, regardless of the shape or size of plates 104 and / or 105, as further illustrated below. In some arrangements, the HV isolation capacitor 102 may be provided as having a racetrack shape or an oblong shape, illustrating an opening of suitable size and shape, such as opening 199, overlying the top plate 105 and extending through the topmost IMD sublayer (e.g., layer 190 of IMD5). A cross-sectional view is generated along a vertical cross-section of a normal plane Y'-Y" orthogonal to the horizontal plane (e.g., layer 190) of device 100, as shown in the reference above. Figures 1A-1 to 1A-3 A detailed view is provided, depending on the location where the conductive post 195 is positioned.

[0055] Figures 2A to 2Q This explanation, based on some examples in this article, is in relation to Figures 1A-1 to 1A-3 A cross-sectional view of a semiconductor device 100 at a continuous manufacturing stage, wherein, in addition to forming Figures 1A-1 to 1A-3 Apart from the three types of conductive pillars described herein, most of the stages are common. Therefore, the descriptions presented below are broadly applicable. Figures 1A-1 to 1A-3 The arrangement, except as otherwise mentioned. Figure 2A The image shows a substrate 101 with transistor 103 already formed therein, with the location of capacitor 102 shown for reference. As previously described, one or more isolation structures 106 may be formed in the substrate 101 relative to capacitor 102 and other circuit components such as transistor 103. Additionally, in some instances where transistor 103 or other circuit systems are not included, such instances illustrate an arrangement of capacitor 102 that can be referred to as a “freestanding” capacitor in a discrete semiconductor device configuration. As previously mentioned, substrate 101 can be any suitable substrate, such as semiconducting or insulating. In some instances, substrate 101 is a silicon wafer or a portion thereof, such as a semiconductor die, and may be doped with suitable dopants, such as p-type dopants.

[0056] Figure 2B This indicates the stage where the PMD layer 114 has been formed. In the illustrated example shown, but not limited to, a dielectric layer 112 is formed over a substrate 101 that projects a vertical and / or conformal surface shape over the transistor 103. The dielectric layer 112 may be a PSG layer, as previously mentioned. Figure 2B As shown, a high-stress PE-TEOS dielectric layer 115 can be formed over dielectric layer 112 and planarized to reduce surface shape. In other examples, such as when device 100 is a stand-alone device, an undoped dielectric, such as high-stress PE-TEOS, can be used for dielectric layer 112, and planarization can be omitted. In such examples, a SiN layer with a compressive stress of approximately -100 MPa can be used for layer 115.

[0057] exist Figure 2C In this configuration, contacts 118 (e.g., including tungsten plugs) formed through dielectric layers 112 and 115 are operable to contact substrate 101 in a region of capacitor 102. Additional unmentioned contacts may be provided to enable connectivity with respect to other components of device 100 (e.g., source / drain regions of transistor 103). A metal layer may be formed over dielectric layer 115 and patterned to form a metal structure 124 connected to contacts 118, and unmentioned interconnects connected to the source / drain contacts of transistor 103. The exemplary metal structure 124 may be used for corresponding via stacks (e.g.,... Figures 1A-1 to 1A-3 The drop pads of subsequent vias (as described in the text) may form closed loops with corresponding other metal structures in metal structure 124. The metal layer forming metal structure 124 may be an Al layer, but is not limited to it, and patterning may include baseline photolithography and metal etching processes.

[0058] Figure 2D This describes the apparatus 100 formed after the deposition of the first IMD layer. An HDP oxide layer 121 of suitable thickness can be initially formed. In some instances, HDP oxide is preferred when the spacing between the metal structure 124 or other metal features outside the view shown is small enough that PE-TEOS may not effectively fill the space. In other instances with more relaxed spacing, PE-TEOS can be used alternatively. In the illustrated example, a dielectric layer 127 of high-stress PE-TEOS is formed over the HDP oxide layer 121. The surface shape associated with the metal structure 124 can extend to the surface of the PE-TEOS layer 127, which can be planarized using a suitable process, such as CMP, to remove a portion of the PE-TEOS layer 127, thereby reducing the surface shape. Figure 2EThe apparatus 100 is shown after planarization of the PE-TEOS layer 127 and after deposition of the PE-TEOS layer 130 on the planarized surface. The HDP oxide layer 121 and the PE-TEOS layer 127 are designated IMD1, and as previously mentioned, the PE-TEOS layer 130 is designated ILD1. In another example not shown, the PE-TEOS layer 127 may be deposited to a sufficient thickness to serve as both the upper portion of the IMD1 level and the ILD1 level, wherein the surface of the single PE-TEOS layer is then planarized. In some instances, this alternative embodiment may be suitable based on the aspect ratio associated with the metal structure 124.

[0059] Figure 2F The illustration illustrates, for example, the formation of a through-hole 133 within an ILD1 using tungsten (W) metallurgy, followed by the formation and patterning of a MET2 layer over a PE-TEOS layer 130 to produce a device 100 with a base plate 104 having a top surface 191 and a MET2 structure 136. The through-hole 133 formed within the ILD1 is operable to connect the MET2 structure 136 to the MET1 structure 124. Similar to the MET1 layer, the MET2 layer may be formed from Al. Depending on the implementation, the MET2 structure 136 may follow a layout similar to that of the MET1 structure 124.

[0060] Figure 2G This describes the stage where the HDP oxide layer 139 and the PE-TEOS layer 141 have been formed above the substrate 104. The surface shape of the PE-TEOS layer 141 conforms to the underlying MET2 structure 136 and the substrate 104. Therefore, the CMP process can also be used at this stage to reduce the surface shape. Figure 2H The apparatus 100 is described after the planarization of the PE-TEOS layer 141. The HDP oxide layer 139 and the remaining PE-TEOS layer 141 may be designated as IMD2, as previously mentioned.

[0061] Figure 2I This describes the apparatus 100 after the formation of the PE-TEOS layer 144, including the through-hole 147 for connecting the MET2 structure 136 and the MET3 structure 150. Figure 2J (As shown in the diagram) can be formed using suitable metallization processes and metallurgical methods (e.g., Al, Cu, W, etc.). In the example presented herein, the PE-TEOS layer 144 is designated as ILD2. During the fabrication of the via 147 through the remaining portions of dielectric layers 144 and 141, 139, one or more conductive pillars 195A are also formed using a via mask layer and metallurgical methods, wherein the conductive pillars 195A having a height 194A and a width 198A contact the top surface 191 of the base plate 104, as previously discussed. Figure 1A-1As mentioned in the examples. In some variations of this example, an additional mask layer may be used to provide the conductive post 195A with a different shape factor and metallurgical method than the through hole 147, which may increase manufacturing costs.

[0062] Figure 2J This describes a stage where another metallization layer (e.g., MET3) with metal structure 150 is formed above the planarized surface of ILD2, wherein HDP oxide layer 153 and PE-TEOS layer 156 are provided as IMD3. Similar to the formation of the lower layer, the surface of PE-TEOS layer 156 can be planarized. The sequence of manufacturing steps used to produce ILD2 and IMD3, as well as via 147 and MET3 structure 150, can be repeated as needed to provide the desired distance (e.g., DTI) between base plate 104 and top plate 105. Suitable adjustments can be made to accommodate metal spacing and thickness, as well as any requirements imposed by baseline and / or qualified processes in a particular manufacturing facility.

[0063] exist Figure 2K-1 The diagram illustrates the formation of a fourth metallization level (e.g., MET4) with a metal structure 165. In this example, a PE-TEOS layer 159 is formed over a planarized PE-TEOS layer 156, followed by an HDP oxide layer 168 and another PE-TEOS layer 171. The MET4 structure 165 is located within the HDP oxide layer 168, wherein vias 162 are formed through the remaining portions of dielectric layers 159 and 153, 156 to connect the MET4 structure 165 to the MET3 structure 150. As previously mentioned, the PE-TEOS layer 159 is designated as ILD3, and the HDP oxide layer 168 and the low-stress dielectric layer 171 are designated as IMD4.

[0064] although Figure 2K-1 The example shown represents Figure 1A-1 The arrangement, but Figure 2K-2 Depicting Figure 1A-2 An example of this arrangement is shown where one or more floating conductive pillars, such as conductive pillar 195C, are fabricated through layers 156 and 159 during the formation of via 162. Similar to the fabrication of conductive pillar 195A, conductive pillar 195C with a height 194C and a width 198C can be fabricated using the via mask layer used to fabricate via 162 and metallurgical methods, but this is not necessary for the purposes of some instances. As shown in the figure... Figure 2K-2 The stage at Figure 2H-2J After the stage, but the formation of conductive pillar 195A is omitted.

[0065] exist Figure 2LIn this configuration, a SiON layer 174 is formed above a PE-TEOS layer 171 as a portion of the composite dielectric layer, located below the top electrode, to improve the HV breakdown performance of the capacitor structure to be formed. In some arrangements, the thickness and compressive stress of the SiON layer 174 may be matched, balanced, or otherwise optimized relative to and / or with regard to the subsequent formation of the SiN layer, which may be a double layer in some of the aforementioned arrangements. Depending on the implementation, various techniques and processes can be used to form the SiON layer using precursors and reactants such as silane (SiH4), hexamethyldisilazane (HMDS), ammonia (NH3), nitrous oxide (N2O), and oxygen (O2), such as thermal CVD or plasma-enhanced CVD, thermal atomic layer deposition (ALD) or plasma-enhanced ALD (PEALD), etc.

[0066] A SiN layer 177, including, for example, a lower SiN layer 177B and an upper SiN layer 177A, can be formed to obtain, as shown below. Figure 2M The structure is shown in the diagram. In some arrangements, the upper SiN layer 177A and the lower SiN layer 177B may each have corresponding RI characteristics; for example, the upper SiN layer 177A may have a lower RI than the lower SiN layer 177B, but this is not required. Regardless of whether a double-layer arrangement is provided, the SiN layer 177 can have an overall target thickness of, for example, about 500 nm to 800 nm, depending on the HV application. Similar to the formation of the SiON layer 174, various techniques and processes can be used to form SiN layers 177A and 177B that can be appropriately varied or modulated to achieve desired characteristics.

[0067] exist Figure 2N-1 In this configuration, a via 183 is formed through the remaining portions of the composite SiON / SiN layers 174 / 177 and the dielectric layers 171 / 168. In alternative and / or additional arrangements, one or more conductive pillars 195B having a height 194B and a width 198B can be fabricated using a via mask layer and metallurgical methods to create the via 183, thereby obtaining… Figure 2N-2 The structure formed by the parts shown represents Figure 1A-3 The arrangement, in some instances as previously mentioned, allows the bottom of the conductive post 195B to extend through the interface between 171 and 168.

[0068] As previously described, in the exemplary arrangement, the composite SiON / SiN layers 174 / 177 can be used as ILD4. Through-holes 183 (e.g., tungsten) extending through ILD4 are operable to connect the MET4 structure 165 to the upper MET5 structure 187, which can be formed at a subsequent stage. Figure 2O-1The text describes the manufacturing stages of the top plate 105, which is part of the MET5 process and may include the formation of the MET5 structure 187. In some optional instances, one or more isolation breaks or cuts 180 may be formed in the ILD4 after the top plate 105 is formed. Figure 2O-1 (Not specifically shown in the text) to further improve the lateral HV breakdown performance of device 100, as previously mentioned.

[0069] although Figure 2O-1 The structure shown in the figure forms a partial representation of the structure. Figure 1A-1 The arrangement, but Figure 2O-2 Described in the manufacturing process as described in the reference above Figure 2N-2 The description of the conductive post 195B and subsequent representations Figure 1A-3 The structure formed by the arrangement of the parts. Therefore, Figure 2O-2 The formation of the top plate 105 causes the conductive post 195B to touch the bottom surface 192 of the top plate 105.

[0070] Figure 2P The optional cutout 180 is depicted as having been formed during the manufacturing stage of ILD4 in device 100. Furthermore, as an illustrative example, Figure 2P The arrangement depicts all three types of conductive pillars, such as plate-coupled pillars 195A, 195B, and floating pillar 195C, but in certain embodiments, any combination of pillars 195A to 195C may be provided. Additionally, in some instances, pillars 195A and 195B may be positioned closer to the edges of the respective capacitor plates 104 and / or 105, as illustrated elsewhere in this disclosure. In some arrangements, an optional notch 180 formed in the ILD4 is operable to limit the dielectric breakdown path between the top plate 105 and the guard ring 109. After the top plate 105 is formed and the notch 180 is optionally formed, an HDP oxide layer 190 is formed over the top plate 105 and fills the notch 180, as shown below. Figure 2P As shown in [the document]. Figure 2Q In this configuration, a TEOS layer 193 has been formed and planarized over an HDP oxide layer 190, and a PO layer 196 has been formed over the TEOS layer 193. In some instances, the PO layer 196 may have a compressive stress of approximately -160 MPa to approximately -180 MPa, but is not limited thereto. Wire bonding openings (e.g., opening 199) can be formed over the top plate 105 using suitable patterning techniques for connection to the bonding wires, thereby obtaining respectively... Figures 1A-1 to 1A-3 The device arrangement described in the document.

[0071] The foregoing description of the exemplary 5LM process sequence for manufacturing conductive pillars is not limited to metal and / or dielectric layers of any particular thickness. Additionally, a similar process sequence for manufacturing conductive pillars can be provided in conjunction with any multilayer metal interconnect system having any number of metallization levels (e.g., 6 to 12 MET levels or more), wherein the conductive pillars can be positioned at different levels to guide discharge between the top / electrode and bottom / electrode of the isolation device in the event of dielectric breakdown.

[0072] Figure 3A and 3B This is a flowchart of an IC manufacturing method according to some examples of this disclosure. In one arrangement, Figure 3A The method 300A shown may begin by forming a bottom metal plate of an isolation component (e.g., a capacitor) above a semiconductor substrate, as illustrated in block 302. Depending on the BEOL embodiment, the bottom electrode may be a lower-level metal layer (e.g., a multilayer metal interconnect (MMI) constructed above the semiconductor substrate). Figure 2F The MET2 layer shown is formed as previously described. At frame 304, one or more conductive pillars may be formed above the base plate, which involve... Figures 2I to 2N-2 Some of the aspects shown herein. At frame 306, a top metal plate for the capacitor may be formed above the conductive post, wherein the conductive post extends or is otherwise positioned between the base plate and the top plate, which relates to... Figure 2O-1 and 2O-2 Some aspects are shown in the diagram. As previously explained, the conductive pillars can be configured in many ways, such as contacting the bottom and / or top metal plates, not connected to any interconnect structure of the MMI construction, etc., wherein the conductive pillars are operable or otherwise configured to guide the discharge between the top and bottom metal plates through the dielectric stack formed between the top and bottom metal plates.

[0073] Figure 3BMethod 300B shown may begin by forming the bottom electrode of an isolation component (e.g., a capacitor) over a semiconductor substrate, the bottom electrode being formed from a lower-level metal layer of an MMI structure over the semiconductor substrate as illustrated in box 320, which is generally similar to box 302 above. At box 322, one or more dielectric layers of a dielectric stack may be formed over the bottom electrode, wherein the one or more dielectric layers include corresponding IMD / ILD layers associated with the MMI structure. In some arrangements, one or more conductive pillars are formed in an inter-layer via forming step, wherein the conductive pillars are operable or otherwise configured to guide a fault path between the top and bottom electrodes of the isolation component, as further illustrated in box 322. In one example, the conductive pillars may directly contact the top surface of the bottom electrode. In one example, the conductive pillars are electrically isolated from any interconnect structure of the MMI structure (e.g., configured as floating pillars). After completing the formation of the dielectric stack including the conductive pillars over the bottom electrode, the top electrode of the isolation component may be formed from the topmost metal layer of the MMI structure, as illustrated in box 324. In one exemplary arrangement, the bottom surface of the top electrode may be in direct contact with the conductive post, as previously mentioned.

[0074] The following describes an exemplary application in the context of a packaging device implementation, wherein an IC die includes capacitive isolation associated with conductor pillars used for guiding a discharge path.

[0075] Figure 4 This is a partial cross-sectional view of an IC package 400 according to some examples. The IC package 400 includes a first IC die 402 and a second IC die 404, wherein the first IC die 402 and the second IC die 404 are attached to a lead frame portion 406, for example, by an adhesive. A molding compound 410 encapsulates the first IC die 402 and the second IC die 404 on the lead frame portion 406, thereby forming the body of the IC package 400.

[0076] The first IC die 402 includes a semiconductor substrate 420 and a metallization structure 422 above the semiconductor substrate 420. In some embodiments, the IC die 402 may represent Figures 1A-1 to 1A-3The semiconductor device 100 shown is illustrated in the figure. The semiconductor substrate 420 may include any semiconductor material and may contain bulk material (e.g., bulk silicon) and one or more epitaxial layers of the semiconductor material. The metallization structure 422 may include the previously mentioned multiple ILD layers and metal levels. The metallization structure 422 of the first IC die 402 includes a capacitor 424, which may be a current-isolation capacitor. The capacitor 424 includes a capacitor base plate 425B disposed in one metallization layer and a capacitor top plate 425A disposed in another metallization layer. The capacitor base plate 425B is electrically connected to a circuit 426 in the first IC die 402. The circuit 426 is on, above, and / or therein of the semiconductor substrate 420 and may include means disposed on, above, and / or therein of the semiconductor substrate 420. The circuit 426 may include electrical connections, such as electrical connections achieved through metal contacts, metal wires, and / or metal vias in the metallization structure 422. The cross-sectional portion 428 of the first IC die 402 is typically in… Figure 4 The identification can be achieved by, as previously mentioned Figures 1A-1 to 1A-3 Any of the cross-sectional views shown are represented.

[0077] Similarly, the second IC die 404 includes a semiconductor substrate 430 and a metallization structure 432 above the semiconductor substrate 430. The semiconductor substrate 430 may include any semiconductor material and may include bulk material (e.g., bulk silicon) and one or more epitaxial layers of the semiconductor material. The metallization structure 432 may include multiple ILD layers and metallization levels, which may be the same as or different from the ILD layers and metallization levels of the first IC die 402.

[0078] like Figure 4 As described, the metallization structure 432 of the second IC die 404 may include bonding pads 434 in the uppermost metallization layer. The second IC die 404 includes circuitry 436 on, above, and / or within the semiconductor substrate 430. The bonding pads 434 are electrically connected to the circuitry 436, which may include one or more devices disposed on, above, and / or within the semiconductor substrate 430. Similar to IC device 402, IC device 404 may include electrical connections, such as those achieved through metal contacts, metal wires, and / or metal vias in the metallization structure 432.

[0079] The capacitor top plate 425A of the first IC die 402 is bonded to line 440, and thus, the capacitor top plate 425A can further serve as a bonding pad. The bonding line 440 is further bonded to the bonding pad 434 of the second IC die 404. Therefore, the capacitor 424 is electrically coupled between circuit 426 in the first IC die 402 and circuit 436 in the second IC die 404 (via line 440 and bonding pad 434). The capacitor 424 can be configured as a DC isolator between circuit 426 in the first IC die 402 and circuit 436 in the second IC die 404. Therefore, the capacitor 424 can provide a degree of current isolation between circuit 426 in the first IC die 402 and circuit 436 in the second IC die 404.

[0080] Typically, a signal path is positioned between circuitry 426 in the first IC die 402 and circuitry 436 in the second IC die 404. This signal path includes a capacitor 424, bonding wires 440, and bonding pads 434. In some instances, the second IC die 404 does not include a current-isolation capacitor in the signal path between circuits 426 and 436. In such instances, the capacitor 424 of the first IC die 402 may need to be particularly robust in high electric fields, which could induce lateral failure modes through discharge paths in the polyimide / molding material. As previously mentioned, polyimide and molding materials have less robust breakdown characteristics than inorganic dielectrics (e.g., SiO2) and can lead to unpredictable and uncontrolled lateral failure modes in high electric fields. In the presence of the conductive pillars of this disclosure, the high electric field encountered by the signal path of capacitor 424 (e.g., which may be approximately kV / m or MV / m or higher) may create a discharge path between the top plate 425A and the bottom plate 425B via DTI, which is more tightly controlled. Therefore, the overall reliability of the packaged device can be improved, for example, resulting in a reduction in early-life failures. Furthermore, because the breakdown characteristics of the inter-plate dielectric layer are better characterized, more reliable time-dependent dielectric breakdown (TDDB) and lifetime estimates, as well as operating voltage predictions, can be obtained in various HV application scenarios.

[0081] Continue to refer to Figure 4The first IC die 402 and the second IC die 404 may include other bonding pads (e.g., bonding pads 450, 452), to which lines (e.g., lines 454, 456) may be bonded. Although not specifically stated, some lines may be further bonded to leads of the leadframe portion 406, which, for a given application environment, provide external electrical connectors outside the IC package 200. Additionally, depending on the application, the IC package 400 may be implemented in various package types, such as dual in-line package (DIP), small integrated circuit (SOIC) package, quad flat package (QFP), small package (SOP), ball grid array (BGA) package, chip-scale package (CSP), and / or similar.

[0082] Figures 5A to 5C A plan view of a metal plate 502 depicting a current isolation assembly having multiple conductive pillars that can operate as discharge path conductors, according to some embodiments of the present disclosure. In one embodiment, the metal plate 502 represents a capacitor (e.g., Figures 1A-1 to 1A-3 The top plate of the capacitor 102 shown is illustrated, with the bottom surface 505 of the metal plate 502 shown in the plan view. In another example, the metal plate 502 represents a capacitor (e.g., Figures 1A-1 to 1A-3 The base plate of the capacitor 102 shown is illustrated, with the top surface 505 of the metal plate 502 shown in the plan view. Figure 5A In one exemplary arrangement 500A shown, a plurality of conductive posts 506A to 506D are arranged in a 2×2 grid 507, having a geometric center 509 aligned with the geometric center 504 of the metal plate 502. The geometric center 504 can be considered the centroid of the grid 507. The centroid of the grid 507 and similar grids is defined as the arithmetic mean position of all conductive posts in the grid as measured from the center of the posts. Figure 5B In another exemplary arrangement 500B shown, the grid 507 is spaced apart from the geometric center 504 of the metal plate 502 (e.g., laterally translated) such that the geometric center 509 of the grid 507 is located at a distance δ1 from the geometric center 504 of the metal plate 502. In such an arrangement, the grid center 509 may be closer to the edge 503 of the metal plate 502, for example, having a distance δ2 from the edge 503, where δ1 > δ2. In some arrangements, grids spaced apart from the center of the metal plate may be more efficient in achieving appropriate breakdown characteristics. Therefore, in some instances, distances δ1 and / or δ2 may be configured relative to the surface 505 in various arrangements and combinations to optimize and / or customize the directionality of the discharge path and the HV breakdown performance of the capacitor for a particular application. Figure 5CIn another arrangement 500C shown, a plurality of conductive posts 511 may be arranged in a curved manner on the plate surface 505, wherein the posts 511 are close to the edge 503 of the metal plate 502, for example, at a certain distance therefrom. In some instances, the posts 511 may be located at different distances (e.g., distances 513, 515, 517, 519) from the corresponding side of the edge 503. In yet other arrangements, the conductive posts 511 may be arranged in various spatial configurations relative to the edge 503 and / or the plate center 504, as previously described.

[0083] Although various examples of this disclosure have been described above, these examples are presented by way of illustration only and not limitation. Many changes may be made to the disclosed examples in accordance with the disclosure herein without departing from the spirit or scope of this disclosure. Therefore, the breadth and scope of this disclosure should not be limited to any of the examples described above. In fact, the scope of this disclosure should be defined by the appended claims and their equivalents.

[0084] For example, in this disclosure and the appended claims, unless otherwise stated and / or specified to the contrary, any one or more of the layers set forth herein may be formed in any number of suitable manners, such as using spin coating, sputtering (e.g., magnetron and / or ion beam sputtering), (thermal) growth techniques, or deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), PECVD, or atomic layer deposition (ALD). As another example, silicon nitride may be silicon-rich silicon nitride or silicon oxynitride. Silicon nitride may contain some oxygen, but not so much as to make the dielectric constant of the material significantly different from that of high-purity silicon nitride.

[0085] Additionally, in at least some additional or alternative embodiments, the functions / actions described in the boxes may not occur in the order shown in the flowchart. For example, depending on the functionality / action involved, two boxes shown consecutively may actually be executed substantially simultaneously, or the boxes may sometimes be executed in reverse order. Furthermore, the functionality of a given box in a flowchart and / or block diagram may be divided into multiple boxes, and / or the functionality of two or more boxes in a flowchart and / or block diagram may be at least partially integrated. Also, some boxes in the flowchart may optionally be omitted. Furthermore, although some diagrams include arrows on communication paths to show the main direction of communication, it should be understood that communication may occur in the opposite direction to the depicted arrows. Finally, additional boxes may be added / inserted between the illustrated boxes.

[0086] The order or sequence of actions, steps, functions, components, or blocks illustrated in any of the flowcharts and / or block diagrams depicted in the accompanying drawings of this disclosure may be modified, altered, replaced, customized, or otherwise rearranged within a particular flowchart or block diagram, including the deletion or omission of specific actions, steps, functions, components, or blocks. Furthermore, actions, steps, functions, components, or blocks illustrated in a particular flowchart may be mixed with or otherwise arranged or rearranged with actions, steps, functions, components, or blocks illustrated in another flowchart to allow for additional changes, modifications, and configurations relative to one or more processes for the purpose of practicing the teachings of this disclosure. Similarly, while various examples have been set forth herein, not all features of a particular example are necessarily limited to and / or necessary for this purpose.

[0087] At least some of the foregoing description may contain specific directional terms, such as “upper,” “lower,” “top,” “bottom,” “left,” “right,” “front,” “rear,” “vertical,” “horizontal,” etc., which may be used with reference to the orientation of some of the described figures or their illustrative elements. Since components in some instances may be positioned in multiple different orientations, directional terms are used for illustrative purposes and are by no means limiting. Similarly, references to features referred to as “first,” “second,” etc., do not indicate any particular order, importance, etc., and such references are interchangeable depending on the context, implementation, etc. Furthermore, terms such as “above,” “below,” “under,” etc., relative to the spatial orientation of two components do not necessarily mean that one component is adjacent to or directly above another component, or that one component is adjacent to or directly below another component. Additionally, unless specifically mentioned otherwise, features and / or components of the instances described herein may be combined with each other.

[0088] Although various embodiments have been shown and described in detail, the claims are not limited to any particular embodiment or example. The specific embodiments described above should not be construed as implying that any particular component, element, step, action, or function is essential and necessarily included within the scope of the claims. In the context of phrases such as "at least one of A and B" or similar expressions, such phrases should be understood to mean "only A, only B, or both A and B." Unless explicitly stated otherwise, references to singular elements are not intended to mean "one and only one," but rather "one or more." Similarly, depending on the context, phrases such as "a plurality" or "multiple" may mean "one or more" or "at least one." All structural and functional equivalents of the elements of the embodiments described above are expressly incorporated herein by reference and are intended to be covered by the appended claims.

Claims

1. An integrated circuit IC, comprising: Semiconductor substrate; A capacitor base plate, which is located above the semiconductor substrate; A capacitor top plate, located above the capacitor bottom plate; as well as A conductive post extends between the base plate and the top plate.

2. The IC according to claim 1, wherein the conductive post touches the top surface of the base plate.

3. The IC according to claim 2, wherein the conductive pillar is one of a plurality of conductive pillars arranged in a grid, the grid having a center aligned with the center of the base plate.

4. The IC of claim 2, wherein the conductive pillar is one of a plurality of conductive pillars arranged in a grid having a center laterally translated away from the center of the base plate.

5. The IC according to claim 1, wherein the conductive post touches the bottom surface of the top plate.

6. The IC of claim 5, wherein the conductive pillar is one of a plurality of conductive pillars arranged in a grid, the grid having a center aligned with the center of the top plate.

7. The IC of claim 1, wherein the conductive pillar is one of a plurality of conductive pillars arranged in a grid, the grid having a center aligned with the center of the top plate.

8. The IC according to claim 1, wherein the conductive pillar is one of a plurality of conductive pillars formed in an interlayer dielectric layer and electrically isolated from both the top plate and the bottom plate.

9. The IC of claim 1, wherein the conductive pillar is a metal pillar having a height in the range of about 2 μm to about 4 μm and a width in the range of about 0.5 μm to about 1.5 μm.

10. The IC of claim 1, wherein the conductive pillars are configured to guide a discharge path between the top plate and the bottom plate through the dielectric stack.

11. An integrated circuit (IC) package, comprising: The first IC die includes: A capacitor comprising a bottom capacitor plate above a first semiconductor substrate, a top capacitor plate above the bottom capacitor plate, and a conductive post between the bottom capacitor plate and the top capacitor plate. A second IC die, comprising circuitry above or extending into the second semiconductor substrate; and Wire bonding connects the top capacitor plate to the circuit.

12. The IC package of claim 11, wherein the conductive post is connected to the top surface of the bottom capacitor plate or the bottom surface of the top capacitor plate.

13. The IC package of claim 12, wherein the conductive pillar is one of a plurality of conductive pillars arranged in a grid, the grid having a center aligned with the center of at least one of the bottom capacitor plate and the top capacitor plate.

14. The IC package of claim 12, wherein the conductive pillar is one of a plurality of conductive pillars arranged in a grid, the grid having a center laterally translated from the center of at least one of the bottom capacitor plate and the top capacitor plate.

15. The IC package of claim 11, wherein the conductive pillar is one of a plurality of conductive pillars formed in an interlayer dielectric layer and electrically isolated from both the top capacitor plate and the bottom capacitor plate.

16. The IC package of claim 11, wherein the conductive pillars are configured to guide a discharge path between the top capacitor plate and the bottom capacitor plate through the dielectric stack.

17. A method for manufacturing an integrated circuit (IC), comprising: A metal base plate for the capacitor is formed above a semiconductor substrate; A conductive pillar is formed above the base plate; as well as A metal top plate of the capacitor is formed above the conductive post, wherein the conductive post extends between the bottom plate and the top plate.

18. The method of claim 17, wherein the conductive post contacts the top surface of the base plate.

19. The method of claim 18, wherein the conductive post is one of a plurality of conductive posts arranged in a grid having a center aligned with the center of the base plate.

20. The method of claim 18, wherein the conductive post is one of a plurality of conductive posts arranged in a grid having a center laterally translated from the center of the base plate.

21. The method of claim 17, wherein the conductive post touches the bottom surface of the top plate.

22. The method of claim 17, wherein the conductive post is one of a plurality of conductive posts arranged in a grid, the grid having a center aligned with the center of the top plate.

23. The method of claim 17, wherein the conductive pillar is one of a plurality of conductive pillars formed in an interlayer dielectric layer and electrically isolated from both the top plate and the bottom plate.

24. The method of claim 17, wherein the conductive pillar is configured to guide a discharge path between the top plate and the bottom plate through the dielectric stack.

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