System and method for implementing temperature compensation in memory device

Abstract

A method of operating a memory cell includes programming the memory cell at a first temperature to a different program state associated with a first read current value confirmed by using a nominal read condition. A modified read condition is determined such that the second read current of the one memory cell at the second temperature is substantially equal to the first read current value of the one memory cell. A read operation is performed on the memory cells using the modified read condition at a second temperature to determine a corresponding third read current value. The error read current value is determined as a respective difference between the first read current value and the third read current value. The higher program state and the lower program state are assigned to respective desired program states, where the read current substantially corresponds to the respective determined error read current value and is substantially separated by a respective target read current value associated with the respective desired program state.

Description

[0001] Related applications

[0002] This application claims the benefit of U.S. Patent Application No. 18 / 367,921, filed on September 13, 2023. Technical Field

[0003] This invention relates to non-volatile memory arrays. Background Technology

[0004] Memory devices having split-gate nonvolatile memory cells and such cell arrays are well known. For example, U.S. Patent 5,029,130 ​​('130 patent) discloses a split-gate nonvolatile memory cell array. The memory cells are... Figure 1 As shown in the figure. Each memory cell 10 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 therebetween. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and is formed over a portion of the drain region 16. A control gate 22 (also referred to as a word line gate or select gate) has a first portion 22b and a second portion 22c, the first portion being disposed over and insulated from (and controlling the conductivity of) the second portion of the channel region 18, the second portion of the control gate extending upward along the floating gate 20 and over the floating gate. The floating gate 20 and the control gate 22 are insulated from the substrate 12 by a gate oxide 26.

[0005] By applying a high positive voltage to the control gate 22, the memory cell is erased (electrons are removed from the floating gate), causing electrons on the floating gate 20 to tunnel from the floating gate 20 through the intermediate insulator 24 (e.g., tunneling oxide) to the control gate 22 via the Fowler-Nordheim tunneling effect.

[0006] Memory cells are programmed by applying a positive voltage to the control gate 22 and a positive voltage to the drain 16 (where electrons are placed on the floating gate). An electron current flows from the source 14 to the drain 16. When electrons reach the gap between the control gate 22 and the floating gate 20, they accelerate and become hot. Due to electrostatic attraction from the floating gate 20, some of the heated electrons are injected onto the floating gate 20 through the gate oxide 26.

[0007] A memory cell is read by applying a positive read voltage to the drain 16 and the control gate 22 (which turns on the channel region below the control gate). If the floating gate 20 is positively charged (i.e., electrons are erased and positively coupled to the drain 16), the portion of the channel region below the floating gate 20 is also turned on, and current flows through the channel region 18, which is sensed as an erased state or a "1" state. If the floating gate 20 is negatively charged (i.e., programmed electronically), the portion of the channel region below the floating gate 20 is mostly or completely turned off, and no current (or very little current) flows through the channel region 18, which is sensed as a programmed state or a "0" state.

[0008] exist Figure 2 The diagram illustrates the architecture of the memory array. Memory cells 10 are arranged in rows and columns. In each column, the memory cells are arranged end-to-end in a mirror manner, such that they form pairs of memory cells, each pair sharing a common source region 14(S), and each adjacent pair of memory cells sharing a common drain region 16(D). All source regions 14(S) of any given row of memory cells are electrically connected together via source lines 14a. Optionally, a set of source lines 14a or all source lines 14a in the memory array can be electrically connected together via a common source line 14b. All drain regions 16(D) of any given column of memory cells are electrically connected together via bit lines 16a. All control gates 22 of any given row of memory cells are electrically connected together via control gate lines 22a (also called word lines or select gate lines). Thus, although memory cells can be programmed and read individually, memory cell erasure is performed row by row (each row of memory cells is erased together by applying a high voltage to the control gate lines 22a). The row and column decoders decode the input row and column addresses and provide appropriate voltages to control gate line 22a and bit line 16a, respectively. The sense amplifier senses the voltage or current on the bit lines during the read operation.

[0009] Those skilled in the art will understand that the source and drain can be interchanged, wherein the floating gate may extend partially over the source rather than the drain, such as... Figure 3 As shown. Figure 4The corresponding memory cell architecture is best illustrated, including memory cell 10, source line 14a, bit line 16a, and control gate line 22a. As can be clearly seen from the figures, memory cells 10 in the same row share the same source line 14a and the same control gate line 22a, while the drains of all cells in the same column are electrically connected to the same bit line 16a. The array design allows for individual programming of selected cells, for example, by applying 1.6V and 7.6V to the selected control gate line 22a and source line 14a respectively, and grounding the selected bit line 16a. Interference with unselected memory cells in the same pair is avoided by applying a voltage greater than 2V to the unselected bit line 16a and grounding the remaining lines.

[0010] Split-gate memory cells with more than two gates are also known. For example, a memory cell has a source region 14, a drain region 16, a floating gate 20 on a first portion of a channel region 18, a control gate 22 on a second portion of the channel region 18, a coupling gate 28 above the floating gate 20, and an erase gate 30 above the source region 14, as shown below. Figure 5 As shown. It should be noted that the coupling gate is sometimes referred to as the control gate, but for clarity (and thus to distinguish it from the control gate 22 used to control a portion of the channel region 18), it will be referred to herein simply as the coupling gate. Programming is illustrated by heated electrons from the channel region 18, which inject themselves onto the floating gate 20. Erasure is illustrated by the tunneling of electrons from the floating gate 20 to the erase gate 30, achieved by applying a high positive voltage to the erase gate 30.

[0011] The architecture of a quad-gate memory cell array can be as follows: Figure 6 The configuration is shown below. In this embodiment, each horizontal control gate line 22a electrically connects all control gates 22 of the row memory cell together. Each horizontal coupling gate line 28a electrically connects all coupling gates 28 of the row memory cell together. Each horizontal source line 14a electrically connects all source regions 14 of the two rows of memory cells sharing a source region 14 together. Each bit line 16a electrically connects all drain regions 16 of the column memory cell together. Each erase gate line 30a electrically connects all erase gates 30 of the two rows of memory cells sharing an erase gate 30 together. As with the previous architecture, individual memory cells can be programmed and read independently. Erasing is performed by applying a high positive voltage to the erase gate line 30a, which results in the simultaneous erasure of two rows of memory cells sharing the same erase gate line 30a. Exemplary operating voltages may include those in Table 1 below, where the selected lines (selected) are those that include the target memory cell, and the unselected lines (not selected) are the remaining lines that do not include the target memory cell:

[0012] Split-gate nonvolatile memory cells with three conductive gates and arrays of such cells are also known. For example, U.S. Patent 7,315,056 ('056 patent) discloses an array of split-gate nonvolatile memory cells. The memory cells are... Figure 7 As shown in the figure. Each memory cell 10 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 therebetween. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and is formed over a portion of the source region 14. A control gate 22 has a first portion 22b and a second portion 22c, the first portion being disposed over and insulated from (and controlling the conductivity of) the second portion of the channel region 18, the second portion of the control gate extending upward along the floating gate 20 and over the floating gate. A programmable / erase gate 32 has a first portion 32a disposed over the source region 14 and laterally adjacent to the floating gate 20, and a second portion 32b extending upward and over the floating gate 20.

[0013] By applying a high positive voltage to the program / erase gate 32, the memory cell is erased (electrons are removed from the floating gate), causing electrons on the floating gate 20 to tunnel from the floating gate 20 through the intermediate insulator to the program / erase gate 32 via the Fowler-Nordheim tunneling effect.

[0014] Memory cells are programmed by applying a positive voltage to the control gate 22, a positive voltage to the source region 14, and a positive voltage to the program / erase gate 32 (where electrons are placed on the floating gate). Electron current flows from the drain 16 to the source 14. When electrons reach the gap between the control gate 22 and the floating gate 20, they accelerate and become heated. Due to electrostatic attraction from the floating gate 20, some of the heated electrons are injected onto the floating gate 20 through the gate oxide.

[0015] A memory cell is read by applying a positive read voltage to the drain 16 and the control gate 22 (which turns on the channel region 18 below the control gate 22). If the floating gate 20 is positively charged (i.e., electrons are erased and positively coupled to the source 14), the portion of the channel region 18 below the floating gate 20 is also turned on, and current flows through the channel region 18, which is sensed as an erased state or a "1" state. If the floating gate 20 is negatively charged (i.e., programmed by electrons), the portion of the channel region below the floating gate 20 is mostly or completely turned off, and no current (or very little current) flows through the channel region 18, which is sensed as a programmed state or a "0" state.

[0016] Example operating voltage could be:

[0017] exist Figure 8 The diagram illustrates the architecture of the memory array. Memory cells 10 are arranged in rows and columns. In each column, the memory cells are arranged end-to-end in a mirror manner, such that they form a pair of memory cells each sharing a common source region 14, and each adjacent pair of memory cells shares a common drain region 16. All source regions 14 of any given row of memory cells are electrically connected together via source line 14a. All drain regions 16 of any given column of memory cells are electrically connected together via bit line 16a. All control gates 22 of any given row of memory cells are electrically connected together via control gate line 22a. All program / erase gates 32 of any given row of memory cells are electrically connected together via program / erase gate line 32a. Thus, although memory cells can be programmed and read individually, memory cell erasure is performed by pairs of rows (each pair of memory cell rows sharing the program / erase gate 32 is erased together by applying a high voltage to the program / erase gate line 32a).

[0018] Recently, new applications for split-gate nonvolatile memory cells have been developed, requiring each memory cell to be programmed to a specific value (including analog values) for multi-bit storage or analog signal storage. Specifically, analog signal storage involves programming the memory cell anywhere along a continuous spectrum extending from fully erased to fully programmed programming states. Programming is performed by programming the memory cell using one or more short programming voltage pulses, followed by a programming verification operation to confirm the programming state of the memory cell. If the cell is not sufficiently programmed, one or more additional programming pulses are applied. This continues until the programming verification operation confirms that the cell has reached the desired programming state. The programming state corresponds to the number of electrons programmed onto the floating gate. A memory cell in its fully erased state has the lowest possible programming state and will provide the highest read current during read operations. The higher the programming state of the memory cell (i.e., the more electrons programmed onto the floating gate 20), the lower the read current generated during read operations.

[0019] The memory cell read current (i.e., the current flowing through the channel region during a read operation) can be adversely affected by the memory cell's operating temperature. Specifically, if a memory cell is programmed at a relatively low temperature (e.g., approximately 30 degrees Celsius), its expected read current is confirmed at an operating temperature of 30 degrees Celsius. However, if a read operation is later performed on the memory cell at a temperature closer to its maximum rated operating temperature (e.g., approximately 85 degrees Celsius), the read current may differ (i.e., the read current of a memory cell programmed to a given programmed state can increase as the operating temperature rises). This increase in read current can be problematic for applications where the memory cell is used for analog signal storage, where the accuracy of the read operation is critical.

[0020] A memory cell device is needed that provides compensation for the adverse effects of changes in operating temperature. Summary of the Invention

[0021] The aforementioned problems and requirements are addressed by a method of operating multiple memory cells, the method comprising: programming a corresponding memory cell among the multiple memory cells to one of a plurality of different programming states when at a first temperature, wherein the corresponding programming state among the different programming states is associated with a corresponding first read current value, the first read current value being confirmed by performing a first read operation using nominal read conditions; determining modified read conditions using a second read operation for at least one memory cell among the memory cells when at a second temperature different from the first temperature, such that a second read current of a memory cell using the modified read conditions in the second read operation is approximately equal to the first read current value of a memory cell using the nominal read conditions in the first read operation; performing a third read operation on the corresponding memory cell among the memory cells using the modified read conditions when at the second temperature to determine a corresponding third read current value of the memory cell; determining an error read current value of the corresponding memory cell among the memory cells, the error read current value being a corresponding difference between the first read current value and the third read current value; and assigning a higher programming state and a lower programming state to a desired programming state among a plurality of desired programming states. The read current value used for the assigned higher programming state and the read current value used for the assigned lower programming state roughly correspond to one of the determined error read current values ​​and are roughly separated by the target read current value associated with the desired programming state.

[0022] The memory device includes a plurality of memory cells and circuitry. The circuitry is configured to: program a corresponding memory cell among the plurality of memory cells to one of a plurality of different programming states when at a first temperature, wherein the corresponding programming state among the different programming states is associated with a corresponding first read current value, the first read current value being determined by a first read operation using nominal read conditions; determine modified read conditions using a second read operation for at least one memory cell among the memory cells when at a second temperature different from the first temperature, such that a second read current of a memory cell using the modified read conditions in the second read operation is approximately equal to the first read current value of a memory cell using the nominal read conditions in the first read operation; perform a third read operation on the corresponding memory cell among the memory cells using the modified read conditions when at the second temperature to determine a corresponding third read current value of the memory cell; determine an error read current value of the corresponding memory cell among the memory cells, the error read current value being a corresponding difference between the first read current value and the third read current value; and assign a higher programming state and a lower programming state to a desired programming state among a plurality of desired programming states. The read current value used for the assigned higher programming state and the read current value used for the assigned lower programming state roughly correspond to one of the determined error read current values ​​and are roughly separated by the target read current value associated with the desired programming state.

[0023] Other objects and features of the invention will become apparent from a review of the specification, claims and drawings. Attached Figure Description

[0024] Figure 1 This is a side cross-sectional view of a conventional 2-gate nonvolatile memory cell.

[0025] Figure 2 It is by Figure 1 A schematic diagram of an array formed by two gate non-volatile memory cells.

[0026] Figure 3 This is a side cross-sectional view of another conventional pair of 2-gate nonvolatile memory cells.

[0027] Figure 4 It is by Figure 3 A schematic diagram of an array formed by two gate non-volatile memory cells.

[0028] Figure 5 This is a side cross-sectional view of a conventional 4-gate non-volatile memory cell.

[0029] Figure 6 It is by Figure 5A schematic diagram of an array formed by 4 gate non-volatile memory cells.

[0030] Figure 7 This is a side cross-sectional view of a conventional 3-gate non-volatile memory cell.

[0031] Figure 8 It is by Figure 7 A schematic diagram of an array formed by three gate non-volatile memory cells.

[0032] Figure 9 This is a schematic diagram of a supercell connected to a differential sense amplifier.

[0033] Figure 10 This is a schematic diagram of a supercell array connected to a differential sense amplifier.

[0034] Figure 11 This is a schematic diagram of an alternative example of a supercell array.

[0035] Figure 12 This is a schematic diagram of another alternative example of a supercell array.

[0036] Figure 13 This is a diagram illustrating a box used to assign programming state pairs to desired programming states.

[0037] Figure 14 This is a graph showing the error read current value as a function of the first read current value.

[0038] Figure 15 It is a table that shows the higher and lower programming state assignments of the expected programming state.

[0039] Figure 16 It is a graph showing the higher and lower programming state assignments of the desired programming state.

[0040] Figure 17 This is a diagram illustrating a block used to program and read memory cells using programming state pairs assigned to the desired programming state.

[0041] Figure 18 This is a schematic diagram illustrating a reference memory cell. Detailed Implementation

[0042] This paper discloses an architectural configuration and technique for temperature compensation in a memory device with a split-gate nonvolatile memory cell array. The architecture involves memory cell pairs (each pair of memory cells 10A and 10B is collectively referred to as a “supercell” 40), wherein the read current output of the memory cell pair is provided as an input to a differential sense amplifier 42, such as... Figure 9As shown. The output 42a of the differential sensing amplifier 42 is based on the amplitude of the signal (i.e., the read current) at the positive (+) amplifier input minus the amplitude of the signal (i.e., the read current) at the negative (-) amplifier input. The output of unit 10A (i.e., its bit line 16a) is connected to the positive (+) amplifier input, and the output of unit 10B (i.e., its bit line 16a) is connected to the negative (-) amplifier input, so that the amplitude of the signal at the output 42a of the differential sensing amplifier 42 is derived from the amplitude of the signal (read current) generated by unit 10A minus the amplitude of the signal (read current) generated by unit 10B. It should be noted that the differential sensing amplifier 42 preferably amplifies the signals on the bit lines (before or after the subtraction), so they are easier to detect and use. Therefore, the amplitude of the signal on output 42a need not be the actual difference between the signals on bit line 16a, but can have an amplified value based on the difference between the signal amplitudes on bit line 16a (e.g., proportional, relative offset, relative to linear increase, or otherwise derived from, without limitation).

[0043] Instead of storing the programming state in a single memory cell, the adverse effects of changing the operating temperature can be reduced by storing the programming state in supercell 40. For example, if a read current of 4nA is expected from the programming state, cell 10A can be programmed to a higher programming state corresponding to 6nA, and cell 10B can be programmed to a lower programming state corresponding to 2nA. During subsequent read operations of supercell 40, the resulting read current from supercell 40 will be 4nA (6nA minus 2nA, where the subtraction can be performed by differential sense amplifier 42). If programming is performed at room temperature, but subsequent read operations are performed at an elevated operating temperature, the elevated operating temperature can cause an increase in the read current of both cells 10A and 10B, and therefore any increase in the read current of cell 10A can be at least partially offset by any increase in the read current of cell 10B, resulting in a lower overall increase in the read current of supercell 40 due to the temperature increase.

[0044] Figure 10 An example is illustrated of a memory device 1 having an array of supercells 40 operating under the control of a controller 44 (i.e., the controller 44 is circuitry (non-limiting) that controls other circuitry such as row drivers 46 and column drivers 48, which supplies various voltages to various memory array lines (non-limiting) such as word lines WL, bit lines BL, and source lines for reading, programming, and erasing memory cells), wherein each supercell 40 includes a pair of memory cells 10A and 10B. The memory cells are arranged in rows and columns and can be any non-volatile memory cells, such as those described above. Figure 1 , Figure 3 , Figure 5 and Figure 7 The described 2-gate, 3-gate, or 4-gate memory cells use floating gates to control the current flowing through the channel region, including stacked gate memory cells in which the floating gates extend along the entire channel region. The memory array includes word lines WL0-WLn (each connected to a row control gate 22 of a memory cell and to a row driver 46 that provides an operating voltage thereto) and bit lines BL0-BLm (each connected to a column drain region 16 of a memory cell and to a column driver 48 that provides an operating voltage thereto). Specifically, bit lines BL0 and BL1 are connected to the first two columns of memory cells, where the corresponding row of such cells contains a pair of memory cells 10A and 10B forming a supercell 40. Therefore, there is a column of supercells 40 connected to bit lines BL0 and BL1. Differential sense amplifiers 42-1 to 42-p are present, wherein differential sense amplifier 42-1 is connected to bit lines BL0 and BL1 (where bit line BL0 is connected to one input of differential sense amplifier 42-1 (e.g., a positive input), and bit line BL1 is connected to the other input of differential sense amplifier 42-1 (e.g., a negative input)), differential sense amplifier 42-2 is connected to bit lines BL2 and BL3, and so on. By activating the appropriate word line WL and bit line BL, the corresponding supercell 40 can be individually programmed and read. For example, by setting WL0 to the read voltage (while all other word lines remain below the read voltage), the first row of supercells 40 can be read individually by differential sense amplifiers 42-1 to 42-p. Temperature sensor 56 can be included on the chip to measure the temperature of the device during operation, and controller 44 can be configured to provide temperature compensation during any of the programming, reading, and erasing operations.

[0045] Figure 11 An alternative example is illustrated, wherein the memory device 2 includes a bit line multiplexer 50 between the supercell 40 and the differential sense amplifier 42. The multiplexer 50 selectively forwards signals from any two bit lines to one of the differential sense amplifiers. Using a multiplexer allows for fewer differential sense amplifiers than the number of bit line pairs in the array. For example, in… Figure 10 In this context, with m bit lines, there are p differential sense amplifiers, where p is m / 2. However, in... Figure 11 In this array, only two differential sensing amplifiers are used, thus reducing the size, complexity, and cost of the device. Although Figure 11 Two sense amplifiers 42 connected to the multiplexer 50 are shown, but any number of differential sense amplifiers 42 can be used, from a single sense amplifier 42 to up to m / 2 sense amplifiers.

[0046] Figure 12Another alternative example is illustrated, in which the memory device 3 includes a sense amplifier 52 that individually senses and amplifies the bit line voltages during a read operation. The sensed voltages are then provided to a conversion circuit 54, which performs a subtraction of the signal values ​​on the even-numbered bit lines (where the even-numbered bit lines include the 0 bit line) from the signal values ​​on the odd-numbered bit lines to determine the read value of the supercell 40.

[0047] It is known to use supercells and differential sense amplifiers to store programming states to mitigate the problem of overprogramming. See, for example, U.S. Patent 10,586,598, which is incorporated herein for all purposes. However, the inventors have found that the read current error caused by variations in operating temperature varies depending on the programming state. Furthermore, the amount of read current error as a function of operating temperature and programming state is not a linear function that can be efficiently solved using linear approximations. Therefore, a more efficient temperature compensation method has been developed, such as... Figure 13 As shown, as described below.

[0048] In block 1, multiple memory cells are programmed to different programming states when a first temperature is present. The first temperature can be confirmed by temperature sensor 56. The programming operation includes a first read operation using nominal read conditions (i.e., using the nominal voltage used to read the memory cells during normal user operation) to confirm that the desired programming state has been achieved. As a non-limiting example, memory cells can be programmed to programming states corresponding to target read current values ​​in the range of 1nA to 100nA, wherein a first memory cell can be programmed to a first programming state corresponding to a read current value of 1nA, a second memory cell can be programmed to a second programming state corresponding to a read current value of 2nA, and so on, up to a hundredth memory cell can be programmed to a hundredth programming state corresponding to a read current value of 100nA. The first read operation can be used as part of the programming operation to confirm that the desired first read current value has been achieved, and therefore the desired programming state has been achieved. The first read current values ​​confirmed in the first read operation for multiple memory cells can be stored in a table.

[0049] In block 2, multiple memory cells are raised to a second temperature (above the first temperature). The second temperature can be confirmed by temperature sensor 56. During normal user operation, both the first and second temperatures are within a specified operating range of the memory device. In one example, the temperature range between the first and second temperatures covers a wide range of typical memory device operation. A non-limiting example could be that the first temperature is around room temperature, such as 30 degrees Celsius, and the second temperature is around the raised temperature, such as 85 degrees Celsius.

[0050] In block 3, a selected memory cell from the plurality of memory cells programmed in block 1 is used to determine modified read conditions, thereby modifying the read conditions until, using the nominal read conditions of the selected memory cell (still in its programmed state in block 1), the resulting read current value at the second temperature is approximately equal to the corresponding first read current value at the first temperature. This determination is achieved by performing a second read operation on the selected memory cell, wherein the read conditions of the second read operation are modified relative to the nominal read conditions of the first read operation (i.e., one or more of the read voltages are modified relative to their nominal values) until the second read current value of the selected memory cell (during the second read operation using the modified read conditions at the second temperature) is approximately equal to the corresponding first read current value of the selected memory cell (during the first read operation using the nominal read conditions in block 1 at the first temperature). As a non-limiting example, regarding Figure 5 For a quad-gate memory cell, the modified read conditions may include a voltage below its nominal voltage on the coupling gate 28, a voltage below its nominal voltage on the erase gate 30, or both. The desired effect here is to use the modified read conditions to generate a second read current value at a higher second temperature, which matches the first read current value for a first read operation (using the nominal read conditions) at a lower first temperature for the same memory cell (in the same programming state). More than one memory cell from a plurality of memory cells may be selected, wherein the determined modified read conditions are averaged.

[0051] In one example, the memory cell selected for box 3 is the memory cell with the highest programming state relative to the programming states of the other memory cells programmed in box 1. As used herein, the programming state corresponds to the number of electrons programmed onto the floating gate, where more electrons on the floating gate result in a lower programming state and a lower read current value; conversely, fewer electrons on the floating gate result in a higher programming state and a higher read current.

[0052] In box 4, a third read operation is performed on multiple memory cells when the second temperature is reached, using the modified read conditions determined in box 3, to determine a third read current value. The third read current value determined during the third read operation on the multiple memory cells can be stored in a table.

[0053] In block 5, the read current values ​​from blocks 1 and 4 are compared to each other to determine the error read current value for a corresponding memory cell among the plurality of memory cells. Specifically, for a corresponding memory cell among the plurality of memory cells, the read current value from the first read operation (using nominal read conditions) in block 1 is compared with the corresponding read current value for the corresponding memory cell from the third read operation (using modified read conditions determined in block 3) in block 4, where the difference between the two values ​​represents the error read current value. The error read current value can be stored in a table.

[0054] Figure 14 This is a graph illustrating the read current error value as a function of a first read current value, according to one example. In this non-limiting example, block 1 is executed at a first temperature of 30 degrees Celsius for 100 memory cells programmed in increments between 1nA and 100nA, block 2 is executed by raising the temperature to a second temperature of 85 degrees Celsius, block 3 is executed using the memory cell with the highest programming state (i.e., the memory cell programmed to have a read current value of 100nA during the nominal read conditions when at the first temperature), and block 5 is executed using the first read current value and the third read current value, respectively, from blocks 1 and 4. Figure 14 The error read current value reflects an absolute error value with some temperature compensation because the third read current is determined using modified read conditions such that there is no error read current value for the selected memory cell (in this case, the memory cell programmed to a programming state corresponding to the first read current value of 100nA). For this first read current value from a selected memory cell, the third read current value is made the same as in block 3, and therefore this is a first read current value with zero read current error.

[0055] Figure 14 The continuous data curve in the graph can be generated from the error readout current values ​​in box 5, and is used, for example, to fit the error readout current values ​​using a polynomial to generate y=a, representing the error readout current values ​​determined in box 5. n x n +a n-1 x n-1 , +…+ a2x 2 The assignment in box 6 is determined by a polynomial equation of the form + a1x + a0. The polynomial equation can be in the form of a continuous function or a discrete function. The equation can be stored on the chip (by storing the polynomial coefficients).

[0056] As from Figure 14It is evident that the error read current value defines a bell-shaped error function, which initially decreases near a first read current value of 1 nA, increases as the first read current value increases, peaks at approximately 30 nA, then decreases back, and finally reaches zero at a first read current value of 100 nA. For any given error read current value below the maximum error read current value (at approximately 30 nA of the first read current value), there exist two corresponding first read current values ​​with approximately the same error read current value. For example, as... Figure 14 As shown by the dashed lines, the first read current values ​​of 14nA and 56nA have approximately the same error read current value (e.g., 5nA). Therefore, assigning 56nA and 14nA to the individual cells of the supercell to represent a programming state corresponding to a read current value of 42nA (i.e., 56nA minus 14nA) will result in less temperature-induced error than using other read current values ​​to represent the same read current value of 42nA.

[0057] Once created Figure 14 The error function reflected in the diagram (represented by the error read current values ​​in Block 5 or by polynomial equations representing these values) can be used to assign higher and lower programming state pairs used by the supercell to store each possible or desired programming state. Specifically, in Block 6, for the corresponding programming state in the desired programming state, a higher programming state and a lower programming state are assigned (to the desired programming state of the supercell), where they (1) correspond to approximately the same error read current value, and (2) correspond to read current values ​​that are approximately separated by the target read current value TRCV of the desired programming state (as determined using nominal read conditions) (i.e., the difference between the two read current values ​​is equal to the target read current value TRCV of the desired programming state). Using the example above, a higher programming state corresponding to a read current value of 56 nA and a lower programming state corresponding to a read current value of 14 nA would be assigned to a programming state corresponding to a target read current value TRCV of 42 nA. The assignments in Block 6 can be stored in a table. It has been found that this assignment method results in less temperature-induced error when reading the supercell at different operating temperatures.

[0058] Figures 15 to 16An example of an assignment that can be generated in Box 6 is illustrated, where there are 32 desired programming states (also referred to herein as programming state levels), each with a target read current value TRCV. In this example, the target read current value TRCV of the programming states is separated by 3nA, with the first programming state (level 0) corresponding to a target read current value TRCV of 3nA, the second programming state (level 1) corresponding to a target read current value TRCV of 6nA, and so on, up to the 32nd programming state (level 31) corresponding to a target read current value TRCV of 96nA. Higher programming states have corresponding read current values ​​Icell+ (representing the positive weight w+ of the neural network), lower programming states have corresponding read current values ​​Icell- (representing the negative weight w- of the neural network), and programming states have a target read current value TRCV (representing the final weight w = w+ minus w-). For each assignment from a higher or lower programming state to a given programming state, the difference between the corresponding read current values ​​is equal to the target read current value TRCV of the programming state, and both the higher and lower programming states correspond to approximately the same error read current value determined in Box 5.

[0059] As an alternative example, polynomial fitting can be used to generate a first polynomial equation representing a continuous data curve for all Icell+ values, and a second polynomial equation representing a continuous data curve for all Icell- values. These two polynomial equations can be used to generate the higher and lower programming state assignments in Box 6, instead of using the original data points or approximations of them. The first and second polynomial equations can be in the form of continuous or discrete functions. This is advantageous in situations where data points at some programming state levels may not exist precisely.

[0060] As another alternative example, such as Figure 16As shown, for the corresponding programming state level, a variable common current (Icommon) can exist, centered between the higher programming state read current Icell+ and the lower programming state read current Icell- (i.e., for any level, Icommon = (Icell+ plus Icell-) / 2). The variable common current Icommon can be represented as individual values ​​stored in a table. Alternatively, polynomial fitting can be used to generate a polynomial equation representing a continuous data curve of the variable common current (Icommon). The polynomial equation of Icommon can then be used to generate the higher and lower programming state assignments in Box 6, instead of using the raw data points. For example, for any given programming state level with a given target read current TRCV, the assigned higher programming state read current Icell+ will be equal to Icommon + TRCV / 2, and the lower programming state read current Icell- will be equal to Icommon - TRCV / 2. The polynomial equation Icommon can be in the form of a continuous function or a discrete function.

[0061] Figure 17 A user operation is illustrated, in which the supercell 40 is programmed using user data according to the allocation in block 6, and then the programmed data is read out. Specifically, in order to program the supercell 40 using user data corresponding to the desired programming state (block 7), one memory cell of the supercell 40 is programmed to a higher programming state assigned to the desired programming state (block 8), and another memory cell of the supercell 40 is programmed to a lower programming state assigned to the desired programming state (block 9). Programming may include a read operation using nominal read conditions to confirm that the higher and lower programming states assigned to the desired programming state have been implemented. Then, at a later time (block 10), the user data stored in the supercell 40 is read out in the read operation using nominal read conditions, wherein the difference between the read current values ​​of the memory cell of the supercell programmed to the higher programming state and the memory cell programmed to the lower programming state is determined (e.g., by using differential sense amplifier 42).

[0062] Figure 18Another example is illustrated where a reference memory cell 60, located on the same chip as supercell 40, is used as a selected memory cell in block 3 to determine modified read conditions at a first temperature and a second temperature, instead of using a memory cell in the memory array later used to store user data. Specifically, the reference memory cell 60 may have the same configuration as memory cell 10, but may be located outside the memory array containing memory cell 10 (i.e., having a separate bit line BLR, a separate word line WLR, and separate lines for gates such as control gate 28 and erase gate 30). The reference memory cell 60 may be programmed to a reference programming state when at the first temperature, wherein the reference programming state may be even higher than the programming states of the plurality of memory cells programmed in block 1. The temperature of the reference memory cell 60 is raised to the second temperature, and a second read operation is performed on the reference memory cell 60, wherein the read conditions of the second read operation are modified relative to the nominal read conditions of the first read operation such that the second read current value of the reference memory cell 60 is approximately equal to the corresponding first read current value of the reference memory cell 60. The advantage of using reference memory cell 60 is that its programming state does not need to be changed during operation, and the programming state can be higher than any nominal programming state used to store user data (i.e., reference memory cell 60 can be deeply erased).

[0063] It should be noted that any number of memory cells on a single chip or in a single array can be used for the techniques described above, not just the example of 100 memory cells described above, and certainly not all memory cells on a given chip. It should also be noted that accuracy can be improved, for example, by programming multiple memory cells in Block 1 to each of the different programming states (e.g., 8 or 16 memory cells for each programming state), thereby determining the error read current value for each programming state in Block 5 by averaging the third read current across all memory cells in Block 4 associated with that programming state. Doing so will average out any small cell-to-cell variations. Accuracy can also be improved by performing multiple first read operations on each memory cell and averaging the results in Block 1 to confirm the implementation of different programming states, and by performing multiple third read operations on each memory cell and averaging the results to determine the third read current value in Block 4 for use in determining the error read current value in Block 5.

[0064] The technique can be performed on any given chip design at once by characterizing one or more representative samples and extrapolating to other identical or similar chip designs, or the technique can be applied to each individually manufactured chip. The techniques in blocks 1 and 3 through 10 can be implemented by the circuitry of controller 44.

[0065] It should be understood that the invention is not limited to the examples described above and illustrated herein, but is covered by any and all variations within the scope of any claims. For example, references to the invention herein are not intended to limit the scope of any claims or claim terminology, but only to one or more features that may be covered by one or more of these claims. The examples of materials, processes, and values ​​described above are merely exemplary and should not be considered as limiting the claims. A single layer of material may be formed as multiple layers of such or similar materials, and vice versa. Finally, although the conversion circuit 54 is shown as separate from the sense amplifier 52, the conversion circuit 54 may be incorporated as part of the sense amplifier circuit 52. Alternatively, the conversion circuit 54 may be incorporated as part of the controller 44. Although a supercell is shown as two adjacent memory cells in the same row, a supercell may include two memory cells in different rows. For example, supercell 40 may include memory cells connected to word lines WL0 and BL0 and memory cells connected to word lines WL1 and BL1. In practice, pairing memory cells to form a supercell 40 for bit lines BL0 and BL1 may include pairing any one of the memory cells connected to bit line BL0 with any one of the memory cells connected to bit line BL1.

Claims

1. A method for operating a plurality of memory cells, the method comprising: When the temperature is at the first temperature, the corresponding memory cell in the plurality of memory cells is programmed into one of a plurality of different programming states, wherein the corresponding programming state in the different programming states is associated with a corresponding first read current value, the first read current value being confirmed by performing a first read operation using nominal read conditions; When at a second temperature different from the first temperature, a second read operation is used for at least one of the memory cells to determine a modified read condition, such that the second read current of the memory cell using the modified read condition in the second read operation is approximately equal to the first read current value of the memory cell using the nominal read condition in the first read operation. When the second temperature is reached, the modified read conditions are used to perform a third read operation on the corresponding memory cell in the memory cell to determine the corresponding third read current value of the memory cell; Determine the error read current value of the corresponding memory cell in the memory cell, wherein the error read current value is the corresponding difference between the first read current value and the third read current value; as well as For a given desired programming state among multiple desired programming states, a higher programming state and a lower programming state are assigned to the desired programming state, wherein the read current value for the assigned higher programming state and the read current value for the assigned lower programming state are: This roughly corresponds to one of the determined error read current values, and They are roughly separated by the target read current value associated with the desired programming state.

2. The method according to claim 1, wherein the second temperature is higher than the first temperature.

3. The method according to claim 1, wherein the method comprises: User data corresponding to one of the desired programming states is programmed using the first memory unit and the second memory unit, by programming a first memory unit among the plurality of memory units to the higher programming state assigned to the desired programming state in the programming states and programming a second memory unit among the plurality of memory units to the lower programming state assigned to the desired programming state in the programming states.

4. The method according to claim 3, wherein the method comprises: In the read operation, the user data is read from the first memory cell and the second memory cell through the following operations: The first read current value of the first memory cell is determined using the nominal read conditions. The second read current value of the second memory cell is determined using the nominal read conditions, and Subtract the second read current value from the first read current value.

5. The method of claim 4, wherein the subtraction is performed using a differential sensing amplifier.

6. The method of claim 1, wherein programming a corresponding memory cell among the plurality of memory cells into one of a plurality of different programming states comprises programming the one memory cell used for the second read operation into a programming state that is the highest programming state among the different programming states relative to the other memory cells among the plurality of memory cells.

7. The method according to claim 1, wherein the method comprises: Generate a polynomial equation representing the corresponding difference between the first read current value and the third read current value.

8. The method of claim 7, wherein the allocation of the higher programming state and the lower programming state is performed using the polynomial equation.

9. The method of claim 1, wherein assigning the higher programming state and the lower programming state comprises: Generate a first polynomial equation representing the higher programming state of the plurality of desired programming states; Generate a second polynomial equation representing the lower programming state of the plurality of desired programming states; as well as The first polynomial equation and the second polynomial equation are used to assign the higher programming state and the lower programming state to the desired programming state.

10. The method of claim 1, wherein assigning the higher programming state and the lower programming state comprises: Generate a polynomial equation representing a variable common current, which is centered between the read current value of the higher programming state and the read current value of the lower programming state for the corresponding programming state in the desired programming state; and The polynomial equations are used to assign the higher programming state and the lower programming state to the desired programming state.

11. A memory device, the memory device comprising: Multiple memory units; and The circuit is used for: When the first temperature is reached, the corresponding memory cell among the plurality of memory cells is programmed into one of a plurality of different programming states, wherein the corresponding programming state among the different programming states is associated with a corresponding first read current value, the first read current value being confirmed by a first read operation using nominal read conditions; When at a second temperature different from the first temperature, a second read operation is used for at least one of the memory cells to determine a modified read condition, such that the second read current of the memory cell using the modified read condition in the second read operation is approximately equal to the first read current value of the memory cell using the nominal read condition in the first read operation. When the second temperature is reached, the modified read conditions are used to perform a third read operation on the corresponding memory cell in the memory cell to determine the corresponding third read current value of the memory cell; Determine the error read current value of the corresponding memory cell in the memory cell, wherein the error read current value is the corresponding difference between the first read current value and the third read current value; as well as For a given desired programming state among multiple desired programming states, a higher programming state and a lower programming state are assigned to the desired programming state, wherein the read current value for the assigned higher programming state and the read current value for the assigned lower programming state are: This roughly corresponds to one of the determined error read current values, and They are roughly separated by the target read current value associated with the desired programming state.

12. The memory device of claim 11, wherein the second temperature is higher than the first temperature.

13. The memory device of claim 11, wherein the circuitry is configured to: Programming user data corresponding to one of the desired programming states using a first memory unit and a second memory unit of the plurality of memory units includes programming the first memory unit to the higher programming state assigned to the desired programming state in the programming states and programming the second memory unit to the lower programming state assigned to the desired programming state in the programming states.

14. The memory device of claim 13, wherein the circuitry is configured to: The read operation reads the user data from the first memory cell and the second memory cell, including: The first read current value of the first memory cell is determined using the nominal read conditions. The second read current value of the second memory cell is determined using the nominal read conditions, and Subtract the second read current value from the first read current value.

15. The memory device of claim 14, wherein the memory device comprises: A differential sensing amplifier used to perform the subtraction.

16. The memory device of claim 11, wherein programming a corresponding memory cell among the plurality of memory cells into one of a plurality of different programming states comprises programming the one memory cell used for the second read operation into a programming state in which the different programming states are the highest programming state relative to the other memory cells among the plurality of memory cells.

17. The memory device of claim 11, wherein the circuitry is configured to: Generate a polynomial equation representing the corresponding difference between the first read current value and the third read current value.

18. The memory device of claim 17, wherein the circuitry is configured to: The higher programming state and the lower programming state are assigned using the polynomial equation.

19. The memory device of claim 11, wherein the circuitry for allocating the higher programming state and the lower programming state comprises: Generate a first polynomial equation representing the higher programming state of the plurality of desired programming states; Generate a second polynomial equation representing the lower programming state of the plurality of desired programming states; as well as The first polynomial equation and the second polynomial equation are used to assign the higher programming state and the lower programming state to the desired programming state.

20. The memory device of claim 11, wherein the circuitry for allocating the higher programming state and the lower programming state comprises: Generate a polynomial equation representing a variable common current, which is centered between the read current value of the higher programming state and the read current value of the lower programming state for the corresponding programming state in the desired programming state; and The polynomial equations are used to assign the higher programming state and the lower programming state to the desired programming state.

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