Silicon carbide semiconductor device and method for manufacturing same

Abstract

This silicon carbide semiconductor device is provided with: a semiconductor substrate (SB) comprising 4H-SiC; a collector region (CR) formed within the semiconductor substrate (SB); a contact layer (CL) that is in contact with the collector region (CR) and includes a silicide region (SCR) and a non-silicide region (NSCR); and a collector (CE) that is in contact with the contact layer (CL). Furthermore, a silicide layer (SC) having an upper surface and a lower surface is formed on the silicide region (SCR), a modified layer (AL) comprising 3C-SiC is sandwiched between the upper surface of the silicide layer (SC) and the collector region (CR), and the lower surface of the silicide layer (SC) is in contact with the collector (CE).

Description

Technical Field

[0001] This disclosure relates to silicon carbide semiconductor devices and methods for manufacturing the same, and particularly to IGBTs. Background Technology

[0002] In an IGBT (Insulated Gate Bipolar Transistor), in order to form a low-resistance ohmic electrode for the p-type silicon carbide semiconductor layer, a silicide layer is placed between the collector region and the collector.

[0003] For example, Patent Document 1 discloses an ohmic electrode comprising: an aluminum-containing silicon alloy layer deposited on the back side of a p-type silicon carbide epitaxial layer (the “collector region” mentioned above), and an aluminum-containing titanium alloy layer deposited on the silicon alloy layer.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2016-154174 Summary of the Invention

[0007] The problem that the invention aims to solve

[0008] In Patent Document 1, an aluminum electrode layer and a titanium electrode layer are sequentially deposited on the back side of a p-type silicon carbide epitaxial layer, and then a laser is irradiated onto the titanium electrode layer and the aluminum electrode layer to form an ohmic electrode. However, according to the research of the inventors of this application, it has been determined that the crystallization state between the p-type silicon carbide epitaxial layer, the ohmic electrode (silicide layer), and the collector affects the contact resistance. That is, depending on the crystallization state, there is a problem of increased on-resistance of the IGBT element.

[0009] Therefore, it is desirable to reduce the on-resistance of silicon carbide semiconductor devices such as IGBT components.

[0010] Other issues and new features will be clarified through the description and accompanying drawings in this specification.

[0011] Methods for solving problems

[0012] In the embodiments disclosed in this application, a summary of representative embodiments is briefly described below.

[0013] One embodiment of a silicon carbide semiconductor device includes: a semiconductor substrate made of 4H-SiC, having a first main surface and a second main surface located opposite each other in its film thickness direction; a semiconductor layer formed on the second main surface of the semiconductor substrate; a contact layer contacting the second main surface of the semiconductor substrate, comprising silicide regions and non-silicide regions; and an electrode contacting the contact layer and formed on the side opposite to the semiconductor substrate relative to the contact layer. Furthermore, a silicide layer having an upper surface and a lower surface is formed in the silicide region, a modified layer made of 3C-SiC is sandwiched between the upper surface of the silicide layer and the semiconductor layer, and the lower surface of the silicide layer contacts the electrode.

[0014] A method for manufacturing a silicon carbide semiconductor device, as one embodiment, includes the following steps: (a) preparing a semiconductor substrate made of 4H-SiC, the semiconductor substrate having a first main surface and a second main surface located opposite each other in its film thickness direction; (b) forming a metal layer on the second main surface of the semiconductor substrate in a manner that contacts a semiconductor layer formed within the semiconductor substrate; (c) selectively irradiating the metal layer with a laser to form a contact layer comprising silicide regions and non-silicide regions; and (d) forming electrodes on the contact layer. Then, in step (c), a silicide layer comprising a metal layer is formed in the silicide regions where the metal layer is irradiated with a laser, a metal layer remains in the non-silicide regions where the metal layer is not irradiated with a laser, and a modified layer made of 3C-SiC is formed at the boundary between the semiconductor layer and the silicide layer in the silicide regions.

[0015] The effects of the invention

[0016] According to one embodiment, the on-resistance of a silicon carbide semiconductor device can be reduced. Attached Figure Description

[0017] Figure 1 This is a cross-sectional view of the IGBT in the implementation method.

[0018] Figure 2 This is a cross-sectional view illustrating the operation (on state) of the IGBT in the implementation method.

[0019] Figure 3 This is a top view of the contact layer of the IGBT in the implementation method.

[0020] Figure 4 This is a graph showing the relationship between the area ratio of the non-silicide region of the IGBT contact layer in the embodiment and the increase in the conduction voltage.

[0021] Figure 5 This is a schematic diagram of the energy band diagram from the collector region to the collector of the IGBT in the implementation embodiment.

[0022] Figure 6 This is a cross-sectional view of the IGBT manufacturing process in the implementation method.

[0023] Figure 7 It continues Figure 6 A cross-sectional view of the manufacturing process of IGBTs.

[0024] Figure 8 It continues Figure 7 A cross-sectional view of the manufacturing process of IGBTs.

[0025] Figure 9 It continues Figure 8 A cross-sectional view of the manufacturing process of IGBTs.

[0026] Figure 10 It continues Figure 9 A cross-sectional view of the manufacturing process of IGBTs.

[0027] Figure 11 This is a cross-sectional view of the IGBT in variation example 1.

[0028] Figure 12 This is a cross-sectional view of the IGBT in variation example 2.

[0029] Figure 13 This is a cross-sectional view of the power MOSFET in Variation Example 3.

[0030] Figure 14 This is a cross-sectional view of the power MOSFET in Variation Example 4.

[0031] Figure 15 This is a cross-sectional view of the power MOSFET in Variation Example 5.

[0032] Figure 16 This is a cross-sectional view of the PN diode in variation example 6.

[0033] Figure 17 This is a cross-sectional view of the JBS diode in Variation Example 7. Detailed Implementation

[0034] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Furthermore, in all the drawings used to explain the embodiments, components with the same function are labeled with the same symbols, and repeated descriptions are omitted. Additionally, in the following embodiments, descriptions of the same or identical parts will generally not be repeated unless specifically required.

[0035] In addition, to facilitate observation of the accompanying drawings, the shading lines are sometimes omitted and sometimes added in the drawings used in the embodiments.

[0036] Furthermore, while the embodiments have been described in sufficient detail to enable those skilled in the art to implement this disclosure, other implementations and forms are also possible. It should be understood that the composition and structure, as well as various elements, can be changed and substituted without departing from the scope and spirit of the technical concept of this disclosure. Therefore, the following descriptions should not be interpreted as limiting them.

[0037] Silicon carbide (SiC) exhibits various crystalline polymorphs (polymorphs) such as 3C-SiC, 4H-SiC, and 6H-SiC due to differences in the stacking of the Si and C planes. In the following embodiments, a silicon carbide layer (silicon carbide substrate) with a 3C-SiC crystal structure is referred to as 3C-SiC, and a silicon carbide layer (silicon carbide substrate) with a 4H-SiC crystal structure is referred to as 4H-SiC.

[0038] In addition, the phrase "a layer composed of..." means "a layer containing... as the main material", including cases where the layer contains other impurities, etc.

[0039] In addition, "p-type" means "p-type conductivity" and "n-type" means "n-type conductivity".

[0040] In addition, in the accompanying drawings of the embodiments and variations, the first main surface side (the upper side of the figure) of the semiconductor substrate is referred to as "upper" and the second main surface side (the lower side of the figure) is referred to as "lower".

[0041] (Implementation Method)

[0042] <Structure of the IGBT in this embodiment>

[0043] use Figures 1 to 5 The silicon carbide semiconductor device (especially the IGBT) in the embodiments will be described. Figure 1 This is a cross-sectional view of an IGBT. Figure 2 It is a cross-sectional diagram illustrating the operation (conduction state) of an IGBT. Figure 3 This is a top view of the IGBT contact layer. Figure 4 This is a graph showing the relationship between the area ratio of the non-silicide region in the IGBT contact layer and the increase in the on-state voltage. Figure 5 This is a schematic diagram of the energy band structure from the collector region to the collector of an IGBT.

[0044] like Figure 1As shown, the IGBT has a semiconductor substrate SB made of 4H-SiC. The semiconductor substrate SB is an epitaxial substrate with a desired film thickness, having a first main surface SBa and a second main surface SBb located opposite each other in its film thickness direction. Here, the side where the emitter electrode EE is formed is called the first main surface SBa, and the side where the collector electrode CE is formed is called the second main surface SBb. However, it is also possible to call the side where the emitter electrode EE is formed the second main surface SBa, and the side where the collector electrode CE is formed the first main surface SBb. The semiconductor substrate SB has a p-type collector region CR (sometimes also called semiconductor layer SL), an n-type buffer layer BL (sometimes also called semiconductor layer SL), and an n-type drift layer DL (sometimes also called semiconductor layer SL) sequentially from the second main surface SBb side toward the first main surface side. Furthermore, the drift layer DL is formed from the end of the buffer layer BL to the first main surface SBa. The p-type collector region CR is a p-type semiconductor region containing, for example, aluminum (Al) or boron (B) as a dopant. The n-type buffer layer BL and the n-type drift layer DL are n-type semiconductor regions containing, for example, nitrogen (N) or phosphorus (P) as dopants. Furthermore, the impurity concentration of the drift layer DL is lower than that of the buffer layer BL. Although dependent on the IGBT device rating, the impurity concentration of the drift layer DL is preferably, for example, 1 × 10⁻⁶. 14 cm -3 Above and 1×10 17 cm -3 Furthermore, the thickness of the drift layer DL is preferably, for example, 30 μm or more and 150 μm or less.

[0045] Within the drift layer DL, multiple p-type host regions PBR (sometimes also called semiconductor layers SL) are formed separately from each other, extending from the first principal surface SBa of the semiconductor substrate SB to a mid-depth point of the drift layer DL. Within the p-type host regions PBR, an n-type emitter region ER (sometimes called semiconductor layer SL) and a p-type host contact region PBC (sometimes called semiconductor layer SL) are formed. The n-type emitter region ER and the p-type host contact region PBC are formed from the first principal surface SBa of the semiconductor substrate SB to a mid-depth point of the host region PBR. The emitter region ER is separated from the drift layer DL in the film thickness direction of the semiconductor substrate SB and along the first principal surface SBa, with the host region PBR sandwiched between the emitter region ER and the drift layer DL. The host region PBR and the host contact region PBC are p-type semiconductor regions containing, for example, aluminum (Al) or boron (B) as dopants. The impurity concentration of the host contact region PBC is higher than that of the host region PBR. The emitter region ER is an n-type semiconductor region containing, for example, nitrogen (N) or phosphorus (P) as dopants. The impurity concentration in the emitter region ER is higher than that in the drift layer DL.

[0046] A gate electrode GE is formed on the first main surface SB of the semiconductor substrate SB, separated by a gate insulating film GI, in a direction along the first main surface SB, covering the main region PBR between the emitter region ER and the drift layer DL. The gate electrode GE spans the emitter region ER, the main region PBR, and the drift layer DL. The gate insulating film GI comprises, for example, a silicon oxide film, with a thickness preferably 0.05 μm or more and 0.15 μm or less. Alternatively, the gate electrode GE comprises, for example, a polysilicon film, with a thickness preferably 0.2 μm or more and 0.5 μm or less. An interlayer insulating film IF is formed on the gate electrode GE. The interlayer insulating film IF covers the upper surface and sidewalls of the gate electrode GE.

[0047] In the first main surface SBa of the semiconductor substrate SB, a silicide layer SCU is formed in the region exposed from the interlayer insulating film IF. The silicide layer SCU contacts the emitter region ER and the body contact region PBC. Furthermore, an emitter electrode EE is formed on the first main surface SBa of the semiconductor substrate SB, covering the gate electrode GE, the emitter region ER, and the body contact region PBC. The emitter electrode EE is electrically isolated from the gate electrode GE through the interlayer insulating film IF. The emitter electrode EE is connected to the emitter region ER and the body contact region PBC via the silicide layer SCU. Alternatively, the silicide layer SCU can be formed to cover both the emitter region ER and the body contact region PBC, but it can also be formed to cover only one of the emitter region ER or the body contact region PBC. That is, the silicide layer SCU can also be a structure that contacts only one of the emitter region ER or the body contact region PBC. The silicide layer SCU is, for example, nickel silicide (NiSi). Furthermore, the emitter electrode EE is a stacked film consisting of, for example, a titanium (Ti) film, a titanium nitride (TiN) film, and an aluminum (Al) film sequentially from the silicide layer SCU side. Additionally, to reduce the resistance of the emitter electrode EE, it is preferable that the aluminum film has a thickness of 1.0 μm or more.

[0048] A contact layer CL is formed on the underside of the second main surface SBb of the semiconductor substrate SB, in contact with the second main surface SBb. A collector electrode CE is formed on the underside of the contact layer CL, in contact with the contact layer CL. In the direction along the second main surface SBb, for example, the contact layer CL covers the entire area of ​​the second main surface SBb, and the collector electrode CE covers the entire area of ​​the contact layer CL.

[0049] Along the direction of the second principal surface SBb, the contact layer CL has a silicide region SCR and a non-silicide region NSCR. A silicide layer SC is formed in the silicide region SCR, and a metal layer ML is formed in the non-silicide region NSCR. Furthermore, corresponding to the silicide region SCR, an n-type semiconductor layer, i.e., a modified layer AL, is formed on the collector region CR. The modified layer AL is contained within the collector region CR.

[0050] The silicide layer SC formed in the silicide region SCR, which is part of the contact layer CL, is an alloy layer comprising aluminum (Al), titanium (Ti), silicon (Si), carbon (C), and oxygen (O). As described later, the silicide layer SC is an alloy layer comprising a metal layer containing aluminum (Al) and titanium (Ti) with a semiconductor substrate SB made of 4H-SiC, or in other words, a collector region CR (semiconductor layer SL) made of 4H-SiC. In the silicide region SCR, the silicide layer SC is sandwiched between the collector region CR (semiconductor layer SL) and the collector electrode CE, and is in contact with both the collector region CR and the collector electrode CE. The metal layer ML formed in the non-silicide region NSCR, which is part of the contact layer CL, comprises, for example, aluminum (Al) and titanium (Ti). The metal layer ML can be a laminate of aluminum (Al) films and titanium (Ti) films, or it can be an alloy layer containing aluminum (Al) and titanium (Ti). In the nonsilicide region NSCR, the metal layer ML is sandwiched between the collector region CR (semiconductor layer SL) and the collector CE, and is in contact with the collector region CR and the collector CE.

[0051] The modified layer AL is part of the p-type collector region CR (semiconductor layer SL) composed of 4H-SiC, and is a p-type semiconductor layer SL composed of 3C-SiC. It is a polymorphic modification of the 4H-SiC p-type collector region CR (semiconductor layer SL) to a 3C-SiC p-type semiconductor layer SL.

[0052] The collector CE comprises a stacked metal film, for example, an aluminum (Al) film and a gold (Au) film. The aluminum (Al) film is in contact with the contact layer CL and is formed on the underside of the contact layer CL. The aluminum (Al) film is formed, for example, in a direction along the second main surface SBb, in a manner that covers the entire area of ​​the contact layer CL. The gold (Au) film is in contact with the aluminum (Al) film and is formed on the underside of the aluminum (Al) film. The gold (Au) film is formed, for example, in a direction along the second main surface SBb, in a manner that covers the entire area of ​​the aluminum (Al) film.

[0053] That is, the IGBT has a stacked structure in the silicide region SCR, which consists of: a collector region CR (semiconductor layer SL) made of 4H-SiC, a metamorphic layer AL made of 3C-SiC, a silicide layer SC, and a collector CE. In the silicide region SCR, the collector CE is ohmically connected to the collector region CR (semiconductor layer SL) via the silicide layer SC. In other words, in the silicide region SCR, the collector CE is ohmically connected to the collector region CR (semiconductor layer SL) containing the metamorphic layer AL made of 3C-SiC via the silicide layer SC. In the silicide region SCR, the silicide layer SC is sandwiched between both the collector region CR and the collector CE, so that the collector region CR and the collector CE are connected with low resistance. In addition, the IGBT has a stacked structure in the non-silicide region NSCR, which consists of: a collector region CR (semiconductor layer SL) made of 4H-SiC, a metal layer ML, and a collector CE. In the non-silicide region NSCR, the metal layer ML is sandwiched between the collector region CR and the collector CE, and the silicide layer SC is not sandwiched, so that the collector region CR and the collector CE are connected with higher resistance than the silicide region SCR.

[0054] In addition, since the silicide layer SC is an alloy layer composed of the collector region CR (semiconductor layer SL) and a metal film, the collector region CR (semiconductor layer SL) is made of 4H-SiC, and the metal film contains aluminum (Al) and titanium (Ti), the upper surface of the silicide layer SC sometimes bites into the collector region CR (semiconductor layer SL) beyond the second main surface SBb.

[0055] <Operation of the IGBT>

[0056] Use Figure 2 Describe the operation (on state) of the IGBT. Although not shown in the figure, in the on state of the IGBT, for example, 0V is applied to the emitter electrode EE, Vge (>Vth>0V) is applied to the gate electrode GE, and Vce (>>0V) is applied to the collector CE. Vge represents the voltage of the gate electrode GE relative to the emitter electrode EE, and Vce represents the voltage of the collector CE relative to the emitter electrode EE. Vth is the threshold voltage of a MOSFET (field effect transistor) composed of the gate electrode GE, an n-type emitter region ER, an n-type drift layer DL, and a p-type body region PBR. That is, a voltage higher than the threshold voltage Vth of the MOSFET is applied to the gate electrode GE, and a positive high voltage is applied to the collector CE.

[0057] When Vge (>Vth) is applied to the gate electrode GE, an inversion layer is formed on the surface of the p-type host region PBR (on the first main plane SBa side), and a large number of electrons (e) flow from the n-type emitter region ER into the n-type drift layer DL. A portion of the electrons (e) flowing into the drift layer DL flows to the p-type collector region CR. Simultaneously with this electron (e) flow, the PN junction formed by the p-type collector region CR, the n-type buffer layer BL, and the n-type drift layer DL becomes forward biased, injecting a large number of holes (h) from the collector region CR into the drift layer DL. This is equivalent to current flowing from the collector electrode CE to the emitter electrode EE. Due to the large injection of electrons (e) and holes (h) into the drift layer DL, the concentration of electrons (e) and holes (h) in the n-type drift layer DL increases sharply, resulting in conductivity modulation of the n-type drift layer DL. Therefore, because the on-resistance for the current flowing from the collector electrode CE to the emitter electrode EE becomes lower, the current drive capability of the IGBT is significantly improved.

[0058] As described above, if a large number of holes (h) are injected from the collector region CR to the drift layer DL, the concentration of holes (h) in the collector region CR decreases. Then, to replenish the holes (h) in the collector region CR, holes (h) are injected from the collector CE to the collector region CR via the contact layer CL. Here, holes (h) are injected from the collector CE to the collector region CR via the silicide region SCR of the contact layer CL. In the non-silicide region NSCR of the contact layer CL, no hole (h) injection from the collector CE to the collector region CR is performed. As described above, this is because in the silicide region SCR, the collector region CR and the collector CE form a low-resistance connection, while in the non-silicide region NSCR, the collector region CR and the collector CE form a high-resistance connection.

[0059] <About the contact layer CL>

[0060] use Figure 3 and Figure 4 The contact layer CL will be explained. Figure 3 This is a plan view of the contact layer CL. For example... Figure 3 As shown, the contact layer CL includes silicide regions SCR and non-silicide regions NSCR. The silicide regions SCR consist of an assembly of multiple units. The shape of each unit is, for example, elliptical when viewed from above. The silicide regions SCR are composed of multiple units arranged in a matrix. However, the shape and arrangement of the units are not limited to this.

[0061] Here, it is important that the contact layer CL includes both the silicide region SCR and the non-silicide region NSCR. When viewed from above, if the entire area of ​​the contact layer CL (in other words, the entire area of ​​the second main surface SBb of the semiconductor substrate SB) is considered as the silicide region SCR, then there is an excess of holes (h) injected from the collector electrode CE into the collector region CR. Therefore, by limiting the area of ​​the silicide region SCR capable of injecting holes (h), the amount of holes (h) injected from the collector CE to the collector region CR can be limited (in other words, the amount of holes (h) injected into the drift layer DL). In other words, limiting the area of ​​the silicide region SCR helps ensure a specified area of ​​the non-silicide region NSCR relative to the entire area of ​​the contact layer CL (in other words, the entire area of ​​the second main surface SBb of the semiconductor substrate SB). According to the inventors' research, the area ratio of the non-silicide region NSCR needs to be 10% or more. Here, the area ratio of the non-silicide region NSCR refers to the ratio of the area of ​​the non-silicide region NSCR to the area of ​​the second main surface SBb of the semiconductor substrate SB.

[0062] Next, the reason for needing a non-silicide region (NSCR) in the contact layer CL will be explained. The aforementioned semiconductor substrate SB made of silicon carbide is generally formed using epitaxial growth. In this silicon carbide semiconductor substrate SB, there exists a defect called a basal plane dislocation (BPD). For example, in… Figure 2 When BPD defects exist in the drift layer DL, a planar stacking defect is generated starting from the BPD defect by supplying a large number of holes (h) to the drift layer DL. Furthermore, the phenomenon of increased on-state voltage of the IGBT due to the planar stacking defect is called bipolar degradation. Bipolar degradation is a phenomenon unique to bipolar devices formed on silicon carbide substrates. In this embodiment, the IGBT can suppress bipolar degradation by limiting the injection of holes (h) into the drift layer DL by ensuring that the area ratio of the non-silicide region NSCR in the contact layer CL is 10% or more.

[0063] Figure 4 This graph shows the relationship between the area ratio of the non-silicide region NSCR in the contact layer CL and the increase in the IGBT's on-state voltage. According to the inventors' research, it has been confirmed that if the area ratio of the non-silicide region NSCR exceeds 60%, the IGBT's on-state voltage increases significantly. Therefore, it is important to keep the area ratio of the non-silicide region NSCR below 60%. Thus, in order to suppress the aforementioned bipolar degradation and reduce the IGBT's on-state voltage, it is important to keep the area ratio of the non-silicide region NSCR between 10% and 60%.

[0064] <About Alpha Metamorphic Layer>

[0065] like Figure 1 As shown, the IGBT of this embodiment has a stacked structure in the silicide region SCR consisting of the following: a collector region CR consisting of 4H-SiC, a modified layer AL consisting of 3C-SiC, a silicide layer SC, and a collector CE. Figure 5 This is a schematic diagram of the energy band structure from the collector region (CR) to the collector (CE) of the IGBT. In other words, it corresponds to the energy band structure of the stacked structure formed in the silicide region of the SCR. Figure 5 This represents the p-type collector region CR composed of 4H-SiC and the p-type collector region CR composed of 3C-SiC (corresponding to...). Figure 1 The modified layer AL), silicide layer SC and the conduction band bottom E in the collector CE C Fermi level E F Price with top E V Additionally, the conduction band bottom E C Price with top E V The width of the band gap is the band gap. The band gap of the p-type collector region CR composed of 3C-SiC (2.4 eV) is smaller than that of the p-type collector region CR composed of 4H-SiC (3.3 eV). By sandwiching the collector region CR composed of 4H-SiC and the silicide layer SC with a collector region CR composed of 3C-SiC with a smaller band gap (corresponding to...) Figure 1 The energy band diagram between the p-type collector region CR and the collector CE, which is composed of 4H-SiC (albedo layer), is shown (here, the valence band top E). V It becomes stepped, which enables the resistance between the collector region CR and the collector CE, which are composed of 4H-SiC, to be low.

[0066] <Features of the IGBT in this embodiment>

[0067] like Figure 1 As shown, the IGBT of this embodiment has a stacked structure in a silicide region SCR consisting of: a collector region CR (semiconductor layer SL) made of 4H-SiC, a modified layer AL made of 3C-SiC, a silicide layer SC, and a collector CE. Therefore, in the silicide region SCR, the collector CE is ohmically connected to the collector region CR (semiconductor layer SL) via the silicide layer SC. Furthermore, by sandwiching a collector region CR (corresponding to a 3C-SiC layer with a small bandgap) between the collector region CR made of 4H-SiC and the silicide layer SC... Figure 1 The modified AL layer can reduce the resistance between the p-type collector region CR and the collector CE, which are composed of 4H-SiC. That is, it can reduce the on-resistance of the IGBT.

[0068] like Figure 1As shown, the IGBT of this embodiment has a contact layer CL between the collector region CR and the collector CE. Furthermore, the contact layer CL comprises a silicide region SCR and a non-silicide region NSCR, with the area ratio of the non-silicide region NSCR being 10% or more and 60% or less. Therefore, bipolar degradation can be suppressed and the on-state voltage of the IGBT can be reduced.

[0069] <Method for manufacturing IGBTs according to this embodiment>

[0070] use Figures 6 to 10 This describes the manufacturing method of the IGBT in this embodiment. Figures 6 to 10 This is a cross-sectional view of the IGBT manufacturing process.

[0071] First, such as Figure 6 As shown, a substrate BSB is prepared. The substrate BSB is a silicon carbide substrate made of 4H-SiC containing n-type impurities (e.g., nitrogen (N)). The impurity concentration of the n-type impurities is 1 × 10⁻⁶. 18 cm -3 Above and 1×10 21 cm -3 The following range applies. The surface of the silicon carbide substrate can be either the Si plane or the C plane. Next, a p-type collector region CR, an n-type buffer layer BL, and an n-type drift layer DL are sequentially formed on the substrate BSB using an epitaxial growth method. The p-type collector region CR, the n-type buffer layer BL, and the n-type drift layer DL constitute the semiconductor substrate SB, which is an epitaxial substrate and is a silicon carbide substrate composed of 4H-SiC. Furthermore, the p-type collector region CR, the n-type buffer layer BL, and the n-type drift layer DL are all silicon carbide layers (semiconductor layers SL) composed of 4H-SiC.

[0072] Next, as Figure 7 As shown, a p-type host region PBR, an n-type emitter region ER, and a p-type host contact region PBC are formed within the drift layer DL. The host region PBR, emitter region ER, and host contact region PBC are formed using ion implantation. Furthermore, their formation sites are as follows: Figure 1 As explained.

[0073] Next, as Figure 8As shown, a gate electrode GE is formed on the first main surface, separated by a gate insulating film GI. The gate insulating film GI is, for example, a thermally oxidized film (silicon oxide film) or a CVD oxide film (silicon oxide film) formed using thermal oxidation or CVD (Chemical Vapor Deposition). The gate insulating film GI can be a stack of a thermally oxidized film and a CVD oxide film formed on the thermally oxidized film. The gate electrode GE is formed by patterning a polysilicon film deposited on the gate insulating film GI. Furthermore, photolithography and etching methods are used in the patterning of the polysilicon film. The polysilicon film constituting the gate electrode GE contains n-type or p-type impurities. The thickness of the gate insulating film GI is, for example, 0.05 μm or more and 0.15 μm or less. Additionally, the thickness of the gate electrode GE is, for example, 0.2 μm or more and 0.5 μm or less.

[0074] Next, as Figure 8 As shown, an interlayer insulating film IF is formed. The interlayer insulating film IF covers the upper surface of the gate electrode GE and the sides of the gate electrode GE and the gate insulating film GI. The interlayer insulating film IF is formed, for example, by plasma CVD to cover the first main surface SBa and the gate electrode GE. Then, the interlayer insulating film IF is processed by photolithography and etching to expose the emitter region ER and the body contact region PBC on the first main surface SBa.

[0075] Next, as Figure 8 As shown, a silicide layer SCU is formed on the surface of the exposed emitter region ER and the body contact region PBC. The silicide layer SCU is, for example, nickel silicide (NiSi). After depositing a nickel (Ni) film with a thickness of, for example, about 0.05 μm on the first main surface SBa, a heat treatment of 600 °C or higher and 1000 °C or lower is performed to form the silicide layer SCU on the surface of the emitter region ER and the body contact region PBC.

[0076] Next, as Figure 8 As shown, an emitter electrode EE is formed on the interlayer insulating film IF and the silicide layer SCU. The emitter electrode EE is composed of a laminated film consisting of a titanium (Ti) film, a titanium nitride (TiN) film, and an aluminum (Al) film sequentially stacked on the first main surface SBa. The emitter electrode EE is electrically connected to the emitter region ER and the body contact region PBC via the silicide layer SCU.

[0077] Next, grinding technology is used to remove... Figure 8The substrate BSB shown exposes the second main surface SBb of the semiconductor substrate SB. Here, after forming the gate electrode GE and emitter electrode EE on the semiconductor substrate SB, the substrate BSB is removed. However, if the semiconductor substrate SB has sufficient strength, the gate electrode GE and emitter electrode EE can be formed on the semiconductor substrate SB after removing the substrate BSB. Furthermore, when using a p-type silicon carbide substrate as the substrate BSB, it is not necessary to completely remove the substrate BSB. Additionally, the grinding process of the substrate BSB can be omitted.

[0078] Next, as Figure 9 As shown, a metal layer ML is formed on the underside of the second main surface SBb. For example, the metal layer ML is a stacked film (2-layer film) consisting of an aluminum (Al) film in contact with the collector region CR on the second main surface SBb and a titanium (Ti) film in contact with the aluminum (Al) film on the underside of the aluminum (Al) film. The stacked film can also be a 3-layer film. For example, a nickel (Ni) film, a molybdenum (Mo) film, a cobalt (Co) film, a titanium nitride (TiN) film, a gold (Au) film, a germanium (Ge) film, or a tungsten (W) film can be further disposed on the underside of the titanium (Ti) film in contact with the underside of the aluminum (Al) film. The total thickness of the stacked film is preferably 50 nm or more and 300 nm or less. Alternatively, the metal layer ML can be an alloy layer containing aluminum (Al) and titanium (Ti).

[0079] Next, as Figure 9 As shown, laser annealing is performed on the IGBT using a laser device LE. Specifically, the metal layer ML is selectively irradiated with laser light from the metal layer ML side towards the collector region CR. The laser light... Figure 3 The silicide region shown is subjected to SCR irradiation. Figure 3 The cells described herein represent the irradiation area of ​​each laser beam. Then, as... Figure 10 As shown, a contact layer CL comprising a silicide region SCR and a non-silicide region NSCR, and a modified layer AL composed of 3C-SiC are formed. In the silicide region SCR irradiated with laser light, the silicide layer SC and the modified layer AL are formed. In the non-silicide region NSCR not irradiated with laser light, the silicide layer SC and the modified layer AL are not formed, leaving a residual metal layer ML. Therefore, in order to form the modified layer AL composed of 3C-SiC, the laser irradiation conditions need to be set to an energy equivalent to or greater than the band gap of 4H-SiC. The laser wavelength is preferably, for example, 290 nm or more and 600 nm or less. Furthermore, the laser irradiation intensity is preferably 3.0 J / cm². 2 Above 3.5 J / cm 2The following applies. If the irradiation intensity is too weak, the aluminum (Al) in the metal layer ML will not react with the SiC in the collector region CR. If the irradiation intensity is too strong, the silicide layer SC may disappear from the SiC in the collector region CR. Furthermore, as described above, the area ratio of the non-silicide region NSCR, which is not irradiated by the laser, is between 10% and 60%.

[0080] In laser annealing, it is important to avoid directly irradiating the aluminum (Al) film contained in the metal layer ML with laser, and instead irradiate the titanium (Ti), nickel (Ni), molybdenum (Mo), cobalt (Co), titanium nitride (TiN), gold (Au), germanium (Ge), or tungsten (W) film with laser. This is because the aluminum (Al) film has a high reflectivity to laser, which weakens the effect of laser irradiation.

[0081] Next, as Figure 1 As shown, a collector electrode CE is formed on the underside of the contact layer CL.

[0082] <Features of the IGBT manufacturing method in this embodiment>

[0083] like Figure 9 and Figure 10 As explained, the metal layer ML is selectively irradiated with a laser to form a silicide layer SC in the silicide region SCR of the contact layer CL, and a modified layer AL made of 3C-SiC is formed on a portion of the collector region CR made of 4H-SiC. The IGBT manufactured in this way has a stacked structure in the silicide region SCR consisting of the following: a collector region CR made of 4H-SiC, a modified layer AL made of 3C-SiC, a silicide layer SC, and a collector electrode CE. Therefore, in the silicide region SCR, the collector electrode CE is ohmically connected to the collector region CR via the silicide layer SC. Furthermore, since the modified layer AL made of 3C-SiC is sandwiched between the p-type collector region CR made of 4H-SiC and the silicide layer SC, the resistance between the p-type collector region CR and the collector electrode CE can be kept low. That is, the on-resistance of the IGBT can be reduced.

[0084] In addition, during the laser annealing process, instead of directly irradiating the aluminum (Al) film contained in the metal layer ML with laser, the laser is irradiated onto the titanium (Ti), nickel (Ni), molybdenum (Mo), cobalt (Co), titanium nitride (TiN), gold (Au), germanium (Ge), or tungsten (W) film covering the aluminum (Al) film, thereby improving the efficiency of laser annealing.

[0085] By ensuring that the area ratio of the non-silicide region (NSCR) is above 10% and below 60%, bipolar degradation and IGBT turn-on voltage can be suppressed.

[0086] <Structure of IGBT in Variation Example 1>

[0087] The structure of the IGBT, which is a modified example of a silicon carbide semiconductor device, will be described. Figure 11 This is a cross-sectional view of the IGBT in Modified Example 1. The structure of the IGBT in Modified Example 1 is that a modified layer AL1 is added to the IGBT of the above-described embodiment. Figure 11 As shown, the IGBT of Modified Example 1 has a modified layer AL1 composed of 3C-SiC between the emitter region ER and the body contact region PBC and the silicide layer SCU.

[0088] The IGBT in Modification Example 1 has a stacked structure consisting of a p-type main contact region PBC, a modified layer AL1 made of 3C-SiC, a silicide layer SCU, and an emitter electrode EE. By sandwiching the modified layer AL1, made of 3C-SiC with a small band gap, between the p-type main contact region PBC made of 4H-SiC and the silicide layer SCU, the resistance between the p-type main contact region PBC made of 4H-SiC and the emitter electrode EE can be made low.

[0089] The IGBT in Modification Example 1 has a stacked structure consisting of an n-type emitter region ER, a modified layer AL1 made of 3C-SiC, a silicide layer SCU, and an emitter electrode EE. By sandwiching the modified layer AL1, made of 3C-SiC with a small band gap, between the n-type emitter region ER made of 4H-SiC and the silicide layer SCU, the resistance between the n-type emitter region ER made of 4H-SiC and the emitter electrode EE can be kept low. Figure 5 As explained in the description, if the collector region CR is replaced with the n-type emitter region ER, and the collector CE is replaced with the emitter electrode EE, then the energy band diagram between the n-type emitter region ER composed of 4H-SiC and the emitter electrode EE (here, the conduction band bottom E) is... C It is stepped.

[0090] In Modification 1, a modified layer AL1 composed of 3C-SiC is provided between the emitter region ER and the main contact region PBC and the silicide layer SCU. However, the modified layer AL1 can also be provided between either the emitter region ER or the main contact region PBC and the emitter electrode EE.

[0091] <Structure of IGBT in Variation Example 2>

[0092] The structure of the trench gate type IGBT of the silicon carbide semiconductor device, which is a variation of Example 2, will be described. Figure 12This is a cross-sectional view of the IGBT in Modification Example 2. In the IGBT of Modification Example 2, the gate electrode GE of the IGBT of the above embodiment is disposed in a trench TR provided on the first main surface SBb. The trench TR extends from the first main surface SBb to the second main surface SBb, penetrating the main body region PBR and reaching the drift layer DL. The gate electrode GE is formed in the trench TR with the gate insulating film GI in between. Except for the structure of the gate electrode GE of the IGBT in Modification Example 2, it is the same as the IGBT of the above embodiment, and therefore has the same effect as the IGBT of the above embodiment. In addition, the modified layer AL1 of Modification Example 1 can be added to the trench gate type IGBT of Modification Example 2.

[0093] <Structure of the power MOSFET in Variation Example 3>

[0094] Modification 3 applies the contact layer CL and the modified layer AL, which are features of the above embodiments, to a power MOSFET. Figure 13 This is a cross-sectional view of the power MOSFET of Modification Example 3. The power MOSFET of Modification Example 3 has a structure in which the p-type collector region CR, collector electrode CE, n-type emitter region ER, and emitter electrode EE of the IGBT of the above embodiments are replaced with an n-type substrate region NSB, drain electrode DE, n-type source region SR, and source electrode SE. The n-type substrate region NSB and the n-type source region SR are n-type semiconductor regions. The components of the drain electrode DE are the same as those of the collector electrode CE, and the components of the source electrode SE are the same as those of the emitter electrode EE.

[0095] The power MOSFET in Modification Example 3 has a stacked structure in the silicide region SCR consisting of: an n-type substrate region NSB (semiconductor layer SL) made of 4H-SiC, a modified layer AL made of 3C-SiC, a silicide layer SC, and a drain electrode DE. By sandwiching the modified layer AL, made of 3C-SiC with a small band gap, between the n-type substrate region NSB and the silicide layer SC, the resistance between the n-type substrate region NSB and the drain electrode DE can be kept low.

[0096] <Structure of the power MOSFET in Variation Example 4>

[0097] Modification 4 is a modification of Modification 3, having a structure in which a modified layer AL1 is added to the power MOSFET of Modification 3. Figure 14 This is a cross-sectional view of the power MOSFET in Variation Example 4.

[0098] The power MOSFET in Modification Example 4 has a stacked structure consisting of a p-type main contact region PBC, a modified layer AL1 made of 3C-SiC, a silicide layer SCU, and a source electrode SE. By sandwiching the modified layer AL1, made of 3C-SiC with a small band gap, between the p-type main contact region PBC made of 4H-SiC and the silicide layer SCU, the resistance between the p-type main contact region PBC made of 4H-SiC and the source electrode SE can be made low.

[0099] The power MOSFET in Modification Example 4 has a stacked structure consisting of an n-type source region SR, a modified layer AL1 made of 3C-SiC, a silicide layer SCU, and a source electrode SE. By sandwiching the modified layer AL1, made of 3C-SiC with a small bandgap, between the n-type source region SR made of 4H-SiC and the silicide layer SCU, the resistance between the n-type source region SR made of 4H-SiC and the source electrode SE can be made low.

[0100] In variation 4, a modified layer AL1 composed of 3C-SiC is provided between the source region SR and the main contact region PBC and the silicide layer SCU. However, the modified layer AL1 can also be provided between either the source region SR or the main contact region PBC and the source electrode SE.

[0101] <Structure of the power MOSFET in Variation Example 5>

[0102] Modification 5 is a modification of Modification 3, and is a trench gate power MOSFET. The gate electrode GE of the power MOSFET of Modification 3 is disposed in a trench TR provided on the first main surface SBa. Figure 15 This is a cross-sectional view of the power MOSFET in Modification Example 5. The trench TR extends from the first main surface SBa to the second main surface SBb, penetrating the main body region PBR and reaching the drift layer DL. The gate electrode GE is formed within the trench TR, separated by the gate insulating film GI. Except for the structure of the gate electrode GE of the power MOSFET in Modification Example 5, it is the same as that in Modification Example 3, and therefore has the same effect as the power MOSFET in Modification Example 3.

[0103] <Structure of the PN diode in Variation Example 6>

[0104] Modification 6 applies the contact layer CL and the altered layer AL, which are features of the above embodiments, to a PN diode. Figure 16This is a cross-sectional view of the PN diode in Modified Example 6. The PN diode in Modified Example 6 also has a contact layer CL1 and a modified layer AL1 on the anode electrode AE ​​side. However, it is also possible to have a structure where the contact layer CL1 and the modified layer AL1 are only provided on the cathode electrode CTE side. Alternatively, it is also possible to have a structure where the contact layer CL1 and the modified layer AL1 are only provided on the anode electrode AE ​​side.

[0105] A PN diode has a semiconductor substrate SB, contact layers CL and CL1, a cathode electrode CTE, and an anode electrode AE. The semiconductor substrate SB, made of 4H-SiC, has a first main surface SBa and a second main surface SBb. Furthermore, the semiconductor substrate SB includes an n-type substrate region NSB (sometimes called semiconductor layer SL), an n-type buffer layer BL (sometimes called semiconductor layer SL), an n-type drift layer DL (sometimes called semiconductor layer SL), and a p-type semiconductor region PR (sometimes called semiconductor layer SL) in the direction from the second main surface SBb toward the first main surface SBa. The contact layer CL is formed below the n-type substrate region NSB, and the cathode electrode CTE is formed below the contact layer CL. The contact layer CL includes a silicide region SCR and a non-silicide region NSCR. A silicide layer SC is formed in the silicide region SCR, and a metal layer ML is formed in the non-silicide region NSCR. Moreover, the area ratio of the non-silicide region NSCR is 10% or more and 60% or less. Furthermore, in the region corresponding to the silicide region SCR, a modified layer AL composed of 3C-SiC is formed on the n-type substrate region NSB, and the modified layer AL is in contact with the silicide layer SC.

[0106] The PN diode of Modification Example 6 has a stacked structure in the silicide region SCR on the cathode electrode CTE side, consisting of an n-type substrate region NSB (semiconductor layer SL) made of 4H-SiC, a modified layer AL made of 3C-SiC, a silicide layer SC, and a cathode electrode CTE. By sandwiching the modified layer AL, made of 3C-SiC with a small band gap, between the n-type substrate region NSB and the silicide layer SC, the resistance between the n-type substrate region NSB and the cathode electrode CTE can be kept low.

[0107] Furthermore, a contact layer CL1 is formed on the upper side of the p-type semiconductor region PR, and an anode electrode AE ​​is formed on the upper side of the contact layer CL1. The contact layer CL1 includes a silicide region SCR and a non-silicide region NSCR. A silicide layer SC is formed in the silicide region SCR, and a metal layer ML is formed in the non-silicide region NSCR. Moreover, the area ratio of the non-silicide region NSCR is 10% or more and 60% or less. Here, the area ratio of the non-silicide region NSCR refers to the ratio of the area of ​​the non-silicide region NSCR to the area of ​​the first main surface SBa of the semiconductor substrate SB. Furthermore, in the region corresponding to the silicide region SCR, a modified layer AL1 composed of 3C-SiC is formed in the p-type semiconductor region PR. The components of the cathode electrode CTE and the collector electrode CE (see reference) Figure 1 The components of the anode electrode AE ​​are the same as those of the emitter electrode EE (refer to...). Figure 1 The components are equal.

[0108] The PN diode of Modification Example 6 has a stacked structure in the silicide region SCR on the anode electrode AE ​​side, consisting of a p-type semiconductor region PR (semiconductor layer SL) made of 4H-SiC, a modified layer AL1 made of 3C-SiC, a silicide layer SC, and an anode electrode AE. Therefore, in the silicide region SCR, the anode electrode AE ​​is ohmically connected to the p-type semiconductor region PR (semiconductor layer SL) via the silicide layer SC. Furthermore, by sandwiching the modified layer AL1, made of 3C-SiC with a small band gap, between the p-type semiconductor region PR (made of 4H-SiC) and the silicide layer SC, the resistance between the p-type semiconductor region PR (made of 4H-SiC) and the anode electrode AE ​​can be kept low. Additionally, in the contact layer CL1, the area ratio of the non-silicide region NSCR is 10% or more and 60% or less. Therefore, bipolar degradation can be suppressed in the PN diode. Since the PN diode in Modified Example 6 is a bipolar device, limiting the area ratio of the nonsilicide region NSCR helps to suppress bipolar degradation.

[0109] Alternatively, a structure can be formed by providing multiple trenches on the first main surface SBa that are shallower than the depth of the p-type semiconductor region PR, and by providing a contact layer CL1 and an anode electrode AE ​​on the first main surface SBa, which includes both recesses and protrusions.

[0110] <Structure of JBS diode in Variation Example 7>

[0111] Modification 7 applies the contact layer CL and the altered layer AL, which are features of the above embodiments, to a JBS (Junction Barrier Shottky) diode. Figure 17This is a cross-sectional view of the JBS diode in Variation Example 7. The structure of the JBS diode is similar to that of the PN diode in Variation Example 6; therefore, the differences between the two will be explained. In the JBS diode, multiple p-type semiconductor regions PR are formed separately on the first main surface SBa of the semiconductor substrate SB. On the first main surface SBa, an n-type drift layer DL is exposed between the multiple p-type semiconductor regions PR. A barrier metal layer BM is formed on the first main surface SBa, and an anode electrode AE ​​is formed on the barrier metal layer BM. The barrier metal layer BM is, for example, made of molybdenum (Mo), titanium (Ti), or vanadium (V).

[0112] The JBS diode of Modification 7 has a stacked structure in the silicide region SCR on the cathode electrode CTE side, consisting of an n-type substrate region NSB (semiconductor layer SL) made of 4H-SiC, a modified layer AL made of 3C-SiC, a silicide layer SC, and a cathode electrode CTE. By sandwiching the modified layer AL, made of 3C-SiC with a small band gap, between the n-type substrate region NSB and the silicide layer SC, the resistance between the n-type substrate region NSB and the cathode electrode CTE can be made low.

[0113] Alternatively, multiple trenches shallower than the p-type semiconductor region PR can be formed on the first main surface SBa, and a barrier metal layer BM and an anode electrode AE ​​can be formed on the first main surface SBa, which includes concave and convex portions.

[0114] Although not illustrated, in another variation of the JBS diode in Modification 7, a structure may be formed where only the barrier metal layer BM is formed on the n-type drift layer DL, and the silicide layer SC is formed on the p-type semiconductor region PR. That is, it includes a first stacked structure consisting of the n-type drift layer DL, the barrier metal layer BM, and the anode electrode AE, and a second stacked structure consisting of the p-type semiconductor region PR, the silicide layer SC, and the anode electrode AE. Furthermore, in the second stacked structure, the modified layer AL1 may be sandwiched between the p-type semiconductor region PR and the silicide layer SC.

[0115] Alternatively, multiple trenches shallower than the p-type semiconductor region PR can be formed on the first main surface SBa. In the first main surface SBa, which includes concave and convex portions, a barrier metal layer BM is formed on the convex portion, and a silicide layer SC is formed on the concave portion.

[0116] Alternatively, if a metal with a Schottky barrier is selected as the metal layer for the anode electrode AE ​​between the n-type drift layer DL and the DL, the barrier metal layer BM can be omitted.

[0117] The invention of this application has been specifically described above according to the embodiments, but the invention of this application is not limited to the above embodiments or variations, and various changes can be made without departing from its spirit.

[0118] In addition, a portion of the content described in the above embodiments is described below.

[0119] [Postscript]

[0120] (Postscript 1)

[0121] A method for manufacturing a silicon carbide semiconductor device includes the following steps:

[0122] (a) The process of preparing a substrate made of 4H-SiC;

[0123] (b) The process of forming a semiconductor layer on the substrate;

[0124] (c) The process of forming an element structure of a silicon carbide semiconductor device including a gate electrode and an emitter electrode on the semiconductor layer;

[0125] (d) The process of exposing the semiconductor layer by grinding the substrate;

[0126] (e) A process of forming a metal layer in contact with the exposed semiconductor layer;

[0127] (f) The step of selectively irradiating the metal layer with a laser to form a contact layer comprising silicide regions and non-silicide regions; and

[0128] (g) The process of forming electrodes on the contact layer,

[0129] In step (f), a silicide layer containing the metal layer is formed in the silicide region where the laser has irradiated the metal layer, and the metal layer remains in the non-silicide region where the laser has not irradiated the metal layer. In the silicide region, a modified layer composed of 3C-SiC is formed at the boundary between the semiconductor layer and the silicide layer.

[0130] Explanation of symbols

[0131] AE anode electrode

[0132] AL, AL1 metamorphic layer

[0133] BL buffer layer

[0134] BM barrier metal layer

[0135] BSB substrate

[0136] CE collector

[0137] CL, CL1 contact layers

[0138] CR collector region

[0139] CTE cathode electrode

[0140] DE drain electrode

[0141] DL drift layer

[0142] DR drain region

[0143] EE emitter electrode

[0144] ER emitter region

[0145] GE gate electrode

[0146] GI gate insulating film

[0147] IF interlayer insulating film

[0148] LE laser device

[0149] ML metal layer

[0150] NSB n-type substrate region

[0151] NSCR nonsilicide region

[0152] PBC main contact area

[0153] PBR Main Area

[0154] PR p-type semiconductor region

[0155] SB semiconductor substrate

[0156] SBa 1st Main Side

[0157] SBb 2nd main side

[0158] SC, SCU silicide layers

[0159] SCa upper surface

[0160] SCb lower surface

[0161] SCR silicide region

[0162] SE source electrode

[0163] SL semiconductor layer

[0164] SR source region

[0165] TR slot.

Claims

1. A silicon carbide semiconductor device, characterized in that, have: A semiconductor substrate made of 4H-SiC has a first main surface and a second main surface located on opposite sides of each other in its film thickness direction; A first semiconductor layer is formed within the semiconductor substrate on the second main surface of the semiconductor substrate; A contact layer that contacts the second main surface of the semiconductor substrate, comprising silicide regions and non-silicide regions; as well as The first electrode, which is in contact with the contact layer, is formed on the side opposite to the semiconductor substrate relative to the contact layer. A first silicide layer having an upper surface and a lower surface is formed in the silicide region. A first modified layer composed of 3C-SiC is sandwiched between the upper surface of the first silicide layer and the first semiconductor layer. The lower surface of the first silicide layer is in contact with the first electrode.

2. The silicon carbide semiconductor device according to claim 1, characterized in that, In the contact layer, the first silicide layer is an alloy layer comprising aluminum, titanium, silicon and carbon.

3. The silicon carbide semiconductor device according to claim 2, characterized in that, In the contact layer, the non-silicide region is a metal layer containing aluminum and titanium.

4. The silicon carbide semiconductor device according to claim 3, characterized in that, The first electrode comprises an aluminum film.

5. The silicon carbide semiconductor device according to claim 1, characterized in that, When viewed from above, the area of ​​the non-silicide region is more than 10% and less than 60% of the area of ​​the second main surface of the semiconductor substrate.

6. The silicon carbide semiconductor device according to claim 1, characterized in that, The silicon carbide semiconductor device includes an insulated-gate bipolar transistor having a collector electrode, an emitter electrode, and a gate electrode. The first semiconductor layer is of the first conductivity type. The first electrode is the collector electrode. Furthermore, the silicon carbide semiconductor device includes: A second semiconductor layer of a second conductivity type, different from the first conductivity type, is formed within the semiconductor substrate on the first main surface of the semiconductor substrate; The third semiconductor layer of the second conductivity type is formed on the first semiconductor layer within the semiconductor substrate; The fourth semiconductor layer of the first conductivity type is formed from the first main surface of the semiconductor substrate across the midway depth of the third semiconductor layer, in a manner that includes the second semiconductor layer; The gate electrode is formed on the first main surface across a gate insulating film in such a way that it covers the fourth semiconductor layer between the second semiconductor layer and the third semiconductor layer; The second electrode, which serves as the emitter electrode, is formed on the first main surface; as well as A second silicide layer is located between the second semiconductor layer and the second electrode.

7. The silicon carbide semiconductor device according to claim 6, characterized in that, The second semiconductor layer is composed of 4H-SiC. The second silicide layer is in contact with the second semiconductor layer and the second electrode.

8. The silicon carbide semiconductor device according to claim 6, characterized in that, The second semiconductor layer is composed of 4H-SiC. The second silicide layer is in contact with the second electrode. A second modified layer composed of 3C-SiC is sandwiched between the second silicide layer and the second semiconductor layer.

9. The silicon carbide semiconductor device according to claim 6, characterized in that, The semiconductor substrate includes a trench formed from the first main surface toward the second main surface, penetrating the fourth semiconductor layer and reaching the third semiconductor layer. The gate insulating film and the gate electrode are formed within the trench.

10. The silicon carbide semiconductor device according to claim 1, characterized in that, The silicon carbide semiconductor device includes a power transistor having a source electrode, a drain electrode, and a gate electrode. The first semiconductor layer is of the first conductivity type. The first electrode is the drain electrode. Furthermore, the silicon carbide semiconductor device includes: The second semiconductor layer of the first conductivity type is formed within the semiconductor substrate on the first main surface of the semiconductor substrate; The third semiconductor layer of the first conductivity type is formed on the first semiconductor layer within the semiconductor substrate; A fourth semiconductor layer of a second conductivity type, different from the first conductivity type, is formed from the first main surface of the semiconductor substrate across the midway depth of the third semiconductor layer in a manner that includes the second semiconductor layer; as well as The gate electrode is formed on the first main surface across a gate insulating film in such a way that it covers the fourth semiconductor layer between the second semiconductor layer and the third semiconductor layer.

11. The silicon carbide semiconductor device according to claim 1, characterized in that, The silicon carbide semiconductor device includes a diode element having an anode electrode and a cathode electrode. The first semiconductor layer is of the first conductivity type. The first electrode is the cathode electrode. Furthermore, the silicon carbide semiconductor device includes: The second electrode, serving as the anode electrode, is formed on the first main surface; A second semiconductor layer of a second conductivity type, different from the first conductivity type, is formed within the semiconductor substrate on the first main surface of the semiconductor substrate; as well as The third semiconductor layer of the first conductivity type is formed on the first semiconductor layer within the semiconductor substrate and has a lower impurity concentration than the first semiconductor layer. The second semiconductor layer and the third semiconductor layer form a PN junction.

12. The silicon carbide semiconductor device according to claim 1, characterized in that, The silicon carbide semiconductor device includes a diode element having an anode electrode and a cathode electrode. The first semiconductor layer is of the first conductivity type. The first electrode is the cathode electrode. Furthermore, the silicon carbide semiconductor device includes: The second electrode, which serves as the anode electrode, is formed on the first main surface; A second semiconductor layer of a second conductivity type, different from the first conductivity type, is selectively formed within the semiconductor substrate on the first main surface of the semiconductor substrate; The third semiconductor layer of the first conductivity type is formed on the first semiconductor layer within the semiconductor substrate in such a way as to include the second semiconductor layer; as well as A barrier metal layer, which covers the second semiconductor layer and the third semiconductor layer, is sandwiched between the second semiconductor layer, the third semiconductor layer, and the second electrode. The second semiconductor layer and the third semiconductor layer form a PN junction.

13. A method for manufacturing a silicon carbide semiconductor device, characterized in that, It includes the following processes: (a) A process for preparing a semiconductor substrate made of 4H-SiC, the semiconductor substrate having a first main surface and a second main surface located on opposite sides of each other in its film thickness direction; (b) A process of forming a first metal layer on the second main surface of the semiconductor substrate in such a way as to contact the first semiconductor layer formed in the semiconductor substrate; (c) The step of selectively irradiating the first metal layer with a laser to form a contact layer comprising silicide regions and non-silicide regions; and (d) The process of forming the first electrode in a manner that makes contact with the contact layer. In step (c), A first silicide layer containing the first metal layer is formed in the silicide region where the first metal layer has been irradiated with the laser. The first metal layer remains in a non-silicide region where the laser does not irradiate the first metal layer. In the silicide region, a modified layer composed of 3C-SiC is formed at the boundary between the first semiconductor layer and the first silicide layer.

14. The method for manufacturing a silicon carbide semiconductor device according to claim 13, characterized in that, The first metal layer includes an aluminum film in contact with the first semiconductor layer and a titanium film located on the opposite side of the first semiconductor layer relative to the aluminum film. In step (c), the laser is irradiated from the titanium film side.

15. The method for manufacturing a silicon carbide semiconductor device according to claim 13, characterized in that, In step (c), When viewed from above, the area of ​​the non-silicide region that is not irradiated by the laser is more than 10% and less than 60% of the area of ​​the second main surface of the semiconductor substrate.

Images