Ethercat synchronization control method and device based on dynamic frequency adjustment and storage medium

Abstract

The application relates to the field of industrial automation servo control and provides an EtherCAT synchronization control method and device based on dynamic frequency adjustment and a storage medium. sync A set of associated dynamic parameters are defined and obtained; in a plurality of continuous synchronization cycles, synchronization errors Sync_Err of a servo driver current loop are collected, when the collection times reach a jitter sampling number N sync , a current synchronization jitter amplitude amp sync is calculated based on the collected synchronization errors Sync_Err; based on the determined adjustment direction and step length, a new pulse width modulation cycle count C pwm(new) is calculated, and the new pulse width modulation cycle count is loaded to a cycle buffer register at the end of the current pulse width modulation cycle to update the control frequency of the servo driver in a non-interrupt manner. The technical scheme of the application realizes adaptive suppression of synchronization jitter by establishing dynamic association between key parameters and the EtherCAT synchronization cycle, and effectively improves the control precision and system stability in a multi-cycle scene.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of industrial automation servo control, and in particular to an EtherCAT synchronization control method and device based on dynamic frequency adjustment and a storage medium. BACKGROUND

[0002] With the continuous improvement of industrial automation level, the synchronization accuracy of multiple servo motors in logistics conveying line and other scenarios is increasingly required. EtherCAT (Ethernet for Control Automation Technology) has become one of the mainstream solutions for realizing synchronization control of distributed servo systems due to its high real-time performance and high synchronization performance. In the system, the master station periodically sends synchronization signals to each servo driver (slave station), and each slave station needs to accurately control the local pulse width modulation (PWM) frequency based on the signals to drive the motors to work cooperatively. Any jitter of the synchronization signals will directly lead to the offset of the servo motor control timing, and then cause a series of problems such as conveying line speed fluctuation and inaccurate positioning, which seriously affects the production efficiency and product quality.

[0003] In order to suppress synchronization jitter, various schemes are proposed in the prior art. Among them, a common scheme is to use fixed frequency adjustment parameters, such as setting a fixed PWM frequency and a fixed adjustment step. Another scheme is to add a low-pass filter at the software level to smooth the synchronization error. In addition, there are also schemes that try to reduce the clock drift at the hardware level by using a high-precision clock source.

[0004] However, the above-mentioned existing schemes still have the following obvious defects, which are difficult to meet the needs of modern logistics conveying lines for multi-cycle, high anti-interference capability and high reliability: 1) the scheme with fixed parameters cannot flexibly adapt to different synchronization cycles that may be issued by the EtherCAT master station, and the synchronization error will increase significantly when the cycle is crossed, resulting in a decrease in control accuracy; 2) simple filtering mainly targets high-frequency random noise, and has limited suppression effect on periodic interference with specific frequencies that exist in the workshop environment, and may introduce phase lag; 3) schemes that rely on specific hardware or require complex manual debugging not only have high cost, but also have low portability and deployment efficiency, and are difficult to quickly adapt to different hardware platforms and application scenarios. SUMMARY

[0005] The present application provides an EtherCAT synchronization control method and device based on dynamic frequency adjustment and a storage medium, which realizes adaptive suppression of synchronization jitter by establishing a dynamic association between key parameters and EtherCAT synchronization cycles, and effectively improves the control accuracy and system stability in multi-cycle scenarios.

[0006] In one aspect, the present application provides an EtherCAT synchronization control method based on dynamic frequency adjustment, which comprises:

[0007] Define and obtain the current EtherCAT synchronization period T. sync A set of associated dynamic parameters, which include at least the frequency adjustment step size Δf and the number of jitter samples N. sync The frequency adjustment step size Δf is related to the synchronization period T. sync The number of jitter samplings N is inversely proportional to the number of jitter samplings. sync With the synchronization period T sync Proportional;

[0008] During multiple consecutive synchronization cycles, the synchronization error Sync_Err of the servo driver current loop is collected. When the number of collections reaches the jitter sampling count N, ... sync At that time, the current synchronization jitter amplitude amp is calculated based on the collected synchronization error Sync_Err. sync ;

[0009] The calculated synchronization jitter amplitude amp sync The value is compared with a preset jitter threshold, and based on the comparison result and the preset adjustment decision rule, the adjustment of the current pulse width modulation frequency f is determined. pwm Adjust the direction and step size;

[0010] Based on the determined adjustment direction and step size, calculate the new pulse width modulation cycle count C. pwm(new) And at the end of the current pulse width modulation cycle, the new pulse width modulation cycle count is loaded into the cycle buffer register to update the control frequency of the servo driver in a non-interruptible manner.

[0011] On the other hand, this application provides an EtherCAT synchronization control device based on dynamic frequency adjustment, the device comprising:

[0012] The acquisition module is used to define and acquire the current EtherCAT synchronization period T. sync A set of associated dynamic parameters, which include at least the frequency adjustment step size Δf and the number of jitter samples N. sync Wherein, the frequency adjustment step size Δf is related to the synchronization period T. sync The number of jitter samplings N is inversely proportional to the number of jitter samplings. sync With the synchronization period T sync Proportional;

[0013] The calculation module is used to collect the synchronization error Sync_Err of the servo driver current loop within multiple consecutive synchronization cycles, and when the number of collections reaches the jitter sampling number N... sync At that time, the current synchronization jitter amplitude amp is calculated based on the collected synchronization error Sync_Err.sync ;

[0014] The determination module is used to determine the calculated synchronization jitter amplitude amp. sync The value is compared with a preset jitter threshold, and based on the comparison result and the preset adjustment decision rule, the adjustment of the current pulse width modulation frequency f is determined. pwm Adjust the direction and step size;

[0015] The update module is used to calculate a new pulse width modulation cycle count C based on a determined adjustment direction and step size. pwm(new) And at the end of the current pulse width modulation cycle, the new pulse width modulation cycle count is loaded into the cycle buffer register to update the control frequency of the servo driver in a non-interruptible manner.

[0016] Thirdly, this application provides an apparatus comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the technical solution of the EtherCAT synchronization control method based on dynamic frequency adjustment as described above.

[0017] Fourthly, this application provides a storage medium storing a computer program, which, when executed by a processor, implements the steps of the technical solution of the EtherCAT synchronization control method based on dynamic frequency adjustment described above.

[0018] As can be seen from the technical solution provided in this application, on the one hand, by establishing a dynamic functional relationship between dynamic parameters such as frequency adjustment step size and jitter sampling number and the current EtherCAT synchronization cycle, the entire suppression strategy can adaptively match different synchronization cycles issued by the master station. No matter how the synchronization cycle changes, the system can automatically calculate the matching adjustment step size and sampling window, thereby ensuring that the optimized adjustment rhythm and state evaluation accuracy are maintained under different cycles, overcoming the performance degradation problem of fixed parameter schemes in multi-cycle application scenarios. On the other hand, by collecting synchronization error within a complete, cycle-related sampling window and calculating the jitter amplitude accordingly, the characteristics of periodic interference can be reflected more realistically and completely. Based on this jitter amplitude and the preset threshold... By comparing values ​​and combining them with the trend of the mean error to make directional decisions, a precise closed-loop adjustment mechanism is formed. This mechanism can effectively distinguish between random jitter and systematic deviations, and make targeted frequency adjustments accordingly, thereby significantly improving the suppression accuracy of various interferences, especially periodic interferences. Thirdly, after calculating the new control parameter, i.e., the pulse width modulation cycle count, it is not immediately forcibly updated, but the processor's cycle buffer register is used to automatically load the new value at the end of the current PWM cycle. This method achieves bumpless switching of the control frequency, avoiding current surges, motor step loss, or control interruptions that may be caused by sudden changes in control parameters during the adjustment process. This ensures that the servo system's own smoothness and continuity are not affected while dynamically adjusting synchronization performance. In summary, the technical solution of this application achieves adaptive suppression of synchronization jitter by establishing a dynamic correlation between key parameters and the EtherCAT synchronization cycle, effectively improving the control accuracy and system stability in multi-cycle scenarios. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart of the EtherCAT synchronization control method based on dynamic frequency adjustment provided in the embodiments of this application;

[0021] Figure 2 This is a schematic diagram of the structure of the EtherCAT synchronization control device based on dynamic frequency adjustment provided in the embodiments of this application;

[0022] Figure 3 This is a schematic diagram of the device provided in the embodiments of this application. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] In this specification, adjectives such as "first" and "second" are used only to distinguish one element or action from another, without necessarily requiring or implying any actual such relationship or order. Where circumstances permit, reference to an element or component or step (etc.) should not be construed as being limited to only one of the elements, components, or steps, but may be one or more of the elements, components, or steps, etc.

[0025] For ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn to actual scale.

[0026] To suppress EtherCAT synchronization jitter, existing technologies have proposed various solutions. One common approach is to use fixed frequency adjustment parameters, such as setting a fixed PWM frequency and a fixed adjustment step size. Another approach is to add a low-pass filter at the software level to smooth the synchronization error. Additionally, some solutions attempt to reduce hardware-level clock drift by using a high-precision clock source. However, these existing solutions still have the following significant drawbacks, making it difficult to meet the requirements of modern logistics conveyor lines for multi-cycle operation, high anti-interference capability, and high reliability: 1) Fixed-parameter solutions cannot flexibly adapt to different synchronization cycles that may be issued by the EtherCAT master station. Synchronization errors will increase significantly in cross-cycle applications, leading to a decrease in control accuracy; 2) Simple filtering is mainly effective against high-frequency random noise, and has limited effect on suppressing periodic interference with specific frequencies commonly found in workshop environments, and may introduce phase lag; 3) Solutions that rely on specific hardware or require complex manual debugging are not only costly but also have low portability and deployment efficiency, making it difficult to quickly adapt to different hardware platforms and application scenarios.

[0027] To address the aforementioned problems in the prior art, this application proposes an EtherCAT synchronization control method based on dynamic frequency adjustment, the flowchart of which is attached. Figure 1 As shown, the main steps include S101 to S104, which are detailed below:

[0028] Step S101: Define and obtain the current EtherCAT synchronization period T. sync A set of associated dynamic parameters, wherein the dynamic parameters include at least the frequency adjustment step size Δf and the number of jitter samples N.sync Frequency adjustment step size Δf and synchronization period T sync Inversely proportional, the number of jitter samplings N sync With synchronization period T sync They are directly proportional.

[0029] Existing technologies typically pre-set fixed frequency adjustment step sizes and filtering windows for servo drives. However, this "one-size-fits-all" approach often performs poorly when faced with different synchronization periods (e.g., 1ms, 2ms, 4ms, 8ms) that may be issued by the EtherCAT master. For example, a fixed step size optimized for a 1ms period may cause system oscillation if used for an 8ms period due to excessively frequent adjustments or a relatively large step size. Conversely, a fixed number of samplings set for an 8ms period may not cover the complete interference period in a 1ms period, leading to evaluation distortion. To address this issue, this application proposes the core idea of ​​dynamically associating parameters with the period. When the system powers on or the period changes, the current EtherCAT synchronization period T is first read. sync Subsequently, key parameters are dynamically calculated:

[0030] 1) Frequency adjustment step size Δf: its frequency adjustment step size is related to the current EtherCAT synchronization period T. sync This inverse relationship ensures that the granularity of adjustment can adapt to the synchronization rhythm. In one embodiment of this application, this relationship is expressed through a first functional relationship Δf=k1 / T. sync To achieve this. For example, if k1 = 10 (Hz•ms), then T sync For periods of 1ms, 2ms, 4ms, and 8ms, the corresponding Δf values ​​are 10Hz, 5Hz, 2.5Hz, and 1.25Hz, respectively. This design allows for finer adjustments at longer periods to avoid overshoot, while enabling relatively larger adjustments at shorter periods for faster response. It should be understood that this inverse relationship can also be achieved through other functional forms, for example, Δf = k1 / (T sync + c ),in c It is a small constant used to prevent Δf from becoming too large in extremely short periods.

[0031] 2) Number of jitter samplings N sync Its synchronization period T with the current EtherCAT is sync This is proportional, ensuring that the time window used for jitter analysis covers the entire cycle. In one embodiment of this application, the relationship is expressed through a second function N. sync = k2×T sync To achieve this. For example, if k2 = 10 (times / ms), then T sync When N is 1ms, 2ms, 4ms, and 8ms, the corresponding values ​​are: syncThe frequencies are 10, 20, 40, and 80 respectively. This allows the evaluation window to effectively capture interference characteristics related to that periodic scale, especially low-frequency periodic interference, regardless of the synchronization period the system is in.

[0032] In another embodiment of this application, the current EtherCAT synchronization period T sync The associated dynamic parameters may also include the synchronization trigger threshold C. sync It is through the third functional relationship C sync = n ×T sync × α It is confirmed that, among them, n This represents the preset number of times the current loop will be executed within a single synchronization cycle. α The preset scaling factor (0 < α <1), and n It is usually determined by the current loop frequency (e.g., 16kHz corresponds to...). n =16). Preset scaling factor. α The introduction of this feature is to avoid potential communication or computation gaps at the end of each synchronization cycle, ensuring that the calibration action is triggered during the stable phase of the cycle. In one specific embodiment, α A value of 0.875 is acceptable. In other embodiments, α The system parameters can also be dynamically configured between 0.8 and 0.95 based on processor processing power or network latency to find the optimal calibration trigger point. Through the above embodiments, this application enables system parameters to intelligently adapt to the current operating rhythm, laying an adaptive foundation for subsequent precise jitter suppression.

[0033] In order to achieve a seamless transition from rapid convergence to fine-grained stability after the system has initially entered a synchronized state, thereby simultaneously considering the system's response speed and steady-state accuracy, Figure 1 The example method may also include a synchronization calibration step, namely: real-time monitoring of the servo controller's loop counter Loop_Counter and the current synchronization error Sync_Err; when the absolute value of the synchronization error Sync_Err is less than or equal to a preset calibration error threshold, and the loop counter Loop_Counter reaches the synchronization trigger threshold C. syncWhen the system synchronization error is large, the proportional gain Sync_P_Gain of the synchronization control loop is switched from a first gain value to a lower second gain value. Thus, when the system synchronization error is large, the higher first gain value is maintained, utilizing its strong correction capability to enable rapid system convergence. When the system is about to stabilize, the lower second gain value is switched, significantly reducing sensitivity to small errors and effectively suppressing minor jitter near the stable point, achieving extremely high steady-state accuracy. This achieves the control objectives of fast, accurate, and stable operation. On the other hand, the synchronization calibration step, as an adaptive process, enables the system to cope with different operating conditions. That is, whether it is a large error during startup or a small disturbance during stable operation, the system can automatically select the most suitable control strategy, enhancing overall adaptability and robustness. Therefore, the above synchronization calibration mechanism fills the gap in single frequency adjustment strategies, and by introducing an intelligent adaptive gain switching mechanism, it resolves the contradiction between speed and stability in synchronization control.

[0034] Considering that in a complex EtherCAT network with dozens of slave stations, the synchronization errors of each node are not completely independent, and there may be systematic deviations caused by network transmission delays and master station clock distribution characteristics, in order to optimize the overall network performance, the synchronization calibration step in the above embodiment can further include master-slave collaborative optimization in an EtherCAT network with multiple slave stations. That is, the master station collects the actual synchronization error values ​​of each slave station when switching gains in the synchronization calibration step; the master station calculates the network-level synchronization error distribution characteristics based on the synchronization error values ​​of all slave stations; if the distribution characteristics indicate the existence of systematic deviations, the master station sends instructions to the relevant slave stations to dynamically adjust the synchronization trigger threshold C. sync Alternatively, an error threshold can be calibrated to optimize the overall synchronization convergence speed and accuracy of the network. Specifically, this process is a distributed optimization strategy coordinated by the EtherCAT master station.

[0035] 1) Data collection at the master station: Local synchronization calibration is performed at the slave station (i.e., reaching C... sync At the threshold and when switching Sync_P_Gain, the master station collects the actual synchronization error value of each slave station when switching gain in the synchronization calibration step. This error value reflects the residual deviation of the slave station when it is considered to be close to the synchronization time.

[0036] 2) Master station calculates network-level characteristics: Based on the synchronization error values ​​of all slave stations, the master station calculates the network-level synchronization error distribution characteristics, which includes the average value of all errors (reflecting the overall network deviation), the standard deviation (reflecting the synchronization dispersion between slave stations), and the possible error distribution patterns.

[0037] 3) Master Station Decision-Making and Command Issuance: If the distribution characteristics indicate a systematic deviation, for example, if the mean synchronization error of all slave stations is significantly non-zero, or if the slave station errors in a certain area are generally biased to one side, it indicates that there is an overall synchronization offset in the network. In this case, the master station sends commands to the relevant slave stations to dynamically adjust the synchronization trigger threshold C. sync Alternatively, the error threshold can be calibrated. For example, if the overall error is biased towards the positive, the master station can instruct the slave station to appropriately reduce its C. sync This allows the gain to switch earlier in the cycle to compensate for systemic lag.

[0038] The aforementioned master-slave collaborative optimization mechanism elevates the control perspective from a single node to the entire network. It allows the master station to fine-tune local control parameters based on global information, thereby guiding the entire network to converge more quickly to a consistent, high-precision synchronization state. This optimizes the overall synchronization convergence speed and accuracy of the network, an effect that cannot be achieved by a single node operating independently.

[0039] It should be noted that, in order to ensure Figure 1 The example method is cross-platform and adaptable to different hardware environments, based on defining and obtaining the current EtherCAT synchronization period T. sync Before the associated set of dynamic parameters, an initialization step is included, namely: automatically identifying and reading the hardware parameters of the processor used by the servo driver, wherein the hardware parameters include at least the system clock frequency f. sys And the pulse width modulation counting mode. Specifically, the software obtains the actual operating frequency of the current kernel (e.g., 552MHz) by reading the processor's specific clock configuration register or calling low-level library functions. This value is the benchmark for all subsequent cycle counting calculations, and its accuracy directly determines the C... pwm The accuracy of the calculation is crucial. Different processor architectures or different models within the same series may have different operating modes for their PWM modules. Common modes include triangular wave mode (the PWM counter counts from 0 to the period value, then counts down to 0, forming a triangular wave) and upward counting mode (the counter counts from 0 to the period value and then resets to zero). The software automatically determines the current hardware's counting mode by reading the device model identifier or specific configuration bits of the PWM control register and sets an identifier (e.g., mode=1 represents triangular wave mode, mode=2 represents upward counting mode). This identification process is essential for correctly selecting the period counting calculation formula in step S104, avoiding frequency calculation errors caused by mode mismatch. Through the above initialization, the solution of this application achieves decoupling from the underlying hardware. The same control algorithm can run on processors that support different PWM modes (e.g., various RISC-V cores or ARM Cortex-M series) without modification, enhancing the portability and deployment efficiency of the solution.

[0040] Step S102: Within multiple consecutive synchronization cycles, collect the synchronization error Sync_Err of the servo driver current loop. When the number of collections reaches the jitter sampling count N, ... sync At that time, the current synchronization jitter amplitude amp is calculated based on the collected synchronization error Sync_Err. sync .

[0041] When quantitatively evaluating synchronization status, existing technologies may only focus on instantaneous errors or simply average them. However, this is easily misled by instantaneous pulse interference or masks periodic jitter characteristics. For example, a jitter with a constant amplitude and varying period may have an average value of zero within a time window, thus being incorrectly judged as jitter-free. Therefore, the technical solution adopted in this application is to collect the synchronization error Sync_Err of the servo driver current loop over multiple consecutive synchronization cycles. When the number of collections reaches the jitter sampling count N... sync At that time, the current synchronization jitter amplitude amp is calculated based on the collected synchronization error Sync_Err. sync The system samples a synchronization error, Sync_Err, at each current loop control cycle (e.g., 16kHz). This error typically originates from a comparison between the synchronization signal of the EtherCAT slave controller (ESC) and the local clock. These error values ​​are sequentially stored in a data structure of length N. sync In the cache array. When the number of samplings reaches the jitter sampling count N. sync This means that a complete analysis data block matching the current synchronization period T_sync has been obtained. At this point, the system calculates the current synchronization jitter amplitude amp based on the collected synchronization error Sync_Err. sync By employing synchronized jitter amplitude amp sync As an evaluation metric, it can intuitively quantify the maximum fluctuation range of the synchronization signal within a cycle and is particularly sensitive to periodic jitter. Combined with a sampling window of equal length to the cycle, it ensures the completeness and representativeness of the evaluation. This allows the system to clearly "see" the true severity of the jitter, providing a reliable basis for subsequent accurate decision-making and avoiding invalid or harmful adjustments due to misjudgment.

[0042] In one embodiment of this application, the current synchronization jitter amplitude amp is calculated based on the collected synchronization error Sync_Err. sync It can be based on: reaching the number of jitter samples N sync Within the time window, collect all synchronization errors Sync_Err(i), calculate the difference between their maximum and minimum values, i.e., amp. sync = max(Sync_Err(i)) - min(Sync_Err(i)), where i=1, 2,…,Nsync This "peak-to-peak" calculation method directly reflects the extreme range of synchronization error fluctuations within the observation window. It is extremely sensitive to periodic jitter and sudden interference, and can accurately and intuitively quantify the severity of jitter, providing a stable and reliable basis for decision-making.

[0043] Step S103: Calculate the synchronization jitter amplitude amp sync The value is compared with a preset jitter threshold, and based on the comparison result and the preset adjustment decision rule, the adjustment of the current pulse width modulation frequency f is determined. pwm Adjust the direction and step size.

[0044] Existing simple on / off control (adjustment upon exceeding a threshold) is prone to oscillations near the threshold, while simple proportional control may lead to continuous integral saturation when steady-state errors exist. The decision-making mechanism of this invention is more intelligent and stable. Therefore, to cope with complex jitter scenarios and make the adjustment process smoother, this application can calculate the synchronous jitter amplitude amp. sync The value is compared with a preset jitter threshold, and based on the comparison result and the preset adjustment decision rule, the adjustment of the current pulse width modulation frequency f is determined. pwm The direction and step size for adjustment are specified, where the preset jitter threshold ΔSyncErr represents the system's allowable synchronization error fluctuation range, for example, it can be set to ±2 internal clock count units. As can be seen from the above embodiments, on the one hand, the synchronization jitter amplitude amp... sync Whether the threshold is exceeded serves as the trigger condition for adjustment, avoiding overreaction to small disturbances. On the other hand, when adjustment is needed, the direction of the average synchronization error is further introduced as the decision-making basis for which direction to adjust, which can effectively correct systematic frequency deviations. In addition, the adjustment step size is fixed (Δf), but its size itself is a dynamic value related to the period. This strategy of "condition triggering + direction judgment + fixed step size adjustment" makes the adjustment process both decisive and stable, able to converge quickly and not easily oscillate, reflecting the characteristics of precise control.

[0045] As one embodiment of this application, based on the comparison results and preset adjustment decision rules, the adjustment of the current pulse width modulation frequency f is determined. pwm The direction of adjustment could be: if amp sync If the average synchronization error within the time window is greater than ΔSyncErr and the average synchronization error within the time window is greater than the first error threshold, then the pulse width modulation frequency f is adjusted in the positive direction with a frequency adjustment step size Δf. pwm ΔSyncErr is the preset jitter threshold; if amp sync If the synchronization error is greater than ΔSyncErr and the average synchronization error is less than the second error threshold, then the pulse width modulation frequency f is negatively adjusted by the frequency adjustment step size Δf. pwm If ampsync If ≤ΔSyncErr, then maintain the current pulse width modulation frequency f. pwm Unchanged. The advantage of the above-mentioned adjustment decision rule lies in its dual judgment, namely: amp sync Exceeding the threshold indicates excessive jitter requiring intervention. The sign of the mean synchronization error indicates whether the system frequency is generally too slow (mean is positive) or too fast (mean is negative), thus determining the direction of adjustment. The adjustment step size directly adopts the frequency adjustment step size Δf that is adaptive to the period. This mechanism ensures that the adjustment is conditional (must exceed the threshold), directional (correcting system deviation), and appropriate in magnitude (matching the period), thereby achieving fast, smooth, and accurate convergence and effectively avoiding unnecessary adjustments or oscillations during the adjustment process. It should be noted that in the above embodiment, the first error threshold is a positive number, the second error threshold is a negative number, and their absolute values ​​are equal.

[0046] Considering that fixed jitter thresholds and step sizes may not adapt to changes in system load, environmental interference, or device aging, this application enables the key parameters themselves to learn and adapt. The system continuously monitors two key metrics over a relatively long statistical period (e.g., containing hundreds of adjustment decisions): the amp value at each adjustment trigger. sync The value and the system reach stability after each adjustment (i.e., amp) sync The system stabilization time required to remain below ΔSyncErr. This means that the jitter threshold (ΔSyncErr) and / or the frequency adjustment step size Δf in this application are not fixed values, but are dynamically optimized according to the system operating state. Specifically, this includes: recording the adjusted system stabilization time each time a frequency adjustment is triggered within a statistical period; when the average system stabilization time exceeds a preset threshold, increasing the jitter threshold ΔSyncErr and decreasing the frequency adjustment step size Δf in the next statistical period; when the frequency adjustment trigger frequency is lower than a preset lower limit for multiple consecutive statistical periods, decreasing the jitter threshold ΔSyncErr and increasing the frequency adjustment step size Δf in the next statistical period. More detailed dynamic optimization rules are as follows:

[0047] 1) When the average system stabilization time exceeds the preset threshold, it indicates that the current adjustment process may be too aggressive or sensitive, and frequent adjustments make it difficult for the system to converge quickly. At this time, in the next statistical period, the system will increase the jitter threshold ΔSyncErr (so that the system is more "tolerant" of small jitters) and decrease the frequency adjustment step size Δf (so that the magnitude of each adjustment is more precise), aiming to make the system adjustment behavior smoother and promote stability.

[0048] 2) When the frequency adjustment trigger frequency is lower than the preset lower limit for several consecutive statistical periods, it indicates that the current parameters may be too "conservative" and the system is slow to respond to potential performance degradation. In this case, in the next statistical period, the system will reduce the jitter threshold ΔSyncErr (thereby increasing the sensitivity to jitter) and increase the frequency adjustment step size Δf (to make the adjustment more decisive), aiming to improve the dynamic response performance of the system.

[0049] The aforementioned parameter-level adaptive optimization enables the entire synchronization suppression system to learn from experience, allowing it to self-adjust based on actual operating performance, thereby maintaining near-optimal performance under different operating conditions and at different stages of its life cycle.

[0050] The decision in step S103 of the above embodiment is mainly based on the overall amplitude and mean of a past window, which is a kind of "reactive" control. In order to deal with regular interference more proactively, this application also introduces a prediction mechanism, that is, predicting the jitter trend based on historical synchronization error data. Specifically, it can be: performing spectral analysis on the synchronization error sequence within the time window to extract the characteristic frequency and characteristic amplitude of the periodic interference component; predicting the interference intensity corresponding to the characteristic frequency in the next adjustment period based on the historical change trend of the characteristic frequency and characteristic amplitude; when the predicted interference intensity exceeds the preset warning threshold, after determining the adjustment direction and step size according to the adjustment decision rules, multiplying the frequency adjustment step size Δf by a weighting coefficient that is positively correlated with the predicted interference intensity to obtain the final adjustment step size. Specifically, the system performs N syncThe system performs spectral analysis (e.g., Fast Fourier Transform (FFT) or Wavelet Transform) on the Sync_Err sequence of synchronization errors to extract the characteristic frequencies and amplitudes of periodic interference components. For example, the analysis may identify power frequency harmonic components such as 50Hz and 100Hz and their amplitudes. The system continuously tracks the amplitude changes of these characteristic frequency components. Based on the historical trends of the characteristic frequencies and amplitudes (e.g., using simple moving average or linear regression analysis), the interference intensity corresponding to the characteristic frequencies in the next adjustment period can be predicted. For example, if the amplitude of the 50Hz component is detected to have been rising linearly over the past few periods, it can be predicted that it will continue to increase in the next period. When the predicted interference intensity exceeds a preset warning threshold, it indicates that the upcoming interference may be severe. At this time, after making a decision using the adjustment decision rule in step S103, the system does not directly use Δf, but multiplies it by a weighting coefficient K_pred, K_pred=1+γ*(A_pred / A_norm), where A_pred is the predicted amplitude, A_norm is the reference amplitude, and γ is the gain coefficient. The weighting coefficients are positively correlated with the predicted interference intensity. The final adjustment step size is Δf_final = Δf * K_pred. This is equivalent to applying force in advance before the interference arrives, performing preventative compensation, which may suppress the interference in its early stages, further improving the system's anti-interference capability and control quality.

[0051] Step S104: Based on the determined adjustment direction and step size, calculate the new pulse width modulation cycle count C. pwm(new) At the end of the current pulse width modulation cycle, a new pulse width modulation cycle count is loaded into the cycle buffer register to update the control frequency of the servo driver in an uninterrupted manner.

[0052] If the new pulse width modulation cycle count is calculated and immediately written to the PWM cycle register, the integrity of the PWM waveform will be destroyed, generating harmful pulses that are fatal to the servo system and are completely impractical. While updating by waiting for the current cycle to end is feasible, it suffers from low accuracy, is susceptible to software task scheduling, may miss the optimal update time, and is difficult to reliably implement in a 16kHz current loop with high real-time requirements. To prevent the current loop control from being interrupted, motor torque from pulsating, or even damaging the equipment due to sudden truncation or lengthening of the current cycle, this application calculates the new pulse width modulation cycle count C based on a determined adjustment direction and step size. pwm(new) At the end of the current pulse width modulation cycle, a new pulse width modulation cycle count is loaded into the cycle buffer register to update the control frequency of the servo driver in an uninterrupted manner.

[0053] As one embodiment of this application, a new pulse width modulation cycle count C is calculated based on the determined adjustment direction and step size. pwm(new)It could be: reading the processor's system clock frequency f sys And the pulse width modulation counting mode identifier mode; if the pulse width modulation counting mode identifier mode indicates a triangular wave mode, then it is determined by formula C. pwm(new) = f sys / f pwm(new) Calculate the new pulse width modulation cycle count C pwm(new) If the pulse width modulation counting mode indicator (mode) is set to upward counting mode, then the counting is performed using formula C. pwm(new) = f sys / (2×f pwm(new) Calculate the new pulse width modulation cycle count C. pwm(new) , where f pwm(new) The new target frequency, which is the pulse width modulation frequency adjusted according to the comparison results and the preset adjustment decision rules, is the current pulse width modulation frequency f. pwm(old) The result is obtained by increasing or decreasing a Δf based on the adjustment direction. The above embodiment adapts to the hardware differences of different processor architectures (e.g., some DSPs use a triangular wave mode, while some RISC-V cores use an upward counting mode), ensuring the universality of the calculation. The new pulse width modulation cycle count C is then calculated. pwm(new) Finally, the most crucial operation is to load the new pulse width modulation (PWM) cycle count into the cycle buffer register at the end of the current PWM cycle. Modern servo drives typically employ double buffering or shadow register mechanisms in their PWM generation modules. Writing a new value to the buffer register or shadow register does not immediately affect the timing of the current cycle. Only at the end of the current PWM cycle does the hardware automatically update the value of the buffer register into the active cycle register for the next PWM cycle. This process is completed automatically by the hardware without software intervention, thus achieving uninterrupted updates to the servo drive's control frequency. This prepare-and-switch mechanism is the core technology that ensures high real-time servo systems maintain control continuity and stability even when dynamically adjusting parameters.

[0054] In practical applications, due to minute time jitter in processor instruction execution, temperature drift in the clock source, and inherent differences between theoretical calculation models and physical hardware, directly applying the ideal formula C... pwm(new) =f sys / (mode*f pwm The theoretical period count C calculated pwm(new)_theory After loading, the actual generated PWM frequency may differ from the target frequency f. pwm(new) There is a small but systematic bias. If this bias accumulates over a long period or is not compensated for, it may weaken the final accuracy of the dynamic adjustment. To address this model mismatch problem, this application introduces an adaptive correction process, specifically including: identifying mode and f based on the pulse width modulation counting pattern. pwm(new)Calculate the uncorrected theoretical value C of the period count. pwm(new)_theory If the pulse width modulation counting mode indicator (mode) indicates a triangular wave mode, then C pwm(new)_theory = f sys / f pwm(new) If the pulse width modulation counting mode indicator (mode) indicates upward counting mode, then C pwm(new)_theory = f sys / (2×f pwm(new) ); Obtain the actual effective pulse width modulation cycle counts corresponding to the most recent M frequency adjustment decisions in history, and calculate the deviation data between them and the corresponding theoretical value of the cycle count; Based on this deviation data, calculate the cycle count correction coefficient; and set the theoretical value of the cycle count C... pwm(new)_theory Multiplying this by the period count correction factor yields the final new pulse width modulation period count C used for loading. pwm(new) The above process is essentially an online, adaptive calibration of the ideal mathematical model, which makes the final frequency adjustment result more accurate, especially maintaining the consistency of adjustment under different temperature or voltage conditions, thus improving the long-term stability and robustness of the system.

[0055] Considering that load variations in servo motors affect their electrical and mechanical time constants, thus impacting the sensitivity of synchronous control, under high loads, the system has greater inertia and is more sensitive to jitter, requiring stricter stability standards; under low loads or no loads, the system responds more sensitively, allowing for more aggressive adjustments to achieve rapid convergence. Therefore, Figure 1 The example method could also include: when the real-time load rate exceeds a first load threshold based on load status information, and when it exceeds a second load threshold, the system will adjust the frequency adjustment step size (Δf) by a second proportion (e.g., to 1.5 times the original value). When the real-time load rate exceeds the first load threshold (e.g., 80%), it means the motor is under heavy load or impact load. In this case, the system will temporarily reduce the jitter threshold ΔSyncErr by a first proportion (e.g., to 80% of the original value). This makes the synchronization loop control standard more stringent and responds faster to small jitters, helping to maintain high synchronization accuracy under high load disturbances. When the real-time load rate is below the second load threshold (e.g., 20%), it means the motor is under light load or no load. In this case, the system will temporarily increase the frequency adjustment step size (Δf) by a second proportion (e.g., to 1.5 times the original value). This makes the adjustment more "bold" and can take advantage of the system's fast response to quickly eliminate any existing synchronization deviations, achieving rapid positioning or start-up. This parameter fine-tuning linked to load status allows the synchronization suppression strategy to better adapt to changes in motor operating conditions, achieving an optimal balance of control performance under different load conditions.

[0056] During extreme transient processes such as system startup, sudden load increases, or strong external shocks, the system state changes drastically. Immediately implementing frequency adjustment based on dynamic sampling at such times may lead to misjudgments or erratic adjustments due to the instability of the initial state. Therefore, Figure 1 The example method may also include a startup and overload suppression mode, i.e., entering this mode during system startup or when a sudden change in total load is detected exceeding a set threshold; in this mode, a temporary fixed high-gain parameter is used to run the synchronization calibration steps, and the frequency adjustment decisions defined in steps S101 to S103 and based on dynamic parameters are suspended; when the system synchronization error stabilizes within a preset range for N consecutive cycles, this mode is exited, and steps S101 to S104 are resumed. Specifically, the startup and overload suppression mode, as a special protection and rapid stabilization mechanism, is triggered under the following conditions: entering this mode during system startup or when a sudden change in total load is detected exceeding a set threshold. In this mode, the system behavior undergoes the following adaptive changes:

[0057] 1) Pause Dynamic Frequency Adjustment: Temporarily run the synchronization calibration steps with fixed high-gain parameters, and suspend the frequency adjustment decisions defined in steps S101 to S103 and based on the dynamic parameters. This means that the system temporarily shuts down the complex jitter assessment and frequency fine-tuning closed loop to avoid potentially erroneous adjustments during periods of severe transient changes.

[0058] 2) Enhanced rapid synchronization: Simultaneously, the system employs a preset, high fixed proportional gain (Sync_P_Gain) to run the synchronization calibration loop. The high gain aims to leverage the mechanism of the synchronization calibration steps to forcefully and rapidly "pull" the motor control loop into a synchronized state within each synchronization cycle, provided the error is small enough, prioritizing the rapid establishment of initial synchronization lock.

[0059] 3) Smooth Exit: When the system synchronization error stabilizes within the preset range for N consecutive cycles, it indicates that the system has recovered from the startup or impact state and entered a relatively stable stage. At this time, the system exits this mode and resumes execution steps S101 to S104, that is, reactivates the complete dynamic frequency adjustment and adaptive optimization closed loop, and enters the high-precision synchronization maintenance stage.

[0060] The establishment of the aforementioned startup and heavy load suppression modes reflects the comprehensive consideration of all operating conditions in the technical solution of this application. It ensures the robustness and rapid recovery capability of the system under severe transients, while leveraging the advantages of high-precision adaptive suppression during the steady phase, thereby achieving reliable and high-performance synchronous control throughout the entire process from startup to steady state, and from normal load to impact load.

[0061] From the above appendix Figure 1The example of the EtherCAT synchronization control method based on dynamic frequency adjustment shows that, on the one hand, by establishing a dynamic functional relationship between dynamic parameters such as frequency adjustment step size and jitter sampling count and the current EtherCAT synchronization cycle, the entire suppression strategy can adaptively match different synchronization cycles issued by the master station. Regardless of how the synchronization cycle changes, the system can automatically calculate the matching adjustment step size and sampling window, thereby ensuring optimized adjustment rhythm and state evaluation accuracy under different cycles, overcoming the performance degradation problem of fixed parameter schemes in multi-cycle application scenarios. On the other hand, by collecting synchronization errors within a complete, cycle-related sampling window and calculating the jitter amplitude accordingly, the characteristics of periodic interference can be reflected more realistically and completely. Based on this jitter... The comparison of amplitude with a preset threshold, combined with the trend of the mean error, constitutes a precise closed-loop adjustment mechanism. This mechanism can effectively distinguish between random jitter and systematic deviation, and make targeted frequency adjustments accordingly, thereby significantly improving the suppression accuracy of various interferences, especially periodic interference. Thirdly, after calculating the new control parameter, i.e., the pulse width modulation cycle count, it is not immediately forcibly updated, but rather the processor's cycle buffer register is used to automatically load the new value at the end of the current PWM cycle. This method achieves bumpless switching of the control frequency, avoiding potential current surges, motor step loss, or control interruptions caused by sudden changes in control parameters during adjustment. This ensures that the servo system's stability and continuity are not affected while dynamically adjusting synchronization performance. In summary, the technical solution of this application achieves adaptive suppression of synchronization jitter by establishing a dynamic correlation between key parameters and the EtherCAT synchronization cycle, effectively improving control accuracy and system stability in multi-cycle scenarios.

[0062] Please see the appendix Figure 2 This application provides an EtherCAT synchronization control device based on dynamic frequency adjustment. The device may include an acquisition module 201, a calculation module 202, a determination module 203, and an update module 204, as detailed below:

[0063] Module 201 is used to define and obtain the current EtherCAT synchronization period T. sync A set of associated dynamic parameters, wherein the dynamic parameters include at least the frequency adjustment step size Δf and the number of jitter samples N. sync Frequency adjustment step size Δf and synchronization period T sync Inversely proportional, the number of jitter samplings N sync With synchronization period T sync Proportional;

[0064] Calculation module 202 is used to collect the synchronization error Sync_Err of the servo driver current loop within multiple consecutive synchronization cycles, and when the number of collections reaches the jitter sampling count N... sync At that time, the current synchronization jitter amplitude amp is calculated based on the collected synchronization error Sync_Err. sync ;

[0065] Module 203 is used to determine the calculated synchronization jitter amplitude amp sync The value is compared with a preset jitter threshold, and based on the comparison result and the preset adjustment decision rule, the adjustment of the current pulse width modulation frequency f is determined. pwm Adjust the direction and step size;

[0066] Update module 204 is used to calculate a new pulse width modulation cycle count C based on a determined adjustment direction and step size. pwm(new) At the end of the current pulse width modulation cycle, a new pulse width modulation cycle count is loaded into the cycle buffer register to update the control frequency of the servo driver in an uninterrupted manner.

[0067] From the above appendix Figure 2As illustrated by the example of the EtherCAT synchronization control device based on dynamic frequency adjustment, on the one hand, by establishing a dynamic functional relationship between dynamic parameters such as frequency adjustment step size and jitter sampling count and the current EtherCAT synchronization cycle, the entire suppression strategy can adaptively match different synchronization cycles issued by the master station. Regardless of how the synchronization cycle changes, the system can automatically calculate the matching adjustment step size and sampling window, thereby ensuring that the optimized adjustment rhythm and state evaluation accuracy are maintained under different cycles, overcoming the performance degradation problem of fixed parameter schemes in multi-cycle application scenarios. On the other hand, by collecting synchronization errors within a complete, cycle-related sampling window and calculating the jitter amplitude accordingly, the characteristics of periodic interference can be reflected more realistically and completely. Based on this jitter... The comparison of amplitude with a preset threshold, combined with the trend of the mean error, constitutes a precise closed-loop adjustment mechanism. This mechanism can effectively distinguish between random jitter and systematic deviation, and make targeted frequency adjustments accordingly, thereby significantly improving the suppression accuracy of various interferences, especially periodic interference. Thirdly, after calculating the new control parameter, i.e., the pulse width modulation cycle count, it is not immediately forcibly updated, but rather the processor's cycle buffer register is used to automatically load the new value at the end of the current PWM cycle. This method achieves bumpless switching of the control frequency, avoiding potential current surges, motor step loss, or control interruptions caused by sudden changes in control parameters during adjustment. This ensures that the servo system's stability and continuity are not affected while dynamically adjusting synchronization performance. In summary, the technical solution of this application achieves adaptive suppression of synchronization jitter by establishing a dynamic correlation between key parameters and the EtherCAT synchronization cycle, effectively improving control accuracy and system stability in multi-cycle scenarios.

[0068] Figure 3 This is a schematic diagram of the structure of a device provided in one embodiment of this application. For example... Figure 3 As shown, the device 3 in this embodiment mainly includes: a processor 30, a memory 31, and a computer program 32 stored in the memory 31 and executable on the processor 30, such as a program for an EtherCAT synchronization control method based on dynamic frequency adjustment. When the processor 30 executes the computer program 32, it implements the steps described in the embodiment of the EtherCAT synchronization control method based on dynamic frequency adjustment, for example... Figure 1 The steps S101 to S104 are shown. Alternatively, when the processor 30 executes the computer program 32, it implements the functions of each module / unit in the above-described device embodiments, for example... Figure 2 The functions of the acquisition module 201, calculation module 202, determination module 203, and update module 204 are shown.

[0069] For example, the computer program 32 of the EtherCAT synchronization control method based on dynamic frequency adjustment mainly includes: defining and obtaining the current EtherCAT synchronization period T. sync A set of associated dynamic parameters, wherein the dynamic parameters include at least the frequency adjustment step size Δf and the number of jitter samples N. sync Frequency adjustment step size Δf and synchronization period T sync Inversely proportional, the number of jitter samplings N sync With synchronization period T sync Proportional; within multiple consecutive synchronization cycles, the synchronization error Sync_Err of the servo driver current loop is collected. When the number of collections reaches the jitter sampling count N, the error is directly proportional to the jitter sampling count N. sync At that time, the current synchronization jitter amplitude amp is calculated based on the collected synchronization error Sync_Err. sync The calculated synchronization jitter amplitude amp sync The value is compared with a preset jitter threshold, and based on the comparison result and the preset adjustment decision rule, the adjustment of the current pulse width modulation frequency f is determined. pwm The adjustment direction and step size are determined; based on the determined adjustment direction and step size, the new pulse width modulation cycle count C is calculated. pwm(new) And at the end of the current pulse width modulation cycle, a new pulse width modulation cycle count is loaded into the cycle buffer register to update the control frequency of the servo driver in an uninterrupted manner. The computer program 32 can be divided into one or more modules / units, which are stored in memory 31 and executed by processor 30 to complete this application. One or more modules / units can be a series of computer program instruction segments capable of performing specific functions, which describe the execution process of the computer program 32 in device 3. For example, the computer program 32 can be divided into the functions of an acquisition module 201, a calculation module 202, a determination module 203, and an update module 204 (a module in a virtual device). The specific functions of each module are as follows: Acquisition module 201 is used to define and acquire the current EtherCAT synchronization cycle T. sync A set of associated dynamic parameters, wherein the dynamic parameters include at least the frequency adjustment step size Δf and the number of jitter samples N. sync Frequency adjustment step size Δf and synchronization period T sync Inversely proportional, the number of jitter samplings N sync With synchronization period T sync Proportional relationship; Calculation module 202 is used to collect the synchronization error Sync_Err of the servo driver current loop in multiple consecutive synchronization cycles. When the number of collections reaches the jitter sampling number N, sync At that time, the current synchronization jitter amplitude amp is calculated based on the collected synchronization error Sync_Err. sync; Determine module 203, used to determine the calculated synchronization jitter amplitude amp sync The value is compared with a preset jitter threshold, and based on the comparison result and the preset adjustment decision rule, the adjustment of the current pulse width modulation frequency f is determined. pwm The adjustment direction and step size are determined; update module 204 is used to calculate a new pulse width modulation cycle count C based on the determined adjustment direction and step size. pwm(new) At the end of the current pulse width modulation cycle, a new pulse width modulation cycle count is loaded into the cycle buffer register to update the control frequency of the servo driver in an uninterrupted manner.

[0070] Device 3 may include, but is not limited to, processor 30 and memory 31. Those skilled in the art will understand that... Figure 3 This is merely an example of device 3 and does not constitute a limitation on device 3. It may include more or fewer components than shown, or combine certain components, or different components. For example, the device may also include input / output devices, network access devices, buses, etc.

[0071] The processor 30 may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0072] The memory 31 can be an internal storage unit of the device 3, such as a hard disk or RAM of the device 3. The memory 31 can also be an external storage device of the device 3, such as a plug-in hard disk, Smart MediaCard (SMC), Secure Digital (SD) card, or Flash Card equipped on the device 3. Furthermore, the memory 31 can include both internal and external storage units of the device 3. The memory 31 is used to store computer programs and other programs and data required by the device. The memory 31 can also be used to temporarily store data that has been output or will be output.

[0073] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed. That is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above-described device can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0074] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0075] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0076] In the embodiments provided in this application, it should be understood that the disclosed apparatus / device and method can be implemented in other ways. For example, the apparatus / device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0077] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0078] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0079] If integrated modules / units are implemented as software functional units and sold or used as independent products, they can be stored in a storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program for the EtherCAT synchronization control method based on dynamic frequency adjustment can be stored in a storage medium. When executed by a processor, this computer program can implement the steps of the various method embodiments described above, namely, defining and obtaining the current EtherCAT synchronization period T. sync A set of associated dynamic parameters, wherein the dynamic parameters include at least the frequency adjustment step size Δf and the number of jitter samples N. sync Frequency adjustment step size Δf and synchronization period T sync Inversely proportional, the number of jitter samplings N sync With synchronization period T sync Proportional; within multiple consecutive synchronization cycles, the synchronization error Sync_Err of the servo driver current loop is collected. When the number of collections reaches the jitter sampling count N, the error is directly proportional to the jitter sampling count N. sync At that time, the current synchronization jitter amplitude amp is calculated based on the collected synchronization error Sync_Err. sync The calculated synchronization jitter amplitude amp sync The value is compared with a preset jitter threshold, and based on the comparison result and the preset adjustment decision rule, the adjustment of the current pulse width modulation frequency f is determined. pwm The adjustment direction and step size are determined; based on the determined adjustment direction and step size, the new pulse width modulation cycle count C is calculated. pwm(new)At the end of the current pulse width modulation (PWM) cycle, a new PWM cycle count is loaded into the cycle buffer register to update the servo drive's control frequency without interruption. The computer program includes computer program code, which can be in source code form, object code form, executable files, or some intermediate form. The storage medium can include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the contents of the storage medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the storage medium does not include electrical carrier signals and telecommunication signals.

[0080] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application. The specific embodiments described above further illustrate the purpose, technical solutions, and beneficial effects of this application. It should be understood that the above descriptions are merely specific embodiments of this application and are not intended to limit the protection scope of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An EtherCAT synchronization control method based on dynamic frequency adjustment, characterized in that, Includes the following steps: Define and obtain the current EtherCAT synchronization period T. sync A set of associated dynamic parameters, which include at least the frequency adjustment step size Δf and the number of jitter samples N. sync The frequency adjustment step size Δf is related to the synchronization period T. sync The number of jitter samplings N is inversely proportional to the number of jitter samplings. sync With the synchronization period T sync Proportional; During multiple consecutive synchronization cycles, the synchronization error Sync_Err of the servo driver current loop is collected. When the number of collections reaches the jitter sampling count N, ... sync At that time, the current synchronization jitter amplitude amp is calculated based on the collected synchronization error Sync_Err. sync ; The calculated synchronization jitter amplitude amp sync The value is compared with a preset jitter threshold, and based on the comparison result and the preset adjustment decision rule, the adjustment of the current pulse width modulation frequency f is determined. pwm Adjust the direction and step size; Based on the determined adjustment direction and step size, calculate the new pulse width modulation cycle count C. pwm(new) At the end of the current pulse width modulation cycle, the new pulse width modulation cycle count is loaded into the cycle buffer register to update the control frequency of the servo driver in an uninterrupted manner; the new pulse width modulation cycle count C is calculated based on the determined adjustment direction and step size. pwm(new) Includes: reading the processor's system clock frequency f sys and pulse width modulation counting mode identifier mode; If the pulse width modulation counting mode identifier mode indicates a triangular wave mode, then by formula C pwm(new) = f sys / f pwm(new) Calculate the new pulse width modulation cycle count C pwm(new) If the pulse width modulation counting mode indicator (mode) indicates an upward counting mode, then the counting is performed using formula C. pwm(new) = f sys / (2 × f pwm(new) Calculate the new pulse width modulation cycle count C. pwm(new) The f pwm(new) The pulse width modulation frequency is adjusted based on the comparison results and the preset adjustment decision rules.

2. The EtherCAT synchronization control method based on dynamic frequency adjustment according to claim 1, characterized in that, The frequency adjustment step size Δf is determined by the first functional relationship Δf=k1 / T sync It is determined that the number of jitter samplings N sync Through the second functional relationship N sync =k2×T sync It is confirmed that k1 and k2 are preset positive coefficients.

3. The EtherCAT synchronization control method based on dynamic frequency adjustment according to claim 2, characterized in that, The current synchronization jitter amplitude is calculated based on the collected synchronization error Sync_Err. sync Including: based on reaching the number of jitter samples N sync Within the time window, collect all synchronization errors Sync_Err(i), calculate the difference between their maximum and minimum values, i.e., amp. sync = max(Sync_Err(i))-min(Sync_Err(i)), where i =1,2,…,Nsync.

4. The EtherCAT synchronization control method based on dynamic frequency adjustment according to claim 3, characterized in that, The step involves determining the adjustment frequency f of the current pulse width modulation frequency based on the comparison results and preset adjustment decision rules. pwm The direction of adjustment: If amp sync If the average synchronization error within the time window is greater than the first error threshold, then the current pulse width modulation frequency f is adjusted in the positive direction by the frequency adjustment step size Δf. pwm ΔSyncErr is the preset jitter threshold; If amp sync If the average synchronization error is less than the second error threshold and the frequency adjustment step size is greater than ΔSyncErr, then the current pulse width modulation frequency f is negatively adjusted by the frequency adjustment step size Δf. pwm ; If amp sync If ≤ΔSyncErr, then maintain the current pulse width modulation frequency f. pwm The value remains unchanged, and ΔSyncErr is the preset jitter threshold.

5. The EtherCAT synchronization control method based on dynamic frequency adjustment according to claim 1, characterized in that, Based on the determined adjustment direction and step size, a new pulse width modulation cycle count C is calculated. pwm(new) It also includes an adaptive correction process: Based on the pulse width modulation counting mode identifier mode and the f pwm(new) Calculate the uncorrected theoretical value C of the period count. pwm(new)_theory If the pulse width modulation counting mode identifier mode indicates a triangular wave mode, then C pwm(new)_theory =f sys / f pwm(new) If the pulse width modulation counting mode identifier mode indicates an upward counting mode, then C pwm(new)_theory =f sys / (2 × f pwm(new) ); Obtain the actual effective pulse width modulation cycle counts corresponding to the most recent M frequency adjustment decisions in history, and calculate the deviation data between them and the theoretical values ​​of the corresponding cycle counts; Based on the aforementioned deviation data, the cycle count correction coefficient is calculated; The theoretical value of the period count C pwm(new)_theory Multiplying this by the cycle count correction factor yields the final new pulse width modulation cycle count C used for loading. pwm(new) .

6. The EtherCAT synchronization control method based on dynamic frequency adjustment according to claim 1, characterized in that, The dynamic parameters also include the synchronization trigger threshold C. sync It is through the third functional relationship C sync = n × T sync × α It is confirmed that the n The preset number of executions of the current loop within a single synchronization cycle, the α This is a preset proportionality coefficient; The method also includes a synchronous calibration step: Real-time monitoring of the servo controller's loop counter (Loop_Counter) and current synchronization error (Sync_Err); When the absolute value of the synchronization error Sync_Err is less than or equal to a preset calibration error threshold, and the loop counter Loop_Counter reaches the synchronization trigger threshold C... sync At this time, the proportional gain Sync_P_Gain of the synchronization control loop is switched from the first gain value to a lower second gain value.

7. An EtherCAT synchronization control device based on dynamic frequency adjustment, characterized in that, The device includes: The acquisition module is used to define and acquire the current EtherCAT synchronization period T. sync A set of associated dynamic parameters, which include at least the frequency adjustment step size Δf and the number of jitter samples N. sync Wherein, the frequency adjustment step size Δf is related to the synchronization period T. sync The number of jitter samplings N is inversely proportional to the number of jitter samplings. sync With the synchronization period T sync Proportional; The calculation module is used to collect the synchronization error Sync_Err of the servo driver current loop within multiple consecutive synchronization cycles, and when the number of collections reaches the jitter sampling number N... sync At that time, the current synchronization jitter amplitude amp is calculated based on the collected synchronization error Sync_Err. sync ; The determination module is used to determine the calculated synchronization jitter amplitude amp. sync The value is compared with a preset jitter threshold, and based on the comparison result and the preset adjustment decision rule, the adjustment of the current pulse width modulation frequency f is determined. pwm Adjust the direction and step size; The update module is used to calculate a new pulse width modulation cycle count C based on a determined adjustment direction and step size. pwm(new) At the end of the current pulse width modulation cycle, the new pulse width modulation cycle count is loaded into the cycle buffer register to update the control frequency of the servo driver in an uninterrupted manner; the new pulse width modulation cycle count C is calculated based on the determined adjustment direction and step size. pwm(new) Includes: reading the processor's system clock frequency f sys And the pulse width modulation counting mode identifier mode; if the pulse width modulation counting mode identifier mode indicates a triangular wave mode, then by formula C pwm(new) = f sys / f pwm(new) Calculate the new pulse width modulation cycle count C pwm(new) If the pulse width modulation counting mode indicator (mode) indicates an upward counting mode, then the counting is performed using formula C. pwm(new) = f sys / (2 × f pwm(new) Calculate the new pulse width modulation cycle count C. pwm(new) The f pwm(new) The pulse width modulation frequency is adjusted based on the comparison results and the preset adjustment decision rules.

8. An apparatus comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method as described in any one of claims 1 to 6.

9. A storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1 to 6.

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