Clock gating circuit and corresponding system

Abstract

The invention relates to a clock gating circuit and a corresponding system. A reset domain crossover circuit deasserts a clock enable signal in response to receiving an asserted software reset write request signal, and asserts the clock enable circuit in response to detecting a falling edge on the software reset signal. The reset domain crossover circuit comprises a synchronizer, a falling edge detection circuit and a clock enable circuit, wherein the synchronizer receives a software reset signal and generates a synchronous software reset signal; the falling edge detection circuit receives a synchronization software reset signal from a synchronizer and generates a falling edge signal when a falling edge on the synchronization software reset signal is detected. The clock enable circuit is coupled to a falling edge detection circuit that receives a falling edge signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Italian Patent Application No. 102024000017590, filed on July 29, 2024, the entire contents of which are incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This specification relates to clock technology in sequential circuits.

[0004] The solutions described in this article can be applied to processor circuits such as microcontroller circuits (MCUs) to handle reset domain crossover issues. Background Technology

[0005] Processors (e.g., microprocessors) may include modules configured to perform independent resets by writing to dedicated bit registers; these are typically referred to as software (SW) reset modules.

[0006] Multiple reset domains can coexist in a design. For example, two reset domains can be interconnected so that, in response to an SW reset asserted in the source reset domain, a trigger (FF) in the destination reset domain can be violated during the corresponding hold / set phase.

[0007] in this regard, Figure 1 An exemplary portion of a processor is shown, which includes a first reset domain (e.g., a source reset domain) and a second reset domain (e.g., a destination reset domain).

[0008] Figure 1 A portion of the processor is shown, highlighting that two reset domains may exist (shown here as first reset domain 10 and second reset domain 20). As illustrated, first reset domain 10 includes conversion decoding circuitry 50, software reset register 60, and first flip-flop 70, while second reset domain 20 includes second flip-flop 80. Typically, first flip-flop 70 and second flip-flop 80 can represent any general-purpose sequential circuitry that receives an external clock and reset signal.

[0009] The conversion decoding circuit 50 is coupled to the software reset register 60 and receives multiple input signals X1, ..., X5.

[0010] Therefore, the conversion decoding circuit 50 generates a write request signal WR pointing to the software reset register 60 as an output, which is coupled to the first flip-flop 70 and generates a software reset signal SR as an output in response to receiving the write request signal WR from the conversion decoding circuit 50.

[0011] The software reset signal SR is received as input by delay unit 91 and AND gate 92, which has an inverting input coupled to delay unit 91. AND gate 92 also receives reset signal RST2 on another input terminal and has an output terminal coupled to reset terminal R of third element 90.

[0012] For simplicity, the third element 90 is represented as a flip-flop in the figure. In fact, the third element 90 can be a reset synchronizer comprising two flip-flops. The input terminal D of the first flip-flop is coupled to a constant logic '1' value. The output terminal Q of the first flip-flop is coupled to the D input of the second flip-flop. The output terminal Q of the second flip-flop is coupled to the reset terminal R of the first flip-flop 70. The clock terminal is coupled to the master system clock signal PCLK and is adapted to time in the destination clock domain. The reset signal is passed through the flip-flops in element 90 to facilitate an assertion that is adequately aligned with the destination clock signal.

[0013] Component 90 is configured to synchronize reset signals; for example, to synchronize a first reset signal RST1 pointing to a first reset domain 10 and a second reset signal RST2 pointing to a second reset domain 20. Reset signals RST1 and RST2 are deasserted so that a reset is performed in the circuit they point to, such as flip-flop 70. In fact, as shown, the reset signals are received by the corresponding circuit at the inverting terminal, therefore reset signals RST1 and RST2 should be deasserted to reset the flip-flop.

[0014] By counteracting timing violations on flip-flop 70 (and flip-flop 60), reset synchronizer 90 can facilitate operation such that the reset assertion at output Q (to 1, reset release) is synchronized with the destination clock domain. Conversely, the reset deassertion (to 0 for reset applications) can be asynchronous.

[0015] During a software reset operation involving multiple reset domains (e.g., source reset domain 10 and destination reset domain 20, where the software reset signal originates from the aforementioned source reset domain 10), the input terminal D of a flip-flop (e.g., a second flip-flop 80) included in the destination reset domain may trigger the flip-flop near the clock edge (rising or falling edge) when the source reset domain flip-flop 70 is reset, resulting in possible metastability in the circuit.

[0016] To address this shortcoming, for example, the possibility of violating the clock on the destination flip-flop (FF) during the hold / set phase, it may be necessary to gating the clock on the destination FF. This approach relies on the fact that if the destination FF is not receiving a clock in response to a source reset, the aforementioned set / hold problem can be effectively resolved.

[0017] For example, a hardware (HW) module can disable the clock in the destination reset domain in response to a SW reset in the source reset domain. Such a clock can be re-enabled (only) after waiting a predetermined number of clock cycles from the SW reset assertion in the source reset domain to allow the reset signal to propagate correctly through the circuit, thus creating an open-loop solution.

[0018] Referring to U.S. Patent Application Publication No. 2016 / 048155A1, which is incorporated herein by reference, this patent application relates to this method and discloses an onboard reset circuit for a System-on-Chip (SoC) that addresses the metastability problem of flip-flops when asynchronous resets occur when different power domains or reset domains receive resets from different sources. To mitigate this problem, the reset signal is asserted and deasserted when the clock is strobed. After assertion or deassertion, the clock recovers in the shortest possible time, allowing logic with synchronous reset to also receive resets.

[0019] As references to related technologies, U.S. Patent Application Publications Nos. 2024 / 094789A1, 2020 / 374377A1, 2023 / 244841A1 and 2018 / 004876A1, U.S. Patent No. 11,693,461B1 and Chinese Patent Reference No. CN 116126116 A are all incorporated herein by reference.

[0020] Therefore, an open-loop hardware solution to prevent reset domain crossover can be defined as the propagation of the reset signal occurring within a predetermined number of clock cycles, the value of which can depend on process, voltage, and temperature parameters (PVT).

[0021] This can happen when a delay unit is added to the reset signal path for functional purposes, so the number of clock cycles can vary in a highly extended manner.

[0022] There is a need in this field for solutions that can help address the above problems. Summary of the Invention

[0023] The embodiments described herein relate to a circuit including a first timing circuit, a second timing circuit, a conversion decoding circuit, a software reset register, a reset domain crossover circuit, and a clock gating unit. The first timing circuit is configured to operate under a first clock signal in a first clock domain; the second timing circuit is configured to operate under a second clock signal in a second clock domain; the conversion decoding circuit is configured to generate a software reset write request signal; the software reset register is coupled to the conversion decoding circuit and configured to generate a software reset signal in response to a software reset write request signal from the conversion decoding circuit; the reset domain crossover circuit is configured to deassert a clock enable signal in response to receiving a software reset write request signal from the conversion decoding circuit and to assert the clock enable signal in response to a falling edge detected on the software reset signal from the software reset register; the clock gating unit is coupled to the reset domain crossover circuit and configured to disable the second clock signal of the second timing circuit in response to the clock enable signal being deassertified by the reset domain crossover circuit.

[0024] In the solution described herein, the reset domain crossover circuit may include a clock enable circuit configured to: deassert the clock enable signal in response to receiving a software reset write request signal from the conversion decoding circuit in the event of a missing falling edge detected on the software reset signal from the software reset register; and assert the clock enable signal in response to a falling edge detected on the software reset signal from the software reset register in the event of a missing software reset write request signal from the conversion decoding circuit.

[0025] In the solution described herein, the clock enable circuit in the reset domain crossover circuit may include a flip-flop and a multiplexer. The flip-flop is configured to generate a clock enable signal at its output terminal. The multiplexer is configured to apply to the flip-flop a multiplexed input signal selected based on a reset write request signal from the conversion decoding circuit and a falling edge signal indicating a falling edge detected on a software reset signal from the software reset register. The value of the multiplexed input signal is selected from a first constant value, a second constant value, and the value of the clock enable signal generated by the flip-flop.

[0026] In the solution described herein, the reset domain crossover circuit may include a sampling flip-flop, a rising edge detection circuit, and a corresponding clock enable circuit. The sampling flip-flop is configured to receive a software reset write request signal and generate a sampling write request signal. The rising edge detection circuit is coupled to the sampling flip-flop and configured to generate a rising edge signal indicating a rising edge detected in the sampling write request signal. The corresponding clock enable circuit is configured to: deassert the clock enable signal in response to receiving the rising edge signal; and assert the clock enable signal in response to a falling edge detected on the software reset signal from the software reset register.

[0027] In the solution described herein, the corresponding clock enable circuit may include an OR gate configured to generate a clock enable signal based on a falling edge detected on a software reset signal from a software reset register and the output of an AND gate that receives a logically inverted version of the rising edge signal and the output of a corresponding flip-flop to which the clock enable signal is applied.

[0028] In the solution described herein, the rising edge detection circuit may include: a rising edge detection flip-flop to which a sample write request signal is applied, and a rising edge detection AND gate of the logic inversion version to which the sample write request signal and the output of the rising edge detection flip-flop are applied.

[0029] In the solution described herein, the reset domain crossover circuit may include a falling edge detection circuit, which includes a falling edge detection circuit configured to detect the falling edge of a software reset signal, wherein the falling edge detection circuit includes a falling edge detection flip-flop to which the software reset signal is applied, and a falling edge detection AND gate consisting of a logic inverted version of the software reset signal and the output of the falling edge detection flip-flop.

[0030] In the solution described herein, the reset domain crossover circuit may include a synchronizer configured to receive a software reset signal and generate a synchronous copy of the software reset signal, and the reset domain crossover circuit is configured to process the software reset signal based on the synchronous copy of the software reset signal.

[0031] In the solutions described herein, the synchronizer may include: a two-stage synchronizer comprising a cascaded arrangement of a first synchronizer trigger and a second synchronizer trigger.

[0032] The solutions described herein also relate to a system that includes circuitry according to the solutions described herein. For example, a processor system, such as a microcontroller circuit, can be an example of such a system, which includes a first IP core, a second IP core, and a register set. The first IP core includes first timing circuitry configured to operate under a first clock signal; the second IP core is configured to operate under a second clock signal; and the register set includes a software reset register coupled to a conversion / decoding circuit and configured to generate a software reset signal in response to a software reset write request signal from the conversion / decoding circuit. Attached Figure Description

[0033] One or more embodiments will now be described by way of example only with reference to the accompanying drawings, in which:

[0034] Figure 1 A portion of the processor is shown, highlighting the two reset domains that may exist.

[0035] Figure 2 A portion of the processor system is shown, which includes two separate reset domains and a reset domain crossover circuit.

[0036] Figure 3 This illustrates one possible way to implement the reset domain crossover circuit;

[0037] Figure 4 This demonstrates another possible way to implement the reset domain crossover circuit;

[0038] Figure 5 It is a block diagram of a microcontroller circuit including clock / reset control circuitry; and

[0039] Figure 6 It is a circuit diagram of a clock / reset control circuit that includes a reset domain crossover circuit. Detailed Implementation

[0040] These figures are drawn to clearly illustrate relevant aspects of the embodiments and are not necessarily drawn to scale.

[0041] The feature edges drawn in the diagram do not necessarily indicate the end of the feature range.

[0042] In the following description, one or more specific details are shown to provide a thorough understanding of examples of embodiments of this specification. Embodiments may be obtained without one or more specific details, or may be obtained through other methods, components, materials, etc. In other instances, known structures, materials, or operations are not shown or described in detail, so that certain aspects of the embodiments are not obscured.

[0043] References to "embodiment" or "an embodiment" within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear in one or more locations within this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular configurations, structures, or features may be combined in any suitable manner.

[0044] The headings / references used herein are provided for convenience only and therefore do not define the scope or range of protection of the embodiments.

[0045] In the accompanying drawings, unless the context otherwise indicates, the same parts or elements are denoted by the same references / numericals, and for the sake of brevity, the corresponding descriptions will not be repeated.

[0046] In addition, for simplicity and ease of explanation, the same names can be used throughout the description to specify: a node or line and the signal present at that node or line, and / or a component (such as a capacitor, resistor, or inductor or coil) and its electrical parameters.

[0047] When a component is referred to below as being “connected to” or “coupled to” another component, it should be understood that another component may be inserted in between, and that the component may be directly connected to or coupled to another component. Conversely, when a component is referred to below as being “directly connected to” or “directly coupled to” another component, it should be understood that no other component is inserted in between.

[0048] Figure 2 It shows that it is based on the combination Figure 1 The processor discussed is part of a processor with the same overall layout as the processor, which includes a first reset domain 10 and a second reset domain 20.

[0049] Therefore, in Figure 2 (and any other figures that may be included) in, unless the context otherwise requires, are combined Figure 1 The components or elements discussed are represented by the same references / numbers, and for the sake of brevity, their corresponding descriptions will not be repeated: Essentially, they are combined with... Figure 1 Compared to the processors discussed, Figure 2 The processor shown includes a reset domain crossover circuit 100 and a clock gating unit 93, and operates as follows.

[0050] exist Figure 2In the processor shown (as an example), the conversion decoding circuit 50 can generate a software reset write request WR, which is directed to the software reset register 60, to which the conversion decoding circuit 50 is coupled. Therefore, the software reset register 60 receives the software reset write request 60 as input and generates a software reset signal SR as output.

[0051] In response, a software reset signal SR is output to delay line 91, which in turn outputs a delayed software reset signal SR to the inverting input terminal of AND gate 92 after a predetermined delay. Therefore, another input terminal of AND gate 92 (not inverted in the considered example) is coupled to a reset signal RST2 pointing to the second reset domain 20, while the output terminal of AND gate 92 is coupled to the inverted reset terminal R of the third flip-flop 90.

[0052] As previously described, the third element 90 is a synchronizer configured to synchronize reset signals, such as a first reset signal RST1 pointing to the first reset domain 10 and a second reset signal RST2 pointing to the second reset domain 20. For this purpose, synchronizer 90 is coupled to the master system clock PCLK, and its input terminal D is coupled to a constant logic level, such as a reference voltage, and its output terminal Q is coupled to the reset terminal R of a flip-flop (e.g., first flip-flop 70) included in the first reset domain 10. Typically, the reset signals RST1 and RST2 are deasserted to perform a reset in the circuitry they point to (e.g., flip-flop 70).

[0053] In fact, as shown in the figure, the reset signal is received by the corresponding circuit at the inverting terminal, so the reset signals RST1 and RST2 should be deasserted to reset the flip-flop.

[0054] In a possible implementation, the reset domain crossover circuit 100 is configured to disable the clock signal CLK2 pointing to the second reset domain 20 in response to an assertion of the software reset signal SR in the first reset domain 10 (i.e., the source reset domain), and thus re-enable the clock signal CLK2 pointing to the second reset domain 20 in response to a deassertion of the software reset signal SR in the first reset domain 10. Therefore, the reset domain crossover circuit 100 is operable such that when one or more source flip-flops (e.g., the first flip-flop 70) have pending reset operations, the destination flip-flop (i.e., the second flip-flop 80) does not receive the corresponding clock signal CLK2.

[0055] For this purpose, the reset domain crossover circuit 100 can output a clock enable signal CE, which, together with the clock signal CLK1 (i.e., the clock signal received by the circuit in the first reset domain 10), is received by the clock gating unit 93. Therefore, the clock gating unit 93 generates a clock signal CLK2 (i.e., the clock signal received by the second reset domain 20) as an output based on the value of the clock enable signal CE.

[0056] For example, this operation can be implemented using an AND gate. Therefore, if the clock enable signal CE is asserted, the clock gating unit 93 essentially forwards the clock signal CLK2 to the second reset domain 20; conversely, if the clock enable signal CE is deasserted, the clock gating unit gating the clock signal CLK2. Thus, as described above, the reset domain crossover circuit 100 can control whether the clock signal is forwarded or gated to the destination reset domain.

[0057] Figure 3 This paper illustrates one possible way to implement a reset domain crossover circuit based on the solution described herein.

[0058] like Figure 3 As shown, the reset domain crossover circuit 100 receives the software reset write request signal WR, the software reset signal SR, the self-oscillating clock FCLK, and the reset signal RST, and outputs the clock enable signal CE.

[0059] As shown in the figure, the reset domain crossover circuit 100 includes a falling edge detection circuit 110, a clock enable circuit 120, and a synchronizer 130. Furthermore, the falling edge detection circuit 110 includes a flip-flop 111 and an AND gate 112, and the clock disable circuit 120 includes a multiplexer 121 and a flip-flop 122.

[0060] The falling edge detection circuit 110 is configured to assert a falling edge signal FE for a duration of one full clock cycle in response to the detection of a falling edge on the software reset signal SR, thereby detecting the deassertion of the software reset signal SR.

[0061] The flip-flop 111 of the falling edge detection circuit 110 has an input terminal D coupled to the output terminal Q of the synchronizer 130, an output terminal Q coupled to the input terminal of the AND gate 112, a reset terminal R coupled to the reset signal RST, and a clock terminal coupled to the self-oscillating clock FCLK.

[0062] AND gate 112 has another inverted input terminal coupled to the output terminal Q of synchronizer 130, and generates a falling edge signal FE as the output (i.e., as the result of the AND operation).

[0063] Clock enable circuit 120 is configured to generate output clock enable signal CE based on the values ​​of the falling edge signal FE and the software reset write request signal WR, which are received as selection signals by multiplexer 121. Specifically, the values ​​of the falling edge signal FE and the software reset write request signal WR define three different possible cases: a first case where both the write request signal WR and the falling edge signal FE are deasserted, and the clock enable signal CE retains its value from the previous clock cycle; a second case where the write request signal WR is asserted, the falling edge signal FE is deasserted, and the clock enable signal CE is deasserted; and a third case where the write request signal WR is deasserted, the falling edge signal FE is asserted, and the clock enable signal CE is asserted.

[0064] For this purpose, multiplexer 121 receives a 2-bit select signal including a write request signal WR and a falling edge signal FE, and the output terminal of multiplexer 121 is coupled to the input terminal D of flip-flop 122.

[0065] Flip-flop 122: receives a reset signal RST on its set terminal S; has an output terminal Q that generates a clock enable signal CE as an output; and is coupled to a self-oscillating clock FCLK.

[0066] like Figure 3 As shown, the clock enable signal CE generated by the flip-flop 122 as an output is fed back to the '00' input of the multiplexer 121. This corresponds to the case where both the write request signal WR and the falling edge signal FE are deasserted. In this way, when both the write request signal WR and the falling edge signal FE are deasserted, the multiplexer 121 generates the value taken by the clock enable signal CE in the previous clock cycle as its output.

[0067] The '01' input of multiplexer 121 (corresponding to the case where the write request signal WR is asserted and the falling edge signal FE is deasserted) is connected to a constant logic '0' value, such as a ground terminal. In this way, when the write request signal WR is asserted and the falling edge signal FE is deasserted, multiplexer 121 outputs a '0' value to flip-flop 122, which in turn outputs a deasserted clock enable signal CE.

[0068] Similarly, the '10' input of multiplexer 121 (corresponding to the case where the write request signal WR is deasserted and the falling edge signal FE is asserted) is connected to a constant logic '1' value, such as a reference voltage, so that when the write request signal WR is deasserted and the falling edge signal FE is asserted, multiplexer 121 outputs a '1' value to flip-flop 122, which in turn outputs the assertion clock enable signal CE.

[0069] The '11' input of multiplexer 121 is not used and remains floating: this can actually be considered a disabled configuration, where the '11' condition is maintained to correspond to the default condition, '00'.

[0070] When the software reset signal SR is asynchronously deasserted (i.e., deasserted at the moment between the rising and falling edges of the system clock), synchronizer 130 facilitates the correct operation of the falling edge detection circuit 110. For this purpose, synchronizer 130 has an input terminal D coupled to the software reset signal SR, a reset terminal R coupled to the reset signal RST, a clock terminal coupled to the self-oscillating clock FCLK, and an output terminal Q coupled to the falling edge detection circuit 110 (as shown, coupled to the input terminal D of flip-flop 111 and the inverting input of AND gate 112) to output a synchronous (e.g., delayed) copy of the software reset signal SR.

[0071] Synchronizer circuit 130 can be considered as comprising two cascaded flip-flops (i.e., the output terminal of the first flip-flop is coupled to the input terminal of the second flip-flop, wherein the first flip-flop samples the input signal from the source clock domain, and the second flip-flop samples the signal thus synchronized using the destination clock, thereby making the output of the second flip-flop safe for use in the destination clock domain).

[0072] In summary, the reset domain crossover circuit 100 is configured to output a clock enable signal CE, which is deasserted when a software reset write request WR assertion is detected, and asserted when a software reset SR deassertion is detected (in fact, since PCLK is strobed, another WR request cannot occur).

[0073] A self-excited clock FCLK with the same frequency as the clock frequency of the software reset register 60 helps the reset domain cross circuit 100 to operate correctly.

[0074] For example, in an embodiment involving a solution conforming to the Advanced Microcontroller Bus Architecture (AMBA) (where the software reset register 60 is accessed via the APB (Advanced Peripheral Bus), and thus a software reset write request signal WR is generated in response to an APB transaction), the self-oscillating clock FCLK advantageously has the same frequency as the APB master system clock PCLK. In fact, the clock PCLK can be derived from the clock FCLK.

[0075] In its role as the clock responsible for generating the software reset signal SR (i.e., the master system clock PCLK), the clock is selected by the clock enable signal CE, and the master system clock PCLK, having the same frequency as the self-oscillating clock FCLK, contributes to... Figure 3 The circuit shown is operating fully.

[0076] It was observed that if the main system clock PCLK frequency is lower than the self-oscillating clock FCLK frequency, the software reset information SR can be omitted as long as the reset domain crossover circuit 100 disables the main system clock PCLK before generating the software reset signal SR (in fact, the flip-flop 60 uses another PCLK edge to sample the WR request), because the reset domain crossover signal 100 operates at the clock frequency given by the self-oscillating clock FCLK, assuming that the clock frequency is higher than the main system clock PCLK.

[0077] like Figure 4 As shown, a clock frequency-related problem can be solved. This figure illustrates another possible way to implement the reset domain crossover circuit according to the solution described in this article.

[0078] like Figure 4 As shown, the reset domain crossover circuit 200 receives the software reset write request signal WR, the software reset signal SR, the self-oscillating clock FCLK, the reset signal RST, and the auxiliary clock signal SCLK as inputs, and generates the clock enable signal CE as output.

[0079] The reset domain crossover circuit 200 includes a falling edge detection circuit 210, a rising edge detection circuit 220, a clock enable circuit 230, a synchronizer 240, and a flip-flop 250.

[0080] Furthermore, the falling edge detection circuit 210 includes a flip-flop 211 and an AND gate 212, the rising edge detection circuit 220 includes a flip-flop 221 and an AND gate 222, and the clock enable circuit 230 includes a flip-flop 231, an AND gate 232, and an OR gate 233.

[0081] The falling edge detection circuit 210 is configured to assert a falling edge signal FE for a duration of one full clock cycle in response to the detection of a falling edge on the software reset signal SR, thereby detecting the deassertion of the software reset signal SR.

[0082] The flip-flop 211 of the falling edge detection circuit 110 has an input terminal D coupled to the output terminal Q of the synchronizer 240, an output terminal Q coupled to the input of the AND gate 212, a reset terminal R coupled to the reset signal RST, and a clock terminal coupled to the self-oscillating clock FCLK.

[0083] Therefore, AND gate 212 has another inverted input terminal coupled to the output terminal Q of synchronizer 240, and as a result of the AND operation, generates a falling edge signal FE as the output.

[0084] Flip-flop 250 is used to sample the software reset write request signal WR at a sampling frequency specified by the auxiliary clock signal SCLK. Specifically, flip-flop 250 receives the write request signal WR as input at input terminal D, where the auxiliary clock signal SCLK is used as the local clock of flip-flop 250, and therefore, the sampled write request signal SWR is generated at output terminal Q of flip-flop 250.

[0085] The auxiliary clock signal SCLK is synchronized with the self-excited clock signal FCLK, and can have a frequency lower than that of the self-excited clock signal.

[0086] In solutions conforming to the Advanced Microcontroller Bus Architecture (AMBA), the software reset write request signal WR is generated in response to an APB (Advanced Peripheral Bus) transaction, and the auxiliary clock signal SCLK can be synchronized with the master system clock PCLK (therefore, the clock signal SCLK can be synchronized with the clock signal applied to the software reset register 60).

[0087] It was observed that the difference between the self-excited clock FCLK and the main system clock PCLK is that the self-excited clock FCLK runs continuously, while the main system clock PCLK may be stopped or turned on under certain conditions.

[0088] Similar to the falling edge detection circuit 210, the rising edge detection circuit 220 is configured to assert an rising edge signal RE for a full clock cycle duration in response to the detection of a rising edge on the sample write request signal SWR originating from the flip-flop 250, thereby detecting the assertion of the sample write request signal SWR.

[0089] The flip-flop 221 of the rising edge detection circuit 220 has an input terminal D coupled to the output terminal Q of the flip-flop 250, an output terminal Q coupled to the inverted input of the AND gate 222, a reset terminal R coupled to the reset signal RST, and a clock terminal coupled to the self-oscillating clock FCLK.

[0090] AND gate 222 has another input terminal coupled to the output terminal Q of flip-flop 250, and as an output, i.e. as the result of the AND operation, generates a rising edge signal RE.

[0091] The clock enable circuit 230 is configured to generate an output clock enable signal CE based on the values ​​of the falling edge signal FE and the rising edge signal RE.

[0092] The value of the clock enable signal CE depends on the values ​​of the falling edge signal FE and the rising edge signal RE, defining three cases:

[0093] In the first case, both the falling edge signal FE and the rising edge signal RE are deasserted: the clock enable signal CE retains its value from the previous clock cycle;

[0094] In the second case, the falling edge signal FE is deasserted, while the rising edge signal RE is asserted, and the clock enable signal CE is deasserted to disable the clock signal pointing to the second clock domain 20, i.e., clock strobing is performed; and

[0095] In the third case, the falling edge signal FE is asserted, while the rising edge signal RE is deasserted, and the clock enable signal CE is asserted to enable the clock signal pointing to the second clock domain 20, i.e., the clock strobe is interrupted.

[0096] OR gate 233 receives the falling edge signal FE from falling edge detection circuit 210 and the output signal generated by AND gate 232 as inputs.

[0097] Furthermore, the AND gate 232 receives the rising edge signal RE (which is received at the inverting input terminal) from the rising edge detection circuit 220 and the output signal generated by the flip-flop 231 as inputs.

[0098] The flip-flop 231 has a data input terminal D connected to the output of the OR gate 233, an output terminal Q connected to the inverting input of the AND gate 232, and a set terminal S and a clock terminal respectively coupled to the reset signal RST and the self-oscillating clock FCLK.

[0099] Therefore, in Figure 4 In the arrangement shown, flip-flop 231 samples the output clock enable signal CE so as to provide a sampled value as the output of clock enable circuit 230 when both the falling edge signal FE and the rising edge signal RE are deasserted.

[0100] In fact, as Figure 4 As shown, when both the falling edge signal FE and the rising edge signal RE are deasserted, the value of the clock enable signal CE is sampled by the flip-flop 231 and then fed to the AND gate 232.

[0101] In the example under consideration, the rising edge signal RE is deasserted and received at the inverting input; the final output of AND gate 232 retains the same value as the sampling clock enable signal CE output by flip-flop 231.

[0102] Therefore, the output of AND gate 232 is fed to OR gate 233, which performs an OR operation with the falling edge signal FE. In the example under consideration, the falling edge signal is deasserted (i.e., equal to '0'), so the clock enable signal CE sampled from the previous clock cycle is output by OR gate 233.

[0103] exist Figure 4 In the implementation, in response to the falling edge signal FE being deasserted and the rising edge signal RE being asserted, the AND gate 232 and the OR gate 233 output a value equal to '0'. This is because the rising edge signal RE is received at the inverting input of the AND gate 232, which causes the clock enable signal CE to be equal to '0'.

[0104] Similarly, when the falling edge signal FE is asserted and the rising edge signal RE is deasserted, the outputs of AND gate 232 and OR gate 233 are equal to '1'. This is because the falling edge signal FE is equal to '1' and it is received at the input of OR gate 233, which causes the clock enable signal CE to be equal to '1'.

[0105] Synchronizer 240 is provided to facilitate full operation of falling edge detection circuit 210 when the software reset signal SR is asynchronously asserted or deasserted (i.e., asserted or deasserted at a time between the rising and falling edges of the system clock).

[0106] To this end, synchronizer 240 has an input terminal D coupled to the software reset signal SR, a reset terminal R coupled to the reset signal RST, a clock terminal coupled to the self-oscillating clock FCLK, and an output terminal Q coupled to the falling edge detection circuit 210, which is specifically coupled to the input terminal D of the flip-flop 211 and the inverting input terminal of the AND gate 212. As previously described, in this case, synchronizer 240 also outputs a synchronized (e.g., delayed) copy of the software reset signal SR, which is received at input terminal D of synchronizer 240. In various possible implementations, synchronizer 240 introduces a two-clock-cycle delay.

[0107] As described above, the synchronizer circuit 240 may include two cascaded flip-flops, i.e., the output terminal of the first flip-flop is coupled to the input terminal of the second flip-flop, wherein the first flip-flop samples the input signal from the source clock domain (i.e., the software reset signal SR), and the second flip-flop samples the synchronous (e.g., delayed) signal using the destination clock, thereby enabling the output of the second flip-flop to be safely used in the destination clock domain.

[0108] For reference Figure 3 The first implementation of the reset domain crossover circuit 100 shown can be observed, in combination with Figure 4 The second implementation of the described domain crossover circuit 200 advantageously solves the problem related to... Figure 3 Some issues related to the first implementation of the reset domain cross circuit 100 shown.

[0109] Figure 4The flip-flop 250 added to the reset domain crossover circuit 200 helps sample the write request signal WR originating from the conversion decoding circuit 50, which operates at a frequency determined by the auxiliary clock signal SCLK. Therefore, the reset signal SR is generated before the master system clock PCLK, received as the auxiliary clock signal SCLK, is disabled.

[0110] Such as combination Figure 3 The first implementation of the reset domain crossover circuit 100 discussed here. Figure 4 The implementation also benefits from the self-oscillating clock FCLK having a frequency higher than or equal to the main system clock PCLK frequency, ensuring proper operation. Figure 4 Compared to the implementation, Figure 4 The implementation has negligible die area overhead.

[0111] Figure 5 A microcontroller circuit 300 including a reset domain crossover circuit 100 according to the solution described herein is shown by way of example.

[0112] In the example under consideration, the microcontroller 300 includes a processor 334 coupled to a main system bus 330, a peripheral bus 332, and an interface circuit 331 coupled to the main system bus 330 and the peripheral bus 332.

[0113] In embodiments involving an Advanced Microcontroller Bus Architecture (AMBA), the main system bus 330 may be an Advanced High-Performance Bus (AHB), while the peripheral bus 332 may be an Advanced Peripheral Bus (APB).

[0114] Peripheral bus 332 is coupled to register group 320, which includes software reset register 60. Register group 320 is further coupled to clock / reset control circuitry 310, which receives write request signal WR and software reset signal SR from register group 320, wherein delay unit 333 is provided along the path carrying software reset signal SR.

[0115] In various embodiments, the microcontroller 300 may include multiple IP (intellectual property) cores (i.e., reusable units of logic, cell or integrated circuit layout design belonging to a particular party), such as a first IP core 341 and a second IP core 342.

[0116] In the example shown, the first IP core is included in the source reset domain 10 because it receives clock signal CLK1 and reset signal RST1 from the clock / reset control circuit 310, while the second IP core is included in the destination reset domain 20 because it receives clock signal CLK2 and reset signal RST2 from the clock / reset control circuit 310. Specifically, the first IP core 341 can generate output data directed to the second IP core 342. Typically, the first IP core 341 and the second IP core 342 can be considered to respectively include a first timing circuit 70 (e.g., a first flip-flop 70) and a second timing circuit 80 (e.g., a second flip-flop 80). Since the two IP cores are included in different reset domains and coupled to each other, the clock / reset control circuit 310 must correctly perform clock gating and / or clock forwarding to ensure the correct operation of the microcontroller 300. This clock / reset control circuit 310 can be configured (in a manner known to those skilled in the art) to manage the generation and / or gating of clock and reset signals in the microcontroller circuit 300.

[0117] Figure 6 This is an exemplary detailed circuit diagram of the clock / reset control circuit 310.

[0118] As shown in the figure, the clock / reset control circuit 310 receives one or more clock signals (e.g., clock signals generated by the phase-locked loop LCLK and / or clock signals generated by the oscillator OCLK), a software reset write request signal WR, and a software reset signal SR as inputs, and generates one or more system clock signals FCLK and one or more reset signals RST1, RST2 (i.e., a reset signal for each reset domain included in the microcontroller 300) as outputs.

[0119] In various possible implementations, the clock / reset control circuit 310 includes a clock control circuit 350, a reset control circuit 360, and a reset domain crossover circuit 100 implemented according to the aforementioned solution.

[0120] Furthermore, the clock control circuit 350 is configured to perform clock signal forwarding or gating throughout the microcontroller circuit 300. For this purpose, the clock control circuit 350 includes a glitch-free multiplexer 351. This facilitates dynamic switching of clock sources (e.g., in this case, switching from LCLK to OCLK and vice versa) without generating glitches on the clock output.

[0121] Multiplexer 351 receives one or more clock signals (e.g., phase-locked loop clock LCLK and oscillator clock OCLK) as inputs and generates a system clock signal FCLK as output. The system clock signal FCLK, together with the clock enable signal CE generated by the reset domain crossover circuit 100, is received by clock gating circuit 352. In various possible implementations, the provided clock gating circuit 352 corresponds to the previously described clock gating unit 93, which can be implemented using AND gates.

[0122] The reset domain crossover circuit 100 receives the system clock signal FCLK, the write request signal WR, and the software reset signal SR as inputs, and generates a clock enable signal CE as output. Therefore, the clock gating circuit 352 generates the system clock signal FCLK as output, which is ultimately divided by the frequency divider 353.

[0123] The reset control circuit 360 includes an AND gate 361, which receives a software reset signal SR and a reset signal RST2 at its inverting input terminal as inputs. Therefore, the AND gate 361 generates a reset signal RST1 (i.e., a reset signal pointing to the source reset domain 10) as an output.

[0124] AND gate 361 generates a first reset signal RST1 in response to the software reset signal SR being de-asserted and the second reset signal RST2 being asserted. Therefore, the arrangement of the clock / reset control circuit 310 described herein advantageously provides correct timing of the reset signal on the microcontroller circuit 300, as well as correct timing of the clock gating.

[0125] In summary, the solution described in this paper provides a hardware-implemented closed-loop gating of the clock signal that, in response to the deassertion of the software reset signal in the source domain, re-enables the clock signal pointing to the destination clock domain.

[0126] Gating the clock for the flip-flops in the destination reset domain during the reset of the source reset domain can handle possible metastabilities in the set / hold phase, since the destination flip-flops are not receiving a clock when the source is reset. The hardware module (i.e., the reset domain crossover circuit (100 or 200) described herein) disables the clock for the destination reset domain in response to a software reset in the source reset domain, and then re-enables the clock only after the reset propagates from the source reset domain.

[0127] Even with delay units along the reset signal path, the closed-loop structure of this solution advantageously prevents reset domain crossover issues across the entire area of ​​the integrated circuit die. In contrast to other well-known open-loop solutions, where the number of clock cycles for the destination clock to be gated is typically determined considering the worst-case scenario, the closed-loop reset domain crossover circuit 100 advantageously allows for speed savings because the clock gating time varies accordingly with the reset delay, thus avoiding harmful time losses.

[0128] Without prejudice to the fundamental principles, details and embodiments may vary, even significantly, from what has been described by example only, without departing from the scope of protection.

[0129] The scope of protection is determined by the appended claims.

Claims

1. A circuit comprising: a first sequential circuit device configured to operate in response to a first clock signal in a first clock domain; a second sequential circuit device configured to operate in response to a second clock signal in a second clock domain; a translation decode circuit device configured to generate a software reset write request signal; a software reset register coupled to the translation decode circuit device and configured to produce a software reset signal in response to the software reset write request signal from the translation decode circuit device; a reset domain crossing circuit device configured to de-assert a clock enable signal in response to receiving the software reset write request signal from the translation decode circuit device and to assert the clock enable signal in response to a falling edge detected on the software reset signal from the software reset register; and a clock gating cell coupled to the reset domain crossing circuit device and configured to disable the second clock signal of the second sequential circuit device in response to the clock enable signal being de-asserted by the reset domain crossing circuit device.

2. The circuit of claim 1, wherein the reset domain crossing circuit device comprises a clock enable circuit configured to: de-assert the clock enable signal in response to receiving the software reset write request signal from the translation decode circuit device in the absence of a falling edge detected on the software reset signal from the software reset register; and assert the clock enable signal in response to a falling edge detected on the software reset signal from the software reset register in the absence of a software reset write request signal from the translation decode circuit device.

3. The circuit of claim 2, wherein the clock enable circuit in the reset domain crossing circuit device comprises: a flip-flop configured to produce the clock enable signal at an output terminal of the flip-flop; and a multiplexer configured to apply a multiplexed input signal selected based on the reset write request signal from the translation decode circuit device to the flip-flop and a falling edge signal indicating a falling edge detected on the software reset signal from the software reset register, wherein a value of the multiplexed input signal is selected from: a first constant value; a second constant value different from the first constant value; and a value of the clock enable signal produced by the flip-flop.

4. The circuit of claim 1, wherein the reset domain crossing circuit device comprises: a sample flip-flop configured to receive the software reset write request signal and produce a sampled write request signal; a rising edge detection circuit coupled to the sample flip-flop and configured to produce a rising edge signal indicating a rising edge detected in the sampled write request signal; and a respective clock enable circuit configured to: de-assert the clock enable signal in response to receiving the rising edge signal; and assert the clock enable signal in response to a falling edge detected on the software reset signal from the software reset register. ​ ​ ​ ​ 5. The circuit of claim 4, wherein the respective clock enable circuitry comprises: an OR gate configured to generate the clock enable signal based on a falling edge detected on the software reset signal from the software reset register and an output from an AND gate, inputs of the AND gate receiving: a logical inversion of the rising edge signal; and an output from a respective flip-flop to which the clock enable signal is applied.

6. The circuit of claim 4, wherein the rising edge detection circuitry comprises: a rising edge detection flip-flop to which the sampled write request signal is applied; and a rising edge detection AND gate to which the sampled write request signal and a logical inversion of an output of the rising edge detection flip-flop are applied.

7. The circuit of claim 1, wherein the reset domain crossing circuitry comprises falling edge detection circuitry, the falling edge detection circuitry comprising a falling edge detection circuit configured to detect a falling edge of a software reset signal, wherein the falling edge detection circuitry comprises: a falling edge detection flip-flop to which the software reset signal is applied; and a falling edge detection AND gate to which a logical inversion of the software reset signal and an output of the falling edge detection flip-flop are applied.

8. The circuit of claim 1, wherein: the reset domain crossing circuitry comprises a synchronizer configured to receive the software reset signal and generate a synchronized copy of the software reset signal; and the reset domain crossing circuitry is configured to process the software reset signal based on the synchronized copy of the software reset signal.

9. The circuit of claim 8, wherein the synchronizer comprises a two-stage synchronizer, the two-stage synchronizer comprising a cascaded arrangement of a first synchronizer flip-flop and a second synchronizer flip-flop.

10. A system comprising the circuit of claim 1, wherein the system comprises: a first IP core comprising the first timing circuitry configured to operate under the first clock signal; a second IP core configured to operate under the second clock signal; and a register bank comprising the software reset register, the software reset register coupled to the translation decode circuitry and configured to generate the software reset signal in response to the software reset write request signal from the translation decode circuit. ​ ​ ​ ​

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