Memory control method and storage device

Abstract

The application relates to the technical field of storage control, in particular to a memory control method, which comprises the following steps: in response to a read request from a host system, a target logical address is acquired; based on historical access information, a data access mode associated with the target logical address is determined in real time, wherein the data access mode at least comprises a continuous mode, a random mode and a hotspot mode; according to the determined data access mode, a data prefetch strategy and a flash translation layer query strategy matched with the access mode are triggered; based on the data prefetch strategy and the flash translation layer query strategy, target data is acquired from a memory module; and according to a predetermined resource management strategy, cache resources and input / output bandwidth are scheduled, and the target data is returned to the host system. The accuracy of data prefetching and the utilization rate of cache are improved.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a memory control method and storage device. Background Technology

[0002] NAND Flash is a non-volatile storage medium widely used in storage products such as Secure Digital Cards (SD cards), Embedded Multi Media Cards (eMMC), Universal Flash Storage (UFS), and Solid State Drives (SSDs). Because NAND Flash cannot be directly overwritten, data updates are typically not performed by directly overwriting the original physical address; instead, the updated data is written to a new physical address.

[0003] To improve read performance, storage devices (such as SSDs and eMMC) are typically configured with a cache to temporarily store frequently accessed data, thereby improving read performance. However, existing cache prefetch strategies mostly use static rule-based methods such as sequential prefetching and fixed-depth prefetching, whose prefetching timing and depth are fixed and cannot adapt to the dynamically changing data access patterns in real-world applications.

[0004] For example, in random access scenarios, sequential prefetching strategies may still continuously trigger data loading for subsequent consecutive addresses, resulting in a large amount of invalid prefetched data. This invalid prefetched data not only occupies valuable cache space and crowds out the opportunity for potentially useful data to reside, but also consumes additional cache bandwidth and cache space, thus causing problems such as blind prefetching timing, low resource utilization efficiency, and poor scenario adaptability. Summary of the Invention

[0005] This application aims to address the problems of traditional cache prefetching strategies. First, relying on a fixed trigger threshold results in a low prefetch hit rate in scenarios dominated by random input / output (I / O). Second, invalid prefetching operations consume a large amount of cache bandwidth and space, causing frequently accessed useful data to be prematurely evicted, thus increasing read latency. Third, a single prefetching strategy cannot adapt to mixed load scenarios, resulting in significant performance fluctuations.

[0006] To address the aforementioned technical problems, embodiments of this application provide a memory control method applied to a storage device including a memory module and a memory controller. The memory module includes multiple planes, each plane including multiple blocks, and each block including multiple pages. The method includes: in response to a read request from a host system, obtaining a target logical address; determining in real-time a data access pattern associated with the target logical address based on historical access information, wherein the data access pattern includes at least a continuous mode, a random mode, and a hotspot mode; triggering a data prefetching strategy and a flash translation layer query strategy matching the determined data access pattern; obtaining target data from the memory module based on the data prefetching strategy and the flash translation layer query strategy; and scheduling cache resources and input / output bandwidth according to a predetermined resource management strategy, and returning the target data to the host system.

[0007] In one implementation, the step of determining the data access pattern associated with the target logical address in real time based on historical access information includes: maintaining a cyclic history structure for sequentially recording the logical addresses of the most recent input / output operations; and executing a first identification process, a second identification process, and a third identification process in parallel. The first identification process calculates a weighted moving average based on the offset sequence of logical addresses in the cyclic history structure to assess access continuity; the second identification process calculates a deterministic metric based on the distribution of logical addresses in the cyclic history structure to assess access randomness; and the third identification process determines the access frequency of the target logical address under an attenuation model based on a probabilistic frequency statistics structure.

[0008] In one implementation, in the first identification process, the weighted moving average assigns a higher weight to the recent logical address offset than to the distant offset.

[0009] In one implementation, the weighted moving average is an exponentially weighted moving average.

[0010] In one embodiment, the deterministic metric in the second identification process is Shannon entropy.

[0011] In one embodiment, in the third identification process, the probabilistic frequency statistics structure is a count-minimum sketch, and the decay model is an exponential decay model.

[0012] In one implementation, after executing the first identification process, the second identification process, and the third identification process in parallel, the method further includes: obtaining a continuous confidence level generated by the first identification process, a random confidence level generated by the second identification process, and a hotspot confidence level generated by the third identification process, wherein the hotspot confidence level is generated based on the updated decayed access frequency; judging the continuous confidence level, the random confidence level, and the hotspot confidence level according to a preset priority arbitration rule to output the final data access pattern; wherein, in the third identification process, the step of determining the access hotspot based on the probabilistic frequency statistical structure includes: for the target logical address, multiplying the multiple counter values ​​located by multiple hash functions in the count-minimum sketch by a decay factor and then adding 1 to obtain and update their decayed access frequency.

[0013] In one implementation, the preset priority arbitration rule is as follows: if the hotspot confidence exceeds a first threshold, it is determined to be the hotspot mode; if it is not determined to be the hotspot mode, and the continuous confidence exceeds a second threshold while the random confidence is lower than a third threshold, it is determined to be the continuous mode; if it is not determined to be the hotspot mode or the continuous mode, and the random confidence exceeds a fourth threshold, it is determined to be the random mode.

[0014] In one implementation, the step of triggering a data prefetching strategy and a flash translation layer query strategy matching the access mode includes: if the data access mode is determined to be a continuous mode, then a prefetching operation is initiated, wherein the prefetching depth of the prefetching operation is dynamically calculated based on an evaluation value of the current access continuity strength, and a mapping relationship merging query is initiated to the flash translation layer for a continuous logical address sequence starting from the target logical address; if the data access mode is determined to be a random mode, then the prefetching operation is prohibited, and only a single mapping relationship for the target logical address is queried from the flash translation layer; if the data access mode is determined to be a hotspot mode, then the data corresponding to the target logical address is marked as a high-priority cache item, and maintained using a protected cache management mechanism.

[0015] In one implementation, the prefetch depth is determined by: calculating an initial depth based on the assessment value of the current access continuity strength; applying a smoothing filter to the initial depth to suppress short-term drastic fluctuations in the depth value; and limiting the filtered depth value between a preset minimum depth value and a preset maximum depth value to obtain the prefetch depth.

[0016] In one implementation, the mapping relationship merging query includes sending a query request to the flash translation layer, the request carrying the target logical address and a subsequent logical address range determined according to the prefetch depth; and receiving a list of physical addresses corresponding to all logical addresses within the range returned by the flash translation layer.

[0017] In one implementation, the protected cache management mechanism includes:

[0018] Define a separate hotspot data protection zone within the cache space;

[0019] Data marked as high-priority cache items are stored in the hot data protection area;

[0020] Based on access frequency and combined with a time decay factor, data items within the hotspot data protection zone are replaced and managed.

[0021] In one implementation, the step of scheduling cache resources and input / output bandwidth according to a predetermined resource management strategy and returning the target data to the host system includes:

[0022] Based on the type and urgency of input / output commands, assign them to different priority queues;

[0023] Allocate a corresponding bandwidth resource quota to each priority queue, wherein the bandwidth quota allocated for prefetching operations is dynamically reduced based on the real-time resource utilization of higher priority queues.

[0024] In one implementation, the bandwidth resource quota is implemented through a token bucket mechanism, whereby the token generation rate allocated for prefetching operations is negatively correlated with the token consumption rate of synchronous write operations, asynchronous write operations, and host read operations in the most recent statistical period.

[0025] In one embodiment, the method further includes:

[0026] Within a sliding window of configurable duration, the effective hit rate of statistical prefetching operations is calculated.

[0027] Compare the effective hit rate with a range of expected hit rates;

[0028] Based on the error signal generated by the comparison results, at least one control parameter related to determining the data access mode or triggering the data prefetching strategy is dynamically adjusted.

[0029] In one implementation, a conservative strategy is adopted when the storage device is in the initial startup phase or when historical access information is insufficient. The conservative strategy includes setting the prefetch depth to a minimum value or temporarily disabling prefetch operations.

[0030] In one implementation, when there is a logical address without a valid mapping in the continuous logical address sequence queried for a prefetch operation, the prefetch operation for the unmapped logical address is ignored, and the event is recorded for storage device adaptive optimization.

[0031] In one embodiment, embodiments of this application further provide a storage device including a connection interface, a memory module, and a memory controller. The memory controller includes error checking and correction circuitry, a buffer memory, and memory control circuitry, electrically connected to the connection interface and the memory module. The memory module includes multiple planes, each plane including multiple blocks, each block including multiple pages, and the memory controller is configured to execute the memory control method described in any of the preceding embodiments.

[0032] Based on the above technical solution, the memory control method of this disclosure includes: in response to a read request from a host system, obtaining a target logical address; determining in real time a data access mode associated with the target logical address based on historical access information, wherein the data access mode includes at least a continuous mode, a random mode, and a hotspot mode; triggering a data prefetching strategy and a flash translation layer query strategy matching the determined data access mode; based on the data prefetching strategy and the flash translation layer query strategy, wherein for the continuous mode, a depth-dynamically adjustable prefetching and mapping relationship merging query is performed, for the random mode, prefetching is disabled, and for the hotspot mode, protected cache management is adopted; obtaining target data from the memory module; and according to a predetermined resource management strategy, scheduling cache and I / O bandwidth based on a priority queue and a dynamic bandwidth quota mechanism, and returning the target data to the host system. This synergistically improves prefetching accuracy and cache utilization, and enhances the adaptive capability of the storage device. Attached Figure Description

[0033] The above and other features of this application will be further explained below in conjunction with the accompanying drawings and their detailed description. It should be understood that these drawings only illustrate several exemplary embodiments according to this application and should not be considered as limiting the scope of protection of this application. Unless otherwise specified, the drawings are not necessarily to scale, and similar reference numerals denote similar parts.

[0034] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of this application;

[0035] Figure 2 This is a schematic diagram of a memory controller shown according to an embodiment of this application;

[0036] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of this application;

[0037] Figure 4 This is an overall flowchart of the memory control method according to an embodiment of this application;

[0038] Figure 5 This is a flowchart illustrating the identification and processing mode according to an embodiment of this application;

[0039] Figure 6 This is a flowchart illustrating a differentiated policy triggering based on access patterns, according to an embodiment of this application.

[0040] Figure 7 This is a schematic diagram of priority-based I / O queues and bandwidth scheduling according to an embodiment of this application. Detailed Implementation

[0041] The following detailed description incorporates the accompanying drawings, which form part of this specification. The illustrative embodiments mentioned in the specification and drawings are for illustrative purposes only and are not intended to limit the scope of protection of this application. Those skilled in the art will understand that many other embodiments can be employed, and various changes can be made to the described embodiments without departing from the spirit and scope of this application. It should be understood that the various aspects of this application illustrated herein can be arranged, substituted, combined, separated, and designed in many different configurations, all of which are included in this application.

[0042] The technical solution and objectives of this application will be further explained below with reference to the accompanying drawings.

[0043] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of this application. Please refer to... Figure 1 The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, tablet computer, laptop computer, desktop computer, industrial computer, game console, server, or computer system installed in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host system 11 is not limited to these. In addition, the storage device 12 may include a solid-state drive (SSD), a universal flash storage device (UFS), a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0044] Storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect storage device 12 to host system 11. For example, connection interface 121 may support embedded multi-media card (eMMC), universal flash storage (UFS), peripheral component interconnect express (PCI Express), non-volatile memory express (NVM express), Serial Advanced Technology Attachment (SATA), universal serial bus (USB), or other types of connection interface standards. Therefore, storage device 12 can communicate with host system 11 (e.g., exchange signals, instructions, and / or data) via connection interface 121.

[0045] Memory module 122 is used to store data. For example, memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also known as threshold voltage). For example, memory module 122 may include a Single Level Cell (SLC) NAND flash memory module, a Multi Level Cell (MLC) NAND flash memory module, a Triple Level Cell (TLC) NAND flash memory module, a Quad Level Cell (QLC) NAND flash memory module, and / or other memory modules with the same or similar characteristics.

[0046] Memory controller 123 is connected to connection interface 121 and memory module 122. Memory controller 123 can be considered the control core of storage device 12 and is used to control storage device 12. For example, memory controller 123 can be used to control or manage the overall or partial operation of storage device 12. For example, memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device or combination of these devices. In one embodiment, memory controller 123 may include flash memory controller.

[0047] The memory controller 123 can send instruction sequences to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited in this application. The memory module 122 can receive instruction sequences from the memory controller 123 and access the memory cells inside the memory module 122 according to these instruction sequences.

[0048] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of this application. Please refer to... Figure 1 and Figure 2 The memory controller 123 includes a host system interface 21, a memory interface 22, and a memory control circuit 23. The host system interface 21 is used to connect to the host system 11 via the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0049] Memory control circuitry 23 is connected to host system interface 21 and memory interface 22. Memory control circuitry 23 can be used to control or manage the overall or partial operation of memory controller 123. For example, memory control circuitry 23 can communicate with host system 11 via host system interface 21 and access memory module 122 via memory interface 22. For example, memory control circuitry 23 may include control circuitry such as embedded controllers or microcontrollers. In the following embodiments, the description of memory control circuitry 23 is equivalent to the description of memory controller 123.

[0050] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuitry 23 and is used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122. In particular, the logical-to-physical mapping table and its higher-level address management unit are typically resident or cached in the buffer memory 24 to support high-speed access and updates.

[0051] In one embodiment, the memory controller 123 may further include an error checking and correction circuit 25. The error checking and correction circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data integrity. For example, the error checking and correction circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code. In one embodiment, the memory controller 123 may also include other types of circuit modules (e.g., power management circuits), which are not limited in this application.

[0052] In one embodiment, the memory controller 123 may further include a power management circuit 26. The power management circuit 26 is connected to the memory control circuit 23 and is used to control the power supply to the storage device 10.

[0053] Figure 3 This is a schematic diagram illustrating a memory management module according to an embodiment of this application. Please refer to... Figures 1 to 3 The memory module 122 includes multiple physical units 301(1)-301(B). Each physical unit includes multiple storage units for non-volatile data storage.

[0054] In one embodiment, an entity unit may include an entity programming unit. In one embodiment, an entity programming unit is also referred to as an entity programming unit. In one embodiment, an entity programming unit may be considered as an entity page.

[0055] In one embodiment, an entity programming unit may include multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit can be adjusted according to practical needs, and this application is not limited thereto. For example, the storage capacity of an entity programming unit may be 16 kilobytes, and this application is not limited thereto.

[0056] In one embodiment, a physical programming unit is the smallest unit of synchronously written data in memory module 122. For example, when performing a programming operation (also called a write operation) on a physical programming unit to write data to that physical programming unit, multiple memory cells in that physical programming unit can be synchronously programmed to store the corresponding data. For example, when programming a physical programming unit, a write voltage can be applied to that physical programming unit to change the threshold voltage of at least some of the memory cells in that physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in that memory cell.

[0057] In one embodiment, an entity erasure unit may include multiple entity programmatic units. In another embodiment, an entity erasure unit may be considered as an entity block.

[0058] In one embodiment, multiple programmed units in a physical erase unit can be erased simultaneously. For example, when an erase operation is performed on a physical erase unit, an erase voltage can be applied to multiple programmed units in this physical erase unit to change the threshold voltage of at least some of the memory cells in these programmed units. By performing an erase operation on a physical erase unit, the data stored in this physical erase unit can be erased.

[0059] In one embodiment, the memory control circuit 23 can logically associate entity units 301(0)-301(A) and 301(A+1)-301(B) with the data area 31 and the idle area 32, respectively. Entity units 301(0)-301(A) in the data area 31 all store data (also referred to as user data) from the host system 11. For example, any entity unit in the data area 31 can store valid data and / or invalid data. In addition, entity units 301(A+1)-301(B) in the idle area 32 do not store any data (e.g., valid data).

[0060] In one embodiment, if a certain entity unit does not store valid data, this entity unit can be associated with the free area 32. Furthermore, entity units in the free area 32 can be erased to clear the data in that entity unit. In one embodiment, entity units in the free area 32 are also referred to as idle entity units. In one embodiment, the free area 32 is also referred to as the free pool.

[0061] In one embodiment, when data needs to be stored, the memory control circuit 23 can select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data into the selected physical units. After the data is stored into this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be used cyclically between the data area 31 and the idle area 32.

[0062] In one embodiment, the memory control circuit 23 may be configured with multiple logic units 302(0)-302(C) to map physical units (i.e., physical units 301(0)-301(A)) in the data area 31. For example, a logic unit may correspond to a logical block address (LBA) or other logical management unit. A logic unit may be mapped to one or more physical units.

[0063] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0064] In one embodiment, the memory control circuit 23 may record the mapping relationship between logical units and physical units in at least one management table (also known as a logic-to-physical mapping table, or L2P table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing, or erasing based on the information in this management table (i.e., the logical address to physical address mapping table).

[0065] In one embodiment, such as Figure 4 As shown, Figure 4 This is an overall flowchart of a memory control method according to an embodiment of this application. The method is applied to a storage device 12 including a memory module 122, and aims to improve shu read performance through cache prefetch management. A memory controller 123 (or memory control circuitry 23) is configured to execute this method. The method includes the following steps:

[0066] S401: In response to a read request from the host system, parse the request to obtain the target logical address.

[0067] S402: Based on maintained historical access information, perform real-time analysis and determine the data access pattern associated with the target logical address. The data access pattern includes at least continuous mode, random mode, and hotspot mode to adapt to different I / O behavior characteristics of the host system 11.

[0068] S403: Based on the determined specific data access pattern, trigger the data prefetching strategy and Flash Translation Layer (FTL) query strategy that precisely match the access pattern. For example, the amount of data prefetched and the method of querying the FTL mapping table are different for different patterns. S404: Based on the data prefetching strategy and the flash translation layer query strategy, obtain the physical address from the FTL and read the target data from the memory module 122, which may also include prefetched adjacent data;

[0069] S405: Based on the predetermined resource management strategy, schedule the limited cache space (resources) and input / output bandwidth, and return the target data to the host system 11 while ensuring the quality of service for high-priority operations.

[0070] For example, in continuous mode, the continuous mode prefetch and query strategy is triggered, data is retrieved from memory module 122, bandwidth and cache are allocated according to resource management strategy, and the target data is returned to host system 11. In random mode, the random mode strategy (prefetch disabled) is triggered, a single mapping is queried from FTL, data is retrieved from memory module 122, bandwidth and cache are allocated according to resource management strategy, and the target data is returned to host system 11. In hotspot mode, the hotspot mode strategy (protected cache) is triggered, data is placed in a protected area, data is retrieved from memory module 122, bandwidth and cache are allocated according to resource management strategy, and the target data is returned to host system 11.

[0071] By integrating access pattern recognition, prefetching decision-making, FTL collaborative querying, and resource scheduling, storage device 12 can adapt to different workloads.

[0072] In one embodiment, such as Figure 5 As shown, Figure 5 Flowchart for identifying processing modes. Figure 5 In this method, the method is applied to a storage device 12 that includes a memory module 122. A memory controller 123 (or memory control circuitry 23) is configured to execute this method. Figure 5As shown, the memory control circuit 23 first reads the logical address sequence from the circular history buffer, and then initiates the first, second, and third identification processes in parallel. The first identification process calculates a weighted moving average of the logical address offsets to assess continuity; the second identification process statistically analyzes the logical address distribution and calculates Shannon entropy to assess randomness; the third identification process determines access popularity using a count-minimum sketch combined with an exponential decay model. The three processes output continuity confidence, randomness confidence, and hotspot confidence, respectively, and input them to the confidence arbitrator. The arbitrator makes a final determination based on preset priority rules and outputs a label for continuous mode, random mode, hotspot mode, or conservative mode.

[0073] In one embodiment, a step is also proposed to determine the data access pattern associated with the target logical address in real time based on historical access information, including: maintaining a cyclic history structure for sequentially recording the logical addresses of the most recent input / output operations; and executing a first identification process, a second identification process, and a third identification process in parallel. The first identification process calculates a weighted moving average based on the offset sequence of logical addresses in the cyclic history structure to evaluate access continuity; the second identification process calculates a deterministic metric based on the distribution of logical addresses in the cyclic history structure to evaluate access randomness; and the third identification process determines the access frequency of the target logical address under an attenuation model based on a probabilistic frequency statistics structure.

[0074] Specifically, the circular history structure can be a ring buffer set in the buffer memory 24. Whenever an I / O request from a host system 11 is processed, its logical address is recorded in this buffer, overwriting the oldest record, thus always maintaining the trajectory of the most recent N (e.g., 256) accesses. The first, second, and third identification processes are executed in parallel as three independent tasks. They share reading this buffer but use different mathematical tools for analysis: the first identification process focuses on the trend of address changes; the second identification process focuses on the degree of disorder in address distribution; and the third identification process focuses on the intensity of repeated access to a single address. This parallel design reduces the latency of pattern recognition, enabling real-time decision-making. By extracting the three key features of continuity, randomness, and frequency in parallel, the data storage system 10 / storage device 12 can adapt to mixed access loads more comprehensively and accurately.

[0075] In one embodiment, the first identification process further proposes that the weighted moving average assigns a higher weight to recent logical address offsets than to earlier offsets. This means that when calculating the weighted moving average reflecting access trends, the storage device 12 places more emphasis on recently occurring address offsets and assigns less weight to earlier historical offsets. For example, a smoothing factor α (0 < α < 1) is used in the calculation, with the weight of the new observation being α and the weight of the old average being (1-α). This design makes trend judgment more sensitive to recent changes in access patterns, enabling it to quickly capture the turning point where the access pattern changes from random to continuous (or vice versa), thereby adjusting the prefetch strategy and improving the response speed of the storage device 12.

[0076] In one embodiment, the weighted moving average is proposed to be an exponentially weighted moving average (EWMA). The exponentially weighted moving average is a preferred and efficient implementation of the weighted moving average. The weight of each historical offset decays exponentially with the event interval. Its calculation is incremental; only the previous average value needs to be retained. When a new offset ΔLBA_t arrives, the new average value EWMA_t is updated using the formula EWMA_t = α * ΔLBA_t + (1-α) * EWMA_{t-1}, where α is a smoothing factor. This computational characteristic with such time complexity is very suitable for embedded products with high-speed I / O, achieving smoothing and continuous tracking of access trends without increasing computational overhead, laying the foundation for stable determination of continuous patterns.

[0077] In one embodiment, a second identification process is proposed, in which the deterministic metric is Shannon entropy. Shannon entropy is used to quantify access randomness: first, the probability of occurrence of each unique logical address in the recent access sequence is statistically analyzed; then, the entropy value is calculated according to the Shannon entropy formula. The calculated entropy value is compared with a preset threshold to scientifically determine whether the current access pattern belongs to a random pattern. Specifically, Shannon entropy is a classic indicator in information theory for measuring information uncertainty; this application applies it to quantify the randomness of logical address access sequences. Considering the recent N LBAs as a source, the frequency P_i of each different LBA value is statistically analyzed; then the entropy value H is equal to a negative sum of all P_i multiplied by log2(P_i).

[0078] A higher entropy value indicates a more uniform and unpredictable distribution of LBAs, meaning stronger randomness; a lower entropy value indicates that access may be concentrated in a few LBAs or exhibit regularity (such as continuity). By setting an entropy threshold (e.g., 0.7), strong random access patterns can be effectively distinguished. This embodiment utilizes Shannon entropy, a mathematical tool, to transform the abstract concept of "randomness" into a precisely calculable and comparable value, providing a quantifiable basis for the decision to "disable prefetching" and avoiding misjudgments.

[0079] In one embodiment, a third identification process is proposed where the probabilistic frequency statistical structure is a Count-Min Sketch (CMS), and the decay model is an exponential decay model. A Count-Min Sketch is a probabilistic frequency statistical structure that uses multiple hash functions and a counting array to approximate the frequency of statistical data streams with minimal memory overhead and extremely high speed. When a target logical address is input, it is mapped to k different counters in the sketch through multiple (e.g., k) hash functions. For each of the k counter values ​​corresponding to the address, it is first multiplied by (1 - λ) and then incremented by 1 to obtain and update the decayed new frequency. This achieves dynamic hotspot identification and prevents obsolescence. Specifically, in this embodiment, the CMS is used to track the access frequency of each address in the entire LBA address space. To prevent obsolescence, an exponential decay model is introduced: each time an LBA is accessed, instead of simply incrementing the corresponding count in the CMS, an update is performed; the new count = old count * (1 - λ) + 1, where λ is a small decay factor (e.g., 0.01). In this way, the count of "hot spots" that have not been accessed for a long time will decrease exponentially over time, while the count of currently active "hot spots" will remain high. This combination allows hot spot identification to dynamically reflect the latest access situation, prevents historical hot spots from occupying cache resources for a long time, and improves the timeliness and fairness of hot spot data management.

[0080] In one embodiment, after the first, second, and third identification processes are executed in parallel, the method further includes: obtaining the continuous confidence score generated by the first identification process, the random confidence score generated by the second identification process, and the hotspot confidence score generated by the third identification process, respectively, wherein the hotspot confidence score is generated based on the updated decayed access frequency; judging the continuous confidence score, random confidence score, and hotspot confidence score according to a preset priority arbitration rule to output the final data access pattern; wherein, in the third identification process, the step of determining the access hotspot based on the probabilistic frequency statistical structure includes: for the target logical address, multiplying the multiple counter values ​​located by multiple hash functions in the count-minimum sketch by a decay factor and then adding 1 to obtain and update its decayed access frequency. Since the three identification processes are executed in parallel, the same I / O request may be identified by multiple processes (for example, an address may be both a hotspot and in a continuous stream). This embodiment introduces "confidence" quantization and "arbitration rules" to resolve conflicts. Each identification process not only outputs a binary "yes / no" result but also a confidence score between 0 and 1, indicating the likelihood that the access pattern is valid. Then, these confidence scores are comprehensively evaluated according to a pre-defined priority arbitration rule, resulting in a unique and definitive final pattern label. This mechanism ensures the uniqueness of the decision and avoids potential strategy conflicts arising from parallel multi-pattern identification.

[0081] In one embodiment, the aforementioned preset priority arbitration rule is proposed as follows: if the hotspot confidence exceeds a first threshold, it is determined to be a hotspot mode; if it is not determined to be a hotspot mode, and the continuous confidence exceeds a second threshold while the random confidence is lower than a third threshold, it is determined to be a continuous mode; if it is not determined to be a hotspot mode or the continuous mode, and the random confidence exceeds a fourth threshold, it is determined to be a random mode. This arbitration rule clarifies the principle of "hotspot priority". Once an LBA is identified as a hotspot with high confidence, regardless of whether it exhibits continuity, it is prioritized for hotspot data management, because ensuring extremely low access latency for hotspot data is crucial for user experience. If it is not a hotspot, continuity is further judged: only when the continuous confidence is high and the random confidence is low (i.e., not random) is it determined to be a continuous mode, which improves the accuracy of continuous determination and prevents misjudgment in slightly fluctuating sequential flows. If none of the above is satisfied, and the randomness confidence is very high, it is determined to be a random mode. Through this logically clear and hierarchical rule, the parallel identification processing outputs are integrated into a globally optimal decision.

[0082] In one embodiment, such as Figure 6 As shown, Figure 6 This is a flowchart for triggering differentiated strategies based on access patterns. Figure 6In this method, the method is applied to a storage device 12 that includes a memory module 122. A memory controller 123 (or a memory control circuit 23) is configured to perform this method. Figure 6 In this process, the memory control circuit 23 executes distinctly different strategies based on the final mode label output by the arbitrator: continuous mode triggers dynamic prefetching and merge lookup; random mode disables prefetching and performs only a single lookup; and hotspot mode switches to protected cache management. Figure 6 This embodies the core forking logic of strategy execution.

[0083] Specifically, the steps for triggering the data prefetching strategy and flash translation layer query strategy that match the access mode include: if the data access mode is determined to be a continuous mode, a prefetching operation is initiated, and the prefetching depth of the prefetching operation is dynamically calculated based on the evaluation value of the current access continuity strength, and a mapping relationship merging query is initiated to the flash translation layer for a continuous logical address sequence starting from the target logical address; if the data access mode is determined to be a random mode, the prefetching operation is prohibited, and only a single mapping relationship for the target logical address is queried from the flash translation layer; if the data access mode is determined to be a hotspot mode, the data corresponding to the target logical address is marked as a high-priority cache item, and a protected cache management mechanism is used for maintenance.

[0084] This embodiment is the core of implementing the differentiated strategy. For continuous mode, not only is prefetching initiated, but the prefetch depth is also dynamic. Furthermore, the request to the FTL is a one-time query for the mapping of a continuous LBA range, which is called "merged query". For random mode, the strategy is to completely disable prefetching, only querying the current address to maximize the saving of cache bandwidth and space. For hotspot mode, the strategy shifts from prefetching more to protecting existing data by marking it and placing it in a protected area to prevent it from being crowded out by subsequent ordinary data. These three distinct strategies precisely match the essential needs of the three modes, achieving a fundamental shift to on-demand allocation, which is key to improving resource utilization.

[0085] In one embodiment, the prefetch depth is further proposed to be determined by: calculating an initial depth based on an evaluation value of the current access continuity strength; applying a smoothing filter to the initial depth to suppress short-term drastic fluctuations in the depth value; and limiting the filtered depth value between a preset minimum depth value and a maximum depth value to obtain the prefetch depth.

[0086] Specifically, the continuous intensity assessment value can be calculated by the changing trend or difference value of the EWMA value in the first identification process.

[0087] Initial depth:

[0088] Where base is the base depth (e.g., 2), and β is a coefficient. A first-order low-pass filter is applied to D_raw: D_smoothed = γ * D_smoothed_old + (1-γ) * round (D_raw), where γ is the filter factor (e.g., 0.8). Finally, D_smoothed is clamped within the interval [D_min, D_max], for example, [1, 8]. This determination process includes three stages: dynamic calculation, smoothing and stabilization, and boundary protection. Specifically, dynamic calculation allows the depth to vary with the load of the storage device 12; smoothing filtering avoids depth jumps caused by minor I / O fluctuations, making the prefetch commands received by the memory controller 123 more stable; and limiting ensures that the performance of the storage device 12 remains within a controllable range, preventing excessive or invalid prefetches.

[0089] In one embodiment, a mapping relationship merging query scheme is also proposed. Specifically, a query request is sent to the flash translation layer, carrying the target logical address and the subsequent logical address range determined according to the prefetch depth. The flash translation layer returns a list of physical addresses corresponding to all logical addresses within the range. In related technologies, each LBA prefetch requires an independent FTL query, resulting in multiple query overheads. In this embodiment, when prefetching is required, the memory control circuit 23 sends a request to the FTL, which includes the starting LBA (i.e., the target LBA) and the number of requests (i.e., the prefetch depth). The FTL internally optimizes its mapping table lookup process, traversing and collecting all valid logical-to-physical mapping relationships within the continuous LBA interval at once, and returning them in the form of a list of physical addresses. This operation reduces the original O(N) FTL query overhead to a near O(1) one-time operation, which effectively reduces mapping query latency and improves sequential read performance.

[0090] In one embodiment, a protected cache management mechanism is also proposed, which includes: defining an independent hot data protection zone in the cache space; storing data marked as high-priority cache items in the hot data protection zone; and managing the replacement of data items in the hot data protection zone based on access frequency and time decay factor.

[0091] Storage device 12 can logically partition a cache area within DRAM or buffer memory 24 specifically for storing data identified as hotspots. This area (hotspot data protection zone) is isolated from the regular buffer. Once data is marked as a hotspot, it is loaded or moved from this area. In addition to using the LRU algorithm to manage hot data in this area, memory control circuitry 23 can also employ a strategy consistent with the identification phase described above, based on access frequency (e.g., obtained from Count-Min-Sketch) and considering time decay. For example, using LFU combined with a decay algorithm. This ensures that only truly recently active, high-frequency accessed data is retained in this area, preventing false hotspot data caused by short-term burst access from occupying cache space for extended periods, thus achieving precise management of hotspot data.

[0092] In one embodiment, the capacity of the aforementioned hotspot data protection zone relative to the total capacity of the cache (DRAM or buffer memory 24) can be configured. This embodiment provides flexibility. For example, in database applications, where hotspot access may be highly concentrated, this proportion can be configured higher (e.g., 20%). In video playback scenarios, where sequential reading is predominant and hotspot data is less prominent, the proportion can be lowered (5%). Dynamically optimizing the buffer space partitioning enhances the adaptability of the storage device 12 to different scenarios.

[0093] In one embodiment, such as Figure 7 As shown, Figure 7 This is a diagram illustrating priority-based I / O queues and bandwidth scheduling. Figure 7 In this method, the method is applied to a storage device 12 that includes a memory module 122. A memory controller 123 (or a memory control circuit 23) is configured to perform this method. Figure 7 The description describes how I / O commands are categorized into different priority queues based on their type and urgency (e.g., synchronous writes are the highest, prefetch reads are the lowest). Memory control circuitry 23 monitors these queues and dynamically allocates bandwidth quotas according to priority to ensure the quality of service for high-priority commands.

[0094] Specifically, the method involves scheduling cache resources and input / output bandwidth according to a predetermined resource management strategy, and returning target data to the host system 11. Specifically, this includes: allocating input / output commands to different priority queues based on their type and urgency; allocating a corresponding bandwidth resource quota to each priority queue, wherein the bandwidth quota allocated for prefetching operations is dynamically reduced based on the real-time resource utilization of higher priority queues.

[0095] Specifically, the memory control circuit 23 maintains multiple I / O scheduling queues, such as a synchronous write queue (highest priority, ensuring data persistence), an asynchronous write queue, a host system 11 read queue, and a prefetch read queue (lowest priority). Each type of I / O command is inserted into the appropriate queue based on its type and deadline. The channel bandwidth resources to the memory module 122 are allocated to these queues. Specifically, the bandwidth quota for prefetching operations is not fixed but dynamically adjusted, calculated based on the real-time utilization of high-priority queues (such as synchronous writes and host reads). If high-priority queues are busy, the quota for the prefetch queue is reduced or suspended. When the storage device 12 is idle, the prefetch queue can obtain more bandwidth. This ensures that this background optimization operation of prefetching does not interfere with critical foreground I / O requests.

[0096] In one embodiment, the aforementioned bandwidth resource quota is implemented through a token bucket mechanism. The token generation rate allocated to prefetch operations is negatively correlated with the token consumption rate of synchronous write operations, asynchronous write operations, and host read operations in the most recent statistical period. Specifically, each queue is associated with a token bucket, and tokens are generated at a fixed rate. An I / O data packet can only be sent when there are enough tokens in the bucket. Furthermore, the token generation rate in the prefetch queue can be dynamically adjusted. That is, the busier the high-priority queue is, the higher its bandwidth utilization rate (i.e., the proportion of its own quota to its token consumption rate) over a past period, and consequently, the lower its prefetch token rate. Based on this mechanism, the bandwidth occupied by prefetch operations can be simply and efficiently limited to the idle bandwidth of the storage device 12.

[0097] In one embodiment, it is also proposed to statistically analyze the effective hit rate of the data prefetching operation within a sliding window of configurable time length; compare the effective hit rate with a range of expected hit rates; and dynamically adjust at least one control parameter related to determining the data access mode or triggering the data prefetching strategy based on the error signal generated by the comparison result.

[0098] Specifically, the memory control circuit 23 continuously monitors the prefetching effect and calculates the proportion of prefetched data subsequently accessed by the host system 11 within a time window (e.g., 30 seconds), i.e., the hit rate. An ideal hit rate range is set (e.g., 40%-60%). If the actual hit rate consistently falls below this range, it indicates that the current prefetching may be too aggressive or the pattern recognition is inaccurate. Based on this result, the memory control circuit 23 generates a negative error signal. Then, based on this error signal, the memory control circuit 23 outputs an adjustment amount to fine-tune certain parameters, such as increasing the confidence threshold for continuous pattern determination (even if it is more difficult to trigger prefetching), or increasing the entropy threshold for random determination (making it easier to be determined as random and disable prefetching). Accordingly, the storage device 12 can automatically adapt to long-term load changes, maintain optimal performance, and achieve an evolution from static configuration to dynamic self-tuning.

[0099] In one embodiment, a conservative strategy is proposed to be adopted during the initial startup of the storage device 12 or when historical access information is insufficient. This conservative strategy includes setting the prefetch depth to a minimum or temporarily disabling prefetching operations. This embodiment defines the boundaries and initialization state of the storage device 12. Specifically, when the storage device 12 is first powered on or wakes up from a long-term hibernation, the circular buffer is empty or the data is outdated. At this time, pattern recognition operations lack sufficient samples, and the structure is unreliable. If a normal strategy is used, erroneous prefetching is highly likely. Therefore, the memory control circuit 23 will enable a safe conservative strategy as the default value at this time. For example, it may force the prefetch depth to 1 (i.e., no prefetching) or directly disable the prefetching function. Simultaneously, the memory control circuit 23 will accelerate the filling of the historical buffer. Only after collecting a sufficient number (e.g., the buffer is half full) of valid historical I / O records will it gradually switch to the normal decision-making mode. Based on this mechanism, the storage device 12 can operate stably in any state, avoiding performance degradation or resource waste due to insufficient historical information.

[0100] In one embodiment, it is also proposed that when there is a logical address without a valid mapping in the continuous logical address sequence queried for a prefetch operation, the prefetch operation for the unmapped logical address is ignored, and the event is recorded for adaptive optimization of the storage device 12.

[0101] Specifically, when initiating a merge query to the FTL, the requested contiguous LBA range may contain some logical addresses that have not yet been written to by the host system 11 (prefetch holes). During the query, the FTL may return a specific error code or a null value for these unmapped LBAs. In detail, the memory control circuit 23 only performs prefetching on those LBAs that successfully return valid physical addresses, skipping unmapped LBAs. Simultaneously, the memory control circuit 23 records this event as statistical information. This statistical information is then used to adjust the prefetch management described in the above embodiments. For example, if prefetch holes frequently occur in a certain LBA region, the prefetching activity for that region can be reduced, or the prefetch depth calculation strategy can be adjusted.

[0102] A real-time pattern recognition implementation based on circular buffers, parallel multi-feature (trend, entropy, frequency) extraction, confidence quantification, and arbitration improves the accuracy of access pattern classification. This enhances prefetch hit rate in sequential scenarios and allows for dynamic prefetching disabling in random scenarios, eliminating invalid prefetch data and avoiding the problem of blind prefetching timing.

[0103] By employing a patterned differentiation strategy and coordinating dynamic prefetch depth and mapping-merge query in FTL, the proportion of effective data in the cache is maximized, thereby reducing average read latency. Simultaneously, an exception handling mechanism ensures the stability of performance optimization. Furthermore, a hot data protection mechanism accelerates high-frequency access. Ultimately, this results in smoother performance fluctuations in random read IOPS under mixed loads for storage device 12.

[0104] The bandwidth scheduling mechanism using priority queues and dynamic token buckets ensures that prefetching operations utilize only the idle bandwidth of storage device 12, eliminating resource contention with critical I / O. Furthermore, the isolation management of hotspot protection zones and ordinary cache areas improves the effective utilization of cache space.

[0105] However, Figures 4 to 7 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figures 4 to 7 Each step can be implemented as multiple program codes or circuits, and this application does not impose any limitations. Furthermore, Figures 4 to 7 The method can be used in conjunction with the above examples and embodiments, or it can be used alone; this application does not impose any restrictions.

[0106] In summary, the memory control method and storage device proposed in the embodiments of this application solve the problems of blind prefetching timing, low resource utilization efficiency, and poor scenario applicability in existing cache prefetching. The memory control method includes: in response to a read request from the host system 11, obtaining a target logical address; determining in real time the data access mode associated with the target logical address based on historical access information, wherein the data access mode includes at least a continuous mode, a random mode, and a hotspot mode; triggering a data prefetching strategy and a flash translation layer query strategy matching the determined data access mode; based on the data prefetching strategy and the flash translation layer query strategy, wherein for the continuous mode, a depth-dynamically adjustable prefetching and mapping relationship merging query is performed, for the random mode, prefetching is disabled, and for the hotspot mode, protected cache management is adopted; obtaining target data from the memory module 122; and scheduling cache and I / O bandwidth according to a predetermined resource management strategy and based on a priority queue and dynamic bandwidth quota mechanism, and returning the target data to the host system 11. This synergistically improves prefetching accuracy and cache utilization, and enhances the adaptive capability of the storage device.

[0107] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0108] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

[0109] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the function involved, as will be understood by those skilled in the art to which embodiments of this application pertain.

Claims

1. A memory control method, characterized in that, For use in a storage device, the storage device including a memory module, the memory module including a plurality of physical units, and the memory control method including: In response to a read request from the host system, obtain the target logical address; Based on historical access information, the data access pattern associated with the target logical address is determined in real time, wherein the data access pattern includes at least continuous mode, random mode and hotspot mode. Based on the determined data access pattern, trigger a data prefetching strategy and a flash conversion layer query strategy that match the access pattern; Based on the data prefetching strategy and flash translation layer query strategy, target data is obtained from the memory module. The step of triggering the data prefetching strategy and flash translation layer query strategy matching the access mode includes: if the data access mode is determined to be a continuous mode, a prefetching operation is initiated, the prefetching depth of the prefetching operation is dynamically calculated based on the evaluation value of the current access continuity strength, and a mapping relationship merging query is initiated to the flash translation layer for a continuous logical address sequence starting from the target logical address; if the data access mode is determined to be a random mode, the prefetching operation is prohibited, and only a single mapping relationship of the target logical address is queried from the flash translation layer; if the data access mode is determined to be a hotspot mode, the data corresponding to the target logical address is marked as a high-priority cache item, and a protected cache management mechanism is used for maintenance. The prefetch depth is determined by: calculating an initial depth based on the assessment value of the current access continuity strength; applying a smoothing filter to the initial depth to suppress short-term drastic fluctuations in the depth value; and limiting the filtered depth value between a preset minimum depth value and a preset maximum depth value to obtain the prefetch depth; and According to the predetermined resource management strategy, cache resources and input / output bandwidth are scheduled, and the target data is returned to the host system.

2. The memory control method according to claim 1, characterized in that, The step of determining the data access pattern associated with the target logical address in real time based on historical access information includes: Maintain a loop history structure to record the logical addresses of the most recent input / output operations in sequence; The first identification process, the second identification process, and the third identification process are executed in parallel. The first identification process is used to calculate a weighted moving average based on the offset sequence of logical addresses in the cyclic history structure to evaluate access continuity. The second identification process is used to calculate a deterministic metric to assess access randomness based on the distribution of logical addresses in the circular history structure; The third identification process is used to determine the access frequency of the target logical address under the attenuation model based on a probabilistic frequency statistical structure.

3. The memory control method according to claim 2, characterized in that, In the first identification process, the weighted moving average is a weight that assigns a higher weight to the recent logical address offset than to the distant offset.

4. The memory control method according to claim 3, characterized in that, The weighted moving average is an exponentially weighted moving average.

5. The memory control method according to claim 2, characterized in that, In the second identification process, the deterministic metric is Shannon entropy.

6. The memory control method according to claim 2, characterized in that, In the third identification process, the probabilistic frequency statistics structure is a count-minimum sketch, and the decay model is an exponential decay model.

7. The memory control method according to claim 6, characterized in that, After performing the first recognition process, the second recognition process, and the third recognition process in parallel, the method further includes: The continuous confidence level generated by the first identification process, the random confidence level generated by the second identification process, and the hotspot confidence level generated by the third identification process are obtained respectively, wherein the hotspot confidence level is generated based on the updated decayed access frequency; According to a preset priority arbitration rule, the continuous confidence level, random confidence level, and hot spot confidence level are judged to output the final data access mode. In the third identification process, the step of determining the access popularity based on the probabilistic frequency statistical structure includes: for the target logical address, multiplying the multiple counter values ​​located by multiple hash functions in the count-minimum sketch by a decay factor and then adding 1 to obtain and update the decayed access frequency.

8. The memory control method according to claim 7, characterized in that, The preset priority arbitration rule is as follows: If the confidence level of the hotspot exceeds the first threshold, it is determined to be the hotspot pattern; If it is not determined to be the hotspot pattern, and the continuous confidence score exceeds the second threshold while the random confidence score is lower than the third threshold, then it is determined to be the continuous pattern. If it is not determined to be the hotspot pattern or the continuous pattern, and the random confidence level exceeds the fourth threshold, then it is determined to be the random pattern.

9. The memory control method according to claim 1, characterized in that, The mapping relationship merging query includes, Send a query request to the flash translation layer, the request carrying the target logical address and the subsequent logical address range determined according to the prefetch depth; Receive the list of physical addresses corresponding to all logical addresses within the range returned by the flash translation layer.

10. The memory control method according to claim 1, characterized in that, The protected cache management mechanism includes: Define a separate hotspot data protection zone within the cache space; Data marked as high-priority cache items are stored in the hot data protection area; Based on access frequency and combined with a time decay factor, data items within the hotspot data protection zone are replaced and managed.

11. The memory control method according to claim 1, characterized in that, The step of scheduling cache resources and input / output bandwidth according to a predetermined resource management strategy and returning the target data to the host system includes: Based on the type and urgency of input / output commands, they are assigned to different priority queues. Allocate a corresponding bandwidth resource quota to each priority queue, wherein the bandwidth quota allocated for prefetching operations is dynamically reduced based on the real-time resource utilization of higher priority queues.

12. The memory control method according to claim 11, characterized in that, The bandwidth resource quota is implemented through a token bucket mechanism. The token generation rate allocated for prefetching operations is negatively correlated with the token consumption rate of synchronous write operations, asynchronous write operations, and host read operations in the most recent statistical period.

13. The memory control method according to claim 1, characterized in that, The method further includes: Within a sliding window of configurable duration, the effective hit rate of statistical prefetching operations is calculated. Compare the effective hit rate with a range of expected hit rates; Based on the error signal generated by the comparison results, at least one control parameter related to determining the data access mode or triggering the data prefetching strategy is dynamically adjusted.

14. The memory control method according to claim 1, characterized in that, When the storage device is in the initial startup phase or when historical access information is insufficient, a conservative strategy is adopted, which includes setting the prefetch depth to the minimum value or temporarily disabling prefetching operations.

15. The memory control method according to claim 1, characterized in that, When there is a logical address without a valid mapping in the continuous logical address sequence queried for a prefetch operation, the prefetch operation for the logical address without a valid mapping is ignored, and the event is recorded for storage device adaptive optimization.

16. A storage device, characterized in that, include: A connection interface for electrically connecting to a host system; The memory module includes multiple planes, each plane includes multiple blocks, and each block includes multiple pages; as well as The memory controller includes an error checking and correction circuit, a buffer memory, and a memory control circuit, and is electrically connected to the connection interface and the memory module; The memory controller is configured to perform the memory control method as described in any one of claims 1 to 15.

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