Accelerator and request processing method

Abstract

The application provides an accelerator and a request processing method, which can be applied to the technical field of computers. The accelerator comprises a computing unit configured to send an access request for a target virtual address to a memory management unit; and the memory management unit comprises an address translation cache module, and the memory management unit is configured to, in response to receiving the access request, find a corresponding physical page number in the address translation cache module according to the target virtual address to determine a physical address; wherein the address translation cache module comprises a plurality of cache units, and the address translation cache module is configured to determine a target cache unit from the plurality of cache units according to a virtual base address in the target virtual address; and find the physical page number corresponding to the target virtual address from the physical page numbers corresponding to at least two different virtual base addresses stored in the target cache unit according to address identification information in the target virtual address to determine the physical address.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more specifically to an accelerator and a request processing method. Background Technology

[0002] With the widespread adoption of multitasking and virtualization technologies, multiple applications can share the same accelerator to perform computational tasks. During task execution, each application needs to access its virtual address space and quickly translate virtual addresses into physical addresses by querying the address translation buffer.

[0003] In the process of realizing the concept of this invention, it was found that the related technology has at least the following problems: when multiple applications switch frequently or access concurrently, the address translation mapping will compete with each other in the address translation buffer, resulting in the effective mapping entries being swapped out before being fully utilized, thereby reducing the address translation efficiency. Summary of the Invention

[0004] In view of the above problems, the present invention provides an accelerator and a request processing method.

[0005] According to a first aspect of the present invention, an accelerator is provided, comprising: a computing unit configured to send an access request for a target virtual address to a memory management unit; the memory management unit including an address translation buffer module, the memory management unit being configured to, in response to receiving the access request, search for a corresponding physical page number in the address translation buffer module based on the target virtual address to determine a physical address; wherein the address translation buffer module includes a plurality of buffer units, the address translation buffer module being configured to, based on a virtual base address in the target virtual address, determine a target buffer unit from the plurality of buffer units; and, based on address identification information in the target virtual address, search for a physical page number corresponding to the target virtual address from physical page numbers stored in the target buffer unit corresponding to at least two different virtual base addresses to determine the physical address; the memory management unit is further configured to: access system memory according to the physical address, and send data obtained from the system memory to the computing unit.

[0006] A second aspect of the present invention provides a request processing method, characterized in that it is applied to an accelerator, the method comprising: receiving an access request for a target virtual address from a computing unit; responding to the access request, searching for a corresponding physical page number in an address translation buffer module based on the target virtual address to determine a physical address; wherein the address translation buffer module includes multiple buffer units, and searching for the corresponding physical page number in the address translation buffer module includes: determining a target buffer unit from the multiple buffer units based on a virtual base address in the target virtual address; searching for a physical page number corresponding to the target virtual address from physical page numbers stored in the target buffer unit corresponding to at least two different virtual base addresses based on address identification information in the target virtual address; accessing system memory according to the physical address, and sending data obtained from the system memory to the computing unit.

[0007] According to an embodiment of the present invention, in response to an access request for a target virtual address issued by the computing unit, the memory management unit invokes the address translation buffer module to locate the target buffer unit from multiple buffer units based on the virtual base address in the target virtual address, effectively narrowing the search range. Subsequently, based on the address identification information in the target virtual address, the corresponding physical page number is matched and obtained in the target buffer unit. Since the target buffer unit can simultaneously store physical page numbers corresponding to at least two different virtual base addresses, this not only improves the storage efficiency of the buffer unit but also enhances the system's address translation capability in multi-task concurrent scenarios. Based on the finally synthesized physical address, the memory management unit accesses the system memory to obtain data and returns it to the computing unit. The above process significantly improves address translation efficiency and reduces overall access latency by optimizing the storage structure of the buffer unit, while enhancing the accelerator's resource utilization and processing capability under multi-task concurrency, effectively improving system performance. Attached Figure Description

[0008] The above-mentioned contents, as well as other objects, features and advantages of the present invention, will become clearer from the following description of embodiments of the present invention with reference to the accompanying drawings.

[0009] Figure 1 A schematic diagram of an accelerator according to an embodiment of the present invention is shown.

[0010] Figure 2 A schematic diagram of a buffer unit group according to an embodiment of the present invention is shown.

[0011] Figure 3 A schematic diagram of a target virtual address according to an embodiment of the present invention is shown.

[0012] Figure 4 A flowchart illustrating the module interaction process for address translation according to an embodiment of the present invention is shown.

[0013] Figure 5 A schematic diagram of the storage structure of the target buffer unit according to an embodiment of the present invention is shown.

[0014] Figure 6 A schematic diagram of the address translation process according to an embodiment of the present invention is shown.

[0015] Figure 7 A flowchart of a request processing method according to an embodiment of the present invention is shown. Detailed Implementation

[0016] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the invention. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the invention for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0017] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0018] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0019] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0020] In the technical solution of this invention, the data involved (including but not limited to data used for analysis, data stored, data displayed, etc.) are all information and data authorized by the user or fully authorized by all parties. The collection, storage, use, processing, transmission, provision, disclosure and application of related data all comply with relevant laws, regulations and standards, necessary confidentiality measures have been taken, and they do not violate public order and good morals. Corresponding operation entry points are provided for users to choose to authorize or refuse.

[0021] Embodiments of the present invention provide an accelerator, comprising: a computing unit configured to send an access request for a target virtual address to a memory management unit; the memory management unit including an address translation buffer module, configured to, in response to receiving an access request, search for a corresponding physical page number in the address translation buffer module based on the target virtual address to determine a physical address; wherein the address translation buffer module includes multiple buffer units, configured to, based on a virtual base address in the target virtual address, determine a target buffer unit from the multiple buffer units; and, based on address identification information in the target virtual address, search for a physical page number corresponding to the target virtual address from physical page numbers stored in the target buffer unit corresponding to at least two different virtual base addresses to determine a physical address; the memory management unit is further configured to: access system memory according to the physical address and send data obtained from the system memory to the computing unit.

[0022] Figure 1 A schematic diagram of an accelerator according to an embodiment of the present invention is shown.

[0023] like Figure 1 As shown, the accelerator 100 includes: a computing unit 101 configured to send an access request for a target virtual address to a memory management unit 102; the memory management unit 102 includes an address translation buffer module 1021, configured to, in response to receiving an access request, search for the corresponding physical page number in the address translation buffer module 1021 according to the target virtual address to determine the physical address; wherein, the address translation buffer module 1021 includes multiple buffer units, configured to, determine a target buffer unit from the multiple buffer units according to the virtual base address in the target virtual address; and, based on the address identification information in the target virtual address, search for the physical page number corresponding to the target virtual address from the physical page numbers stored in the target buffer unit corresponding to at least two different virtual base addresses to determine the physical address; the memory management unit 102 is also configured to: access system memory 103 according to the physical address, and send the data obtained from system memory 103 to the computing unit 101.

[0024] According to embodiments of the present invention, the computing unit 101 of the accelerator 100 may be implemented in hardware as a processor (CPU) core, a graphics processing unit (GPU) stream processor, or a dedicated accelerator 100 core. During the execution of a computational task, when data in the system memory 103 needs to be accessed, an access request containing a target virtual address is generated. This access request is transmitted to the memory management unit 102 via an internal bus or a dedicated communication interface. The target virtual address is pre-divided into a virtual base address segment and an address identification information segment. The virtual base address segment represents the starting virtual address identifier of the memory block, and the address identification information segment represents the data unit index within the memory block.

[0025] The memory management unit 102 integrates an address translation buffer module 1021, which consists of multiple independent buffer units. Each buffer unit uses a cache array structure built with static random access memory, supporting parallel storage and retrieval of multiple sets of mapping relationships. Each buffer unit has a built-in virtual base address matching circuit, address identifier comparator, and physical page number storage area. The physical page number storage area is specifically used to store at least two sets of mapping entries between different virtual base addresses and corresponding physical page numbers. Each mapping entry is associated with a virtual base address identifier, address identifier information, and physical page number data.

[0026] When the memory management unit 102 receives an access request, it first extracts the virtual base address segment from the target virtual address using an address decoder. The virtual base address segment is then parsed using a hash mapping algorithm or address high-bit matching logic to generate a selection signal for the buffer unit. Based on this selection signal, a unique target buffer unit is located from multiple buffer units, ensuring a precise correspondence between the virtual base address and the buffer unit.

[0027] After the target buffer unit is determined, the memory management unit 102 controls the address identifier comparator to extract the address identifier information from the target virtual address and compares it in parallel with the address identifier information in each mapping entry stored in the target buffer unit. When a matching address identifier is detected, the corresponding physical page number is directly read from the physical page number storage area, and then the physical page number is combined with the page offset in the target virtual address by the address synthesis circuit to generate a complete physical address. If no matching entry is detected, the page table traversal mechanism is triggered to query the physical page number corresponding to the target virtual address from the page table of the system memory 103, and the mapping relationship is updated to the physical page number storage area of ​​the target buffer unit so that subsequent similar access requests can be quickly reused.

[0028] After generating the physical address, the memory management unit 102 sends an access request based on that physical address to the system memory 103 through the memory controller. Upon responding to the access request, the system memory 103 reads data from the storage unit corresponding to the physical address and transmits it to the memory management unit 102 via the data bus. The memory management unit 102 then feeds back the verified data to the computing unit 101, allowing the computing unit 101 to continue executing its computational tasks.

[0029] In response to an access request for a target virtual address issued by the computing unit, the memory management unit invokes the address translation buffer module to locate the target buffer unit from multiple buffer units based on the virtual base address in the target virtual address, effectively narrowing the search range. Subsequently, based on the address identifier information in the target virtual address, the corresponding physical page number is matched and obtained in the target buffer unit. Since the target buffer unit can simultaneously store physical page numbers corresponding to at least two different virtual base addresses, this not only improves the storage efficiency of the buffer unit but also enhances the system's address translation capabilities in multi-task concurrent scenarios. Based on the finally synthesized physical address, the memory management unit accesses system memory to retrieve data and returns it to the computing unit. This process, by optimizing the storage structure of the buffer unit, significantly improves address translation efficiency, reduces overall access latency, and enhances the accelerator's resource utilization and processing capabilities under multi-task concurrency, effectively improving system performance.

[0030] According to an embodiment of the present invention, each buffer unit includes multiple buffer sub-units; the address translation buffer module is further configured to: determine multiple candidate sub-units corresponding to address identification information in the target buffer unit, wherein each candidate sub-unit is allocated to store the physical page number corresponding to the virtual base address; determine the target sub-unit from the multiple candidate sub-units based on the sub-unit index in the target virtual address; concatenate the physical page number stored in the target sub-unit with the page offset in the target virtual address to obtain the physical address, wherein the page offset is used to indicate the specific location within the physical page identified by the physical page number.

[0031] Each buffer unit adopts a hierarchical storage architecture, internally divided into multiple independent buffer sub-units. Each buffer sub-unit consists of an entry storage array composed of static random access memory, an index identifier register, and read / write control circuitry. Furthermore, all buffer sub-units within the same buffer unit are pre-bound to the virtual base address corresponding to that buffer unit, and are used only to store different physical page number mapping entries associated with the corresponding virtual base address. Each mapping entry synchronously records the corresponding address identifier information and sub-unit index.

[0032] After determining the target buffer unit, the address translation buffer module performs a parallel comparison between the address identification information in the target virtual address and the address identification information of the mapping entries stored in each buffer sub-unit within the target buffer unit. This allows for the selection of multiple candidate sub-units whose address identification information matches, ensuring that each candidate sub-unit stores the physical page number data related to the current address identification information under that virtual base address.

[0033] The Address Identifier Block (AIB) is an n-bit field used to distinguish which virtual base address a buffer sub-unit within the target buffer cell belongs to. For example, when n=1, the AIB has 1 bit, which can represent two states: 0 and 1. Specifically, when AIB=0, it indicates that the current buffer sub-unit belongs to the "first virtual base address," and when AIB=1, it indicates that the current buffer sub-unit belongs to the "second virtual base address."

[0034] The target virtual address has a pre-defined sub-cell index field (usually a fixed number of bits in the address segment). The address translation buffer module parses this sub-cell index field through an index decoder to generate a sub-cell selection signal. This selection signal corresponds one-to-one with the candidate sub-cell number. Subsequently, based on this selection signal, the unique target sub-cell is accurately located from multiple candidate sub-cells, avoiding read / write conflicts between candidate sub-cells and improving address lookup efficiency.

[0035] Once the target subunit is determined, its internal physical page number is quickly extracted via the data read circuit. Simultaneously, the address translation buffer module extracts the page offset field from the target virtual address (typically a fixed number of bits in the lower bits of the address, corresponding to the size of the physical page's storage unit). This page offset precisely indicates the data's exact storage location within the physical page. Finally, the extracted physical page number and page offset are combined according to a preset format using an address concatenation circuit (the physical page number occupies the higher bits of the address, and the page offset occupies the lower bits), generating a complete and unique physical address that provides precise address pointers for subsequent system memory accesses.

[0036] By identifying multiple candidate sub-units in the target buffer unit based on address identification information, and accurately locating the target sub-unit based on the sub-unit index, the physical address is obtained by concatenating the physical page number in the target sub-unit with the page offset. This achieves efficient address translation and accurate memory location, improving the system's memory access efficiency and data processing capabilities.

[0037] Figure 2 A schematic diagram of a buffer unit group according to an embodiment of the present invention is shown.

[0038] According to an embodiment of the present invention, the multiple buffer units in the address translation buffer module are divided into multiple buffer unit groups; the address translation buffer module is further configured to: determine a target buffer unit group from the multiple buffer unit groups based on the unit index information in the target virtual address; and in the target buffer unit group, find the corresponding physical page number based on the virtual base address and address identification information in the target virtual address to determine the physical address.

[0039] The address translation buffer module adopts a grouped architecture design. Multiple buffer units are divided into several buffer unit groups according to the allocation rules of unit index information. Each buffer unit group contains a preset number of buffer units (e.g., 4 or 8 buffer units as a group). The buffer unit groups work in parallel through independent group controllers, address matching circuits and data storage buses to avoid inter-group access conflicts.

[0040] Each buffer unit group is equipped with a group identifier register to store the range of unit index information corresponding to the buffer unit group. At the same time, each buffer unit in the buffer unit group maintains an independent virtual base address storage area, address identifier information matching circuit and physical page number cache area, supporting parallel lookup operations of multiple buffer units in the group.

[0041] like Figure 2 As shown, the buffer unit group integrates multiple independent buffer units (buffer unit 1, buffer unit 2, and buffer unit 3 in the figure) into the same group-level hardware module. Each buffer unit is further constructed with multiple buffer sub-units through static random access memory. Each buffer sub-unit corresponds to the mapping entry storage area of ​​the address translation buffer module.

[0042] This hierarchical grouping structure allows multiple buffer units within a buffer unit group to respond to different address translation requests in parallel, improving the concurrent processing capability of the address translation buffer module. Each buffer unit's multiple buffer sub-units can store multiple sets of mapping relationships corresponding to the same virtual base address, effectively improving the storage resource utilization of a single buffer unit. Simultaneously, the grouping architecture isolates access operations from different buffer units, reducing resource contention during address translation and lowering latency caused by access conflicts.

[0043] When the address translation buffer module receives the target virtual address, it first extracts the cell index information from a specified field of the target virtual address (usually a fixed number of bits between the high and middle bits) using its built-in index extraction circuit. The number of bits in this field is pre-configured according to the total number of buffer cell groups (for example, if there are 16 groups, the cell index information occupies 4 address bits). Then, the extracted cell index information is decoded to generate a group selection signal. This group selection signal is matched with the group identifier register of each buffer cell group through a group selection circuit, quickly locating the unique target buffer cell group. This ensures accurate mapping between the cell index information and the buffer cell group, improving group selection efficiency.

[0044] After the target buffer unit group is determined, the group controller is activated and receives the virtual base address and address identification information from the target virtual address. The group controller first controls the virtual base address storage areas of all buffer units in the group to perform parallel comparisons with the virtual base address of the target virtual address, and filters out candidate buffer units that store the mapping entry corresponding to the virtual base address (if there is no buffer unit with a matching virtual base address in the group, the group page table lookup or cross-group mapping mechanism is triggered).

[0045] Next, for each candidate buffer unit, the address identification information of the target virtual address is precisely compared with the address identification information in the mapping entries stored in the candidate buffer unit through its built-in address identification information matching circuit. When a completely matching mapping entry is detected, the corresponding physical page number is directly read from the physical page number cache area of ​​the candidate buffer unit.

[0046] The address translation buffer module uses the address synthesis circuit to concatenate the read physical page number with the page offset field in the target virtual address according to a preset address format (the physical page number occupies the high bits of the address, and the page offset occupies the low bits of the address), generating a complete physical address.

[0047] If a mapping entry is already directly associated with a complete physical address, no concatenation operation is needed; the physical address is directly output to the memory management unit for subsequent system memory access. Simultaneously, the group controller records the buffer unit and mapping entry information found during this lookup. If subsequent access requests with the same virtual base address and address identifier information occur, the physical address can be quickly reused through the group's cache hit mechanism, further improving address translation efficiency.

[0048] By dividing the buffer unit into multiple buffer unit groups, determining the target buffer unit group based on the unit index information in the target virtual address, and then combining the virtual base address and address identifier information to find the corresponding physical page number, efficient address translation and accurate physical address location are achieved, significantly improving address translation efficiency and system performance.

[0049] Figure 3A schematic diagram of a target virtual address according to an embodiment of the present invention is shown.

[0050] like Figure 3 As shown, the target virtual address is implemented using a segmented structure, dividing the complete address into five fields: virtual base address (30 bits), address identifier information (n bits), sub-cell index (m bits), cell index information (7 bits), and page offset (16 bits). The address identifier information is used to distinguish which virtual base address each buffer sub-cell in the target buffer unit belongs to.

[0051] For example, when n=1, the address identifier has 1 bit, which can represent two states: 0 and 1. When it is 0, it indicates that the current buffer sub-unit belongs to the first virtual base address; when it is 1, it indicates that it belongs to the second virtual base address. The sub-unit index (m bits) corresponds to the sub-entry allocated to each virtual base address, with an index range of 2^m. The unit index information (7 bits) is used to locate the target buffer unit group in the address translation buffer module. The total number of bits in this modified virtual address structure is 30+n+m+7+16, not exceeding 64 bits.

[0052] By setting a segmented virtual address structure, the function of each field is clearly defined, allowing for layered or parallel processing of buffer unit group location, buffer unit matching, and sub-unit selection during address translation, effectively shortening the overall latency of address translation. Fixed-bit virtual base address, unit index information, and page offset ensure the standardization of the address structure, reducing the design complexity and adaptation cost of the hardware parsing circuit. Variable-bit address identification information and sub-unit indexes enhance the flexibility of the structure, adapting to the configuration requirements of address translation buffer modules of different sizes. Simultaneously, independent parsing of each field reduces resource conflicts during address processing, further improving the operating efficiency of the address translation buffer module.

[0053] According to an embodiment of the present invention, the memory management unit further includes a page table traversal module; the address translation buffer module is further configured to: send a translation missing request to the page table traversal module in response to the absence of a physical address corresponding to the target virtual address in the target buffer unit; the page table traversal module is configured to: in response to receiving the translation missing request, access the page table structure in the system memory and perform page table traversal to obtain the physical page number corresponding to the target virtual address; the address translation buffer module is further configured to: receive the physical page number from the page table traversal module and insert the physical page number into the free subunit in the target buffer unit corresponding to the address identification information.

[0054] The page table traversal module of the memory management unit adopts a hardware-based architecture, with its core comprising a page table base address register, a multi-level traversal controller, an address generator, a data buffer, and page table entry parsing circuitry. The page table base address register stores the starting physical address of the page table structure in system memory. The multi-level traversal controller supports adaptive traversal logic for different page table levels (such as page directory, page table, and second-level page table). The address generator generates access addresses for page table entries at each level based on the virtual address field and page table hierarchy rules. The data buffer temporarily stores page table entry data read from system memory, preventing latency caused by repeated memory accesses. The page table traversal module connects to the address translation buffer module via a dedicated control bus and communicates with system memory through the memory controller interface, ensuring efficient transmission and parsing during the page table traversal process.

[0055] After the address translation buffer module performs address matching in the target buffer unit, if the address identification information of all candidate sub-units does not match the target virtual address, or if there is no mapping entry for the corresponding virtual base address in the target buffer unit, the missing detection circuit of the address translation buffer module will generate a translation missing signal, triggering the construction of a translation missing request. This request packet contains key information such as the complete target virtual address and the target buffer unit number, and is sent to the page table traversal module through a synchronization signal mechanism to ensure that the page table traversal module accurately obtains the core parameters required for address translation.

[0056] After receiving a missing conversion request, the page table traversal module first reads the starting physical address of the page table from the page table base address register. The multi-level traversal controller then parses the structure of the target virtual address (such as dividing it into fields like page directory index, page table index, and page offset according to a preset number of bits) and starts the multi-level traversal process.

[0057] The address generator calculates the physical address of the first-level page directory entry based on the page table start address and page directory index. It then sends an access request to system memory via the memory controller, reads the corresponding page directory entry data, and temporarily stores it in a data buffer. The page table entry parsing circuit decodes the page directory entry, extracts the base address of the next-level page table (this step is repeated for multi-level page tables until the final page table entry is located), and combines it with the page table index in the target virtual address to generate the physical address of the final page table entry. It then accesses system memory again to read the page table entry data. The parsing circuit extracts the physical page number corresponding to the target virtual address from this page table entry, while simultaneously verifying the validity of the page table entry (e.g., checking valid bits, permission bits, etc.) to ensure the legality and availability of the physical page number.

[0058] After receiving the physical page number and related verification information returned by the page table traversal module, the address translation buffer module first scans the free sub-units of all buffer sub-units in the target buffer unit through the free sub-unit detection circuit (each buffer sub-unit is configured with a 1-bit free status register, 0 indicates free and 1 indicates occupied), and quickly locates the free sub-unit corresponding to the address identification information (that is, the buffer sub-unit does not store other physical page number mappings and belongs to the candidate sub-unit set corresponding to the virtual base address).

[0059] If multiple free sub-units exist, the first free sub-unit can be selected as the target sub-unit using a simple priority strategy (such as by the order of the buffer sub-unit numbers). After determining the target sub-unit, the write control circuit of the address translation buffer module writes the mapping parameters, such as the physical page number, the corresponding virtual base address, the address identifier information, and the sub-unit index, into the storage array of the target sub-unit according to a preset format. At the same time, the free flag of the target sub-unit is updated to an occupied state, completing the cache update of the mapping relationship. Subsequently, when an access request with the same virtual base address and address identifier information is received again, the address translation buffer module can directly read the physical page number from the target sub-unit to achieve fast address translation.

[0060] By introducing a page table traversal module, when the physical address corresponding to the target virtual address is missing in the address translation buffer module, a page table traversal operation can be triggered to obtain the correct physical page number and insert it into the free sub-unit of the buffer module, thereby effectively handling address translation errors and improving the overall operating efficiency and stability of the system.

[0061] Figure 4 A flowchart illustrating the module interaction process for address translation according to an embodiment of the present invention is shown.

[0062] like Figure 4 As shown, the computation unit sends an access request for the target virtual address to the memory management unit. The memory management unit has a built-in address translation buffer module. Upon receiving the request, it first attempts to match the corresponding physical address in the buffer. If no match is found, a translation miss request is sent to the page table traversal module. The page table traversal module is equipped with independent page table access logic. Upon receiving the request, it accesses the page table structure through the system memory interface, completes multi-level page table traversal to obtain the target physical page number, and then sends the physical address back to the memory management unit. Finally, the memory management unit feeds back the physical address to the computation unit through the response bus, and simultaneously updates the mapping relationship in the address translation buffer.

[0063] The memory management unit prioritizes using buffers for address translation, significantly reducing the frequency of direct access to the system memory page table and lowering memory access latency and system resource overhead. Furthermore, the independent deployment of the page table traversal module decouples the core address translation logic from the page fault handling logic, improving the specialization and maintainability of each module.

[0064] According to an embodiment of the present invention, the address translation buffer module is further configured to: in response to the absence of a free sub-unit corresponding to the address identification information in the target buffer unit, update the target buffer unit from a shared mode capable of simultaneously storing physical page numbers corresponding to at least two different virtual base addresses to an exclusive mode storing only the physical page numbers corresponding to the virtual base addresses in the target virtual address; in the exclusive mode, clear the physical page numbers corresponding to other virtual base addresses in the target buffer unit that are different from the virtual base addresses in the target virtual address; in response to the buffer sub-unit storing physical page numbers corresponding to other virtual base addresses becoming a free sub-unit, insert the physical page numbers into the free sub-unit of the target buffer unit.

[0065] Each buffer unit of the address translation buffer module is equipped with a mode identifier register and a mode control circuit to manage the switching between shared and exclusive modes. In shared mode, multiple buffer sub-units within the buffer unit can be bound to different virtual base addresses and store corresponding physical page numbers. The mode identifier register is identified as "01" or "10" to further distinguish between the two distribution modes.

[0066] Continuous Distribution Mode (identified by "01"): Allocates consecutive buffer subunits for each virtual base address. For example, virtual base address 1 can occupy buffer subunits 0-7, and virtual base address 2 can occupy buffer subunits 8-15. This mode is suitable for applications with "contiguous access" characteristics and can effectively reduce the fragmentation of physical page numbers under the same virtual base address within buffer units, improving spatial locality.

[0067] Non-contiguous distribution mode (identified by "10"): Buffer sub-units are allocated alternately for different virtual base addresses. For example, virtual base address 1 occupies even-numbered buffer sub-units (0, 2, 4, ...), and virtual base address 2 occupies odd-numbered buffer sub-units (1, 3, 5, ...). This mode is suitable for applications with "step-size access" characteristics (such as matrix transpose), and can reduce the centralized removal of physical page numbers from multiple buffer sub-units of the same virtual base address due to conflicts or replacement policies, thereby enhancing the robustness of the access mode.

[0068] In exclusive mode, a buffer unit is allowed to bind only a single target virtual base address, and all buffer sub-units are used to store the physical page number corresponding to that virtual base address. The mode flag is set to "00". This mode is designed for applications with "high demand" for buffer sub-units, ensuring sufficient residency of the mapping by concentrating resources.

[0069] When the address translation buffer module searches for a free sub-unit in the target buffer cell that corresponds to the address identifier information, it iterates through the free status bits of all buffer sub-units using a sub-unit free detection circuit. If the detection result is no matching free sub-unit (i.e., all buffer sub-units are in an occupied state and the bound virtual base addresses are not unique), a mode switching process is triggered. At this time, the control unit of the address translation buffer module sends a mode update signal to the mode control circuit of the target buffer cell, and simultaneously passes in the virtual base address in the target virtual address as the binding base address for exclusive mode. After receiving the signal, the mode control circuit updates the mode identifier bit in the mode identifier register from "01" or "10" to "00", completing the switch from shared mode to exclusive mode.

[0070] After the exclusive mode switch is completed, the virtual base address comparison circuit compares the virtual base address of each buffer sub-unit with the target virtual base address one by one, filtering out the mismatched buffer sub-units (i.e., buffer sub-units storing physical page numbers corresponding to other virtual base addresses). Subsequently, a cleanup control signal is sent to these buffer sub-units, triggering their internal storage data erase logic. This clears all mapping entries such as physical page numbers and address identification information corresponding to non-target virtual base addresses stored in the sub-units, and updates the idle status bit of these buffer sub-units to "idle" (the idle flag bit is set to "0"), completing the cleanup of non-target base address data and releasing idle storage resources.

[0071] Once the buffer sub-unit storing the physical page number corresponding to other virtual base addresses is cleared and becomes a free sub-unit, the write control circuit of the address translation buffer module immediately responds, selecting the first free sub-unit as the target sub-unit from these free sub-units according to a preset priority (such as the order of buffer sub-unit numbers). Subsequently, the physical page number obtained from the page table traversal module, along with the mapping parameters such as the virtual base address and corresponding address identification information in the target virtual address, is written into the storage array of the target sub-unit in a standard format. At the same time, the free status bit of the buffer sub-unit is updated to "occupied," and its virtual base address tag is updated to the target virtual base address.

[0072] After the write operation is completed, the mode control circuit maintains the exclusive mode state of the target buffer unit, ensuring that all subsequent buffer sub-units of the buffer unit provide storage services only for the target virtual base address, thereby improving the conversion efficiency of accessing the same type of address.

[0073] By setting a switching mechanism between shared and exclusive modes in the address translation buffer module, when there are no free sub-units in the target buffer unit, the mode is updated from shared to exclusive, and the physical page numbers corresponding to other virtual base addresses that are different from the target virtual address are cleared, thereby freeing up space for the physical page number of the current virtual base address, ensuring efficient utilization of the buffer unit and fast response of address translation.

[0074] Figure 5 A schematic diagram of the storage structure of the target buffer unit according to an embodiment of the present invention is shown.

[0075] like Figure 5 As shown, in the address translation buffer module, each storage entry is divided into functional areas with a fixed bit width. First, a 2-bit validity flag is configured to indicate whether the buffer sub-unit corresponding to the current virtual base address is in an available state. This is followed by a 30-bit virtual base address, supporting the storage of n independent virtual base addresses. A mode flag bit is set in the middle (e.g., "01" in the example indicates a continuous distribution mode in shared mode, or "10" indicates a non-contiguous distribution mode in shared mode) to record the access mode of the target buffer unit.

[0076] The subsequent "address identification information + physical address space" area is divided into multiple sets of identifier fields, each corresponding to multiple buffer sub-units, used to store the address identification information and matching physical page number under the corresponding virtual base address.

[0077] By integrating the core information required for address translation into a single buffer unit, the information lookup path for address translation is effectively shortened, the lookup efficiency of the buffer module is improved, and the fixed-width area division also reduces the redundant occupation of storage resources.

[0078] Figure 6 A schematic diagram of the address translation process according to an embodiment of the present invention is shown.

[0079] like Figure 6 As shown, during the address translation process, the virtual address is first split into fields such as virtual base address, address identification information, sub-cell index, cell index information, and page offset. Based on the cell index information, the target buffer cell group is located, and then the entry structure of the corresponding buffer cell (containing a validity identifier, multiple sets of virtual base addresses and address identification information + physical address space, etc.) is called from the target buffer cell group.

[0080] Subsequently, a parallel comparator synchronously compares multiple virtual base addresses within the buffer unit, and the status validity confirmation module verifies the availability status of the entry. Then, the address identification information comparison module matches the data in the corresponding physical address space, and finally, the hit confirmation module outputs a valid physical address.

[0081] By segmenting and parsing virtual addresses, the functional positioning of each field becomes more precise, effectively reducing redundant steps in the address processing. Simultaneously, the parallel comparison of virtual base addresses significantly shortens the latency of base address matching, thereby substantially improving the speed of a single round of address translation. Furthermore, state validity verification filters invalid entries in advance, reducing resource consumption caused by invalid matches. Building upon this, targeted comparison of address identification information further ensures the accuracy of physical addresses. Overall, the process achieves efficient, accurate, and low-overhead address translation, effectively supporting the low-latency requirements of accelerator memory access.

[0082] According to an embodiment of the present invention, the address translation buffer module is further configured to: in response to the absence of a target buffer unit corresponding to the virtual base address among a plurality of buffer units, determine candidate buffer units that satisfy the sharing conditions from other buffer units within the target buffer unit group where the target buffer unit is located, wherein the sharing conditions include the candidate buffer unit having an exclusive access mode and having a free sub-unit; in response to the presence of at least one candidate buffer unit, determine a target shared buffer unit from at least one candidate buffer unit and update the access mode of the target shared buffer unit to the shared mode; and insert the virtual base address, address identification information, and physical page number as a mapping relationship into the free sub-unit of the target shared buffer unit.

[0083] Each buffer unit group in the address translation buffer module is equipped with an intra-group unit status management circuit. This circuit synchronizes the core status information of all buffer units within the group in real time, including the access mode (exclusive mode / shared mode) of each buffer unit, the virtual base address binding list, the idle status mapping table of the buffer sub-units, and the most recent access timestamp. This core status information is stored in a shared status register within the buffer unit group, supporting parallel reading and fast querying, providing a data foundation for the selection of candidate buffer units.

[0084] When the address translation buffer module determines the target buffer unit group based on the virtual base address, and detects that no buffer unit in the group is bound to that virtual base address (i.e., there is no corresponding target buffer unit), it immediately triggers the candidate buffer unit search process within the group. At this time, the unit status management circuit within the group receives the search instruction, extracts the status information of all non-target buffer units (i.e., other buffer units in the group) from the status register, and verifies them one by one through the shared condition judgment module.

[0085] Specifically, the access mode identifier register of the buffer unit is first checked to confirm whether it is in exclusive mode (mode identifier bit is "00"). If it is in exclusive mode, the sub-unit idle status mapping table of the buffer unit is further queried. Bitwise operations are used to quickly determine whether there is an idle sub-unit (buffer sub-unit with idle status bit is "0"). Only buffer units that meet both the requirements of "exclusive mode" and "existence of idle sub-unit" will be marked as candidate buffer units, and their unit number and idle sub-unit location information will be recorded.

[0086] If the shared condition judgment module selects at least one candidate buffer unit, the unit selection logic of the address translation buffer module will determine the unique target shared buffer unit from the candidate buffer units according to the preset priority strategy (such as prioritizing the buffer unit with the most free sub-units or the buffer unit with the earliest recent access time).

[0087] In addition, the priority strategy also includes prioritizing buffer units whose access requests originate from the "same process". Since applications within the same process have similar access patterns (e.g., both are sequential or out-of-order accesses), the probability of conflicts between buffer sub-units within a shared buffer unit is low, resulting in higher utilization.

[0088] Specifically, during implementation, a process identifier is added to the access request data packet of the computing unit, and a process identifier register and a process access mode feature register are configured simultaneously for each buffer unit of the address translation buffer module. The former is used to store the unique identifier of the process currently bound to the buffer unit, while the latter marks it as a typical mode such as "sequential access" or "out-of-order random access" by recording the offset pattern of the process's most recent address access in real time.

[0089] When the address translation buffer module receives an access request, it first extracts the process identifier from the request. Then, through the process matching circuit within the target buffer unit group, it traverses the process identifier registers of all buffer units in the target buffer unit group and filters out candidate buffer units with matching process identifiers. At the same time, it calls the process access pattern matcher to compare the address access characteristics of the current request (calculated in real time from the address offset sequence) with the process access pattern characteristic register records of the candidate buffer units, and only retains buffer units with a pattern matching degree higher than a preset matching threshold (such as 80%).

[0090] Building upon this foundation, a process address space overlap calculation module will be introduced. For candidate buffer units of the same process, this module calculates in real-time the overlap ratio between the virtual address range of the current request and the virtual address range of the already stored mapped entries in the buffer unit, prioritizing buffer units with an overlap ratio not lower than a preset overlap threshold (e.g., 30%). Simultaneously, a process unit marker can be configured for buffer units. When requests from the same process hit a certain buffer unit multiple times, an independent buffer unit is automatically allocated to that process, preventing other processes from occupying the partition's resources during subsequent mode switching.

[0091] Subsequently, the mode switching control circuit sends a mode update signal to the target shared buffer unit, updating the mode flag bit of its access mode flag register from "00" (exclusive mode) to "10" or "01" (shared mode), and at the same time updates the virtual base address binding list of the buffer unit, allowing it to bind multiple different virtual base addresses at the same time, thus removing the restriction that only a single virtual base address can be bound in exclusive mode.

[0092] After the mode switch is completed, the write control circuit of the address translation buffer module selects a free sub-unit from the free sub-units of the target shared buffer unit, either in numerical order or randomly, as the mapping storage unit. It then writes the virtual base address, address identifier information from the target virtual address, and the physical page number obtained from the page table traversal module into the storage array of the free sub-unit according to a preset mapping entry format. Simultaneously, it updates the virtual base address of the free sub-unit to the current virtual base address, updates its free status bit to "1" (occupied status), and synchronously updates the corresponding status information in the unit status management circuit within the group.

[0093] At this point, the mapping relationship has been inserted into the target shared buffer unit. Subsequent access requests for this virtual base address and address identifier information can directly and quickly find the corresponding physical page number from this buffer unit, thereby improving address translation efficiency.

[0094] By setting a sharing mechanism for buffer units in the address translation buffer module, when there is no target buffer unit corresponding to the virtual base address, a candidate buffer unit that satisfies the exclusive mode and has free sub-units is searched from other buffer units, and it is updated to the sharing mode and a new mapping relationship is inserted, thereby improving the utilization rate of buffer units and the efficiency of address translation.

[0095] According to an embodiment of the present invention, the address translation buffer module is further configured to: in response to the absence of a candidate buffer unit, determine a replacement buffer unit from other buffer units within the target buffer unit group where the target buffer unit is located, according to a preset replacement strategy; clear the physical page numbers corresponding to other virtual base addresses in the replacement buffer unit that are different from the virtual base address in the target virtual address; and in response to the buffer sub-unit storing the physical page numbers corresponding to other virtual base addresses becoming an idle sub-unit, insert the virtual base address, address identification information, and physical page number as a mapping relationship into the idle sub-unit of the replacement buffer unit.

[0096] The address translation buffer module incorporates a replacement strategy management unit and an intra-group unit filtering circuit. The replacement strategy management unit pre-stores at least one preset replacement strategy (such as least recently used, least recently used, first-in-first-out, etc.) and can dynamically switch strategy types through a configuration interface. The intra-group unit filtering circuit establishes real-time communication with the status register of the target buffer unit group, enabling it to quickly extract the core status of all other buffer units (non-target buffer units) within the group, including access mode, buffer sub-unit occupancy status, most recently accessed timestamp, number of mapping entries, etc., providing data support for determining the replacement buffer unit.

[0097] When it is detected that there are no candidate buffer units that meet the sharing conditions in the target buffer unit group, the address translation buffer module immediately triggers the replacement process. The replacement strategy management unit issues a screening instruction to the unit screening circuit in the group according to the currently enabled preset strategy.

[0098] If a Least Recently Used (LRU) strategy is adopted, the unit filtering circuit within the group extracts the most recent access timestamp of each buffer unit and uses a time comparator to select the buffer unit with the earliest recent access time. If a First-In-First-Out (FIFO) strategy is adopted, the buffer units are sorted according to the write timestamp of the earliest mapping entry within them, and the buffer unit with the earliest write time is selected. If a Recently Unused (RUW) strategy is adopted, the access flag bits of each buffer unit are checked to select the buffer units that have not been accessed recently. During the filtering process, buffer units in a locked state (such as those storing critical task mapping entries) are automatically excluded, and a unique replacement buffer unit is finally determined, and its unit number and sub-unit distribution information are recorded.

[0099] Once the replacement buffer unit is determined, the cleanup control circuit of the address translation buffer module is activated, sending a cleanup command to the buffer unit and passing in the virtual base address in the target virtual address as the comparison benchmark. After receiving the command, the virtual base address comparison circuit built into the replacement buffer unit reads the virtual base address of each sub-unit one by one, performs a precise comparison with the target virtual base address, and marks all sub-units with mismatched tags (i.e., sub-units storing the physical page number corresponding to other virtual base addresses).

[0100] Subsequently, the cleanup control signal triggers the internal data erasure logic of these marked sub-units, clearing all data stored in the sub-units, such as the physical page number, address identification information, and mapping entry validity flags corresponding to the non-target virtual base address. Simultaneously, the idle status bit of these sub-units is updated to "idle" (idle flag bit is set to "0"), completing the cleanup of non-target base address data and releasing available storage resources.

[0101] Once the sub-cells storing the physical page numbers corresponding to other virtual base addresses are cleared and become free sub-cells, the write control circuit of the address translation buffer module immediately responds and selects the first available sub-cell from these free sub-cells as the mapped storage unit according to a preset priority (such as ascending sub-cell numbering).

[0102] Subsequently, the virtual base address, address identification information, and physical page number obtained from the page table traversal module in the target virtual address are written into the storage array of the sub-unit according to the standard mapping entry format (including base address field, identification information field, physical page number field, and validity field).

[0103] After the write operation is complete, the virtual base address tag of the sub-unit is updated to the target virtual base address, its idle status bit is updated to "occupied" (the idle flag is set to "1"), and the latest status of the replacement buffer unit (including information on newly added mapping entries and sub-unit occupancy) is synchronized to the group status register to ensure the accuracy of subsequent group unit status queries. This completes the insertion of the new mapping relationship into the replacement buffer unit, ensuring that subsequent access to the target virtual address can achieve fast address translation through this buffer unit.

[0104] By using the intelligent replacement mechanism of the address translation buffer module, when there is a lack of candidate buffer units, a replacement buffer unit is selected according to a preset strategy, irrelevant physical page numbers are cleared, space is made up for new mapping relationships and inserted, which effectively improves the flexibility of the buffer unit and the efficiency of address translation, and optimizes the utilization of system resources.

[0105] According to an embodiment of the present invention, the address translation buffer module is further configured to: in response to determining a target shared buffer unit, identify the index distribution pattern of the buffer sub-units already occupied in the target shared buffer unit; determine an insertion strategy for inserting address identification information and physical page number according to the index distribution pattern; and insert the virtual base address, address identification information, and physical page number as a mapping relationship into the free sub-unit of the target shared buffer unit according to the insertion strategy; wherein the index distribution pattern includes a continuous distribution pattern and a non-continuous distribution pattern, and the insertion strategy corresponds to the index distribution pattern.

[0106] Each target shared buffer unit of the address translation buffer module is equipped with a sub-unit index status table and a distribution detection circuit. The sub-unit index status table records in real time the index number (assigned in a continuous integer sequence, such as 0~N-1, where N is the total number of sub-units) and occupancy status (occupied / idle) of all sub-units. The distribution detection circuit is directly connected to this status table and is used to extract the index information of occupied sub-units and analyze their distribution characteristics.

[0107] Once the target shared buffer unit is identified, the distribution detection circuit first traverses the sub-unit index status table through parallel reading logic, filtering out all sub-unit indices with an "occupied" status, sorting them by value, and storing them in a temporary index cache. Subsequently, the sorted index sequence is verified through continuous judgment logic. If the index sequence satisfies the continuous relationship of "next index value = previous index value + 1" without any numerical gaps, it is determined to be a continuous distribution pattern, generating a pattern identifier signal "01". If there is at least one numerical gap in the index sequence (i.e., next index value > previous index value + 1), it is determined to be a non-continuous distribution pattern, generating a pattern identifier signal "10", thus completing the identification of the index distribution pattern.

[0108] For different index distribution patterns, the address translation buffer module presets corresponding insertion strategies, and the strategy logic is integrated into the insertion strategy selection circuit, which is linked with the mode identifier signal of the distribution detection circuit. When the mode identifier bit is "01" (continuous distribution mode), the corresponding insertion strategy is "continuous continuation strategy". The core purpose is to maintain the continuous distribution characteristics of occupied sub-units and reduce index fragmentation.

[0109] The insertion strategy selection circuit retrieves the maximum value (tail index) or minimum value (head index) of occupied indices from the temporary index cache and calculates adjacent free indices (tail index + 1 or head index - 1). If the adjacent index is free, the sub-cell corresponding to that index is preferentially selected as the insertion position. If the adjacent index is occupied (e.g., head index - 1 is out of range or tail index + 1 is out of range), the free sub-cell closest to the contiguous index block is selected to ensure that the newly inserted mapping relationship forms a new contiguous distribution with the original contiguous blocks.

[0110] When the mode identifier is "10" (non-continuous distribution mode), the corresponding insertion strategy is "gap filling strategy," the core purpose of which is to optimize sub-cell utilization by utilizing existing index gaps. The insertion strategy selection circuit scans the index gaps in the temporary index cache (e.g., gaps 3 and 4 between index 2 and index 5), filters out the smallest gap (i.e., the free index segment with the smallest span), and preferentially selects the first free sub-cell within that gap as the insertion position. If there are multiple smallest gaps with equal spans, the first gap is selected in ascending order of index value to avoid further fragmentation of free sub-cells.

[0111] After determining the insertion strategy, the write control circuit of the address translation buffer module locates the corresponding free sub-unit in the target shared buffer unit according to the target insertion index output by the strategy. The write control circuit writes the virtual base address in the target virtual address to the base address storage field of the free sub-unit, writes the address identification information to the identification information field, writes the physical page number to the page number storage field, and sets the validity flag bit corresponding to the free sub-unit to "01" (indicating that the mapping relationship is valid).

[0112] Subsequently, the occupancy status of the free sub-unit in the sub-unit index status table is updated to "occupied," and the index sequence in the temporary index cache is updated synchronously. If the original continuous distribution pattern remains continuous after insertion, or the gaps in the non-continuous distribution pattern are filled and reduced, the distribution detection circuit will update the index distribution pattern record of the target shared buffer unit, providing an accurate pattern basis for subsequent insertion of new mapping relationships. The entire insertion process is controlled by a synchronous clock signal to ensure that the mapping relationship between the virtual base address, address identification information, and physical page number is stored completely and accurately, without affecting the validity of other stored mapping relationships within the target shared buffer unit.

[0113] By identifying the index distribution pattern of occupied buffer sub-units in the target shared buffer unit and determining the corresponding insertion strategy based on the pattern, the address translation buffer module can efficiently insert new mapping relationships into free sub-units, optimize data storage layout, and improve the utilization rate of buffer units and address translation efficiency.

[0114] According to an embodiment of the present invention, the address translation buffer module is further configured to: switch the access mode of the target buffer unit to a shared mode in response to the target buffer unit being in an exclusive mode and the utilization rate of the buffer sub-units in the target buffer unit being lower than a first preset threshold; and switch the access mode of the target buffer unit to an exclusive mode in response to the target buffer unit being in a shared mode and the utilization rate of the buffer sub-units corresponding to the address identification information being higher than a second preset threshold, and clear the stored physical page numbers corresponding to other virtual base addresses.

[0115] The address translation buffer module is configured with a sub-unit utilization statistics circuit, a threshold configuration register, and mode switching trigger logic for each buffer unit. The utilization statistics circuit collects the occupancy status of all sub-units within the buffer unit in real time (by reading the sub-unit idle status bit) and calculates the current utilization rate (number of occupied sub-units / total number of sub-units) using a ratio calculation unit. The threshold configuration register supports writing a first preset threshold (e.g., 20%, used for exclusive-to-share conversion) and a second preset threshold (e.g., 80%, used for shared-to-exclusive conversion) via the system bus, and the thresholds can be dynamically adjusted according to system performance requirements. Simultaneously, each buffer unit's mode identifier register is directly linked to the utilization statistics circuit and threshold comparator to ensure the real-time performance and accuracy of mode switching.

[0116] When the target buffer unit is currently in exclusive mode, the utilization statistics circuit continuously samples the occupancy of its internal sub-units. After each sampling, the ratio calculation unit outputs the current utilization value and transmits it to the threshold comparator for comparison with the first preset threshold.

[0117] If the utilization rate is lower than the first preset threshold for multiple consecutive samplings (e.g., 3 clock cycles), it indicates that the sub-unit resources of the buffer unit are not being fully utilized, and continuing to maintain exclusive mode would result in resource waste. At this time, the threshold comparator generates a mode switching trigger signal and sends it to the buffer unit's mode control circuit. Upon receiving the signal, the mode control circuit updates the mode flag bit in the mode flag register from "00" (exclusive mode) to "10" or "01" (shared mode). Simultaneously, it removes the restriction of "binding only a single virtual base address," updates the buffer unit's virtual base address binding list to the "can add bindings" state, and synchronizes the mode switching result to the group's unit status management circuit. This ensures that other modules within the group obtain the resource availability status of the buffer unit in real time, providing support for the subsequent mapping and insertion of new virtual base addresses.

[0118] When the current access mode of the target buffer unit is the shared mode, the utilization statistics circuit will first use the virtual base address comparison logic to filter out all buffer sub-units bound to the target virtual base address corresponding to the current address identification information (i.e., the set of buffer sub-units exclusive to the virtual base address), and then calculate the utilization rate (number of occupied buffer sub-units in the set / total number of buffer sub-units in the set) for the set of buffer sub-units.

[0119] After the calculation result is transmitted to the threshold comparator, it is compared with the second preset threshold. If the utilization rate of multiple consecutive samples is higher than the second preset threshold, it indicates that the target virtual base address has a high demand for the sub-unit resources of the buffer unit. Continuing to maintain the shared mode is likely to cause access conflicts or conversion delays. At this time, the shared to exclusive mode switching process is triggered.

[0120] The mode control circuit updates the mode identifier bit of the target buffer unit from "01" or "10" to "00" (exclusive mode) and locks the bound virtual base address of the buffer unit to the target virtual base address. Subsequently, the virtual base address comparison circuit iterates through the base addresses of all buffer sub-units, marking those that do not match the target virtual base address as pending cleanup. This triggers the internal data erasure logic of these buffer sub-units, clearing the stored mapping entries such as physical page numbers and address identifiers corresponding to non-target base addresses, and updating the idle status bit of these buffer sub-units to "idle". Finally, the mode switching result and the cleaned buffer sub-unit status are synchronized to the group's unit status management circuit to ensure that the buffer unit subsequently provides dedicated storage services only for the target virtual base address, improving the address translation efficiency corresponding to that base address.

[0121] By dynamically adjusting the access mode of the target buffer unit, the address translation buffer module can flexibly switch between exclusive and shared modes. When the target buffer unit is in exclusive mode and its utilization rate is lower than a first preset threshold, it switches to shared mode to improve resource utilization. When it is in shared mode and the utilization rate of a specific buffer sub-unit is higher than a second preset threshold, it switches to exclusive mode and clears the physical page numbers corresponding to other virtual base addresses, thereby optimizing the utilization efficiency of the buffer unit and improving address translation performance.

[0122] Figure 7 A flowchart of a request processing method according to an embodiment of the present invention is shown.

[0123] like Figure 7 As shown, this embodiment includes operations S710 to S730.

[0124] During operation of S710, an access request for a target virtual address is received from the computing unit.

[0125] In operation of S720, in response to an access request, the corresponding physical page number is searched in the address translation buffer module based on the target virtual address to determine the physical address. The address translation buffer module includes multiple buffer units. Searching for the corresponding physical page number in the address translation buffer module includes: determining the target buffer unit from the multiple buffer units based on the virtual base address in the target virtual address; and searching for the physical page number corresponding to the target virtual address from the physical page numbers stored in the target buffer unit that correspond to at least two different virtual base addresses based on the address identification information in the target virtual address.

[0126] During operation, S230 accesses system memory based on physical address and sends the data obtained from system memory to the computing unit.

[0127] According to an embodiment of the present invention, after receiving a target virtual address access request sent by the computing unit, the memory management unit of the accelerator initiates an address translation process. The address translation buffer module is pre-divided into multiple buffer units, each supporting the storage of physical page number mapping relationships corresponding to at least two different virtual base addresses. The virtual base address in the target virtual address is extracted, and a unique target buffer unit is located from the multiple buffer units through address matching logic. Then, the address identification information is extracted and compared with multiple sets of mapping relationships stored in the target buffer unit to filter out matching physical page numbers and combine them to generate a physical address. Finally, the memory management unit accesses the system memory based on the physical address, obtains the data, and feeds it back to the computing unit via the data bus.

[0128] By sharing the mapping relationship between multiple virtual base addresses in the buffer unit, the storage resource utilization of the address translation buffer module is significantly improved, reducing the waste of excessive buffer resources occupied by a single virtual base address. Based on the hierarchical lookup logic using virtual base addresses and address identifier information, the physical page number lookup path is shortened, address translation latency is reduced, and the real-time access to memory by the computing unit is ensured. The overall process does not require frequent triggering of system memory page table traversal, reducing memory access overhead, improving the accelerator's data acquisition efficiency, and thus enhancing the accelerator's overall computing performance.

[0129] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0130] Those skilled in the art will understand that the features described in the various embodiments of the present invention can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments of the present invention can be combined and / or combined in various ways without departing from the spirit and teachings of the present invention. All such combinations and / or combinations fall within the scope of the present invention.

[0131] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. An accelerator characterized by, The accelerator comprises: a computing unit configured to send an access request for a target virtual address to a memory management unit; the memory management unit comprises an address translation cache module, and the memory management unit is configured to, in response to receiving the access request, find a corresponding physical page number in the address translation cache module according to the target virtual address to determine a physical address; wherein the address translation cache module comprises a plurality of cache units, and the address translation cache module is configured to determine a target cache unit from the plurality of cache units according to a virtual base address in the target virtual address; and find a physical page number corresponding to the target virtual address from physical page numbers corresponding to at least two different virtual base addresses stored in the target cache unit according to address identification information in the target virtual address, to determine the physical address; the memory management unit is further configured to access a system memory according to the physical address, and send data obtained from the system memory to the computing unit; wherein the address translation cache module is further configured to: in response to the absence of a free subunit corresponding to the address identification information in the target cache unit, update the target cache unit from a shared mode capable of simultaneously storing physical page numbers corresponding to at least two different virtual base addresses to an exclusive mode of storing only a physical page number corresponding to a virtual base address in the target virtual address; in the exclusive mode, clear the physical page numbers corresponding to other virtual base addresses different from the virtual base address in the target virtual address in the target cache unit; in response to a cache subunit storing the physical page numbers corresponding to the other virtual base addresses becoming a free subunit, insert the physical page number into the free subunit of the target cache unit.

2. The accelerator of claim 1, wherein Each of the cache units comprises a plurality of cache subunits, and the address translation cache module is further configured to: in the target cache unit, determine a plurality of candidate subunits corresponding to the address identification information, wherein each of the candidate subunits is allocated to store a physical page number corresponding to the virtual base address; determine a target subunit from the plurality of candidate subunits based on a subunit index in the target virtual address; splice the physical page number stored in the target subunit and an intra-page offset in the target virtual address to obtain the physical address, wherein the intra-page offset is used to indicate a specific position in a physical page identified by the physical page number.

3. The accelerator of claim 1, wherein The plurality of cache units in the address translation cache module are divided into a plurality of cache unit groups, and the address translation cache module is further configured to: determine a target cache unit group from the plurality of cache unit groups according to unit index information in the target virtual address; in the target cache unit group, find a corresponding physical page number according to the virtual base address and the address identification information in the target virtual address to determine the physical address.

4. The accelerator of claim 1, wherein The memory management unit further comprises a page table traversal module, and the address translation cache module is further configured to: in response to the fact that the target virtual address does not correspond to a physical address in the target buffer unit, sending a translation miss request to the page table walking module; the page table walking module is configured to, in response to receiving the translation miss request, access a page table structure in the system memory and perform page table walking to obtain a physical page number corresponding to the target virtual address; the address translation buffer module is further configured to:

5. The accelerator of claim 3, wherein in response to the fact that there is no target buffer unit corresponding to the virtual base address in the plurality of buffer units, determine a candidate buffer unit that satisfies a sharing condition from other buffer units in a target buffer unit group in which the target buffer unit is located, wherein the sharing condition includes that the access mode of the candidate buffer unit is an exclusive mode and there is a free sub-unit in the candidate buffer unit; in response to the fact that there is at least one candidate buffer unit, determine a target shared buffer unit from the at least one candidate buffer unit and update the access mode of the target shared buffer unit to a shared mode; insert the virtual base address, the address identification information, and the physical page number as a mapping relationship into the free sub-unit of the target shared buffer unit. the address translation buffer module is further configured to:

6. The accelerator of claim 5, wherein, in response to the fact that there is no candidate buffer unit, determine a replacement buffer unit from other buffer units in a target buffer unit group in which the target buffer unit is located according to a preset replacement policy; clear the physical page numbers corresponding to virtual base addresses other than the virtual base address in the target virtual address in the replacement buffer unit; in response to the fact that the buffer sub-units storing the physical page numbers corresponding to the other virtual base addresses become free sub-units, insert the virtual base address, the address identification information, and the physical page number as a mapping relationship into the free sub-units of the replacement buffer unit. the address translation buffer module is further configured to:

7. The accelerator of claim 5, wherein in response to determining the target shared buffer unit, identify an index distribution mode of the occupied buffer sub-units in the target shared buffer unit; determine an insertion strategy for inserting the address identification information and the physical page number according to the index distribution mode; insert the virtual base address, the address identification information, and the physical page number as a mapping relationship into the free sub-units of the target shared buffer unit according to the insertion strategy; wherein the index distribution mode includes a continuous distribution mode and a non-continuous distribution mode, and the insertion strategy corresponds to the index distribution mode. the address translation buffer module is further configured to:

8. The accelerator of claim 5, wherein, in response to the fact that the access mode of the target buffer unit is an exclusive mode and the utilization rate of the buffer sub-units in the target buffer unit is lower than a first preset threshold, switch the access mode of the target buffer unit to a shared mode; ​ In response to the access mode of the target buffer unit being the shared mode and the utilization of the buffer sub-unit corresponding to the address identification information being higher than a second preset threshold, the access mode of the target buffer unit is switched to the exclusive mode, and the stored physical page numbers corresponding to other virtual base addresses are emptied.

9. A request processing method characterized by comprising: The method is applied to an accelerator, and the method comprises: receiving an access request for a target virtual address from a computing unit; in response to the access request, finding a corresponding physical page number in an address translation buffer module according to the target virtual address to determine a physical address; wherein the address translation buffer module comprises a plurality of buffer units, and the finding of the corresponding physical page number in the address translation buffer module comprises: determining a target buffer unit from the plurality of buffer units according to a virtual base address in the target virtual address; and finding a physical page number corresponding to the target virtual address from physical page numbers corresponding to at least two different virtual base addresses stored in the target buffer unit according to address identification information in the target virtual address; accessing a system memory according to the physical address and sending data obtained from the system memory to the computing unit; wherein the method further comprises: in response to the absence of an idle sub-unit corresponding to the address identification information in the target buffer unit, updating the target buffer unit from the shared mode capable of simultaneously storing physical page numbers corresponding to at least two different virtual base addresses to the exclusive mode of storing only a physical page number corresponding to a virtual base address in the target virtual address; in the exclusive mode, emptying the physical page numbers corresponding to other virtual base addresses different from the virtual base address in the target virtual address in the target buffer unit; in response to the buffer sub-unit storing the physical page numbers corresponding to the other virtual base addresses becoming an idle sub-unit, inserting the physical page number into the idle sub-unit of the target buffer unit.

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