A method for input independence analysis of large-scale digital circuits based on BDD

Abstract

This invention discloses a method for input independence analysis of large-scale digital circuits based on BDD. The method converts the circuit Verilog file into a NAND graph (AIG) and performs logic optimization to extract the sets of input and output variables. It then converts the AIG network into a global BDD representation and reduces the number of nodes. A multivariate product term cube is constructed with respect to input groups S and X. The Boolean derivative of Di with respect to each input variable in input group S is calculated, and the result is logically ORed to obtain the synthesis sensitivity function diff_or_i. The method then performs the logical inverse operation and full quantization, extracts the specific logical assignment vector of input group L, and determines the independence of Di with respect to input group S. This method avoids the computational bottleneck of exponential complexity and still possesses good computational performance and scalability in large-scale digital circuits. Its independence determination results are unique and reliable, and it can be widely applied in scenarios such as logic synthesis, formal verification, security and testability analysis.

Description

Technical Field

[0001] This invention relates to logic and structural analysis methods for large-scale digital circuits, specifically to a method for input independence analysis of large-scale digital circuits based on BDD (Binary Decision Diagram). Background Technology

[0002] As integrated circuit design scales up, modern large-scale digital circuits often contain tens of thousands of logic gates and complex modules, posing significant challenges to circuit analysis and verification due to their high complexity and computational demands. In circuit optimization and verification, the identification of "don't-care" terms plays a crucial role. Don't-care terms refer to inputs that, when some input conditions are fixed, are no longer correlated with the circuit output; that is, these inputs have no impact on the final output. Accurately determining whether a given input is a don't-care term not only helps eliminate redundant logic but also provides key support for circuit optimization, power consumption reduction, area reduction, and verification complexity control.

[0003] However, existing methods still have significant shortcomings in the identification of circuit-independent terms. Traditional Boolean function independence analysis often relies on algebraic reasoning or exhaustive search. When the circuit size increases and the number of free inputs becomes enormous, the analysis process easily incurs exponential overhead, making it difficult to directly apply to the efficient analysis and optimization of large-scale digital circuits. This methodological bottleneck limits the full utilization of circuit-independent terms in the design and verification process of large-scale digital circuits. Due to the above-mentioned shortcomings, there is an urgent need for an efficient method for identifying circuit-independent terms to support the design optimization and formal verification of large-scale digital circuits. Summary of the Invention

[0004] For any large-scale digital circuit containing three input groups L, S, X and one output group D, we analyze each output variable Di separately and propose how to determine whether there exists a logic vector assigned to input group L such that the output variable Di is completely independent of input group S under this assignment condition, that is, the output variable Di does not depend on any input variable in input group S.

[0005] The core challenge in solving the aforementioned judgment problem lies in the fact that, in large-scale digital circuits, using traditional enumeration methods (such as simulation and exhaustive traversal of circuit networks) inevitably leads to exponential time and space overhead, making it difficult to meet the efficiency and scalability requirements of engineering applications. Furthermore, the existence of the input group X increases the complexity of the problem; its values ​​and logical relationships need to be reasonably constrained and efficiently processed while ensuring the correctness of the judgment. For large-scale digital circuits, to reduce running time and memory consumption, an efficient logical representation structure needs to be selected to support accurate modeling and fast computation of irrelevant terms.

[0006] To address the aforementioned judgment problem, existing circuit function analysis methods typically rely on algebraic expansion, Boolean equation simplification, or step-by-step verification methods based on SAT. These methods have the following limitations in large-scale digital circuits:

[0007] 1) High complexity: As the number of input variables increases, traditional methods face exponential operations, and the computation is not scalable;

[0008] 2) The judgment is not intuitive: It lacks a systematic framework for analyzing function independence, making it difficult to quickly locate key inputs in large-scale digital circuits;

[0009] 3) Limited application: Existing methods are often limited to equivalence verification or variable elimination, and cannot be extended to broader application scenarios such as logic synthesis and sensitivity analysis.

[0010] To address the aforementioned problem in determining independence, this invention provides a method for input independence analysis of large-scale digital circuits based on BDD (Browser-Driven Design). This method avoids the computational bottleneck of exponential complexity, maintaining good computational performance and scalability in large-scale digital circuits. Furthermore, its independence determination results are unique and reliable, making it widely applicable to scenarios such as logic synthesis, formal verification, security and testability analysis. This provides an efficient and scalable solution for the optimization and verification of ultra-large-scale digital circuits.

[0011] The technical solution adopted by this invention to solve the above-mentioned technical problems is as follows: a method for input independence analysis of large-scale digital circuits based on BDD. The circuit to be analyzed by this method includes three input groups L, S, and X and one output group D. The steps of this method are as follows:

[0012] S1. Convert the Verilog file containing the circuit information to be analyzed into an And-InverterGraph (AIG), perform logic optimization, and then extract the set of input variables and the set of output variables of the circuit.

[0013] S2. Convert the optimized AIG network into a global BDD representation and reduce the number of BDD nodes through a dynamic variable reordering strategy.

[0014] S3. Construct a multivariate product cube with respect to the input sets S and X;

[0015] S4. For each output variable Di in the output group D, calculate its Boolean derivative with respect to each input variable in the input group S in turn, and perform a logical OR operation on all derivative results to obtain the comprehensive sensitivity function diff_or_i.

[0016] S5. Take the logical inverse operation on diff_or_i to obtain ¬diff_or_i, and perform full quantization on ¬diff_or_i with respect to the cube;

[0017] S6. Extract the specific logic assignment vector of input group L from the full quantization result. If there is a set of assignments that makes the full quantization result true, then determine that the output variable Di does not depend on the input group S under the assignment of input group L, and its logic value is determined only by the combinational logic of input group L and X.

[0018] As a preferred option, the specific process of step S1 is as follows: use the open-source logic synthesis tool Yosys to parse the Verilog file containing the circuit information to be analyzed, convert it into a logic netlist representation and uniformly generate a NAND graph AIG. Then, call the ABC tool to perform logic optimization on the AIG network, remove redundant nodes, and then extract the circuit's input variable set L={L1,L2,…,Li,…,La}, S={S1,S2,…,Si,…,Sb}, X={X1,X2,…,Xi,…,Xc} and output variable set D={D1,D2,…,Di,…,Dn}.

[0019] Preferably, in step S2, the optimized AIG network is converted into a global BDD representation by calling the function interface in the open-source BDD code library CUDD (Colorado University DecisionDiagram Package).

[0020] Preferably, in step S3, S={S1,S2,…,Si,…,Sb} and X={X1,X2,…,Xi,…,Xc} are used as the set of free variables for sensitivity analysis. A multivariate product term cube for the input set S and X is constructed through the function interface provided by CUDD. This cube represents all possible assignment spaces for the input set S and X.

[0021] As a preferred option, the specific process of step S4 is as follows:

[0022] S4.1 For each output function Di, calculate its Boolean derivative with respect to each input variable in the input set S:

[0023] ,

[0024] in and Boolean functions with respect to variables x The positive and negative cofactors; if This means that the value of function F does not depend on the variable. x That is, the output variable Di does not depend on the input variable;

[0025] S4.2 Perform a logical OR operation on all differential results to obtain the comprehensive sensitivity function diff_or_i:

[0026] ,

[0027] in b The number of input variables in the input group S; the comprehensive sensitivity function diff_or_i is used to characterize the dependence of the output variable Di on any input variable in the input group S.

[0028] Preferably, step S5 is performed as follows: The logical inverse operation on diff_or_i is taken to obtain ¬diff_or_i, which indicates whether the output variable is insensitive to any input variable in the input group S under the current input conditions. Then, universal quantization is performed on ¬diff_or_i with respect to the cube.

[0029] ,

[0030] This formula represents a Boolean function. F For variables x Are all possible values ​​true?

[0031] Compared with existing technologies, this invention has the following advantages: The method of this invention utilizes the shared subgraph and uniqueness representation mechanism of BDD, avoiding the exponential complexity of traditional Boolean expansion when determining whether a circuit output depends on some inputs, thus significantly improving computational efficiency. In practical applications, as the scale of the circuit increases, this invention maintains high computability and stability, making it suitable for the analysis needs of large-scale digital circuits. Simultaneously, the independence determination process of this invention has standardized and formalized guarantees, independent of the order of variable elimination, thus ensuring unique and reliable results. By combining with logic synthesis, formal verification, security analysis, and testability analysis, this invention can not only help discover and eliminate redundant inputs and simplify logic structures, but also quickly identify redundant signals in circuit equivalence, determine the impact of sensitive inputs on key outputs, and reduce testing complexity. Compared with traditional methods, this invention has significant advantages in efficiency, scalability, and application breadth, providing a new approach for the logic and structural analysis of large-scale digital circuits and bringing greater practical value to the optimization and verification stages of the EDA toolchain. Attached Figure Description

[0032] Figure 1 This is a flowchart of the input independence analysis method for large-scale digital circuits based on BDD in the embodiment.

[0033] Figure 2 This is a simple circuit example described in Case01.v of the embodiments;

[0034] Figure 3 The diagram shows the result of running the method of the present invention on a simple circuit example in the embodiment. Detailed Implementation

[0035] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0036] Example: A method for input independence analysis of large-scale digital circuits based on BDD. This method targets a circuit with three input groups L, S, and X and one output group D, such as... Figure 1 As shown, the steps of this method are as follows:

[0037] S1. Use the open-source logic synthesis tool Yosys to parse the Verilog file containing the circuit information to be analyzed, convert it into a logic netlist representation, and generate a unified NAND graph AIG. Then, call the ABC tool to perform logic optimization on the AIG network, remove redundant nodes, and then extract the circuit's input variable set L={L1,L2,…,Li,…,La}, S={S1,S2,…,Si,…,Sb}, X={X1,X2,…,Xi,…,Xc} and output variable set D={D1,D2,…,Di,…,Dn}.

[0038] S2. Call the function interface in the open-source BDD code library CUDD to convert the optimized AIG network into a global BDD representation, and reduce the number of BDD nodes through a dynamic variable reordering strategy.

[0039] Boolean Component Derivatives (BDDs) are an efficient and standardized representation of Boolean functions, ensuring good computational characteristics for both logical equivalence determination and operations on input variables. This invention converts the optimized AIG network into a global BDD representation. Furthermore, during BDD construction, a dynamic variable reordering strategy is used to reduce the number of BDD nodes, thereby avoiding the exponential expansion of the state space.

[0040] S3. Using S={S1,S2,…,Si,…,Sb} and X={X1,X2,…,Xi,…,Xc} as the set of free variables for sensitivity analysis, construct a multivariate product term cube for the input set S and X through the function interface provided by CUDD. This cube represents all possible assignment spaces for the input set S and X and is the basic operation object for subsequent quantification and sensitivity analysis.

[0041] S4. For each output variable Di in the output group D, calculate its Boolean derivative with respect to each input variable in the input group S in turn, and perform a logical OR operation on all derivative results to obtain the comprehensive sensitivity function diff_or_i.

[0042] The specific process of step S4 is as follows:

[0043] S4.1 For each output function Di, calculate its Boolean derivative with respect to each input variable Si in the input set S:

[0044] ,

[0045] in and Boolean functions with respect to variables x The positive and negative cofactors; if This means that the value of function F does not depend on the variable. x That is, the output variable Di does not depend on the input variable.

[0046] Boolean differentiation is used to measure the sensitivity of an output function to changes in an input variable. The result is a Boolean function that indicates under what conditions the output function depends on the input variable.

[0047] S4.2 Perform a logical OR operation on all the differential results of Si to obtain the comprehensive sensitivity function diff_or_i:

[0048] ,

[0049] in b The number of input variables in the input group S; the comprehensive sensitivity function diff_or_i is used to characterize the dependence of the output variable Di on any input variable in the input group S.

[0050] S5. Take the logical inverse operation on diff_or_i to obtain ¬diff_or_i, which indicates whether the output variable is insensitive to any input variable in the input group S under the current input conditions. Then, perform full quantization on ¬diff_or_i with respect to the cube:

[0051] ,

[0052] This formula represents a Boolean function. F For variables x Are all possible values ​​true?

[0053] If `diff_or_i` is 0, it means that under the current input conditions, the output variable `Di` is insensitive to any input variable in the input set `S`. The purpose of performing full quantization on `diff_or_i` with respect to the cube is to ensure that the output variable `Di`'s dependence on the input set `S` depends only on the input set `L`. If the quantization result is always true, it can be determined that under the current input conditions, the output variable `Di` is completely independent of the input set `S`.

[0054] S6. Extract the specific logic assignment vector of input group L from the full quantization result. If there exists an assignment that makes the full quantization result true, then the output variable Di is determined to be independent of input group S under the assignment of input group L, and its logic value is determined only by the combinational logic of input groups L and X. This assignment result is the determination condition obtained by the method of this invention, providing a complete calculation process for circuit independence analysis.

[0055] Figure 2 As an example of a simple circuit described in Case01.v, this circuit includes three input groups L={L1,L2}, S={S1,S2}, X={X1} and one output group D={D1}. The result of running the method of this invention on this circuit is shown in the figure below. Figure 3 .

[0056] The test cases and test results of the method of this invention provided by Innoda are shown in Table 1. Test case Case01.v in Table 1 is... Figure 2 The simplified circuit is shown in Table 1. As can be seen from Table 1, this invention has a significant advantage in terms of runtime while ensuring correct solution. Furthermore, the peak memory overhead occurs during the Yosys network transformation process, which fully demonstrates the superiority of this invention in terms of logical completeness and computational performance.

[0057] Table 1

[0058]

[0059] This invention combines advanced Boolean algebra with BDD representation to achieve efficient determination of whether an output depends on a specific input in large-scale digital circuits. Compared to traditional methods that rely on algebraic simplification or SAT verification, this invention utilizes the shared subgraph and uniqueness representation mechanism of BDD to avoid the computational bottleneck of exponential complexity, while still maintaining good computational performance and scalability in large-scale digital circuits. Furthermore, its independence determination process is standardized and complete, independent of the order of variable elimination, and yields unique and reliable results. It can be widely applied to scenarios such as logic synthesis, formal verification, security and testability analysis, providing an efficient and scalable solution for the optimization and verification of large-scale digital circuits.

Claims

1. A method for input independence analysis of large-scale digital circuits based on BDDs, characterized by, The method is aimed at a to-be-analyzed circuit comprising three input groups L, S and X and one output group D, and the steps of the method are as follows: S1, converting a Verilog file containing information of the to-be-analyzed circuit into an AND graph AIG, performing logic optimization, and extracting an input variable set and an output variable set of the circuit; S2, converting the optimized AIG network into a global BDD representation, and reducing the number of BDD nodes through a dynamic variable reordering strategy; S3, constructing a multi-variable product item cube about the input groups S and X; S4, for each output variable Di in the output group D, sequentially calculating a Boolean differential about each input variable in the input group S, and performing a logical or operation on all differential results to obtain a comprehensive sensitivity function diff_or_i; S5, taking a logical NOT operation on diff_or_i to obtain ¬diff_or_i, and performing a universal quantification on ¬diff_or_i about the cube; S6, extracting a specific logic assignment vector of the input group L from the universal quantification result, and when there is a set of assignments that makes the universal quantification result true, it is determined that the output variable Di is not dependent on the input group S under the assignment of the input group L, and the logic value is determined by the combined logic of the input groups L and X.

2. The method for input independence analysis of large scale digital circuits based on BDD according to claim 1, wherein, The specific process of step S1 is as follows: a Verilog file containing information of the to-be-analyzed circuit is parsed by using an open-source logic synthesis tool Yosys, which is converted into a logic netlist representation and uniformly generated into an AND graph AIG, then the ABC tool is called to optimize the AIG network, remove redundant nodes, and extract the input variable set L={L1, L2, …, Li, …, La}, S={S1, S2, …, Si, …, Sb}, X={X1, X2, …, Xi, …, Xc} and the output variable set D={D1, D2, …, Di, …, Dn} of the circuit.

3. The method for input independence analysis of large scale digital circuits based on BDD according to claim 2, wherein, In step S2, the function interface in the open-source BDD code library CUDD is called to convert the optimized AIG network into a global BDD representation.

4. The method for input independence analysis of large scale digital circuits based on BDD according to claim 3, wherein, In step S3, S={S1, S2, …, Si, …, Sb} and X={X1, X2, …, Xi, …, Xc} are taken as a sensitivity analysis free variable set, and a multi-variable product item cube about the input groups S and X is constructed through the function interface provided by CUDD, which represents all possible assignment spaces of the input groups S and X.

5. The method for input independence analysis of large scale digital circuits based on BDD according to any one of claims 1-4, characterized in that, The specific process of step S4 is as follows: S4.1, for each output function Di, a Boolean differential about each input variable in the input group S is sequentially calculated: ， in and Boolean functions with respect to variables x The positive and negative cofactors; if This means that the value of function F does not depend on the variable. x That is, the output variable Di does not depend on the input variable; S4.2, a logical or operation is performed on all differential results to obtain a comprehensive sensitivity function diff_or_i: ， wherein b is the number of input variables in the input set S; the comprehensive sensitivity function diff_or_i is used to depict the dependency of the output variable Di on any input variable in the input set S.

6. The method for input independence analysis of large scale digital circuits based on BDD according to claim 5, wherein, The specific process of step S5 is as follows: a logical NOT operation is performed on diff_or_i to obtain ¬diff_or_i, which represents whether the output variable is insensitive to any input variable in the input group S under the current input condition, and then a universal quantification is performed on ¬diff_or_i about the cube: ， The formula represents the Boolean function F is true for all values of the variable x .

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