Multi-process packaging chip heterogeneous integration design simulation method and device

Abstract

The application discloses a multi-process packaging chip heterogeneous integration design simulation method and device, the method comprises the following steps: obtaining at least two design files of chip design and packaging design, analyzing geometric and layering information in the design files and generating chip three-dimensional model and packaging three-dimensional model; the chip three-dimensional model is placed with the packaging three-dimensional model to form a stacking structure, and an electrical interconnection relationship is established between the chip and the packaging based on a preset interconnection mode; adding a simulation port to the stacking structure to be analyzed and defining port parameters; different electromagnetic simulation parameters are configured for different physical scale components in the stacking structure; for the configured model, the intelligent grid technology is applied for dissection and the moment method solver is used for calculation to obtain a packaging simulation result. The embodiment of the application solves the technical problems of slow simulation operation and low precision in the related art.

Description

TECHNICAL FIELD

[0001] The application relates to a multi-process packaging chip heterogeneous integration design simulation method and device, and belongs to the technical field of electronic design automation (EDA). BACKGROUND

[0002] With Moore's law approaching the physical limit, heterogeneous integration through advanced packaging technology has become a key path to improve the performance of chip systems. 2.5D / 3D packaging and Chiplet technology can integrate chips of different process technologies and different functions, but face serious challenges in electromagnetic simulation:

[0003] Model construction is complex: traditional tools are difficult to efficiently process the complex three-dimensional stacked structure of chips, Interposer and packaging across scales (nanometers to centimeters).

[0004] Simulation efficiency is low: existing electromagnetic tools often have problems such as slow calculation speed, large memory occupation and long iteration period when processing large-scale heterogeneous integration systems.

[0005] Design process is fragmented: chip, packaging and system design simulation are often independent of each other, lacking efficient collaborative analysis means, which can easily lead to repeated design due to collaboration problems. SUMMARY

[0006] Therefore, the application provides a multi-process packaging chip heterogeneous integration design simulation method and device, which can simplify the modeling process of complex heterogeneous integration structure while ensuring accuracy and shorten the model preparation time.

[0007] The first aspect of the embodiment of the application discloses a multi-process packaging chip heterogeneous integration design simulation method, which comprises the following steps: obtaining at least two design files of chip design and packaging design, analyzing the geometric and stacking information in the design files and generating a chip three-dimensional model and a packaging three-dimensional model; placing the chip three-dimensional model and the packaging three-dimensional model relative to each other to form a stacked structure and establishing an electrical interconnection relationship between the chip and the packaging based on a preset interconnection mode; adding a simulation port to the network to be analyzed of the stacked structure and defining port parameters; for different physical scale components in the stacked structure, different electromagnetic simulation parameters are configured respectively; for the configured model, the intelligent grid technology is applied for subdivision and the method of moments solver is used for calculation to obtain a packaging simulation result.

[0008] Further, the method further comprises: configuring different electromagnetic simulation parameters for different physical scale components in the stacked structure, respectively, including: for a first metal layer and a first via representing a chip, setting a model approximation manner of the first metal layer as a thick film model, setting a model approximation manner of the first via as a lumped model, and applying a first numerical value of a fine mesh; for a second metal layer and a second via representing a package, setting model approximation manners of the second metal layer and the second via as three-dimensional full-wave models, and applying a second numerical value of a sparse mesh, wherein the second numerical value is greater than the first numerical value.

[0009] Further, the method further comprises: establishing an electrical interconnection relationship between the chip and the package based on a preset interconnection manner, including: providing a visual assembly interface; and implementing electrical interconnection of upper and lower chip and package structures in at least one of a bump, a bonding wire, and a hybrid bonding manner; wherein the visual assembly interface supports flipping, rotating, mirroring, and local area cutting operations on any three-dimensional model; and wherein the local area cutting operation is used for cutting a layout arbitrarily for subsequent simulation on a region of interest.

[0010] Further, the method further comprises: cutting upper and lower chip and package structures of the electrical interconnection based on the local area cutting operation to obtain a single chip three-dimensional model, and further obtaining a simulation result without a package based on the single chip three-dimensional model; and evaluating an influence of a package effect based on the simulation result with the package and the simulation result without the package, wherein the simulation result includes at least one of an S parameter, a power supply impedance, and a DC voltage drop.

[0011] Further, the network to be analyzed is a signal network and / or a power supply network; and the method further comprises: adding a simulation port and defining a port parameter on the network to be analyzed of the stacked structure, including: adding a lumped port and defining a port type and an impedance parameter on the signal network and / or the power supply network.

[0012] A second aspect of the embodiments of the present application discloses a multi-process package chip heterogeneous integration design simulation device, the device comprising: an acquisition module configured to acquire at least two design files of a chip design and a package design, parse geometric and layering information in the design files, and generate a chip three-dimensional model and a package three-dimensional model; an interconnection module configured to relatively place the chip three-dimensional model and the package three-dimensional model to form a stacked structure, and establish an electrical interconnection relationship between the chip and the package based on a preset interconnection manner; a setting module configured to add a simulation port and define a port parameter on a network to be analyzed of the stacked structure; a configuration module configured to configure different electromagnetic simulation parameters for different physical scale components in the stacked structure, respectively; and a simulation module configured to, for a configured model, apply an intelligent mesh technology for subdivision and use a moment method solver for calculation to obtain a simulation result with a package.

[0013] Further, the configuration module includes: a first setting and application module, used to set the model approximation method of the first metal layer representing the chip to a thick film model, set the model approximation method of the first via to a lumped model, and apply a fine mesh of a first value; a second setting and application module, used to set the model approximation method of the second metal layer representing the package to a three-dimensional full-wave model, and apply a sparse mesh of a second value, wherein the second value is greater than the first value.

[0014] Furthermore, the interconnect module includes: a providing module for providing a visual assembly interface; and an electrical connection module for implementing electrical interconnection between upper and lower layer chips and the package structure using at least one method of bumps, bonding wires, and hybrid bonding; wherein the visual assembly interface supports flipping, rotating, mirroring, and local area cutting operations on any three-dimensional model; wherein the local area cutting operation is used to arbitrarily cut the layout for subsequent simulation of the area of ​​interest.

[0015] Furthermore, the device also includes: a cutting module, used to cut the upper and lower layers of electrically interconnected chips and packaging structures based on local area cutting operations to obtain a separate chip three-dimensional model, and then obtain a simulation result without packaging based on the separate chip three-dimensional model; and an evaluation module, used to evaluate the impact of packaging effect based on the simulation result with packaging and the simulation result without packaging, wherein the simulation result includes at least one of S-parameters, power supply impedance and DC voltage drop.

[0016] Furthermore, the network to be analyzed is a signal network and / or a power network; the setting module is specifically used to add lumped ports to the signal network and / or the power network and define the port type and impedance parameters.

[0017] A third aspect of this application discloses a computer-readable storage medium comprising a stored program, wherein the program, when running, controls the execution of the multi-process packaged chip heterogeneous integration design simulation method of the above embodiments in the processor of the device.

[0018] A fourth aspect of this application discloses a computer device, the computer device including a processor and a memory; wherein the memory stores a computer program, the computer program being adapted to be loaded by the processor and executed by the processor to perform the multi-process packaged chip heterogeneous integration design simulation method of the above embodiments.

[0019] Compared with the prior art, the embodiments of this application have the following beneficial effects:

[0020] 1. Significantly improved modeling efficiency: Through multi-format support, visual stacking, wizard-driven workflows, and intelligent meshes, the modeling process for complex heterogeneous integrated structures is greatly simplified, and model preparation time is shortened.

[0021] 2. Excellent simulation performance: The MoM Solver Plus solver, combined with cross-scale mesh technology and three simulation modes, improves the calculation speed by nearly 10 times compared with traditional methods while ensuring accuracy, and the memory usage is only 1 / 20.

[0022] 3. Precise cross-scale analysis capability: Intelligent mesh and tunneling technology perfectly solve the contradiction between accuracy and scale when co-simulating nanoscale chips and centimeter-scale packages.

[0023] 4. Accelerated Design Iteration: "One-stop" multi-process simulation and efficient parallel solution reduce the number of design iterations in chip-packaging-system collaborative analysis and accelerate design convergence. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0025] Figure 1 A flowchart illustrating the simulation method for heterogeneous integrated design of multi-process packaged chips provided in this application embodiment.

[0026] Figure 2 This is a schematic diagram illustrating the import of GDS format design files as provided in an embodiment of this application.

[0027] Figure 3 This is a schematic diagram illustrating the stacking and editing of three-dimensional models provided in the embodiments of this application.

[0028] Figure 4 This is a schematic diagram illustrating the addition of an edge port as provided in an embodiment of this application.

[0029] Figure 5 This is a schematic diagram illustrating the setting of simulation parameters for an embodiment of this application.

[0030] Figure 6 This is a schematic diagram illustrating the setting of simulation parameters for an embodiment of this application.

[0031] Figure 7 This is a structural diagram of the simulation device for heterogeneous integrated design of multi-process packaged chips provided in an embodiment of this application. Detailed Implementation

[0032] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0033] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0034] While existing technologies support partial co-simulation, there is still room for improvement in modeling speed, cross-scale processing accuracy, and the convenience of system co-simulation workflows. Therefore, this invention aims to propose a more efficient and accurate rapid modeling method for heterogeneous integration of multi-process packaged chips, building upon existing technologies to construct a simulation platform for advanced 2.5D / 3DIC packaging and Chiplet heterogeneous integration designs, thus laying the foundation for solving the aforementioned problems. The specific implementation scheme is as follows:

[0035] Example 1:

[0036] Figure 1 A flowchart illustrating the simulation method for heterogeneous integration design of multi-process packaged chips provided in this application embodiment. Figure 1 As shown, the method includes:

[0037] S101. Obtain at least two design files for chip design and packaging design, parse the geometric and stack-up information in the design files, and generate a 3D model of the chip and a 3D model of the packaging.

[0038] First, prepare the chip layout file (e.g., GDS), the package substrate file (e.g., MCM or GDS), and the corresponding layer mapping file (e.g., Layer Map). Then, open the electromagnetic simulation platform and create a new project. Finally, as follows... Figure 2 As shown, by using the file import function, the design files of the chip and package are imported in sequence, and the software automatically generates a 3D visualization model.

[0039] S102. The chip 3D model and the package 3D model are placed relative to each other to form a stacked structure and an electrical interconnection relationship is established between the chip and the package based on a preset interconnection method.

[0040] In this step, establishing an electrical interconnection between the chip and the package based on a preset interconnection method includes:

[0041] S1021. Provides a visual assembly interface.

[0042] S1022. Electrical interconnection between upper and lower layer chips and package structure is achieved by using at least one method of bumps, bonding wires and hybrid bonding.

[0043] The visual assembly interface supports flipping, rotating, mirroring, and cutting local areas of any 3D model.

[0044] The local region cutting operation is used to arbitrarily cut the layout for subsequent simulation of the area of ​​interest. It should be noted that local region cutting is equivalent to a removal operation, and its removal range is flexible: it can target a part of a chip or package, cover the entire package, or even remove one or more chips simultaneously.

[0045] For example, such as Figure 3 As shown, in the software's stacking interface, the chip model is set to "Upper Model" and the package model is set to "Lower Model". By dragging and rotating, the chip is precisely placed above the corresponding pads on the package. Then, an appropriate bump model is selected, and connections are added one by one or in batches to the corresponding pads on the chip and package, ultimately completing the three-dimensional electrical interconnection between the chip and the package.

[0046] S103. Add simulation ports and define port parameters on the network to be analyzed in the stacked structure.

[0047] This invention supports multiple methods for creating ports.

[0048] In one embodiment, the network to be analyzed is a signal network and / or a power network. Adding simulation ports and defining port parameters on the network to be analyzed in the stacked structure includes: adding lumped ports on the signal network and / or the power network and defining port type and impedance parameters.

[0049] As an optional implementation, in the 3D view, lumped ports can be added directly to the signal network or power network to be analyzed, and parameters such as port type and impedance can be defined.

[0050] In another embodiment, such as Figure 4As shown, edge port parameters can be set in the stacked structure.

[0051] S104. Configure different electromagnetic simulation parameters for the components of different physical scales in the stacked structure.

[0052] In this step, different electromagnetic simulation parameters are configured for the components at different physical scales in the stacked structure, including:

[0053] S1041. For the first metal layer and the first via representing the chip, the model approximation method of the first metal layer is set to a thick film model, the model approximation method of the first via is set to a lumped model, and a fine mesh of the first value is applied.

[0054] S1042. For the second metal layer and the second via representing the package, the model approximation method of the second metal layer and the second via is set to a three-dimensional full-wave model, and a sparse mesh of a second value is applied, wherein the second value is greater than the first value.

[0055] The core operation of this invention lies in implementing differentiated settings for the network and model of the chip and the package. Specifically, the metal layer of the chip (nanoscale microstructure) adopts the "Thick" model, and its vias adopt the "Lumped" model, with a mesh size set to 5~60μm; correspondingly, the metal and vias of the package (centimeter-scale large structure) are set to a "3D" full-wave model, with a mesh size set to 150~250μm. This is the core of achieving accurate simulation across scales (balancing accuracy and computational scale).

[0056] As a preferred embodiment, the mesh size for nanoscale microstructures is 10 μm, and the mesh size for centimeter-scale large structures is 200 μm. Different mesh sizes and subdivision methods can be set in the table on the Mesh page.

[0057] The above is one of the steps for simulation configuration.

[0058] The configuration of this embodiment also includes: S1040. Select the corresponding simulation type (such as signal EM, power supply DC) according to the analysis target (such as signal integrity S-parameter, power supply DC).

[0059] The configuration of this embodiment also includes: S1043. Depending on whether the current design stage is initial verification or final approval, select the appropriate mode in the simulation settings: "Speed" mode is used for rapid iteration, and "Accuracy" mode is used for high-precision verification.

[0060] The above simulation configuration can be completed through a visual interface.

[0061] S105. For the configured model, apply smart mesh technology to divide it and use the method of moments solver to perform calculations to obtain encapsulated simulation results.

[0062] In this step, the settings are as follows: Figure 5 and Figure 6 The solution parameters are shown. Start the simulation. The software will mesh according to the mesh size set for different models and use an efficient method of moments solver to perform calculations. It also supports multi-machine parallel acceleration.

[0063] Specifically, such as Figure 5 As shown, three simulation modes are available: Speed, Balanced, and Accuracy, along with the setting of the simulation frequency. The purpose is to enable the electromagnetic simulation engine to accurately calculate the true electrical performance of the designed 2.5D / 3DIC advanced package structure at different frequencies.

[0064] Specifically, Figure 6 The diagram illustrates the settings for Mesh and Advanced. On the Mesh page, you can specify the meshing method for each layer. The Advanced page is used to configure solver parameters, such as sweep settings (maximum number of iterations, convergence tolerance) and geometric operation options (e.g., merging ground vias, removing floating ground networks, removing redundant vias), aiming to improve simulation accuracy and speed.

[0065] The core advantage of the accelerated Method of Moments solver lies in its provision of a fast, efficient, and flexible simulation solution for advanced package designs such as 2.5D / 3DIC. Through algorithm optimization and distributed computing, this solution achieves a significant increase in computation speed and a substantial reduction in memory usage. Its flexible simulation modes also help engineers autonomously balance efficiency and accuracy, effectively addressing cross-scale simulation challenges.

[0066] After the simulation is completed, the software interface displays the results of S-parameters (such as return loss RL and insertion loss IL), power supply impedance, DC voltage drop, etc. Users can compare the simulation results with and without the package to intuitively evaluate the impact of the package effect, thereby guiding the optimization design, as follows:

[0067] S106. Based on the local region cutting operation, the upper and lower layer chips and the packaging structure of the electrical interconnection are cut to obtain a three-dimensional model of a single chip, and then the simulation results without packaging are obtained based on the three-dimensional model of the single chip.

[0068] S107. Evaluate the impact of the packaging effect based on the simulation results with and without the package, wherein the simulation results include at least one of S-parameters, power supply impedance, and DC voltage drop.

[0069] Figure 7 This is a structural diagram of the multi-process packaged chip heterogeneous integration design simulation device provided in an embodiment of this application. Figure 7 As shown, the device includes:

[0070] The acquisition module 701 is used to acquire at least two design files for chip design and packaging design, parse the geometric and layer information in the design files, and generate a 3D model of the chip and a 3D model of the packaging.

[0071] Interconnect module 702 is used to place the chip 3D model and the package 3D model relative to each other to form a stacked structure and establish an electrical interconnection relationship between the chip and the package based on a preset interconnection method.

[0072] The configuration module 703 is used to add simulation ports and define port parameters on the network to be analyzed in the stacked structure.

[0073] The configuration module 704 is used to configure different electromagnetic simulation parameters for components of different physical scales in the stacked structure.

[0074] Simulation module 705 is used to perform subdivision of the configured model using smart mesh technology and calculations using the method of moments solver to obtain encapsulated simulation results.

[0075] Further, the configuration module includes: a first setting and application module, used to set the model approximation method of the first metal layer representing the chip to a thick film model, set the model approximation method of the first via to a lumped model, and apply a fine mesh of a first value; a second setting and application module, used to set the model approximation method of the second metal layer representing the package to a three-dimensional full-wave model, and apply a sparse mesh of a second value, wherein the second value is greater than the first value.

[0076] Furthermore, the interconnect module includes: a providing module for providing a visual assembly interface; and an electrical connection module for implementing electrical interconnection between upper and lower layer chips and the package structure using at least one method of bumps, bonding wires, and hybrid bonding; wherein the visual assembly interface supports flipping, rotating, mirroring, and local area cutting operations on any three-dimensional model; wherein the local area cutting operation is used to arbitrarily cut the layout for subsequent simulation of the area of ​​interest.

[0077] Furthermore, the device also includes: a cutting module, used to cut the upper and lower layers of electrically interconnected chips and packaging structures based on local area cutting operations to obtain a separate chip three-dimensional model, and then obtain a simulation result without packaging based on the separate chip three-dimensional model; and an evaluation module, used to evaluate the impact of packaging effect based on the simulation result with packaging and the simulation result without packaging, wherein the simulation result includes at least one of S-parameters, power supply impedance and DC voltage drop.

[0078] Furthermore, the network to be analyzed is a signal network and / or a power network; the setting module is specifically used to add lumped ports to the signal network and / or the power network and define the port type and impedance parameters.

[0079] The above embodiments can achieve the following effects:

[0080] 1. Significantly improved modeling efficiency: Through multi-format support, visual stacking, wizard-driven workflows, and intelligent meshes, the modeling process for complex heterogeneous integrated structures is greatly simplified, and model preparation time is shortened.

[0081] 2. Excellent simulation performance: The MoM Solver Plus solver, combined with cross-scale mesh technology and three simulation modes, improves the calculation speed by nearly 10 times compared with traditional methods while ensuring accuracy, and the memory usage is only 1 / 20.

[0082] 3. Precise cross-scale analysis capability: Intelligent mesh and tunneling technology perfectly solve the contradiction between accuracy and scale when co-simulating nanoscale chips and centimeter-scale packages.

[0083] 4. Accelerated Design Iteration: "One-stop" multi-process simulation and efficient parallel solution reduce the number of design iterations in chip-packaging-system collaborative analysis and accelerate design convergence.

[0084] Example 2:

[0085] Embodiments of this application also provide a computer device, including: a memory storing an executable program; and a processor for running the program, wherein the program executes the methods in various embodiments of the present invention during runtime.

[0086] The aforementioned memory can refer to devices inside a computer used to store data and programs, including RAM, hard disks, etc. RAM can be used to temporarily store running programs and data, while hard disks can be used to store programs and data long-term. Memory enables the computer to read and write data and execute programs. The aforementioned processor is responsible for executing instructions in computer programs and performing data processing. It can also be responsible for controlling and executing various operations, including arithmetic operations, logical operations, and data transmission.

[0087] Example 3:

[0088] Embodiments of this application also provide a computer-readable storage medium including a stored executable program, wherein, when the executable program is running, it controls the device where the computer-readable storage medium is located to perform the methods of various embodiments of the present invention.

[0089] The aforementioned computer storage media can refer to the media used in computer memory to store certain discontinuous physical quantities. Computer storage media mainly include semiconductors, magnetic cores, magnetic drums, magnetic tapes, laser discs, etc. Computer-readable storage media include stored programs, which can be a set of instructions that a computer can recognize and execute, running on an electronic computer to meet certain information needs.

[0090] Example 4:

[0091] Embodiments of this application also provide a computer program product, including a computer program that, when executed by a processor, implements the methods of various embodiments of the present invention.

[0092] The aforementioned computer program products can refer to software programs that have been written, tested, and released, and can run on computers or other devices. Computer program products can include application programs, operating systems, utility software, etc., used to achieve specific functions or solve specific problems.

[0093] Example 5:

[0094] Embodiments of this application also provide a computer program product, including a non-volatile computer-readable storage medium for storing a computer program that, when executed by a processor, implements the methods in various embodiments of the present invention.

[0095] The aforementioned non-volatile computer-readable storage medium can refer to a medium for storing data. Non-volatile computer-readable storage media can retain data without loss when power is off and can be used to store long-term data, such as operating systems, applications, and user files. Non-volatile storage media can include hard disk drives, solid-state drives, optical disks, and flash memory storage devices, etc.

[0096] Example 6:

[0097] Embodiments of this application also provide a computer program that, when executed by a processor, implements the methods described in the various embodiments of the present invention.

[0098] The aforementioned computer program can refer to a set of instructions used to tell the computer to perform specific tasks or operations. Computer programs can be written by programmers using specific programming languages ​​and can include algorithms, data structures, logic, and control flow. Computer programs can be used for a variety of purposes, including application software, operating systems, etc.

[0099] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0100] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For instance, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces; the indirect coupling or communication connection between units or modules may be electrical or other forms.

[0101] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0102] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0103] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0104] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A simulation method for heterogeneous integration design of multi-process packaged chips, characterized in that, include: Obtain at least two design files, one for chip design and one for packaging design, parse the geometric and stack-up information in the design files, and generate a 3D model of the chip and a 3D model of the packaging. The chip 3D model and the package 3D model are placed relative to each other to form a stacked structure, and an electrical interconnection relationship is established between the chip and the package based on a preset interconnection method; Add a simulation port to the network to be analyzed in the stacked structure and define the port parameters; Different electromagnetic simulation parameters are configured for the components of the stacked structure at different physical scales. For the configured model, intelligent mesh technology is applied to divide it and the method of moments solver is used to perform calculations to obtain encapsulated simulation results; The electromagnetic simulation parameters are configured for different components at different physical scales in the stacked structure, including: For the first metal layer and the first via representing the chip, the model approximation method of the first metal layer is set to a thick film model, the model approximation method of the first via is set to a lumped model, and a fine mesh with a first value is applied. For the second metal layer and the second via representing the package, the model approximation method of the second metal layer and the second via is set to a three-dimensional full-wave model, and a sparse mesh with a second value is applied, wherein the second value is greater than the first value.

2. The simulation method for heterogeneous integration design of multi-process packaged chips according to claim 1, characterized in that, The establishment of an electrical interconnection between the chip and the package based on a preset interconnection method includes: Provides a visual assembly interface; Electrical interconnection between upper and lower layer chips and the package structure is achieved by using at least one method of bump bonding, bonding wire bonding, and hybrid bonding. The visual assembly interface supports flipping, rotating, mirroring, and cutting local areas of any 3D model. The local region cutting operation is used to arbitrarily cut the layout for subsequent simulation of the region of interest.

3. The simulation method for heterogeneous integration design of multi-process packaged chips according to claim 2, characterized in that, Also includes: The upper and lower layer chips and the package structure of the electrical interconnection are cut by local area cutting operation to obtain a three-dimensional model of a single chip, and then the simulation results without package are obtained based on the three-dimensional model of the single chip. The impact of the packaging effect is evaluated based on the simulation results with and without the package, wherein the simulation results include at least one of S-parameters, power supply impedance, and DC voltage drop.

4. The simulation method for heterogeneous integration design of multi-process packaged chips according to claim 1, characterized in that, The network to be analyzed is a signal network and / or a power network; The step of adding a simulation port and defining port parameters on the network to be analyzed in the stacked structure includes: Add lumped ports to the signal network and / or the power network and define the port type and impedance parameters.

5. A simulation device for heterogeneous integration design of multi-process packaged chips, characterized in that, include: The acquisition module is used to acquire at least two design files, namely chip design and packaging design, parse the geometric and stack-up information in the design files, and generate a 3D model of the chip and a 3D model of the packaging. An interconnect module is used to place the chip 3D model and the package 3D model relative to each other to form a stacked structure and establish an electrical interconnect relationship between the chip and the package based on a preset interconnect method; The configuration module is used to add simulation ports and define port parameters on the network to be analyzed in the stacked structure. A configuration module is used to configure different electromagnetic simulation parameters for components of different physical scales in the stacked structure. The simulation module is used to perform subdivision of the configured model using smart mesh technology and calculations using the method of moments solver to obtain encapsulated simulation results. The configuration module includes: The first setting and application module is used to set the model approximation method of the first metal layer to a thick film model, set the model approximation method of the first via to a lumped model, and apply a fine mesh of the first value for the first metal layer and the first via representing the chip. The second setting and application module is used to set the model approximation mode of the second metal layer and the second via representing the package to a three-dimensional full-wave model and apply a sparse mesh of a second value, wherein the second value is greater than the first value.

6. The simulation device for heterogeneous integration design of multi-process packaged chips according to claim 5, characterized in that, The interconnect module includes: Provide modules for offering a visual assembly interface; An electrical interconnect module is used to achieve electrical interconnection between upper and lower layer chips and the package structure using at least one method of bumps, bonding wires and hybrid bonding; The visual assembly interface supports flipping, rotating, mirroring, and cutting local areas of any 3D model. The local region cutting operation is used to arbitrarily cut the layout for subsequent simulation of the region of interest.

7. The simulation device for heterogeneous integration design of multi-process packaged chips according to claim 6, characterized in that, Also includes: The cutting module is used to cut the upper and lower layer chips and packaging structure of electrical interconnection based on local area cutting operations to obtain a separate chip three-dimensional model, and then obtain simulation results without packaging based on the separate chip three-dimensional model. An evaluation module is used to evaluate the impact of the packaging effect based on the simulation results with and without the package, wherein the simulation results include at least one of S-parameters, power supply impedance, and DC voltage drop.

8. The simulation device for heterogeneous integration design of multi-process packaged chips according to claim 5, characterized in that, The network to be analyzed is a signal network and / or a power network; The configuration module is specifically used to add lumped ports to the signal network and / or the power network and define the port type and impedance parameters.

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