Signal simulation analysis method and system

Abstract

The application relates to the technical field of circuit design, and discloses a signal simulation analysis method and system. The method comprises the following steps: building a simulation structure; acquiring scattering parameters of a main control chip substrate, a PCB board and a storage chip particle substrate respectively according to the built simulation structure; optimizing a second wiring design according to the scattering parameters of the PCB board, optimizing a third wiring design according to the scattering parameters of the storage chip particle substrate, and obtaining an optimized simulation structure; inputting the optimized simulation structure into pre-configured simulation software for signal transmission simulation test, and obtaining eye diagram data; analyzing the signal quality index of corresponding pins based on the eye diagram data, and determining whether the optimized simulation structure meets the preset transmission rate requirement according to the signal quality index; and through the above method, the interconnection link outside the main control chip and the internal wiring structure of the storage chip can be optimized simultaneously.

Description

Technical Field

[0001] This invention relates to the field of circuit design technology, and in particular to a signal simulation analysis method and system. Background Technology

[0002] During the manufacturing process of memory chips, the metal interconnect wiring design (usually including a multi-layer metal layer via-metal stack structure) from the internal wafer memory cell array to the surface electrical pins must be completed in advance, and the wiring structure must be verified by signal integrity simulation to ensure that it can meet the target data transmission rate requirements (such as the timing constraints of DDR interface).

[0003] The limitation of existing technical solutions lies in the fact that their signal simulation verification only targets the external interconnect links of the memory chip (i.e., the PCB-level or package-level traces between the host system SOC chip pins and the memory chip package pins), without conducting targeted simulation optimization of the internal metal wiring structure of the memory chip (such as bit line / word line routes, high-speed channels between the memory array and I / O buffers, crosstalk control of multi-channel parallel signals, etc.). This external link testing method suffers from problems such as the invisibility of internal wiring defects and the difficulty in locating transmission rate bottlenecks.

[0004] Therefore, there is an urgent need for a full-link signal simulation and analysis method and system that can cover the internal metal wiring structure of memory chips in order to optimize the end-to-end transmission performance from wafer memory cells to package pins. Summary of the Invention

[0005] This invention provides a signal simulation analysis method and system that can simultaneously optimize the interconnect links outside the main control chip and the internal wiring structure of the memory chip.

[0006] To solve the above-mentioned technical problems, one technical solution adopted by the present invention is to provide a signal simulation analysis method, comprising:

[0007] A simulation structure is built, which includes the IBIS model of the main control chip, the first routing design from the wafer to the corresponding pin inside the main control chip, the second routing design on the PCB board between the pins of the main control chip and the pins of the memory chip, the third routing design from the wafer to the corresponding pin inside the memory chip, and the IBIS model of the memory chip.

[0008] Based on the constructed simulation structure, the scattering parameters of the main control chip substrate, PCB board, and memory chip substrate are obtained respectively; the second trace design is optimized based on the scattering parameters of the PCB board, and the third trace design is optimized based on the scattering parameters of the memory chip substrate to obtain the optimized simulation structure.

[0009] The optimized simulation structure is input into the pre-configured simulation software for signal transmission simulation testing to obtain eye diagram data;

[0010] Based on the eye diagram data, analyze the signal quality indicators of the corresponding pins, and determine whether the optimized simulation structure meets the preset transmission rate requirements based on the signal quality indicators.

[0011] According to an embodiment of the present invention, the scattering parameters of the main control chip substrate, the PCB board, and the memory chip substrate are obtained respectively based on the constructed simulation structure; the second wiring design is optimized based on the scattering parameters of the PCB board, and the third wiring design is optimized based on the scattering parameters of the memory chip substrate, resulting in an optimized simulation structure including:

[0012] The simulation structure is imported into a pre-configured electromagnetic simulator to build the corresponding multi-port network model;

[0013] Based on the multi-port network model, scattering parameters are simulated for the network ports corresponding to the main control chip substrate, the PCB board, and the memory chip particle substrate, respectively, to obtain the scattering parameters of the main control chip substrate, the scattering parameters of the PCB board, and the scattering parameters of the memory chip particle substrate.

[0014] The second trace design is optimized based on the scattering parameters of the PCB board, and the third trace design is optimized based on the scattering parameters of the memory chip substrate to obtain the optimized simulation structure.

[0015] According to one embodiment of the present invention, the optimization of the second trace design based on the scattering parameters of the PCB board and the optimization of the third trace design based on the scattering parameters of the memory chip substrate, to obtain the optimized simulation structure, includes:

[0016] The second trace design is optimized based on the scattering parameters of the PCB board to obtain the optimized PCB board design.

[0017] The third trace design is optimized based on the scattering parameters of the memory chip substrate to obtain the optimized memory chip substrate design.

[0018] The optimized PCB board design and the memory chip substrate design are imported into the electromagnetic simulator and electromagnetic simulation is performed again to obtain the optimized scattering parameter file.

[0019] The optimized scattering parameter file is integrated with the IBIS model of the main control chip to form the optimized simulation structure.

[0020] According to one embodiment of the present invention, the eye diagram data includes a first simulated eye diagram corresponding to the pin of the memory chip and a second simulated eye diagram corresponding to the pin of the main control chip.

[0021] According to an embodiment of the present invention, the step of analyzing the signal quality index of the corresponding pin based on the eye diagram data and determining whether the simulation structure meets the preset transmission rate requirement based on the signal quality index includes:

[0022] Based on the first simulated eye diagram, analyze the first signal quality index of the memory chip pin and determine whether the first signal quality index meets the performance index under the preset transmission rate.

[0023] Based on the second simulated eye diagram, analyze the second signal quality index of the main control chip pin, and determine whether the second signal quality index meets the performance index under the preset transmission rate;

[0024] If both the first signal quality index and the second signal quality index meet the performance index under the preset transmission rate, then the optimized simulation structure is determined to meet the preset transmission rate requirement.

[0025] Otherwise, it is determined that the optimized simulation structure does not meet the preset transmission rate requirement.

[0026] According to one embodiment of the present invention, the preset transmission rate requirement includes at least one of the following: data transmission rate, corresponding eye height threshold, eye width threshold, setup time and hold time margin.

[0027] According to one embodiment of the present invention, the scattering parameters are used to characterize the insertion loss, return loss, or crosstalk characteristics of the interconnect link.

[0028] According to one embodiment of the present invention, the main control chip is a SOC chip and the storage chip is a DDR chip.

[0029] According to one embodiment of the present invention, before constructing the simulation structure, the method further includes:

[0030] Based on parametric modeling and optimization algorithms, the memory chip package routing design is traversed to obtain multiple candidate third routing designs;

[0031] Based on each of the candidate third routing designs, a package model for multiple memory chips is constructed.

[0032] Multiple packaging models are imported into a pre-configured electromagnetic simulator to obtain the scattering parameters of the corresponding memory chip substrate.

[0033] Based on the scattering parameters of the memory chip substrate, a target third trace design is selected from a plurality of candidate third trace designs to build the simulation structure.

[0034] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is: to provide a signal simulation analysis system applied to the aforementioned signal simulation analysis method, wherein the signal simulation analysis system comprises:

[0035] The building module is used to build a simulation structure, which includes the IBIS model of the main control chip, the first routing design from the wafer to the corresponding pin inside the main control chip, the second routing design on the PCB board between the pins of the main control chip and the pins of the memory chip, the third routing design from the wafer to the corresponding pin inside the memory chip, and the IBIS model of the memory chip.

[0036] The optimization module is used to obtain the scattering parameters of the main control chip substrate, PCB board, and memory chip particle substrate respectively according to the constructed simulation structure; optimize the second routing design according to the scattering parameters of the PCB board, and optimize the third routing design according to the scattering parameters of the memory chip particle substrate to obtain the optimized simulation structure.

[0037] The simulation execution module is used to input the optimized simulation structure into the pre-configured simulation software to perform signal transmission simulation testing and obtain eye diagram data;

[0038] The analysis module is used to analyze the signal quality indicators of the corresponding pins based on the eye diagram data, and determine whether the optimized simulation structure meets the preset transmission rate requirements based on the signal quality indicators.

[0039] The beneficial effects of this invention are as follows: A signal simulation analysis method includes: constructing a simulation structure, the simulation structure including an IBIS model of a main control chip, a first routing design from the wafer to the corresponding pin inside the main control chip, a second routing design on a PCB board between the main control chip pin and the memory chip pin, a third routing design from the wafer to the corresponding pin inside the memory chip, and an IBIS model of the memory chip; obtaining scattering parameters of the main control chip substrate, the PCB board, and the memory chip particle substrate based on the constructed simulation structure; optimizing the second routing design based on the scattering parameters of the PCB board, and optimizing the third routing design based on the scattering parameters of the memory chip particle substrate, to obtain... The optimized simulation structure is then input into pre-configured simulation software for signal transmission simulation testing to obtain eye diagram data. Based on the eye diagram data, the signal quality indicators of the corresponding pins are analyzed, and it is determined whether the optimized simulation structure meets the preset transmission rate requirements based on the signal quality indicators. This invention elevates the simulation, which traditionally only uses IBIS behavioral-level models and ideal transmission line models, to the level of full-channel frequency domain modeling. By extracting the scattering parameters of the main control chip substrate, PCB board, and memory chip particle substrate respectively, the loss, reflection, and coupling effects of the channel can be simulated with extremely high accuracy. At the same time, the interconnection links outside the main control chip and the internal wiring structure of the memory chip are optimized. Attached Figure Description

[0040] Figure 1 This is a schematic flowchart of a signal simulation analysis method according to an embodiment of the present invention.

[0041] Figure 2 This is a schematic diagram of a simulation structure according to an embodiment of the present invention.

[0042] Figure 3 This is a flowchart illustrating step S2 in the signal simulation analysis method of this invention.

[0043] Figure 4 This is a flowchart illustrating step S203 in the signal simulation analysis method of this invention.

[0044] Figure 5 This is a flowchart illustrating step S4 in the signal simulation analysis method of this invention.

[0045] Figure 6 This is a flowchart illustrating a signal simulation analysis method according to another embodiment of the present invention.

[0046] Figure 7 This is a schematic diagram of the signal simulation analysis system according to an embodiment of the present invention. Detailed Implementation

[0047] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0048] The terms "first," "second," and "third" used in this invention are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this invention are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0049] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0050] Figure 1 This is a flowchart illustrating a signal simulation analysis method according to an embodiment of the present invention. It should be noted that if substantially the same result is obtained, the method of the present invention is not necessarily identical. Figure 1 The illustrated process sequence is limited. For example... Figure 1 As shown, the method includes the following steps:

[0051] Step S1: Build the simulation structure, which includes the IBIS model of the main control chip, the first routing design from the wafer to the corresponding pin inside the main control chip, the second routing design on the PCB board between the pins of the main control chip and the pins of the memory chip, the third routing design from the wafer to the corresponding pin inside the memory chip, and the IBIS model of the memory chip.

[0052] In step S1, the goal is to construct a physical model that includes all critical interconnect links and can be used for electromagnetic simulation extraction. The main control chip is a SOC chip, used to send test commands to the memory chip and acquire test operation data during testing. The memory chip is a DDR chip, used to store data and commands that the main control chip frequently needs to access. For example, the simulation structure is as follows: Figure 2 As shown.

[0053] The IBIS model and first routing design of the main control chip can be obtained from the main control chip supplier. The IBIS model (such as a .ibs file) is used to define the electrical behavior of the chip's I / O buffers and to obtain the package design files of the main control chip, such as files in APD (Advanced Package Designer) or IPD (Integrated Passive Device) formats. These files contain the stacking of each package layer, material properties, and precise three-dimensional geometric information such as BGA solder balls, main control chip substrate traces, and chip pads. The first routing design is called package interconnect in the packaging field. For high-speed BGA packaging, flip-chip technology is usually used, connecting to the package substrate through microbumps.

[0054] The second routing design can be done using PCB design tools (such as Cadence Allegro, Mentor Xpedition). After the initial routing of critical networks (such as memory chip data lines, address lines, and clock lines), their layout information is exported. The layout information can include: the precise shape, width, and length of the traces; the dielectric material and copper foil used in the stack-up; the via model (including anti-pads and pad dimensions); the geometric model of the connectors, etc.

[0055] The third routing design and the IBIS model of the memory chip are similar to those of the main control chip. They can be based on the IBIS model of the memory chip designed by the user or obtained from the memory supplier.

[0056] Step S2: Based on the constructed simulation structure, obtain the scattering parameters of the main control chip substrate, PCB board, and memory chip substrate respectively; optimize the second routing design based on the scattering parameters of the PCB board, and optimize the third routing design based on the scattering parameters of the memory chip substrate to obtain the optimized simulation structure.

[0057] In step S2, the physical structure is transformed into electrical performance indicators (scattering parameters, S-parameters), and optimization design is performed based on these indicators to ultimately obtain a channel model with "excellent electrical performance." This step can use a 3D full-wave electromagnetic field simulator, such as Ansys HFSS, CST Studio Suite, or Ansys SIwave, to extract the scattering parameters of the main control chip substrate, PCB board, and memory chip substrate, respectively. Please refer to [link to relevant documentation]. Figure 3 Specifically, it includes the following steps:

[0058] Step S201: Import the simulation structure into the pre-configured electromagnetic simulator to build the corresponding multi-port network model.

[0059] The prepared models of the main control chip substrate, PCB board, and memory chip substrate are imported into the electromagnetic simulator, with each model corresponding to at least one excitation port and one response port.

[0060] Step S202: Based on the multi-port network model, scattering parameters are simulated for the network ports corresponding to the main control chip substrate, PCB board and memory chip substrate respectively, to obtain the scattering parameters of the main control chip substrate, the scattering parameters of the PCB board and the scattering parameters of the memory chip substrate.

[0061] In this step, electromagnetic simulations are run at each port of each model to obtain the scattering parameters (e.g., .sNp files) for each substrate. These scattering parameters characterize the insertion loss, return loss, or crosstalk characteristics of the interconnect links. Scattering parameters include, but are not limited to, S11, S21, S12, S22, and S41. Here, S11 represents return loss (reflection characteristics), S21 represents insertion loss (transmission characteristics), and S41 represents far-end crosstalk. For example, if the S21 curve drops significantly at the Nyquist frequency (e.g., 1.6GHz for DDR4-3200), it indicates excessive channel loss.

[0062] Step S203: Optimize the second trace design based on the scattering parameters of the PCB board, and optimize the third trace design based on the scattering parameters of the memory chip substrate to obtain the optimized simulation structure.

[0063] In this step, the goal of improving insertion loss (S21), reducing return loss (S11), and reducing far-end crosstalk (S41) is achieved through optimized design.

[0064] Optimizing the second trace design based on the scattering parameters of the PCB board includes: if the insertion loss is too high, consider replacing it with a PCB board with lower loss (such as upgrading from FR-4 to Megtron 4 / 6 / 8); if the return loss is too high, check and optimize the via structure, such as increasing the anti-pad size and using backdrill to remove useless stubs to improve impedance continuity; if the far-end crosstalk is too high, increase the trace spacing.

[0065] Among them, optimizing the third trace design based on the scattering parameters of the memory chip substrate includes: if the return loss is too large, the via structure can be checked and optimized, such as increasing the anti-pad size and using backdrill to remove useless stubs to improve impedance continuity; if the far-end crosstalk is too large, the trace spacing can be increased.

[0066] This embodiment elevates simulations that traditionally rely solely on IBIS behavioral-level models and ideal transmission line models to the level of full-channel frequency domain modeling. By extracting scattering parameters from the main control chip substrate, PCB board, and memory chip substrate separately, channel losses, reflections, and coupling effects can be simulated with extreme precision. This allows for targeted design optimization before simulation, significantly increasing the probability of a successful initial design.

[0067] In some embodiments, see Figure 4 Step S203 further includes the following steps:

[0068] Step S2031: Optimize the second trace design based on the scattering parameters of the PCB board to obtain the optimized PCB board design.

[0069] If the insertion loss is too high, consider replacing it with a PCB board with lower loss (such as upgrading from FR-4 to Megtron 4 / 6 / 8); if the return loss is too high, check and optimize the via structure, such as increasing the anti-pad size and using backdrill to remove unwanted traces to improve impedance continuity; if the far-end crosstalk is too high, increase the trace spacing.

[0070] Step S2032: Optimize the third trace design based on the scattering parameters of the memory chip substrate to obtain the optimized memory chip substrate design.

[0071] If the return loss is too high, the via structure can be checked and optimized, such as increasing the size of the anti-pad or using backdrill to remove unwanted traces to improve impedance continuity; if the far-end crosstalk is too high, the trace spacing can be increased.

[0072] Step S2033: Import the optimized PCB board design and memory chip substrate design into the electromagnetic simulator to perform electromagnetic simulation again and obtain the optimized scattering parameter file.

[0073] Step S2034: Integrate the optimized scattering parameter file with the IBIS model of the main control chip to form the optimized simulation structure.

[0074] This embodiment achieves an overall improvement in signal transmission quality by finely controlling the electromagnetic characteristics of the interconnect structure, enabling the simulated structure to exhibit superior signal transmission characteristics in the frequency domain.

[0075] Step S3: Input the optimized simulation structure into the pre-configured simulation software to perform signal transmission simulation testing and obtain eye diagram data.

[0076] In step S3, SI / PI simulation software (such as Cadence Sigrity SystemSI, Synopsys HSPICE, ANSYS Nexxim) is used. Eye diagram data is generated by building the simulation circuit, simulation topology, setting simulation conditions, and performing transient time-domain simulation. Eye diagram data is an important means of evaluating the quality of high-speed signal transmission. The shape of the eye diagram (such as eye height and eye width) directly reflects the signal's discernibility and bit error rate at the receiver, thus indirectly indicating whether the communication requirements at a specific transmission rate are met.

[0077] Step S4: Analyze the signal quality indicators of the corresponding pins based on the eye diagram data, and determine whether the optimized simulation structure meets the preset transmission rate requirements based on the signal quality indicators.

[0078] In step S4, the signal quality metrics include at least one of eye height, eye width, jitter, rise time, and fall time. Eye height refers to the degree to which the eye diagram opens vertically, representing noise margin. The eye height must be greater than the input sensitivity of the receiver chip. Eye width refers to the degree to which the eye diagram opens horizontally, representing timing margin. The eye width must be greater than the setup and hold time requirements. Jitter refers to the degree of blurring at the edges of the eye diagram.

[0079] The judgment of signal quality indicators is based on a preset eye diagram template (such as the JEDEC standard) or industry standard specifications.

[0080] The preset transmission rate requirements include at least one of the following: data transmission rate, corresponding eye height threshold, eye width threshold, setup time, and hold time margin.

[0081] If the eye diagram is "opened" large enough and has a certain margin, it indicates that the optimized simulation structure meets the preset transmission rate requirements.

[0082] Preferably, the eye diagram data includes a first simulated eye diagram corresponding to the memory chip pins and a second simulated eye diagram corresponding to the main control chip pins. Please refer to [link to relevant documentation]. Figure 5 Step S4 also includes the following steps:

[0083] Step S401: Analyze the first signal quality index of the memory chip pin based on the first simulated eye diagram, and determine whether the first signal quality index meets the performance index under the preset transmission rate.

[0084] In this step, since the memory chip has multiple pins, it is necessary to determine whether the first signal quality index of the multiple pins of the memory chip meets the performance index under the preset transmission rate.

[0085] Step S402: Analyze the second signal quality index of the main control chip pin based on the second simulated eye diagram, and determine whether the second signal quality index meets the performance index under the preset transmission rate.

[0086] In this step, since the main control chip has multiple pins, it is necessary to determine whether the second signal quality index of the multiple pins of the main control chip meets the performance index under the preset transmission rate.

[0087] Step S403: If both the first signal quality index and the second signal quality index meet the performance index under the preset transmission rate, then it is determined that the optimized simulation structure meets the preset transmission rate requirement.

[0088] In this step, if the first signal quality index of multiple pins of the memory chip and the second signal quality index of multiple pins of the main control chip both meet the performance index under the preset transmission rate, then it is determined that the optimized simulation structure meets the preset transmission rate requirement.

[0089] Step S404: Otherwise, it is determined that the optimized simulation structure does not meet the preset transmission rate requirement.

[0090] In this step, if any one of the first signal quality indicators of multiple pins of the memory chip and the second signal quality indicators of multiple pins of the main control chip fails to meet the performance indicators under the preset transmission rate, then it is determined that the optimized simulation structure does not meet the preset transmission rate requirement.

[0091] This embodiment optimizes the design of the memory chip and the layout of the memory chip and the main control chip on the PCB board by determining whether each pin meets the transmission rate. In addition, distinguishing the eye diagrams of the memory chip pins and the main control chip pins helps to locate problems and improve optimization efficiency.

[0092] In some implementations, please refer to Figure 6 Before step S1, the following steps are also included:

[0093] Step S501: Based on parametric modeling and optimization algorithms, traverse the memory chip package routing design to obtain multiple candidate third routing designs.

[0094] This step automates the exploration of all possible interconnect design spaces within the memory chip, from wafer pads to external pins (such as BGA solder balls), to find the optimal routing structure that meets specific electrical performance objectives (such as impedance matching, minimum insertion loss, and minimum crosstalk). For example, the routing structure includes: routing layers, reference planes, trace widths and spacings, dielectric materials, interconnect structures, etc. Parametric modeling creates a programmable memory chip package model, rather than a fixed geometry; the geometry is controlled via scripts (such as Python, VBScript) using electromagnetic simulation software that supports parametric modeling (such as ANSYS HFSS 3D Layout, CSTStudio Suite, or Cadence Clarity 3D Solver). Optimization algorithms include, but are not limited to, gradient descent and genetic algorithms.

[0095] Step S502: Construct packaging models for multiple memory chips based on each candidate third routing design.

[0096] Step S503: Import multiple packaging models into the pre-configured electromagnetic simulator to obtain the scattering parameters of the corresponding memory chip substrate.

[0097] Step S504: Select a target third trace design from multiple candidate third trace designs to build the simulation structure based on the scattering parameters of the memory chip substrate.

[0098] This embodiment utilizes the scattering parameters of the memory chip packaging substrate to quantitatively analyze and compare multiple candidate third trace designs, selecting the design scheme with the best performance in insertion loss, return loss, and crosstalk as the target trace for building the simulation structure. This achieves precise matching between the interconnect path and the actual electrical characteristics of the chip, effectively improving the reliability and design efficiency of high-speed signal transmission.

[0099] Figure 7 This is a schematic diagram of the signal simulation and analysis system according to an embodiment of the present invention. Figure 7 As shown, the system 70 includes a construction module 71, an optimization module 72, a simulation execution module 73, and an analysis module 74.

[0100] Module 71 is used to build the simulation structure, which includes the IBIS model of the main control chip, the first routing design from the wafer to the corresponding pin inside the main control chip, the second routing design on the PCB board between the pins of the main control chip and the pins of the memory chip, the third routing design from the wafer to the corresponding pin inside the memory chip, and the IBIS model of the memory chip.

[0101] The optimization module 72 is used to obtain the scattering parameters of the main control chip substrate, PCB board, and memory chip particle substrate respectively according to the constructed simulation structure; optimize the second routing design according to the scattering parameters of the PCB board, and optimize the third routing design according to the scattering parameters of the memory chip particle substrate to obtain the optimized simulation structure.

[0102] The simulation execution module 73 is used to input the optimized simulation structure into the pre-configured simulation software to perform signal transmission simulation testing and obtain eye diagram data;

[0103] Analysis module 74 is used to analyze the signal quality indicators of the corresponding pins based on eye diagram data, and to determine whether the optimized simulation structure meets the preset transmission rate requirements based on the signal quality indicators.

[0104] This embodiment elevates the simulation, which traditionally only uses IBIS behavioral-level models and ideal transmission line models, to the level of full-channel frequency domain modeling. By extracting the scattering parameters of the main control chip substrate, PCB board, and memory chip particle substrate respectively, it can simulate the channel loss, reflection, and coupling effects with extremely high accuracy, while optimizing the interconnect links outside the main control chip and the internal wiring structure of the memory chip.

[0105] The above are merely embodiments of the present invention and do not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A signal simulation analysis method, characterized by, The method comprises the following steps: constructing a simulation structure, which comprises an IBIS model of a master chip, a first routing design between a wafer and corresponding pins inside the master chip, a second routing design between pins of the master chip and pins of a storage chip on a PCB board, a third routing design between a wafer and corresponding pins inside the storage chip, and an IBIS model of the storage chip; obtaining scattering parameters of a master chip substrate, the PCB board, and a storage chip particle substrate respectively according to the constructed simulation structure; optimizing the second routing design according to the scattering parameters of the PCB board and optimizing the third routing design according to the scattering parameters of the storage chip particle substrate to obtain an optimized simulation structure; inputting the optimized simulation structure into a pre-configured simulation software for signal transmission simulation test to obtain eye diagram data; analyzing signal quality indexes of corresponding pins based on the eye diagram data and determining whether the optimized simulation structure meets a preset transmission rate requirement according to the signal quality indexes; before the step of constructing the simulation structure, the method further comprises the following steps: obtaining multiple candidate third routing designs by traversing storage chip package routing designs based on a parameterized modeling and optimization algorithm; constructing multiple package models of the storage chip respectively according to each candidate third routing design; obtaining scattering parameters of corresponding storage chip particle substrates by importing the multiple package models into a pre-configured electromagnetic simulator respectively; selecting a target third routing design from the multiple candidate third routing designs according to the scattering parameters of the storage chip particle substrates to construct the simulation structure.

2. The signal simulation analysis method according to claim 1, characterized by, The step of obtaining scattering parameters of a master chip substrate, the PCB board, and a storage chip particle substrate respectively according to the constructed simulation structure comprises the following steps: obtaining scattering parameters of a master chip substrate, the PCB board, and a storage chip particle substrate respectively according to the constructed simulation structure; The step of optimizing the second routing design according to the scattering parameters of the PCB board and optimizing the third routing design according to the scattering parameters of the storage chip particle substrate to obtain an optimized simulation structure comprises the following steps: importing the simulation structure into a pre-configured electromagnetic simulator to construct a corresponding multi-port network model; performing scattering parameter simulation on network ports corresponding to the master chip substrate, the PCB board, and the storage chip particle substrate respectively based on the multi-port network model to obtain scattering parameters of the master chip substrate, the PCB board, and the storage chip particle substrate; 3. The signal simulation analysis method of claim 2, wherein, optimizing the second routing design according to the scattering parameters of the PCB board and optimizing the third routing design according to the scattering parameters of the storage chip particle substrate to obtain an optimized simulation structure. The step of optimizing the second routing design according to the scattering parameters of the PCB board and optimizing the third routing design according to the scattering parameters of the storage chip particle substrate to obtain an optimized simulation structure comprises the following steps: optimizing the second routing design according to the scattering parameters of the PCB board to obtain an optimized PCB board design; The third trace design is optimized according to the scattering parameters of the memory chip particle substrate, and an optimized memory chip particle substrate design is obtained; The PCB board design and the memory chip particle substrate design are imported into the electromagnetic simulator to perform electromagnetic simulation again, and an optimized scattering parameter file is obtained; The optimized scattering parameter file, the IBIS model of the host chip and the IBIS model of the memory chip are integrated to form the optimized simulation structure.

4. The signal simulation analysis method of claim 1, wherein The eye diagram data includes a first simulation eye diagram corresponding to the memory chip pin and a second simulation eye diagram corresponding to the host chip pin.

5. The signal simulation analysis method of claim 4, wherein, The signal quality index of the corresponding pin is analyzed based on the eye diagram data, and whether the optimized simulation structure meets the preset transmission rate requirement is determined according to the signal quality index, which includes: The first signal quality index of the memory chip pin is analyzed based on the first simulation eye diagram, and whether the first signal quality index meets the performance index under the preset transmission rate is determined; The second signal quality index of the host chip pin is analyzed based on the second simulation eye diagram, and whether the second signal quality index meets the performance index under the preset transmission rate is determined; If the first signal quality index and the second signal quality index both meet the performance index under the preset transmission rate, it is determined that the optimized simulation structure meets the preset transmission rate requirement; Otherwise, it is determined that the optimized simulation structure does not meet the preset transmission rate requirement.

6. The signal simulation analysis method of claim 5, wherein, The preset transmission rate requirement includes at least one of data transmission rate, corresponding eye height threshold, eye width threshold, setup time and hold time margin.

7. The signal simulation analysis method of claim 1, wherein, The scattering parameter is used to characterize the insertion loss, return loss or crosstalk characteristics of the interconnection link.

8. The signal simulation analysis method of claim 1, wherein, The host chip is a SOC chip, and the memory chip is a DDR chip.

9. A signal simulation analysis system, characterized by, The signal simulation analysis system is applied to the signal simulation analysis method of any one of claims 1-8, and includes: A construction module is configured to build a simulation structure, which includes an IBIS model of a host chip, a first trace design between a wafer inside the host chip and a corresponding pin, a second trace design between a host chip pin and a memory chip pin on a PCB board, a third trace design between a wafer inside the memory chip and a corresponding pin, and an IBIS model of the memory chip; An optimization module is configured to obtain scattering parameters of a host chip substrate, a PCB board and a memory chip particle substrate respectively according to the built simulation structure, optimize the second trace design according to the scattering parameters of the PCB board, and optimize the third trace design according to the scattering parameters of the memory chip particle substrate, so as to obtain an optimized simulation structure; A simulation execution module is configured to input the optimized simulation structure into a preconfigured simulation software to perform signal transmission simulation test, and obtain eye diagram data; An analysis module is configured to analyze the signal quality index of the corresponding pin based on the eye diagram data, and determine whether the optimized simulation structure meets the preset transmission rate requirement according to the signal quality index.

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