Programmable chip multi-module parallel DFT verification method and system

Abstract

The invention relates to the technical field of integrated circuit testing, in particular to a programmable chip multi-module parallel DFT verification method and system. According to the method, an IO port of a programmable chip is wired to a scanning signal interface of a specified module to generate a customized bit stream, a DFT simulation management and control file is created to combine the scanning signal interfaces of all the specified modules into a unified scanning signal interface, and an excitation data file and a test protocol file are generated according to the DFT simulation management and control file. The customization excitation is generated in combination with the customization bit stream, parallel scanning of the multiple specified modules is achieved according to the customization excitation, and the flexibility and efficiency of DFT verification are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit testing technology, in particular to a programmable chip multi-module parallel DFT verification method and system. BACKGROUND

[0002] Design For Testability (DFT) is a common means of detecting chip defects.

[0003] The traditional DFT scan mode is basically determined in the design stage, and the verification personnel completes the chain insertion and DFT simulation verification by means of EDA tools according to the reserved scan signal interface of the design. This mode is not flexible enough for DFT verification of programmable chips. Generally, due to the small number of reserved scan signal interfaces, the number of IO (Input / Output) resources available for scan signal interfaces is small, which slows down the simulation efficiency. On the other hand, due to the consideration of scan efficiency, the traditional scan chain design may couple multiple modules together, which increases the difficulty of subsequent problem positioning.

[0004] In recent years, new technologies have proposed a test platform suitable for large-scale chip simulation, as well as a method for converting various original test vectors into vectors recognizable by this platform, which has better performance than traditional software simulation platforms and can reduce the time required for simulation. However, this method cannot specify the internal modules of the scan programmable chip, and the available IO resources are determined at the beginning of the design.

[0005] Therefore, it is an urgent problem to propose a DFT simulation verification method suitable for programmable chips that can freely specify simulation modules. SUMMARY

[0006] The present application provides a programmable chip multi-module parallel DFT verification method and system, which generates a customized excitation by exciting data files, test protocol files and customized bit streams, and realizes parallel scanning of multiple specified modules according to the customized excitation, thereby improving the flexibility and efficiency of DFT verification.

[0007] To achieve the above purpose, the present application provides a programmable chip multi-module parallel DFT verification method, which comprises: determining the IO ports of the programmable chip and a plurality of specified modules to be scanned; wiring the IO ports to the scan signal interfaces of the specified modules to generate a chain insertion netlist, and generating a customized bit stream according to the chain insertion netlist; modifying the scan signal interfaces of each of the specified modules to a unified scan signal interface and instantiating the specified modules to generate a DFT simulation control file; inputting the DFT simulation control file and the chain netlist into a preset DFT excitation generation tool to generate an excitation data file and a test protocol file; generating a programmable chip top layer according to the chain netlist; instantiating the test protocol file to generate a test protocol top layer; interconnecting the programmable chip top layer and the test protocol top layer; performing parallel DFT simulation of the specified modules of the programmable chip top layer and the test protocol top layer according to the customized bitstream and the excitation data file to obtain DFT verification results of the specified modules.

[0008] Optionally, the IO ports of the programmable chip and the specified modules to be scanned are determined, comprising: determining the available IO ports in the programmable chip according to pin constraints; determining the specified modules to be scanned, wherein the number of scan signal interfaces of the specified modules to be scanned does not exceed the number of the IO ports.

[0009] Optionally, the IO ports are routed to the scan signal interfaces of the specified modules to obtain a chain netlist, and a customized bitstream is generated according to the chain netlist, comprising: determining position information of the specified modules in the programmable chip; completing routing of the IO ports to the idle interfaces of the specified modules according to the position information to generate a routing netlist; modifying the idle interfaces in the routing netlist to the scan signal interfaces reserved by the specified modules and inserting preset scan logic to obtain a chain netlist; generating a customized bitstream according to the chain netlist.

[0010] Optionally, the scan signal interfaces of each of the specified modules are modified to uniform scan signal interfaces and the specified modules are instantiated to generate a DFT simulation control file, and the method further comprises: determining values of non-scan signal interfaces of the specified modules in a scan mode to generate fixed value constraints, wherein the fixed value constraints are stored in a subsequently generated DFT simulation control file; setting offset circuit components for offsetting reserved circuit components at the scan signal interfaces of the specified modules, wherein the offset circuit components are stored in a subsequently generated DFT simulation control file.

[0011] Optionally, the DFT simulation control file and the chain netlist are inputted into a preset DFT excitation generation tool to generate an excitation data file and a test protocol file, comprising: The preset DFT excitation generation tool determines excitation information of the specified module according to the instantiated specified module, the fixed value constraint and the cancellation circuit component, and generates an excitation data file; The preset DFT excitation generation tool sets an excitation output interface and a result detection interface, and generates a test protocol file.

[0012] Optionally, the test protocol top layer comprises an excitation output interface and a result detection interface. The interconnection of the programmable chip top layer and the test protocol top layer comprises: The excitation output interface of the test protocol top layer is interconnected with the programmable chip top layer, and the result detection interface of the test protocol top layer is interconnected with the programmable chip top layer.

[0013] Optionally, the scan signal interface comprises a scan input interface and a scan output interface. The parallel DFT simulation of the programmable chip top layer and the test protocol top layer according to the customized bit stream and the excitation data file for multiple specified modules comprises: The customized bit stream is input into the programmable chip top layer, a scan path configuration is performed on the programmable chip, and a scan signal is generated. The excitation data signal is generated by the test protocol top layer according to the excitation data file through the scan signal. The excitation data signal is input into the programmable chip top layer through the excitation output interface of the test protocol top layer, and is input into the scan input interface of multiple specified modules through the interposer netlist of the programmable chip top layer, and parallel scanning is performed on multiple specified modules to obtain a scan result. The scan result is output to the result detection interface of the test protocol top layer through the programmable chip top layer through the scan output interface. The test protocol top layer detects according to the scan result to obtain the DFT verification result of multiple specified modules.

[0014] The application further provides a programmable chip multi-module parallel DFT verification system, which comprises: An information confirmation module is configured to determine IO ports of a programmable chip and specified modules to be scanned. A bit stream generation module is configured to wire the IO ports to a scan signal interface of the specified modules to generate an interposer netlist, and generate a customized bit stream according to the interposer netlist. The customization excitation file generation module is configured to modify scan signal interfaces of the specified modules into a unified scan signal interface, instantiate the specified modules, and generate a DFT simulation management file; and input the DFT simulation management file and the chain netlist into a preset DFT excitation generation tool to generate an excitation data file and a test protocol file; The simulation verification module is configured to generate a programmable chip top layer according to the chain netlist, instantiate a test protocol top layer according to the test protocol file, interconnect the programmable chip top layer and the test protocol top layer, and perform parallel DFT simulation of the specified modules on the programmable chip top layer and the test protocol top layer according to the customization bit stream and the excitation data file to obtain DFT verification results of the specified modules.

[0015] Optionally, the test protocol top layer comprises an excitation output interface and a result detection interface. The simulation verification module is configured to: interconnect the excitation output interface of the test protocol top layer with the programmable chip top layer, and interconnect the result detection interface of the test protocol top layer with the programmable chip top layer.

[0016] Optionally, the scan signal interface comprises a scan input interface and a scan output interface. The simulation verification module is configured to: input the customization bit stream into the programmable chip top layer, configure a scan path of the programmable chip, and generate a scan signal; control the test protocol top layer to generate an excitation data signal according to the excitation data file through the scan signal; the excitation data signal is input into the programmable chip top layer through the excitation output interface of the test protocol top layer, and is input into scan input interfaces of the specified modules through the chain netlist of the programmable chip top layer to perform parallel scanning on the specified modules and obtain a scan result; the scan result is output to the result detection interface of the test protocol top layer through the scan output interface and the programmable chip top layer; the test protocol top layer detects according to the scan result to obtain DFT verification results of the specified modules.

[0017] The application wires IO ports of a programmable chip to scan signal interfaces of specified modules to generate a customization bit stream, combines scan signal interfaces of all specified modules into a unified scan signal interface according to a DFT simulation management file, generates an excitation data file and a test protocol file according to the DFT simulation management file, generates a customized excitation in combination with the customization bit stream, and realizes parallel scanning of multiple specified modules according to the customized excitation, thereby improving flexibility and efficiency of DFT verification. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a DFT simulation control file provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a simulation architecture provided for an embodiment of the present invention.

[0019] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0020] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0021] Before introducing this invention, the terms will be explained below.

[0022] FPGA chip: Field-Programmable Gate Array, is a semi-custom integrated circuit whose hardware functions can be defined by software configuration. Its core feature is that it is field-programmable. After leaving the factory, FPGA chips can be modified multiple times by users according to their needs to realize various customized functions, from simple logic control to complex signal processing.

[0023] Bitstream: A bitstream file is a binary format configuration file used to define the connection methods and logic functions of internal hardware resources in an FPGA. It is the core carrier for realizing the field-programmable characteristics of programmable chips.

[0024] EDA tools: Electronic Design Automation refers to a collection of software tools used to assist in the entire process from chip design, simulation, verification, and manufacturing. They can automate the complex wiring process inside the chip and display it through a visual interface.

[0025] A netlist file is a text file used in electronic design to describe circuit components (such as resistors, capacitors, transistors, logic gates, modules, etc.) and their interconnections. It serves as a core bridge connecting "abstract logic design" and "physical implementation / simulation verification," and is essentially a "structured description" of the circuit structure.

[0026] Automatic Test Equipment (ATE): Automatic Test Equipment is a test scheme that uses automatic hardware and software systems to detect electronic components, chips, circuit boards or whole machine products in batches and efficiently. The core goal is to quickly identify "qualified / unqualified" products in the production, research and development or maintenance stage, and to screen out devices with functional defects, performance not meeting standards or reliability problems, while reducing the cost and error of manual testing.

[0027] IO resource: IO resource of a chip is a short name of "input / output resource", which is a general term for hardware module resources for signal and data interaction between the chip and external circuits and devices.

[0028] Insertion chain netlist: The product inserted into the DFT scan chain in the conventional netlist file of the chip, and the scan logic is added to the netlist.

[0029] In an embodiment of the present application, the programmable chip multi-module parallel DFT verification method includes four stages, namely determining the specified module, generating the customized bit stream, generating the customized excitation file, and DFT simulation verification.

[0030] Stage one, determining the specified module, including step S1: S1 determines the IO port of the programmable chip and a plurality of specified modules to be scanned.

[0031] Specifically, step S1 can include S1.1-S1.2: S1.1 determines the available IO port in the programmable chip according to the pin limitation.

[0032] S1.2 determines the specified module to be scanned, and the number of scan signal interfaces of the specified module to be scanned does not exceed the number of IO ports.

[0033] It should be noted that there may be pin limitations such as test base station pin limitations and chip packaging available pin limitations in actual requirements, and the amount of IO resources of the programmable chip that can be used in this DFT verification process is determined according to these pin limitations.

[0034] Stage two, generating a customized bit stream, including step S2: S2 wires the IO port to the scan signal interface of the specified module to generate an insertion chain netlist, and generates a customized bit stream according to the insertion chain netlist.

[0035] Specifically, step S2 can include S2.1-S2.4: S2.1 determines the location information of the specified module in the programmable chip; S2.2 Based on the location information, complete the wiring from the IO port to the idle interface of the designated module, and generate a wiring netlist; S2.3 Modify the idle interface in the wiring netlist to the scan signal interface reserved by the designated module and insert the preset scan logic to obtain the plug-in netlist; S2.4 Generate a custom bitstream based on the pluggable netlist.

[0036] It should be noted that the actual location of a specified module within a programmable chip can be determined using EDA tools. Since the scan signal interfaces of modules within a programmable chip are usually reserved interfaces and not normally visible, EDA tools typically cannot directly route from I / O ports to the scan interfaces. Therefore, EDA tools can be used to route each I / O port to an unused interface of the specified module based on its location. Ideally, the routing lengths from the I / O ports to each module should be approximately the same during this process, generating a routing netlist. Then, the routing netlist is modified, changing the routing interface on the specified module from an unused interface to a reserved scan signal interface and inserting preset scan logic, resulting in a linking netlist. Scan signals typically include Scanin, Scanen, Scanmode, Scanclk, and Scanout. A custom bitstream is generated by inputting the linking netlist into a script.

[0037] Phase 3: Generate a customized incentive file, including steps S3.1-S3.2: S3.1 Modify the scanning signal interface of each specified module to a unified scanning signal interface and instantiate the specified module to generate a DFT simulation control file; S3.2 Input the DFT simulation control file and the pluggable netlist into a preset DFT stimulus generation tool to generate stimulus data file and test protocol file.

[0038] Optionally, the following may be included before step S3.1: Determine the value of the non-scanning signal interface of the specified module in scan mode, and generate fixed value constraints. The fixed value constraints are used to store the subsequently generated DFT simulation control file. The cancellation circuit components are set to cancel the reserved circuit components at the scan signal interface of the specified module. The cancellation circuit components are used to store the subsequently generated DFT simulation control file.

[0039] It should be noted that determining the values ​​of the non-scanning pins of a specified module in scan mode, setting fixed value constraints for the module based on these values, preventing changes in such pin signals from affecting scan coverage, determining whether the designer has reserved circuit components such as inverters at the scan signal interface of the specified module, and setting custom circuit components to offset the influence of reserved circuit components on the scan signal.

[0040] Furthermore, the preset DFT stimulus generation tool determines the stimulus information for the specified module based on the instantiated specified module, the fixed value constraint, and the cancellation circuit components, and generates a stimulus data file; the preset DFT stimulus generation tool sets the stimulus output interface and the result detection interface, and generates a test protocol file.

[0041] like Figure 1 As shown, Figure 1 This is a schematic diagram of a DFT simulation control file provided by the present invention. The DFT simulation control file merges the scan signal interfaces of all specified modules into a unified scan signal interface, instantiates all specified modules within the DFT simulation control file, and places the fixed value constraints and set cancellation circuit components within the DFT simulation control file.

[0042] Phase 4, DFT simulation verification, includes steps S4.1-S4.4: S4.1 Generate the top layer of the programmable chip based on the interleaving netlist; S4.2 Instantiate the test protocol file to generate the top-level test protocol; S4.3 Interconnect the top layer of the programmable chip and the top layer of the test protocol; S4.4 Perform parallel DFT simulations of multiple specified modules on the top layer of the programmable chip and the top layer of the test protocol based on the customized bit stream and the stimulus data file, and obtain the DFT verification results of the specified modules.

[0043] Furthermore, the scan signal interface includes a scan input interface and a scan output interface; the test protocol top layer includes an excitation output interface and a result detection interface. The excitation output interface of the test protocol top layer is interconnected with the programmable chip top layer, and the result detection interface of the test protocol top layer is interconnected with the programmable chip top layer.

[0044] To more clearly illustrate the simulation architecture of this invention, accompanying drawings are provided, such as... Figure 2 As shown, Figure 2 This invention provides a schematic diagram of a simulation architecture. The simulation top layer includes a programmable chip top layer and a test protocol top layer. Step S4.4 specifically includes S4.4.1-S4.4.5: S4.4.1 Input the customized bit stream into the top layer of the programmable chip, configure the scan path of the programmable chip and generate a scan signal; S4.4.2 The scanning signal controls the top layer of the test protocol to generate an excitation data signal based on the excitation data file; The excitation data signal in S4.4.3 is input to the top layer of the programmable chip through the excitation output interface of the top layer of the test protocol, and then input to the scan input interface of multiple designated modules through the plug-in netlist of the top layer of the programmable chip to obtain the scan result by performing parallel scan on multiple designated modules; The scanning result described in S4.4.4 is output to the result detection interface at the top layer of the test protocol via the scanning output interface through the programmable chip. The top-level test protocol described in S4.4.5 performs detection based on the scan results to obtain DFT verification results for multiple specified modules.

[0045] It should be noted that during simulation, the custom bit stream is input to the top layer of the programmable chip to complete the internal scan path configuration of the programmable chip. Then, the scan signal controls the designated module to perform the scan mode and sends the test stimulus. The scan result is automatically detected by the internal detection mechanism of the test protocol top layer.

[0046] The excitation data signal output from the top layer of the test protocol is directly input to the scan input interface corresponding to the specified module in the plug-in netlist through the top layer of the programmable chip. After the scan of the specified module is completed, the scan result is output through the scan output interface to the structure detection interface of the top layer of the test protocol for detection.

[0047] This invention routes the I / O ports of a programmable chip to the scan signal interface of a specified module to generate a custom bit stream. It creates a DFT simulation management file to merge the scan signal interfaces of all specified modules into a unified scan signal interface. Based on the DFT simulation management file, it generates a stimulus data file and a test protocol file. Combined with the custom bit stream, it generates a custom stimulus. Based on the custom stimulus, it realizes parallel scanning of multiple specified modules, thereby improving the flexibility and efficiency of DFT verification.

[0048] In another embodiment of the present invention, a programmable chip multi-module parallel DFT verification system is also provided, the system comprising: The information confirmation module is used to determine the I / O ports of the programmable chip and the specified modules to be scanned. The bit stream generation module is used to generate a plug-in netlist by routing the IO port to the scan signal interface of the designated module, and generate a customized bit stream based on the plug-in netlist; A customized stimulus file generation module is used to modify the scan signal interface of each specified module to a unified scan signal interface and instantiate the specified module to generate a DFT simulation control file; the DFT simulation control file and the pluggable netlist are input into a preset DFT stimulus generation tool to generate a stimulus data file and a test protocol file; The simulation verification module is used to generate a programmable chip top layer based on the interleaving netlist; instantiate the test protocol file to generate a test protocol top layer; interconnect the programmable chip top layer and the test protocol top layer; and perform parallel DFT simulations of multiple specified modules on the programmable chip top layer and the test protocol top layer based on the custom bit stream and the stimulus data file to obtain the DFT verification results of the specified modules.

[0049] Optionally, the top layer of the test protocol includes an excitation output interface and a result detection interface; The simulation verification module is specifically used for: The excitation output interface of the top layer of the test protocol is interconnected with the top layer of the programmable chip, and the result detection interface of the top layer of the test protocol is interconnected with the top layer of the programmable chip.

[0050] Optionally, the scan signal interface includes a scan input interface and a scan output interface; The simulation verification module is specifically used for: The customized bitstream is input into the top layer of the programmable chip to configure the scan path and generate a scan signal. The scanning signal controls the top layer of the test protocol to generate a stimulus data signal based on the stimulus data file. The excitation data signal is input to the top layer of the programmable chip through the excitation output interface of the top layer of the test protocol, and then input to the scan input interface of multiple designated modules through the plug-in netlist of the top layer of the programmable chip to obtain the scan result by performing parallel scan on multiple designated modules; The scan result is output through the scan output interface to the result detection interface at the top layer of the test protocol via the top layer of the programmable chip; The top layer of the test protocol performs detection based on the scan results to obtain DFT verification results for multiple specified modules.

[0051] In the programmable chip multi-module parallel DFT verification system described in this embodiment of the invention, each module adopts the same technical means as the programmable chip multi-module parallel DFT verification method and can produce the same technical effect, which will not be repeated here.

[0052] In the embodiments provided by this invention, it should be understood that the disclosed devices, systems, and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative, and actual implementations may have other classification methods.

[0053] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0054] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional modules.

[0055] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0056] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A programmable chip multi-module parallel DFT verification method, characterized in that, The method comprises: determining IO ports of a programmable chip and a plurality of specified modules to be scanned; wiring the IO ports to scan signal interfaces of the specified modules to generate a chain insertion netlist, and generating a customized bitstream according to the chain insertion netlist; modifying the scan signal interfaces of each of the specified modules to a unified scan signal interface, instantiating the specified modules, and generating a DFT simulation control file; inputting the DFT simulation control file and the chain insertion netlist into a preset DFT excitation generation tool to generate an excitation data file and a test protocol file; generating a programmable chip top layer according to the chain insertion netlist; instantiating the test protocol file to generate a test protocol top layer; interconnecting the programmable chip top layer and the test protocol top layer; performing parallel DFT simulation of the plurality of specified modules on the programmable chip top layer and the test protocol top layer according to the customized bitstream and the excitation data file to obtain DFT verification results of the specified modules.

2. The programmable chip multi-module parallel DFT verification method of claim 1, wherein, The determination of the IO ports of the programmable chip and the plurality of specified modules to be scanned comprises: determining the available IO ports in the programmable chip according to pin constraints; determining the specified modules to be scanned, wherein the number of scan signal interfaces of the specified modules to be scanned does not exceed the number of the IO ports.

3. The programmable chip multi-module parallel DFT verification method of claim 1, wherein, The wiring of the IO ports to the scan signal interfaces of the specified modules to obtain a chain insertion netlist and the generation of a customized bitstream according to the chain insertion netlist comprise: determining position information of the specified modules in the programmable chip; completing the wiring of the IO ports to idle interfaces of the specified modules according to the position information to generate a wiring netlist; modifying the idle interfaces in the wiring netlist to scan signal interfaces reserved by the specified modules and inserting preset scan logic to obtain a chain insertion netlist; generating a customized bitstream according to the chain insertion netlist.

4. The programmable chip multi-module parallel DFT verification method of claim 1, wherein, The modification of the scan signal interfaces of each of the specified modules to a unified scan signal interface, the instantiation of the specified modules, and the generation of a DFT simulation control file further comprise: determining values of non-scan signal interfaces of the specified modules in a scan mode to generate fixed value constraints, wherein the fixed value constraints are stored in the subsequently generated DFT simulation control file; setting offset circuit components for offsetting reserved circuit components at the scan signal interfaces of the specified modules, wherein the offset circuit components are stored in the subsequently generated DFT simulation control file.

5. The programmable chip multi-module parallel DFT verification method of claim 4, wherein, The inputting of the DFT simulation control file and the chain insertion netlist into a preset DFT excitation generation tool to generate an excitation data file and a test protocol file comprises: the preset DFT excitation generation tool determines excitation information for the specified modules according to the instantiated specified modules, the fixed value constraints, and the offset circuit components to generate an excitation data file; the preset DFT excitation generation tool sets excitation output interfaces and result detection interfaces to generate a test protocol file.

6. The programmable chip multi-module parallel DFT verification method of claim 1, wherein, The test protocol top layer comprises excitation output interfaces and result detection interfaces. The interconnection of the programmable chip top layer and the test protocol top layer comprises: interconnect an excitation output interface of the test protocol top layer with the programmable chip top layer, and interconnect a result detection interface of the test protocol top layer with the programmable chip top layer.

7. The programmable chip multi-module parallel DFT verification method of claim 5, wherein, The scan signal interface comprises a scan input interface and a scan output interface; The parallel DFT simulation of the programmable chip top layer and the test protocol top layer according to the customized bitstream and the excitation data file and for the plurality of specified modules obtains DFT verification results of the specified modules, which comprises: inputting the customized bitstream into the programmable chip top layer, configuring a scan path of the programmable chip, and generating a scan signal; controlling the test protocol top layer to generate an excitation data signal according to the excitation data file through the scan signal; The excitation data signal is input into the programmable chip top layer through an excitation output interface of the test protocol top layer, is input into scan input interfaces of the plurality of specified modules through a chain netlist of the programmable chip top layer, and parallel scanning of the plurality of specified modules obtains a scan result; The scan result is output to a result detection interface of the test protocol top layer through the programmable chip top layer through the scan output interface; The test protocol top layer detects according to the scan result, and obtains the DFT verification results of the plurality of specified modules.

8. A programmable chip multi-module parallel DFT verification system, characterized in that, The system comprises: an information confirmation module configured to determine IO ports of a programmable chip and specified modules to be scanned; a bitstream generation module configured to wire the IO ports to scan signal interfaces of the specified modules to generate a chain netlist, and generate a customized bitstream according to the chain netlist; a customized excitation file generation module configured to modify the scan signal interfaces of the specified modules into uniform scan signal interfaces, instantiate the specified modules, and generate a DFT simulation control file; input the DFT simulation control file and the chain netlist into a preset DFT excitation generation tool to generate an excitation data file and a test protocol file; an simulation verification module configured to generate a programmable chip top layer according to the chain netlist; instantiate the test protocol file to generate a test protocol top layer; interconnect the programmable chip top layer and the test protocol top layer; perform parallel DFT simulation of the programmable chip top layer and the test protocol top layer according to the customized bitstream and the excitation data file and for the plurality of specified modules, and obtain DFT verification results of the specified modules.

9. The programmable chip multi-module parallel DFT verification system of claim 8, wherein, The test protocol top layer comprises an excitation output interface and a result detection interface; The simulation verification module is specifically configured to: interconnect an excitation output interface of the test protocol top layer with the programmable chip top layer, and interconnect a result detection interface of the test protocol top layer with the programmable chip top layer.

10. The programmable chip multi-module parallel DFT verification system of claim 8, wherein, The scan signal interface comprises a scan input interface and a scan output interface; The simulation verification module is specifically configured to: input the customized bitstream into the programmable chip top layer, configure a scan path of the programmable chip, and generate a scan signal; control the test protocol top layer to generate an excitation data signal according to the excitation data file through the scan signal; The excitation data signal is input to the programmable chip top layer through an excitation output interface of the test protocol top layer, is input to a plurality of the specified modules through a chain netlist of the programmable chip top layer, and is input to a scan input interface of the plurality of the specified modules; and parallel scanning is performed on the plurality of the specified modules to obtain a scan result. The scan result is output to a result detection interface of the test protocol top layer through the scan output interface and the programmable chip top layer. The test protocol top layer performs detection according to the scan result to obtain a DFT verification result of the plurality of the specified modules.

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