Ultrasonic fingerprint readout circuit and ultrasonic fingerprint chip

Abstract

The present disclosure provides an ultrasonic fingerprint readout circuit and an ultrasonic fingerprint chip, and relates to the technical field of semiconductors. The ultrasonic fingerprint readout circuit comprises: a piezoelectric transducer configured to convert a return wave into a return wave voltage, the piezoelectric transducer comprising a pixel electrode plate; a pixel circuit comprising a switching component and a continuous integrator, the switching component being configured to connect the continuous integrator to a return wave integral voltage opposite to the return wave voltage, and the switching component being further configured to configure the pixel electrode plate to a preparation state for receiving the return wave voltage; and a sampling module configured to sequentially collect a peak voltage and a trough voltage of the return wave integral voltage based on a multiphase clock, and to output a target signal based on the peak voltage and the trough voltage, the target signal being used to generate or simulate an image containing a biological feature. Through the technical solution of the present disclosure, the voltage clamping of the pixel electrode plate and the preparation state configuration can be realized by only a single reference voltage through the closed-loop feedback mechanism of the continuous integrator in the pixel circuit.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to an ultrasonic fingerprint reading circuit and an ultrasonic fingerprint chip. Background Technology

[0002] An ultrasonic fingerprint chip uses a piezoelectric transducer to emit ultrasonic waves, receives the echoes reflected by the ridges of the finger and converts them into electrical signals, and then processes these electrical signals to identify fingerprints. The chip includes a readout circuit, which requires two reference voltages: one for resetting the pixel plate and the other for the internal operational amplifier. Since the two reference voltages are configured separately and both contribute noise, the signal-to-noise ratio of the ultrasonic fingerprint chip needs to be optimized.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to provide an ultrasonic fingerprint reading circuit and an ultrasonic fingerprint chip, which at least to some extent overcome the problem that the signal-to-noise ratio of ultrasonic fingerprint chips in related technologies needs to be optimized.

[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0006] According to one aspect of this disclosure, an ultrasonic fingerprint reading circuit is provided, comprising: a piezoelectric transducer configured to receive an echo of an emitted ultrasonic wave and convert the echo into an echo voltage, the piezoelectric transducer including a pixel plate; a pixel circuit connected to the piezoelectric transducer, including a switching assembly and a continuous integrator, the switching assembly being configured to cause the continuous integrator to output an echo integrated voltage opposite to the echo voltage, the switching assembly also being configured to configure the pixel plate to a ready state for receiving the echo voltage; and a sampling module connected to the pixel circuit, configured to sequentially acquire the peak voltage and trough voltage of the echo integrated voltage based on a multi-phase clock, and output a target signal based on the peak voltage and the trough voltage, the target signal being used to generate or simulate an image containing biometric features.

[0007] In one embodiment of this disclosure, the continuous integrator includes an integrating amplifier; the switching assembly includes: a first switch, one end of which is connected to the pixel plate, and the other end of which is connected to a first voltage; a second switch, one end of which is connected to one end of the first switch, and the other end of which is connected to a first input terminal of the integrating amplifier, the second input terminal of which is used to connect to a first reference voltage; wherein, if the first switch is closed and the second switch is open, the pixel plate is connected to the first voltage, and the continuous integrator does not receive the echo voltage; if the first switch is open and the second switch is closed, the voltage of the pixel plate is clamped to the first reference voltage to be configured in the ready state.

[0008] In one embodiment of this disclosure, the continuous integrator further includes: an integrating capacitor, one end of which is connected to the other end of the second switch, and the other end of which is connected to the output terminal of the integrating amplifier; and a third switch connected in parallel with the integrating capacitor. When the piezoelectric transducer receives a high-voltage pulse signal, the first switch and the third switch are closed, the integrating capacitor is charged, the piezoelectric transducer stops receiving the high-voltage pulse signal, the first switch is opened, the second switch is closed, the first input terminal is connected to the pixel plate, and the output terminal of the integrating amplifier and the first input terminal form a negative feedback circuit via the integrating capacitor. The integrating amplifier uses the first reference voltage at the second input terminal as a reference and, through closed-loop adjustment of the negative feedback, clamps the voltage of the pixel plate to the first reference voltage. When the pixel plate is unshielded, the third switch is opened, and the integrating amplifier and the integrating capacitor cooperate to perform continuous integration of the echo voltage.

[0009] In one embodiment of this disclosure, a first input terminal is connected to the pixel plate. The first input terminal generates a charging current based on the detected change in the echo voltage. The charging current continuously charges the integrating capacitor, causing the voltage across the integrating capacitor to change periodically over time with reference to the first reference voltage, thereby causing the integrating amplifier to output the echo integrated voltage.

[0010] In one embodiment of this disclosure, the sampling module includes: a plurality of first sampling capacitors for acquiring the trough voltage of the echo integrated voltage; a plurality of second sampling capacitors for acquiring the peak voltage of the echo integrated voltage; a plurality of first control switches connected to one end of each of the plurality of first sampling capacitors; a plurality of second control switches connected to one end of each of the plurality of second sampling capacitors; and a multi-phase clock unit for outputting a multi-phase clock signal, the multi-phase clock signal being used to control the first control switches and the second control switches to be turned on alternately in sequence, so as to acquire the peak voltage and the trough voltage in sequence.

[0011] In one embodiment of this disclosure, the sampling module further includes an operational amplifier, including a third input terminal, a fourth input terminal, a first output terminal, and a second output terminal. The other ends of a plurality of first sampling capacitors are respectively connected to the third input terminal, and the other ends of a plurality of second sampling capacitors are respectively connected to the fourth input terminal. The operational amplifier is configured to operate in a sampling phase or an amplification phase.

[0012] In one embodiment of this disclosure, the sampling module further includes: a first feedback capacitor, one end of which is connected to the third input terminal and the other end of which is connected to the first output terminal; a second feedback capacitor, one end of which is connected to the fourth input terminal and the other end of which is connected to the second output terminal; and a plurality of sampling clocks, including: a first sampling clock switch, one end of which is connected to the third input terminal; a second sampling clock switch, one end of which is connected to the other end of the first feedback capacitor; a third sampling clock switch, one end of which is connected to the fourth input terminal; and a fourth sampling clock switch, one end of which is connected to the other end of the second feedback capacitor; wherein, when the plurality of sampling clocks are closed, the operational amplifier operates in the sampling phase, the first sampling capacitor stores the charge of the trough voltage, the second sampling capacitor stores the charge of the peak voltage, and the first and second feedback capacitors store the offset voltage of the operational amplifier, the offset voltage being used to counteract the offset effect of the operational amplifier.

[0013] In one embodiment of this disclosure, the sampling module further includes multiple amplification clock switches, including: multiple first amplification clock switches, connected in parallel corresponding to multiple first control switches; multiple second amplification clock switches, connected in parallel corresponding to multiple second control switches; a third amplification clock switch, disposed between the other end of the first feedback capacitor and the first output terminal; and a fourth amplification clock switch, disposed between the other end of the second feedback capacitor and the second output terminal. When the multiple sampling clocks are disconnected and the multiple amplification clock switches are closed, the operational amplifier operates in the amplification phase, transferring the charge of the trough voltage to the first feedback capacitor and the charge of the peak voltage to the second feedback capacitor. It also performs signal gain based on the capacitance ratio between the first sampling capacitor and the first feedback capacitor, and the capacitance ratio between the second sampling capacitor and the second feedback capacitor, to output the target signal from the first output terminal and the second output terminal.

[0014] In one embodiment of this disclosure, the sampling module further includes: a differential fractional-to-analog converter, including a third output terminal and a fourth output terminal, wherein the third output terminal is used to output a positive differential voltage and to input a second reference voltage to the first sampling capacitor in the amplified phase, and the fourth output terminal is used to output a reverse differential voltage and to input a third reference voltage to the second sampling capacitor in the amplified phase.

[0015] In one embodiment of this disclosure, the device further includes a conversion module configured to convert the target signal into a digital fingerprint feature signal. In another embodiment of this disclosure, the piezoelectric transducer further includes a piezoelectric electrode plate and a piezoelectric layer disposed between the piezoelectric electrode plate and the pixel electrode plate.

[0016] According to another aspect of this disclosure, an ultrasonic fingerprint chip is provided, comprising: the ultrasonic fingerprint reading circuit provided in the above embodiments.

[0017] The voltage conversion scheme provided in the embodiments of this disclosure, through the closed-loop feedback mechanism of the continuous integrator in the pixel circuit, can realize the voltage clamping and ready state configuration of the pixel plate with only a single reference voltage. Furthermore, the use of continuous integration mode is also beneficial to prevent the superposition of offset errors caused by multiple switching. Combined with the function of the sampling module to collect multiple sets of peak and trough voltages through multi-phase clock and perform differential operation, the positive and negative offset voltages in the operational amplifier cancel each other out. Moreover, the offset storage mode of the operational amplifier in the sampling module is also beneficial to further cancel the offset effect. While simplifying the circuit design, it also significantly optimizes the noise performance in the recognition circuit, thereby improving the accuracy and reliability of fingerprint recognition.

[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0020] Figure 1 A circuit diagram of an ultrasonic fingerprint reading circuit in the related art is shown;

[0021] Figure 2 Show Figure 1 A schematic diagram of the working timing of an ultrasonic fingerprint reading circuit;

[0022] Figure 3 A schematic diagram of an ultrasonic fingerprint reading circuit according to an embodiment of the present disclosure is shown.

[0023] Figure 4 A schematic diagram of the piezoelectric transducer and pixel circuit in the ultrasonic fingerprint reading circuit of this embodiment is shown.

[0024] Figure 5 A circuit diagram of the sampling module in the ultrasonic fingerprint reading circuit of this embodiment is shown;

[0025] Figure 6 This diagram illustrates the timing sequence of an ultrasonic fingerprint reading circuit according to an embodiment of the present disclosure.

[0026] Figure 7 A circuit diagram of another ultrasonic fingerprint reading circuit in an embodiment of this disclosure is shown. Detailed Implementation

[0027] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0028] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0029] An ultrasonic fingerprint chip is a semiconductor chip that uses a piezoelectric transducer to receive ultrasonic echoes and convert them into electrical signals. These signals are then processed by a readout circuit to identify fingerprint ridge features, achieving high-precision biometric identification. In related technologies, an ultrasonic fingerprint chip typically contains many detection units, each integrating a piezoelectric sensing capacitor. ,like Figure 1 The ultrasonic fingerprint reading circuit shown may include a piezoelectric sensing capacitor 102, a pixel circuit 104, a programmable gain amplifier (PGA) 106, and an analog-to-digital converter (ADC) 108. The piezoelectric sensing capacitor 102 includes an upper electrode 1022, a lower electrode (i.e., the top metal electrode of the detection unit) 1024, and a piezoelectric layer 1026 between the upper electrode 1022 and the lower electrode 1024. The top metal electrode of the detection unit is used to receive the ultrasonic echo voltage. When a finger is pressed on the surface of the ultrasonic fingerprint chip, a driving voltage applied to the upper electrode 1022 drives the piezoelectric layer 1026 to generate an ultrasonic wave emission signal. When the echo signal of the ultrasonic wave reaches the piezoelectric layer 1026, the voltage on the lower electrode 1024 changes and is detected by the readout circuit, i.e., the echo voltage is detected. By judging the echo voltage The amplitude is used to determine whether it is a valley or a ridge, thus completing the fingerprint recognition operation. Additionally... The parasitic capacitance in pixel circuit 104 It is the reset voltage of pixel circuit 104. It is the reference voltage of the pixel operational amplifier pxl_op. and The relationship can be: = =1 / 2 power supply voltage.

[0030] Figure 2 It shows Figure 1 The ultrasonic fingerprint reading circuit shown has one possible operating timing, such as... Figure 2 As shown, when the high-voltage coding circuit of the ultrasonic fingerprint chip ( Figure 1 When working (not shown), that is, during the t0 period, S1 is pulled high, which pulls PXL low. After the coding is completed, the t1 period begins, S1 is set low, S4 is pulled high, and pxl_op is reset. Then, the t2 period begins, S2 is pulled high, and PXL is also reset to Vref1. At this point, both pxl_op and PXL have completed their resets. Then S4 is pulled low, and the pxl_op reset ends.

[0031] At some point during time period t3, the PGA samples px_out for the first time to obtain vs1. Then, during time period t4, S2 is pulled low and S3 is pulled high. The PIXEL circuit integrates V1 for the first time, from the peak to the trough. After integration, S3 is pulled low and S2 is pulled high, PXL is reset. After the reset, S2 is pulled low and S3 is pulled high, and the PIXEL circuit integrates V1 for the second time, from the peak to the trough. This integration process is repeated multiple times (e.g., ...). Figure 2 As shown in the figure (integration 5 times), we can see that time period t4 is the integration time of the PIXEL circuit. After the 5 integrations are completed, time period t5 begins. S3 is pulled low and S2 is pulled high. At some point in time period t5, the PGA samples px_out for the second time to obtain vs2. The output of the PGA is gain. (vs2-vs1), where gain is the known gain of the PGA, can be determined by quantizing the output of the PGA using the ADC. This allows us to judge the fingerprint status above the detection unit.

[0032] based on Figure 1 and Figure 2 It can be seen that, on the one hand, the circuit needs to be configured with two independent reference voltages. and ,in Used for pixel plate PXL reset. As reference voltages at the input of the operational amplifier pxl_op, the inherent noise of these two voltages will be directly injected into the signal chain, causing a decrease in the signal-to-noise ratio (SNR). The requirement for strong driving capability and wide bandwidth for multi-pixel parallel reset not only significantly increases the design difficulty of the reference voltage generation circuit, but also increases the chip area and power consumption. On the other hand, the inherent offset voltage Vos of the operational amplifier pxl_op will be transmitted through the circuit's parasitic capacitance. The coupling with the feedback capacitor Cfb generates an error voltage of Vos×Cpar / Cfb at the output px_out after each integration. This offset error accumulates proportionally, requiring an additional chopper calibration circuit to be designed for the operational amplifier pxl_op, which further increases the design complexity of the operational amplifier and may introduce new noise and power consumption burdens.

[0033] like Figure 3As shown, an ultrasonic fingerprint reading circuit according to an embodiment of the present disclosure includes: a piezoelectric transducer 302, a pixel circuit 304, and a sampling module 306.

[0034] The piezoelectric transducer 302 is configured to receive the echo of the emitted ultrasonic wave and convert the echo into an echo voltage. The piezoelectric transducer includes pixel plates.

[0035] In some embodiments, such as Figure 4 As shown, the piezoelectric transducer 302 includes a piezoelectric sensing capacitor. piezoelectric sensing capacitor It includes a pixel electrode plate 3022, a piezoelectric electrode plate 3024, and a piezoelectric layer 3026 disposed between the piezoelectric electrode plate and the pixel electrode plate.

[0036] Among them, the piezoelectric electrode plate refers to the electrode plate covering the piezoelectric layer.

[0037] In some embodiments, the piezoelectric layer may be a piezoelectric material layer such as PVDF (Polyvinylidene Fluoride) or PZT (Lead Zirconate Titanate).

[0038] In some embodiments, electrodes are provided on both sides of the piezoelectric layer for applying high voltage to drive the piezoelectric layer to emit ultrasonic waves and for conducting echo voltage when receiving echoes. One electrode can be designed as a metal electrode, such as a thin metal layer that covers the entire piezoelectric layer, which can be called the first electrode, i.e., the piezoelectric electrode in this disclosure. The piezoelectric electrode can be an Ag layer. The other electrode can be designed as a discrete metal electrode, such as using the top metal layer of a chip, which can be called the second electrode, i.e., the pixel electrode in this disclosure. When ultrasonic waves need to be emitted, the second electrode is grounded and the first electrode is connected to the driving voltage; when ultrasonic waves need to be received, the second electrode is connected to the subsequent readout circuit.

[0039] In some embodiments, the piezoelectric transducer 302 may also be a symmetrical structure with a double piezoelectric layer combined with an intermediate electrode.

[0040] In some embodiments, when the ultrasonic waves emitted by the fingerprint recognition chip come into contact with the fingerprint, the difference in the ridge and valley structure leads to different reflection energy and penetration depth of the echo. The fingerprint ridge reflects ultrasonic waves with strong energy, while the valley reflects them with weak energy. This difference causes the piezoelectric layer to generate corresponding mechanical vibrations. The piezoelectric transducer converts the mechanical vibrations into an echo voltage that matches the echo energy through the piezoelectric effect, thereby realizing the sensing conversion from acoustic signals to electrical signals.

[0041] The pixel circuit 304 is connected to the piezoelectric transducer 302 and includes a switching assembly and a continuous integrator. The switching assembly is configured to output an echo integration voltage that is opposite to the echo voltage from the continuous integrator. The switching assembly is also used to configure the pixel plate to a ready state for receiving the echo voltage, so that the pixel circuit does not need a separate pixel plate reset voltage source, and the voltage of the pixel plate is clamped to the reference voltage through the closed-loop feedback of the continuous integrator.

[0042] In some embodiments, the operating state of the switching component is precisely synchronized with the working stage of the ultrasonic fingerprint chip. During the high-voltage pulse transmission stage, the switching component isolates the pixel plate from the continuous integrator through the corresponding on / off state, while preventing interference signal injection by means of the preset configuration of the continuous integrator. When entering the echo reception stage, the switching component switches to the on state, establishing a signal path between the pixel plate and the continuous integrator. The continuous integrator constructs a closed-loop feedback loop based on a preset reference voltage, and clamps the voltage of the pixel plate to the reference voltage through feedback adjustment, completing the preparation state configuration for echo reception. After the piezoelectric transducer converts the ultrasonic echo into an echo voltage, the voltage signal is input to the continuous integrator through the pixel plate. The continuous integrator outputs an echo integrated voltage that is out of phase with the echo voltage through continuous integration calculation of capacitor charging and discharging. This process does not require an additional independent pixel plate reset voltage source; the voltage calibration and preparation of the pixel plate can be achieved solely through the closed-loop feedback mechanism of the continuous integrator.

[0043] The sampling module 306 is connected to the pixel circuit 304 and is used to sequentially acquire the peak voltage and trough voltage of the echo integral voltage based on the multi-phase clock, and output the target signal based on the peak voltage and trough voltage. The target signal is used to generate or simulate an image containing biological features.

[0044] In some embodiments, the sampling module 306 may be a programmable gain amplifier.

[0045] In some embodiments, by configuring a multi-phase clock unit to output sequentially triggered clock signals, when the echo integral voltage (which fluctuates periodically) is input to the sampling module, the peak voltage and trough voltage of the echo integral voltage are collected respectively. For example, the odd-numbered phase clock triggers the collection of trough voltage, and the even-numbered phase clock triggers the collection of peak voltage. The collected peak and trough voltage signals are stored, and the stored peak and trough voltages are differentially calculated. By superimposing the sum of peak voltages and the sum of trough voltages and taking the difference, a target signal that can reflect the amplitude characteristics of the echo integral voltage is generated. This target signal carries the echo energy difference information corresponding to the fingerprint ridge and valley.

[0046] In this embodiment, the closed-loop feedback mechanism of the continuous integrator in the pixel circuit enables voltage clamping and preparation configuration of the pixel plate with only a single reference voltage. The continuous integration mode also helps to prevent the superposition of offset errors caused by multiple switching. Combined with the sampling module's function of acquiring multiple sets of peak and trough voltages through multi-phase clock and performing differential operations, the positive and negative offset voltages in the operational amplifier cancel each other out. Furthermore, the offset storage mode of the operational amplifier in the sampling module is also conducive to further offsetting the offset effect. While simplifying the circuit design, it also significantly optimizes the noise performance in the recognition circuit, thereby improving the accuracy and reliability of fingerprint recognition.

[0047] In one embodiment of this disclosure, the continuous integrator includes an integrating amplifier Pxl_op; the switching assembly includes: a first switch S1, one end of which is connected to a pixel plate, and the other end of which is connected to a first voltage; and a second switch S2, one end of which is connected to one end of the first switch S1, and the other end of which is connected to a first input terminal of the integrating amplifier Pxl_op, the second input terminal of which is used to connect to the first reference voltage.

[0048] Among them, one of the first input terminal and the second input terminal is an inverting input terminal, and the other is a positive input terminal.

[0049] In some embodiments, if the first switch S1 is closed and the second switch S2 is open, the pixel plate is connected to the first voltage, and the continuous integrator does not receive the echo voltage. If the first switch S1 is open and the second switch S2 is closed, the voltage of the pixel plate is clamped to the first reference voltage to be configured into a ready state.

[0050] In some embodiments, the continuous integrator includes an integrating amplifier Pxl_op, which adapts to different operating stages of the ultrasonic fingerprint chip through the mutual exclusion conduction logic of the first switch S1 and the second switch S2: when the chip emits a high-voltage pulse, the first switch S1 is closed and the second switch S2 is open, and the pixel plate is connected to the first voltage. At this time, the pixel plate and the integrating amplifier Pxl_op remain isolated, and the continuous integrator cannot receive the echo voltage, preventing high-voltage pulse interference from being injected into the integrating circuit; when the high-voltage pulse emission ends, the first switch S1 is open and the second switch S2 is closed, and the pixel plate is connected to the first input terminal of the integrating amplifier Pxl_op through the second switch S2. The integrating amplifier constructs a closed-loop feedback loop based on the first reference voltage connected to the second input terminal, and precisely clamps the voltage of the pixel plate to the first reference voltage through feedback adjustment, so that the pixel plate switches from the interference shielding state to the echo voltage receiving preparation state.

[0051] In some embodiments, the first voltage can be the internal ground voltage of the chip, which can be generated from the external GND through a voltage boosting circuit (such as a level shifter or LDO), denoted as . .

[0052] In some embodiments, the pixel plate is connected to a first voltage. Subsequently, its potential is clamped at a stable first voltage, rather than floating. The interference signal of the high-voltage pulse has a larger amplitude relative to the external GND, but smaller amplitude relative to the first voltage. The potential difference is significantly reduced, which can reduce the injection of interference signals into the pixel electrode.

[0053] In this embodiment, the switching of different states of the pixel circuit is realized through the linkage control of the integrating amplifier and the dual switches. During the high voltage pulse stage, the first voltage is connected by closing the first switch S1 to prevent the integrating amplifier from being impacted by the strong electric signal. During the echo reception stage, the voltage clamping of the pixel plate can be completed without the need for an additional reset circuit, which simplifies the reset logic of the pixel circuit.

[0054] In one embodiment of this disclosure, the continuous integrator further includes: an integrating capacitor. Integrating capacitor One end is connected to the other end of the second switch S2, and the integrating capacitor The other end is connected to the output of the integrating amplifier Pxl_op; the third switch S3 is connected in parallel with the integrating capacitor.

[0055] In this circuit, the piezoelectric transducer receives a high-voltage pulse signal. When the first switch S1 and the third switch S3 are closed, the integrating capacitor is charged. When the piezoelectric transducer stops receiving the high-voltage pulse signal, the first switch S1 is opened, the second switch S2 is closed, and the first input terminal is connected to the pixel plate. The output terminal of the integrating amplifier Pxl_op and the inverting input terminal form a negative feedback circuit through the integrating capacitor. The integrating amplifier Pxl_op uses the first reference voltage at the second input terminal as a reference and clamps the voltage of the pixel plate to the first reference voltage through the closed-loop adjustment of the negative feedback. When the pixel plate is unshielded, the third switch S3 is opened. The integrating amplifier Pxl_op and the integrating capacitor work together to continuously integrate the echo voltage.

[0056] In some embodiments, based on the integrating amplifier Pxl_op and the integrating capacitor The third switch S3 is configured with a continuous integrator, which, together with the first switch S1 and the second switch S2, adapts to the high-voltage transmission and echo reception process of the piezoelectric transducer. Specifically, when the piezoelectric transducer receives a high-voltage pulse signal, the first switch S1 and the third switch S3 close synchronously. On the one hand, the pixel plate is connected to the first voltage to achieve high-voltage interference shielding; on the other hand, the integrating capacitor... The integrator is quickly charged via the closed third switch S3, completing the initialization preparation. High-voltage pulse transmission stops, the first switch S1 opens to release the shielding of the pixel plate, and the second switch S2 closes to connect the pixel plate to the first input terminal (inverting input) of the integrating amplifier Pxl_op. At this time, the output terminal of the integrating amplifier is connected via the integrating capacitor. A stable negative feedback circuit is formed with the first input terminal. The integrating amplifier uses the first reference voltage at the second input terminal (i.e., the positive input terminal) as a reference. Through negative feedback closed-loop adjustment, the voltage of the pixel plate is precisely clamped to the first reference voltage, enabling the pixel plate to receive echo voltage. When the third switch S3 is opened, the piezoelectric transducer converts the received ultrasonic echo into an echo voltage and transmits it to the pixel plate. This voltage change drives the integrating amplifier through the negative feedback loop, causing the integrating capacitor to... When entering a continuous charging and discharging state, the integrating amplifier and the integrating capacitor work together to complete the continuous integration of the echo voltage, and output a periodic echo integrated voltage that is opposite to the echo voltage.

[0057] In this embodiment, during the high-voltage transmission phase, the closing of the third switch S3 completes the rapid charging of the integrating capacitor, preventing signal distortion caused by the initial state drift of the integrator. During the echo reception phase, the synergistic effect of the negative feedback circuit and the integrating capacitor ensures the reference consistency of the echo voltage received by the pixel plate through voltage clamping, and fully preserves the amplitude characteristics of the echo voltage through continuous integration mode. In addition, the combination of the integrating capacitor and negative feedback stabilizes the gain of the integrating amplifier, effectively amplifying weak echo voltage signals and improving signal strength. At the same time, there is no need to set up an additional independent integrating reset circuit, which simplifies the circuit structure and control logic, reduces the power consumption and area overhead of the chip, and provides a stable signal source for the subsequent sampling module to collect peak and trough voltages.

[0058] In one embodiment of this disclosure, the first input terminal is connected to the pixel plate. The first input terminal generates a charging current based on the detected change in echo voltage. The charging current continuously charges the integrating capacitor, causing the voltage across the integrating capacitor to change periodically with time based on a first reference voltage, so that the integrating amplifier Pxl_op outputs the echo integrated voltage.

[0059] In this embodiment, the echo voltage amplitude after the ultrasonic echo is converted by the piezoelectric transducer is weak and carries the energy difference information of fingerprint valleys and ridges. Direct transmission to the subsequent sampling module is easily drowned out by noise. It is necessary to accumulate and amplify the signal amplitude through integration. The echo voltage fluctuates periodically. Based on the change of the echo voltage, the voltage across the integrating capacitor changes periodically with the first reference voltage as a reference. This can accumulate the signal amplitude and completely preserve the fluctuation pattern of the echo voltage. After the first input terminal is connected to the pixel plate, the integrating amplifier clamps the voltage of the pixel plate to the first reference voltage through the negative feedback loop. At this time, the change of the echo voltage is directly converted into a stable charging current. By directly driving the integrating capacitor to charge through the echo voltage, there is no need to set up an additional signal amplification pre-circuit. Signal conditioning can be achieved by the cooperation of the integrating amplifier and the integrating capacitor, reducing the number of components and reducing the complexity and power consumption of the circuit.

[0060] like Figure 5 As shown, in one embodiment of this disclosure, the sampling module includes: multiple first sampling capacitors Cs1 for acquiring the valley voltage of the echo integrated voltage; multiple second sampling capacitors Cs2 for acquiring the peak voltage of the echo integrated voltage; multiple first control switches ks0, each connected to one end of the multiple first sampling capacitors; multiple second control switches ks1, each connected to one end of the multiple second sampling capacitors; and a multi-phase clock unit for outputting a multi-phase clock signal, which controls the first control switches ks0 and the second control switches ks1 to be turned on alternately in sequence, so as to acquire the peak voltage and valley voltage in sequence.

[0061] In some embodiments, such as Figure 5 As shown, the sampling module includes two sets of sampling units. The first set of sampling units may include multiple sets (five sets in this embodiment) of first sampling capacitors Cs1 and first control switches ks0, corresponding to valley voltage acquisition. Each sub-module is independently controlled by a multi-phase clock (i.e., clks0 / clks2 / clks4 / clks6 / clks8). The second set of sampling units may include five sets of second sampling capacitors Cs2 and second control switches ks1, corresponding to peak voltage acquisition. Each sub-module is independently controlled by a multi-phase clock (i.e., clks1 / clks3 / clks5 / clks7 / clks9). The signals of the multi-phase clocks are as follows: Figure 6As shown, the first control switch ks0 and the second control switch ks1 are alternately turned on by a multi-phase clock (clks0 to clks9) to adapt to the periodic fluctuation characteristics of the echo integral voltage px_out. The echo integral voltage changes periodically with the ultrasonic frequency, from trough to peak to trough. By alternately triggering the multi-phase clock, each set of trough and peak voltages can be captured, which can minimize the influence of random noise in a single sampling. Furthermore, the structure of multiple first sampling capacitors Cs1 and multiple second sampling capacitors Cs2 can accumulate the charge of multiple sets of peak / trough voltages, which can amplify the effective difference of the signal.

[0062] In this embodiment, the coordination between the alternating control switch and the multi-phase clock ensures that the valley voltage and peak voltage are collected one by one, preserving the timing characteristics of the echo integral voltage. The charge accumulation of multiple sampling capacitors averages out random noise, while the effective signal difference corresponding to the fingerprint valley ridge is amplified, which helps to improve the signal-to-noise ratio. In addition, the corresponding multiple first sampling capacitors and multiple second sampling capacitors can flexibly adjust the number of sampling groups according to the echo intensity, balancing signal amplification and sampling efficiency.

[0063] like Figure 5 As shown, in one embodiment of this disclosure, the sampling module further includes: an operational amplifier pga_op, including a third input terminal, a fourth input terminal, a first output terminal, and a second output terminal; the other ends of a plurality of first sampling capacitors Cs1 are respectively connected to the third input terminal; the other ends of a plurality of second sampling capacitors Cs2 are respectively connected to the fourth input terminal; the operational amplifier pga_op is configured to operate in the sampling phase or the amplification phase; the operational amplifier pga_op operates in offset storage mode in the sampling phase; and the offset voltage is stored in the feedback capacitor to offset the effect of offset.

[0064] The first output terminal is the inverting output terminal of the operational amplifier pga_op, which outputs the inverting output voltage Von, corresponding to the amplified output of the trough voltage group (the signal stored in Cs1). The second output terminal is used to output the voltage Vop of the non-inverting output terminal of the operational amplifier pga_op, corresponding to the amplified output of the peak voltage group (the signal stored in Cs2).

[0065] In one embodiment of this disclosure, the sampling module further includes:

[0066] The first feedback capacitor Cf1 has one end connected to the third input terminal and the other end connected to the first output terminal; the second feedback capacitor Cf2 has one end connected to the fourth input terminal and the other end connected to the second output terminal.

[0067] Multiple sampling clocks are included: a first sampling clock switch clke1, one end of which is connected to the third input terminal; a second sampling clock switch clke2, one end of which is connected to the other end of the first feedback capacitor Cf1; a third sampling clock switch clke3, one end of which is connected to the fourth input terminal; and a fourth sampling clock switch clke4, one end of which is connected to the other end of the second feedback capacitor Cf2.

[0068] In this process, multiple sampling clocks are closed, and the operational amplifier pga_op operates in the sampling phase. The first sampling capacitor Cs1 stores the charge of the trough voltage, the second sampling capacitor Cs2 stores the charge of the peak voltage, and the first feedback capacitor Cf1 and the second feedback capacitor Cf2 store the offset voltage of the operational amplifier pga_op. The offset voltage is stored in the feedback capacitor to prevent the accumulation of offset error during integration. The offset voltage is used to offset the offset effect of the operational amplifier pga_op.

[0069] In some embodiments, the third and fourth input terminals of the operational amplifier pga_op are respectively connected to multiple sets of first sampling capacitors Cs1 and multiple sets of second sampling capacitors Cs2. The operational amplifier pga_op has an inherent offset voltage, which will lead to sampling error if it directly participates in signal processing. Offset storage is achieved by closing the first sampling clock switch clke1 to the fourth sampling clock switch clke4, storing the offset voltage of the operational amplifier pga_op in the first feedback capacitor Cf1 and the second feedback capacitor Cf2. At the same time, the first sampling capacitor Cs1 stores the charge of the trough voltage, and the second sampling capacitor Cs2 stores the charge of the peak voltage. This achieves the synchronous completion of signal charge storage and offset voltage pre-storage to prevent the offset voltage from introducing errors in the subsequent amplification stage.

[0070] In this embodiment, the offset voltage stored by the first feedback capacitor Cf1 and the second feedback capacitor Cf2 cancels out the real-time offset voltage of the operational amplifier pga_op during the amplification stage, thus solving the problem of offset error accumulation. When the sampling clock is closed, the common-mode voltage Vcm is stabilized by the access of the second sampling clock switch clke2 and the fourth sampling clock switch clke4, preventing the loss of peak and trough charges stored by the first sampling capacitor Cs1 and multiple second sampling capacitors Cs2 due to level drift. This allows the sampling to be synchronized to complete signal sampling and offset storage without the need for additional offset calibration timing, reducing the complexity of the control logic.

[0071] like Figure 5 As shown, in one embodiment of this disclosure, the sampling module further includes multiple amplified clock switches, including:

[0072] Multiple first amplification clock switches clka1 are connected in parallel with multiple first control switches ks0 one by one; multiple second amplification clock switches clka2 are connected in parallel with multiple second control switches ks1 one by one; a third amplification clock switch clka3 is located between the other end of the first feedback capacitor Cf1 and the first output terminal; a fourth amplification clock switch clka4 is located between the other end of the second feedback capacitor Cf2 and the second output terminal.

[0073] In this configuration, multiple sampling clocks are disconnected, multiple amplification clock switches are closed, and the operational amplifier pga_op operates in the amplification phase. This is used to transfer the charge of the trough voltage to the first feedback capacitor Cf1 and the charge of the peak voltage to the second feedback capacitor Cf2. Furthermore, based on the capacitance ratio between the first sampling capacitor Cs1 and the first feedback capacitor Cf1, and the capacitance ratio between the second sampling capacitor Cs2 and the second feedback capacitor Cf2, signal gain is performed to output the target signal from the first output terminal and the second output terminal.

[0074] In some embodiments, the first control switch ks0 is a key switch for controlling the first sampling capacitor Cs1 to collect the valley voltage during the sampling phase, and the second control switch ks1 is a key switch for controlling Cs2 to collect the peak voltage during the sampling phase. During the amplification phase, the sampling clock is disconnected, and the first control switch ks0 and the second control switch ks1 are disconnected synchronously. At this time, the first amplification clock switch clka1 and the second amplification clock switch clka2 are closed as parallel switches.

[0075] In some embodiments, one end of the first feedback capacitor Cf1 is connected to the third input terminal of the operational amplifier pga_op, corresponding to the signal of the first sampling capacitor Cs1, while the other end is left floating and waiting to be turned on. The second feedback capacitor Cf2 operates on the same principle as the first feedback capacitor Cf1. During the amplification phase, the third amplification clock switch clka3 and the fourth amplification clock switch clka4 are closed, which can quickly establish the signal path between the first feedback capacitor Cf1 and the first output voltage Von, and between the second feedback capacitor Cf2 and the second output voltage Vop, so that the operational amplifier pga_op forms a stable negative feedback amplification loop, providing a basis for gain calculation after charge transfer.

[0076] In some embodiments, the operational amplifier pga_op is a differential operational amplifier. The third input terminal is connected to all the first sampling capacitors Cs1, and the fourth input terminal is connected to all the second sampling capacitors Cs2. The first output voltage Von corresponds to the first feedback capacitor Cf1, and the second output voltage Vop corresponds to the second feedback capacitor Cf2. Through the independent capacitance ratio design of Cs1 / Cf1 and Cs2 / Cf2, the trough signal and the peak signal can be amplified respectively. Finally, through the differential output of Vop-Von, the difference between the amplified peak and the trough is extracted. This difference corresponds to the echo energy difference of the fingerprint ridge, thereby further obtaining the target signal, which can be an analog fingerprint feature signal.

[0077] In this embodiment, the capacitance ratio of the first sampling capacitor Cs1 to the first feedback capacitor Cf1 and the capacitance ratio of the second sampling capacitor Cs2 to the second feedback capacitor Cf2 determine the gain factor, and the capacitance can be adjusted to flexibly adapt to the amplification requirements of different echo signals.

[0078] In one embodiment of this disclosure, the sampling module further includes: a differential fractional-to-analog converter (not shown in the figure), including a third output terminal and a fourth output terminal. The third output terminal is used to output a forward differential voltage and to input a second reference voltage to the first sampling capacitor Cs1 in the amplification phase. The fourth output terminal is used to output a reverse differential voltage and to input a third reference voltage to the second sampling capacitor Cs2 in the amplification phase. The second reference voltage is the forward differential voltage Vdacp of the differential fractional-to-analog converter, and the third reference voltage is the reverse differential voltage Vdacn of the differential fractional-to-analog converter. The DC component is canceled by the difference between Vdacp and Vdacn.

[0079] In some embodiments, the first amplifying clock switch clka1 and the second amplifying clock switch clka2 are closed as parallel switches, which can directly switch one end of the first sampling capacitor Cs1 to the positive differential voltage vdacp connected to the differential DAC, and switch one end of the second sampling capacitor Cs2 to the reverse differential voltage vdacn connected to the differential DAC. This can prevent signal path interference of the sampling phase and provide a transfer path for the charge stored in the first sampling capacitor Cs1 and the second sampling capacitor Cs2. That is, through the voltage drive of the positive differential voltage vdacp and the reverse differential voltage vdacn, the charge is pushed to the first feedback capacitor Cf1 and the second feedback capacitor Cf2.

[0080] In this embodiment, by inputting the forward differential voltage Vdacp of the differential fractional-to-analog converter to the first sampling capacitor Cs1 and the reverse differential voltage Vdacn to the second sampling capacitor Cs2, the DC component of the echo signal stored in the two sets of sampling capacitors can be canceled by the preset difference between Vdacp and Vdacn. This prevents the DC component from overwhelming the effective signal or causing the signal to saturate after PGA amplification. Furthermore, it can simultaneously adapt to the parallel structure of multiple sets of first sampling capacitors Cs1 and second sampling capacitors Cs2, and synchronously enhance the DC cancellation effect during the accumulation of multiple sets of charges. This allows the difference in the effective signal to be preserved and amplified by the capacitance ratio gain, ultimately outputting a high-fidelity target signal with a high signal-to-noise ratio that can determine fingerprint features.

[0081] like Figure 7 As shown, in one embodiment of this disclosure, it further includes: a conversion module 308, configured to convert the target signal into a digital fingerprint feature signal. The conversion module is an analog-to-digital converter (ADC).

[0082] In some embodiments, the sampling module 306 includes a PGA, such as Figure 6 As shown, in the sampling phase, the PGA performs 10 alternating samplings of the echo integral voltage px_out based on the multi-phase clock, namely 5 troughs vs1, vs3, vs5, vs7 and vs9, and 5 peaks vs2, vs4, vs6, vs8 and vs10. The corresponding voltage charge is stored through multiple sets of sampling capacitors. Taking advantage of the short peak-to-trough interval and strong noise correlation, the PGA lays the foundation for noise suppression in subsequent differential operations.

[0083] Entering the amplification phase, the PGA is connected to the Vdacp and Vdacn outputs of the differential DAC. A compensation term of 5×(vdacp-vdacn) is used to cancel the superimposed DC component in the sampled signal, preventing the DC offset from drowning out the effective signal or causing the amplified signal to saturate.

[0084] Then, based on the capacitance ratio of the sampling capacitor to the feedback capacitor, the gain is determined, and an amplification operation is performed on (the sum of 5 peak voltages - the sum of 5 trough voltages + DC compensation term) to output the differential voltage Vout = Vop - Von. Since px_out fluctuates periodically, the difference between each peak and the corresponding trough is consistent. Therefore, the sum of the differential results can be simplified to (5 × (px_out peak voltage - px_out trough voltage)). Finally, Vout = gain × 5 × (px_out peak-trough voltage difference + vdacp - vdacn).

[0085] Furthermore, after quantizing Vout by the ADC, combined with the known gain, the number of 5 sampling groups, and (vdacp-vdacn), the peak-valley voltage difference of px_out can be derived in reverse. Then, based on the relationship between the integrating capacitor in the continuous integrator and the capacitance value of the related capacitive piezoelectric transducer Ct, the magnitude of the echo voltage V1 corresponding to each pixel unit can be calculated. By performing the above scanning and signal processing on all detection units one by one, the echo voltage distribution of the entire array of pixels can be obtained. Due to the energy difference of reflected ultrasonic waves, the fingerprint valley and ridge regions will correspond to different amplitude echo voltages. Based on this voltage distribution, the specific pattern of the fingerprint can be reconstructed and distinguished.

[0086] An ultrasonic fingerprint chip according to an embodiment of the present disclosure includes: the ultrasonic fingerprint reading circuit described in any of the above embodiments.

[0087] In this disclosure, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term "multiple" refers to two or more unless otherwise expressly defined. The terms "install," "connect," "link," and "fix" should be interpreted broadly. For example, "connect" can be a fixed connection, a detachable connection, or an integral connection; "link" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0088] In the description of this disclosure, it should be understood that the terms "upper," "lower," "left," "right," "front," "rear," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or unit referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0089] In the description of this specification, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0090] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure. Other embodiments of this disclosure will be readily apparent to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. An ultrasonic fingerprint reading circuit, characterized in that, include: A piezoelectric transducer is configured to receive the echo of an emitted ultrasonic wave and convert the echo into an echo voltage, the piezoelectric transducer including pixel plates; A pixel circuit, connected to the piezoelectric transducer, includes a switching assembly and a continuous integrator. The switching assembly is configured to cause the continuous integrator to output an echo integration voltage that is opposite to the echo voltage. The switching assembly is also used to configure the pixel plate to a ready state for receiving the echo voltage. The sampling module, connected to the pixel circuit, is used to sequentially acquire the peak voltage and trough voltage of the echo integral voltage based on a multi-phase clock, and output a target signal based on the peak voltage and trough voltage. The target signal is used to generate or simulate an image containing biological features.

2. The ultrasonic fingerprint reading circuit according to claim 1, characterized in that, The continuous integrator includes an integrating amplifier; The switching assembly includes: A first switch, one end of which is connected to the pixel electrode plate, and the other end of which is connected to a first voltage; A second switch, one end of which is connected to one end of the first switch, and the other end of which is connected to the first input terminal of the integrating amplifier. The second input terminal of the integrating amplifier is used to connect to the first reference voltage. Specifically, if the first switch is closed and the second switch is open, the pixel plate is connected to the first voltage, and the continuous integrator does not receive the echo voltage. If the first switch is open and the second switch is closed, the voltage of the pixel plate is clamped to the first reference voltage to be configured into the ready state.

3. The ultrasonic fingerprint reading circuit according to claim 2, characterized in that, The continuous integrator further includes: An integrating capacitor, one end of which is connected to the other end of the second switch, and the other end of which is connected to the output terminal of the integrating amplifier; The third switch is connected in parallel with the integrating capacitor. In this configuration, the piezoelectric transducer receives a high-voltage pulse signal, the first and third switches are closed, the integrating capacitor is charged, the piezoelectric transducer stops receiving the high-voltage pulse signal, the first switch is opened, the second switch is closed, the first input terminal is connected to the pixel plate, the output terminal of the integrating amplifier and the first input terminal form a negative feedback circuit through the integrating capacitor, the integrating amplifier uses the first reference voltage at the second input terminal as a reference, and clamps the voltage of the pixel plate to the first reference voltage through closed-loop adjustment of the negative feedback, the pixel plate is unshielded, the third switch is opened, and the integrating amplifier and the integrating capacitor cooperate to perform continuous integration of the echo voltage.

4. The ultrasonic fingerprint reading circuit according to claim 3, characterized in that, The first input terminal is connected to the pixel plate. The first input terminal generates a charging current based on the detected change in the echo voltage. The charging current continuously charges the integrating capacitor, causing the voltage across the integrating capacitor to change periodically with time based on the first reference voltage, so that the integrating amplifier outputs the echo integrated voltage.

5. The ultrasonic fingerprint reading circuit according to claim 1, characterized in that, The sampling module includes: Multiple first sampling capacitors are used to acquire the valley voltage of the echo integrated voltage; Multiple second sampling capacitors are used to acquire the peak voltage of the echo integrated voltage; Multiple first control switches are connected one-to-one with one end of multiple first sampling capacitors; Multiple second control switches are connected one-to-one with one end of multiple second sampling capacitors; A multi-phase clock unit is used to output a multi-phase clock signal, which is used to control the first control switch and the second control switch to be turned on alternately in sequence, so as to collect the peak voltage and the trough voltage in sequence.

6. The ultrasonic fingerprint reading circuit according to claim 5, characterized in that, The sampling module further includes: An operational amplifier includes a third input terminal, a fourth input terminal, a first output terminal, and a second output terminal. The other ends of a plurality of first sampling capacitors are respectively connected to the third input terminal, and the other ends of a plurality of second sampling capacitors are respectively connected to the fourth input terminal. The operational amplifier is configured to operate in a sampling phase or an amplification phase.

7. The ultrasonic fingerprint reading circuit according to claim 6, characterized in that, The sampling module further includes: A first feedback capacitor, one end of which is connected to the third input terminal, and the other end of which is connected to the first output terminal; A second feedback capacitor, one end of which is connected to the fourth input terminal, and the other end of which is connected to the second output terminal. Multiple sampling clocks, including: A first sampling clock switch, one end of which is connected to the third input terminal; A second sampling clock switch, one end of which is connected to the other end of the first feedback capacitor; A third sampling clock switch, one end of which is connected to the fourth input terminal; A fourth sampling clock switch, one end of which is connected to the other end of the second feedback capacitor; In this configuration, the plurality of sampling clocks are closed, the operational amplifier operates in the sampling phase, the first sampling capacitor stores the charge of the trough voltage, the second sampling capacitor stores the charge of the peak voltage, and the first feedback capacitor and the second feedback capacitor store the offset voltage of the operational amplifier, which is used to counteract the offset effect of the operational amplifier.

8. The ultrasonic fingerprint reading circuit according to claim 7, characterized in that, The sampling module also includes multiple amplified clock switches, including: Multiple first amplification clock switches are connected in parallel, corresponding one-to-one with multiple first control switches; Multiple second amplified clock switches are connected in parallel, corresponding one-to-one with multiple second second control switches; The third amplified clock switch is located between the other end of the first feedback capacitor and the first output terminal. The fourth amplifying clock switch is located between the other end of the second feedback capacitor and the second output terminal. In this configuration, the plurality of sampling clocks are disconnected, the plurality of amplification clock switches are closed, and the operational amplifier operates in the amplification phase to transfer the charge of the trough voltage to the first feedback capacitor and the charge of the peak voltage to the second feedback capacitor. Furthermore, based on the capacitance ratio between the first sampling capacitor and the first feedback capacitor, and the capacitance ratio between the second sampling capacitor and the second feedback capacitor, signal gain is performed to output the target signal from the first output terminal and the second output terminal.

9. The ultrasonic fingerprint reading circuit according to claim 8, characterized in that, The sampling module further includes: A differential-to-analog converter includes a third output terminal and a fourth output terminal. The third output terminal is used to output a positive differential voltage to input a second reference voltage to the first sampling capacitor in the amplified phase. The fourth output terminal is used to output a reverse differential voltage to input a third reference voltage to the second sampling capacitor in the amplified phase.

10. The ultrasonic fingerprint reading circuit according to claim 1, characterized in that, Also includes: The conversion module is configured to convert the target signal into a digital fingerprint feature signal.

11. The ultrasonic fingerprint reading circuit according to claim 1, characterized in that, The piezoelectric transducer also includes: A piezoelectric electrode plate and a piezoelectric layer disposed between the piezoelectric electrode plate and the pixel electrode plate.

12. An ultrasonic fingerprint chip, characterized in that, include: The ultrasonic fingerprint reading circuit as described in any one of claims 1 to 11.

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