Group unpacking hardware implementation method for CHI protocol inter-core transmission

Abstract

The invention discloses a group unpacking hardware implementation method for CHI protocol cross-core-particle transmission, a complete group unpacking hardware implementation method is designed, group packing hardware implementation comprises a group packing logic, an arbiter and a selection logic, and the group packing logic is composed of three stages of group unpacking units; the arbiter reads the state of the channel buffer, determines a current arbitration result and outputs the arbitration result to the selection logic; the selection logic decodes the arbitration result into selection signals, and the selection signals correspond to the first-level group of unpacking units respectively; unpacking hardware implementation comprises channel buffering, a selector and packet header analysis logic, buffering of a request channel, buffering of a response channel and buffering of a monitoring channel are divided into sub-buffering, and data of three levels of unpacking units are input into the sub-buffering; a data channel is set as one buffer, and data of the three stages of unpacking units are input at the same time. According to the method, the original CHI protocol is directly subjected to group unpacking based on the format of the CHI-C2C protocol specification, and the efficiency loss caused by secondary conversion of an intermediate layer protocol is eliminated.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of chip design, and particularly relates to a hardware implementation method for group unpacking of CHI protocol cross-chiplet transmission BACKGROUND

[0002] CHI protocol (Coherent Hub Interface) is an on-chip interconnection bus protocol promoted by ARM, which is used for high-performance CPU interconnection. The CHI protocol supports cache coherence and is used to build scalable multi-core processor systems. According to the protocol specification, the CHI protocol mainly has four channels, namely the request channel REQ channel, the response channel RSP channel, the data channel DAT channel and the monitoring channel SNP channel.

[0003] Different CPUs on a single chiplet can be directly interconnected through the native CHI protocol. When the system architecture is expanded to multi-chiplet and multi-chip coherence interconnection, due to the limitation of additional delay and physical connection, it is often necessary to first convert the CHI protocol into other protocols, and then transmit across chiplets and chips through the interface circuit of protocol adaptation. These protocols and corresponding interface circuits include PCIe (Peripheral Component Interconnect Express), UCIe (Universal Chiplet Interconnect Express), CXL (Compute Express Link) and the like.

[0004] Most of the existing solutions in the industry encapsulate these IP protocols into the CXS interface (Credited eXtensible Stream), encapsulate the CHI protocol channel transmission into the CXS format through the conversion bridge, and then transmit through the above interface circuit. After transmission, the opposite end is unpacked into different CHI channels in turn. These schemes need to convert the CHI protocol in two stages, which brings additional conversion delay overhead. In order to solve this problem, ARM promoted a new CHI-C2C (cross-chip) group packaging protocol in 2024, which is used to use a unified protocol specification and encapsulation in a variety of different underlying interfaces, and defines a group packaging format compatible with UCIe and CXL.

[0005] However, the protocol only proposes and specifies the format and requirements of group packaging and unpacking, and does not mention the specific hardware implementation method. The industry has carried out landing exploration, but often has a single structure and simple group packaging method, which cannot meet the balance of bandwidth and delay in different scenarios. Therefore, it is completely necessary to develop a hardware implementation method that can be compatible with high and low bandwidth scenarios, can automatically regulate group packaging delay, and comprehensively considers performance, area and power consumption. It is also an inevitable requirement for commercializing the CHI protocol cross-chiplet transmission. SUMMARY

[0006] The application aims to provide a CHI protocol cross-granule transmission group unpacking hardware implementation method, which designs a complete group packing and unpacking hardware implementation method to directly pack and unpack the original CHI protocol based on the format of CHI-C2C protocol specification, and eliminates the efficiency loss caused by the secondary conversion of the intermediate layer protocol.

[0007] To solve the above technical problems, the following technical solutions are adopted:

[0008] A CHI protocol cross-granule transmission group unpacking hardware implementation method, comprising group packing hardware implementation and unpacking hardware implementation.

[0009] The group packing hardware implementation comprises group packing logic, an arbitrator and selection logic. The CHI protocol channel input buffer is connected to the group packing logic. The group packing logic is composed of three-level group unpacking units. The three-level group unpacking units form a complete packet format, which is transmitted through the cross-granule output port. The arbitrator reads the state of the channel buffer, determines the current arbitration result and outputs the arbitration result to the selection logic. The selection logic decodes the arbitration result into selection signals, each of which corresponds to one of the group unpacking units.

[0010] The unpacking hardware implementation comprises channel buffer, selector and packet header analysis logic. The channel buffer divides the buffer of the request channel, the buffer of the response channel and the buffer of the monitoring channel into sub-buffers. The data of the three-level group unpacking units are input into each sub-buffer. The data channel is set to one buffer, and the data of the three-level group unpacking units are input into the buffer of the data channel at the same time.

[0011] After optimization, the three-level group unpacking units are respectively a first-level group unpacking unit, a second-level group unpacking unit and a third-level group unpacking unit. Each level comprises three group unpacking units. The channel buffer is input into the group unpacking unit. The third-level group unpacking unit is connected to the output and packet header generation logic to form a complete packet format, which is transmitted through the cross-granule output port.

[0012] After optimization, the width of the group unpacking unit is realized by macro parameter configuration, which is recorded as one Granule. The request channel, the response channel and the monitoring channel are compressed and defined as having a length less than or equal to one Granule. The length of the data channel is equal to five Granules.

[0013] Preferably, the input port of the group unpacking unit is provided with a selector, which receives a selection signal of the selection logic, selects one of the four channel buffers according to the selection signal, and inputs the corresponding result into the group unpacking unit.

[0014] Preferably, in the group packing hardware implementation, the data channel needs to be preprocessed: the buffer output port of the data channel is divided into five segments, each segment corresponding to one Granule length; the part less than one Granule length in the fifth segment is filled with 0; each segment is mapped to one of the three parts of the data channel; each data output from the data channel buffer will be split into 2 or 3 taps, output to the group packing logic through the three parts of the data channel.

[0015] Preferably, in the unpacking hardware implementation, the request channel buffer, the response channel buffer, and the monitoring channel buffer are divided into three sub-buffers, each buffer has the same depth, and the data of the three group unpacking units of the first-level group unpacking unit are input into each sub-buffer, and the three group unpacking units of the first-level group unpacking unit are denoted as Granule1 / 2 / 3.

[0016] Preferably, in the unpacking hardware implementation, Granule1 is simultaneously input into the request channel sub-buffer 1, the response channel sub-buffer 1, and the monitoring channel sub-buffer 1, Granule2 is simultaneously input into the request channel sub-buffer 2, the response channel sub-buffer 2, and the monitoring channel sub-buffer 2, and Granule3 is simultaneously input into the request channel sub-buffer 3, the response channel sub-buffer 3, and the monitoring channel sub-buffer 3.

[0017] Preferably, in the unpacking hardware implementation, the length of the data channel is equal to 5 Granules, and Granule1 / 2 / 3 can output a length of at most 3 Granules within 1 tap, and when the unpacking hardware recognizes the data channel, Granule1 / 2 / 3 of 2 consecutive taps are input into the buffer of the data channel.

[0018] Preferably, when the arbitrator arbitrates the data channel, it cannot arbitrate other channels in the same tap, and when the arbitrator arbitrates other channels, it cannot arbitrate the data channel in the same tap, the other channels being the request channel, the response channel, and the monitoring channel, and other channels can be arbitrated in the same tap.

[0019] Preferably, in the group packing hardware implementation, the flow control in different scenarios is realized by inserting in advance into the later stage in the group packing logic; wherein the later stage is the second-level group unpacking unit or the third-level group unpacking unit.

[0020] Due to the adoption of the above technical solutions, the following beneficial effects are achieved:

[0021] The application provides a high-efficiency CHI protocol cross-chiplet transmission packetizing and unpacking hardware implementation method, which greatly improves the bandwidth utilization of cross-chiplet transmission. According to different cross-chiplet transmission technologies, the best solution can be flexibly configured and selected.

[0022] Compared with the prior art

[0023] 1. The polling arbitration mechanism is realized, and the packetizing bandwidth proportion of each channel of CHI is balanced.

[0024] 2. The advanced filling packetizing mechanism is realized, and the cross-chiplet transmission efficiency in a small-bandwidth scenario is improved.

[0025] 3. The direct transmission packetizing mechanism is realized, and the transmission delay in a large-bandwidth scenario is reduced.

[0026] 4. According to the scenario flow, the dynamic conversion of the polling arbitration mechanism of the first point and the advanced filling packetizing mechanism of the second point is automatically realized.

[0027] 5. Based on the original CHI protocol, a complete packetizing and unpacking scheme is realized, which can adapt to the application layer implementation of different cross-chiplet transmission media and has strong expansibility.

[0028] 6. The hardware can be realized, and the balanced optimization ratio of power consumption, performance and area can be obtained. BRIEF DESCRIPTION OF DRAWINGS

[0029] The application will be further described below in combination with the drawings:

[0030] Figure 1 It is a block diagram of the packetizing hardware implementation method.

[0031] Figure 2 It is a block diagram of the unpacking hardware implementation method.

[0032] Figure 3 It is a schematic diagram of data channel preprocessing.

[0033] Figure 4 It is a flowchart of the first polling arbitration.

[0034] Figure 5 It is a flowchart of flow regulation.

[0035] Figure 6 It is a schematic diagram of CHI-C2C format. DETAILED DESCRIPTION

[0036] The application aims to provide a CHI protocol cross-granule transmission group unpacking hardware implementation method, and designs a complete group packing and unpacking hardware implementation method based on the format of the CHI-C2C protocol specification to pack and unpack the original CHI protocol, so as to eliminate the efficiency loss caused by the secondary conversion of the intermediate layer protocol; and designs an efficient dynamic group packing logic to optimize the group packing efficiency in a high-bandwidth scenario and optimize the group packing delay in a low-bandwidth scenario.

[0037] The technical solutions of the application will be described in detail below with specific embodiments.

[0038] A CHI protocol cross-granule transmission group unpacking hardware implementation method, the CHI protocol mainly has four channels, a request channel REQ channel, a response channel RSP channel, a data channel DAT channel and a monitoring channel SNP channel, and the application includes a group packing hardware implementation method and an unpacking hardware implementation method.

[0039] As shown in Figure 1 The group packing hardware implementation method is composed of an input buffer, a group packing logic, an arbitrator, a selection logic and a credit pool, wherein the group packing logic, the arbitrator and the selection logic are the core part of the group packing hardware implementation method; the group packing logic is mainly composed of a three-stage group unpacking pipeline, which is a first-stage group unpacking unit, a second-stage group unpacking unit and a third-stage group unpacking unit, and each stage includes three group unpacking units (Granule). The width of each group unpacking unit can be realized by macro parameter configuration, and the commonly used width selection is 160 bits. Meanwhile, the REQ channel, the SNP channel and the RSP channel are compressed and defined as having a length less than or equal to one Granule, and the DAT channel has a length equal to five Granules. The following describes a typical working process of the group packing hardware (not in sequence, but simultaneously):

[0040] 1. There is a four-to-one selector at the input port of the Granule, which selects one from the four channel buffers and inputs the corresponding result into the Granule.

[0041] 2. The arbitrator reads the states of the four channel buffers (these states include buffer validity, buffer fullness and buffer validity number), and determines the current arbitration result according to the historical arbitration result, and the arbitration result is output to the selection logic.

[0042] 3. The selection logic decodes the arbitration result into three independent selection signals, each of which corresponds to one of the group unpacking units.

[0043] 4. The four-to-one selector before each Granule receives the selection signal, selects a certain channel and inputs it into the Granule

[0044] 5. The third level group unpacking unit splices the output and the packet header generation logic to form a complete packet format and transmits it through the cross-Granule output port.

[0045] Because there are three group unpacking units at each level of the packet assembly logic, and a maximum of three Granule lengths of channels can be input at one time, the DAT channel needs to be split and input. This part of the logic is called data channel preprocessing. As shown in Figure 3 , the buffered output port of the DAT channel is split into five segments, each corresponding to one Granule length. The part less than one Granule length in the fifth segment is filled with zeros. Each segment can be mapped to one of the three parts of the data channel. Each DAT of the DAT channel input buffer output will be split into 2 taps (i.e., 2T) or 3 taps (i.e., 3T) and output to the packet assembly logic through the three parts of the data channel, as shown in Figure 1 , Figure 3 .

[0046] As shown in Figure 2 , the unpacking hardware implementation method is composed of channel buffering, selectors, and packet header analysis logic. The buffer of the request channel, the buffer of the response channel, and the buffer of the monitoring channel are all divided into three sub-buffers, each with the same depth, and input Granule 1 / 2 / 3 data, respectively. Here, Granule 1 / 2 / 3 are the three group unpacking units of the first level group unpacking unit. There are a total of nine independent buffers for the three types of channels. Granule 1 is simultaneously input to the request channel sub-buffer 1 (REQ FIFO 1), the monitoring channel sub-buffer 1 (SNP FIFO 1), and the response channel sub-buffer 1 (RSP FIFO 1). Granule 2 is simultaneously input to the request channel sub-buffer 2 (REQ FIFO 2), the monitoring channel sub-buffer 2 (SNP FIFO 2), and the response channel sub-buffer 2 (RSP FIFO 2). Granule 3 is simultaneously input to the request channel sub-buffer 3 (REQ FIFO 3), the monitoring channel sub-buffer 3 (SNP FIFO 3), and the response channel sub-buffer 3 (RSP FIFO 3). The data channel is set to one buffer, and Granule 1 / 2 / 3 is simultaneously input to the data channel buffer DATA FIFO. Because the length of the DAT channel is equal to five Granules, and a maximum of three Granule lengths can be output within one tap (i.e., 1T), when the unpacking hardware recognizes the DAT channel, it needs to input Granule 1 / 2 / 3 of two consecutive taps to the buffer of the data channel (DATA FIFO).

[0047] The arbitrator arbitrates the DAT channel and cannot arbitrate other channels, and arbitrates other channels and cannot arbitate the DAT channel. Therefore, two arbitrations are required to obtain other channels, the first judgment is whether the DAT channel or the REQ / SNP / RSP channel, and the second judgment is which of the REQ / SNP / RSP channels on the non-DAT channel. The REQ / SNP / RSP channel can be arbitrated at the same time (as long as the corresponding buffer has a valid number). The steps of one polling arbitration are described in detail as follows, as shown in Figure 4

[0048] 1. Query the valid number of each channel input buffer, execute 2;

[0049] 2. If the valid number of all channel input buffers is 0, skip this judgment, and the next judgment starts from 1, otherwise continue to execute 3;

[0050] 3. Query the arbitration polling state, execute 4;

[0051] 4. Arbitrate the DAT channel if the DAT input buffer number is not 0, otherwise execute 5;

[0052] 5. Arbitrate the REQ / SNP / RSP channel if the sum of the REQ / SNP / RSP input buffer numbers is not 0, execute 9

[0053] 6. Output the first half of the DAT channel (whether it is the first part), occupy 1T, execute 7

[0054] 7. Output the second half of the DAT channel (whether it is the second part), occupy 1T, if the complete DAT channel has not been output, execute 8, otherwise execute 1

[0055] 8. Output the last part of the DAT channel (whether it is the third part), occupy 1T, execute 1

[0056] 9. Arbitrate one REQ channel if the REQ input buffer number is not 0, execute 10;

[0057] 10. Arbitrate one RSP channel if the RSP input buffer number is not 0, execute 11;

[0058] 11. Arbitrate one SNP channel if the SNP input buffer number is not 0, execute 1;

[0059] The traffic regulation function in different scenarios is realized by inserting in advance to the second or third level group unpacking unit in the later stage of the group packing logic. The judgment steps in the low bandwidth scenario are described as follows, as shown in Figure 5 ​​

[0060] 1. The arbiter performs the first beat arbitration (as shown in Figure 4 ), and the first beat arbitration outputs the REQ / SNP / RSP channels;

[0061] 2. The first beat arbitration output channels are read from the buffer and enter the first stage of the packet disassembly unit of the packet assembly logic;

[0062] 3. The total number of REQ / SNP / RSP channels of the first beat is less than 3;

[0063] 4. The arbiter performs the second beat arbitration, and the second beat arbitration outputs the REQ / SNP / RSP channels;

[0064] 5. The first beat arbitration output channels are beaten from the first stage of the packet disassembly unit to the second stage of the packet disassembly unit of the packet assembly logic;

[0065] 6. The second beat arbitration output channels are read from the buffer and directly enter the second stage of the packet disassembly unit of the packet assembly logic, bypassing the first stage of the packet disassembly unit;

[0066] 7. Repeat steps 1-6, and cycle back and forth, so that the three Granules on the cross-chip Granule output port have as many valid channel outputs as possible.

[0067] After the above steps, in a low-bandwidth scenario (the total number of REQ / SNP / RSP channels output by arbitration is less than 3), the REQ / SNP / RSP channel input buffer directly enters the second or third stage of the packet disassembly unit, which can effectively reduce the delay. Because the three packet disassembly units of each beat across the Granule will be filled with as many valid REQ / RSP / SNP channels as possible, rather than sending empty packet disassembly units, this scheme can improve the packet assembly efficiency.

[0068] Figure 4 the first polling arbitration step, and Figure 5 the traffic regulation function described above are parallel (simultaneous).

[0069] In this method, the CHI-C2C format is referenced and used for packet disassembly as shown in Figure 6 , the total length is 256 bytes, and there are 2 bytes at the beginning and end of each 64 bytes to form a packet header, and the remaining part is three consecutive packet disassembly units, each of which is 20 bytes (160 bits). The packet header is used to identify the channel type in the packet disassembly unit. In this method, 64 bytes are generated every 1 beat or 2 beats, and the 64-byte length corresponds to a row in Figure 6 . The REQ, RSP, SNP, and DAT channels can be filled in any packet disassembly unit.

[0070] The above merely illustrates the specific embodiments of the present application, but the technical features of the present application are not limited thereto. Any simple change, equivalent replacement or modification, etc. made on the basis of the present application to solve the basically same technical problem and realize the basically same technical effect shall be covered in the protection scope of the present application.

Claims

1. A hardware implementation method for group unpacking in CHI protocol inter-chip transmission, characterized in that: The packet assembling hardware implementation and the packet disassembling hardware implementation are included; The packet assembling hardware implementation includes packet assembling logic, an arbitrator and selection logic. The input buffer of the CHI protocol channel is connected to the packet assembling logic, which is composed of three-level group disassembling units. The three-level group disassembling units form a complete packet format and are transmitted through the cross-granule output port. The arbitrator reads the state of the channel buffer, determines the current arbitration result and outputs the arbitration result to the selection logic. The selection logic decodes the arbitration result into selection signals, each of which corresponds to one of the three-level group disassembling units. The packet disassembling hardware implementation includes channel buffer, selector and packet header analysis logic. The channel buffer divides the buffer of the request channel, the buffer of the response channel and the buffer of the monitoring channel into sub-buffers. The data of the three-level group disassembling units are respectively input to each sub-buffer. The data channel is set to one buffer, and the data of the three-level group disassembling units are simultaneously input to the buffer of the data channel.

2. The hardware implementation method for group unpacking of CHI protocol inter-chip transmission according to claim 1, characterized in that: The three-level group disassembling units are respectively the first-level group disassembling unit, the second-level group disassembling unit and the third-level group disassembling unit. Each level includes three group disassembling units. The channel buffer is input to the group disassembling unit. The output and the packet header generation logic are spliced by the third-level group disassembling unit to form a complete packet format, which is transmitted through the cross-granule output port.

3. The method of claim 2, wherein the CHI protocol cross-core packet transmission is implemented by a group unpack hardware. The width of the group disassembling unit is realized by macro parameter configuration, which is recorded as one Granule. The request channel, the response channel and the monitoring channel are compressed and defined as having a length less than or equal to one Granule. The length of the data channel is equal to five Granules.

4. The method of claim 2, wherein the CHI protocol cross-core packet transmission is implemented by a group unpack hardware. The input port of the group disassembling unit is provided with a selector. The selector receives the selection signal of the selection logic and selects one of the four channel buffers according to the selection signal. The corresponding result is input to the group disassembling unit.

5. The method of claim 2, wherein the CHI protocol cross-core packet transmission is implemented by a group unpack hardware. In the packet assembling hardware implementation, the data channel needs to be preprocessed. The buffer output port of the data channel is divided into five segments, each of which corresponds to one Granule length. The fifth segment is filled with 0 if the length is less than one Granule. Each segment is mapped to one of the three parts of the data channel. Each data output by the data channel buffer will be split into two or three taps and output to the packet assembling logic through the three parts of the data channel.

6. The method of claim 2, wherein the CHI protocol cross-core packet transmission is implemented by a group unpack hardware. In the packet disassembling hardware implementation, the request channel buffer, the response channel buffer and the monitoring channel buffer are divided into three sub-buffers. The depth of each buffer is the same. The data of the three group disassembling units of the first-level group disassembling unit are respectively input to each sub-buffer. The three group disassembling units of the first-level group disassembling unit are recorded as Granule1 / 2 / 3.

7. The method of claim 6, wherein the CHI protocol cross-core packet transmission is implemented by a group unpack hardware. In the packet disassembling hardware implementation, Granule1 is simultaneously input to the request channel sub-buffer 1, the response channel sub-buffer 1 and the monitoring channel sub-buffer 1. Granule2 is simultaneously input to the request channel sub-buffer 2, the response channel sub-buffer 2 and the monitoring channel sub-buffer 2. Granule3 is simultaneously input to the request channel sub-buffer 3, the response channel sub-buffer 3 and the monitoring channel sub-buffer 3.

8. The method of claim 6, wherein the CHI protocol cross-core packet transmission is implemented by a group unpack hardware. In the unpacking hardware implementation, the length of the data channel is equal to 5 Granules, and Granules 1 / 2 / 3 can output a length of 3 Granules at most in 1 beat, and when the unpacking hardware identifies the data channel, Granules 1 / 2 / 3 in 2 continuous beats are input to the buffer of the data channel.

9. The method of claim 1, wherein the CHI protocol cross-core packet transmission is implemented by a group unpack hardware. When the arbitrator arbitrates the data channel, the same beat cannot arbitrate other channels, and when the arbitrator arbitrates other channels, the same beat cannot arbitrate the data channel, the other channels being the request channel, the response channel and the monitoring channel, and other channels can be arbitrated by the same beat.

10. The method of claim 2, wherein the CHI protocol cross-core packet transmission is implemented by a group unpack hardware. In the packing hardware implementation, by inserting in advance into the later stage in the packing logic, traffic regulation in different scenarios is realized, and the later stage is the second-stage group unpacking unit or the third-stage group unpacking unit.

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