Distributed high-precision time synchronization device based on microwave bidirectional ranging and time division multiple access

Abstract

The invention discloses a distributed high-precision time synchronization device based on microwave bidirectional ranging and time division multiple access. The distributed high-precision time synchronization device comprises a plurality of node units with completely same hardware structures; wherein one node unit is configured as a master node through software, and the rest are slave nodes; wherein the node unit adopts a multi-node networking mode, and the method comprises the following steps: each slave node carries out bidirectional distance measurement with a master node in a network; through fusion processing of pairwise measurement data between the master node and the slave node, the device collaboratively solves unified global time. According to the invention, high-precision time synchronization of a distributed network is realized through node units with consistent hardware structures and master-slave software configuration in combination with microwave two-way distance measurement and time division multiple access technologies. The device effectively overcomes the limitation of dependence on satellite signals and wired deployment in the prior art, eliminates clock error by using bidirectional measurement, and achieves nanosecond synchronization precision in a wireless environment.

Description

Technical Field

[0001] This invention relates to the fields of wireless communication and time and frequency technology, and in particular to a distributed high-precision time synchronization device based on microwave bidirectional ranging and time division multiple access. Background Technology

[0002] In distributed systems, such as distributed coherent radar, wireless sensor networks, and scientific experimental facilities, the various dispersed nodes need to maintain extremely high-precision time synchronization. Traditional time synchronization technologies, such as GPS time synchronization, suffer from problems such as reliance on satellite signals, susceptibility to interference, and inability to be used indoors or underground; while wired time transmission has disadvantages such as high deployment costs and poor flexibility.

[0003] Existing wireless time synchronization technologies are susceptible to link asymmetry and latency jitter in complex wireless environments, making it difficult to achieve nanosecond-level synchronization accuracy. While microwave bidirectional time comparison technology can achieve high accuracy, the traditional point-to-point mode is difficult to directly extend to multi-point networking applications. Furthermore, in dynamic networking environments, achieving rapid signal acquisition, tracking, and measurement remains a technical challenge.

[0004] Therefore, there is an urgent need for a wireless time synchronization device that can support multi-point networking, rapid self-organization, and nanosecond-level synchronization accuracy. Summary of the Invention

[0005] The present invention aims to overcome the shortcomings of the prior art and provide a device that supports multi-point networking, is flexible in deployment, and can achieve nanosecond-level high-precision time synchronization in a wireless environment.

[0006] To achieve the above objectives, the present invention provides a distributed high-precision time synchronization device based on microwave bidirectional ranging and time division multiple access, comprising: several node units with identical hardware structures; one node unit is configured as a master node through software, and the rest are slave nodes;

[0007] The node unit adopts a multi-node networking approach, including: each slave node performs bidirectional ranging with the master node in the network; by fusing the pairwise measurement data between the master and slave nodes, the device collaboratively calculates a unified global time.

[0008] Preferably, during the networking process, each slave node and master node is equipped with a transmitter and a receiver; each slave node and master node receives each other's signals and tracks them using pseudocode and carrier phase; each slave node and master node obtains relative pseudorange, eliminates clock error through bidirectional ranging, and realizes inter-station ranging, time synchronization, and data interaction.

[0009] Preferably, each node unit includes an RF transceiver module and a baseband signal processing module;

[0010] The radio frequency transceiver module uses the AD9361 chip as the main chip;

[0011] The baseband signal processing module uses a SOC chip and includes a PL section and a PS section.

[0012] Preferably, in the RF transceiver module, the RF transceiver board receives an external 20MHz clock input through the SMA interface as the working clock source for each module inside the AD9361 chip. The 20MHz clock is used to generate the clock frequency required by each internal module through the BPLL.

[0013] Preferably, in the baseband signal processing module, the PL section receives the digital intermediate frequency signal, completes carrier and pseudocode signal acquisition, carrier and pseudocode signal tracking, despreading, demodulation, measurement and output of 1PPS signal; the PL section also implements the spread spectrum and modulation functions of the baseband signal of the transmitting section, generates local spread spectrum code and digital intermediate frequency, and finally outputs digital modulation signal.

[0014] The PS section contains two ARM9 CPUs. The PS interacts with the PL via the AXI bus. The PS controls and configures the baseband PL section, and performs flow control, function scheduling, information transmission and reception, and parsing functions. The PS section also implements bidirectional ranging and interface data protocol packaging functions.

[0015] The preferred bidirectional ranging procedure includes:

[0016] The master node measures the arrival time of the reverse ranging signal sent by the slave node to obtain the first time delay measurement value T1;

[0017] The second delay measurement value T2 is obtained by measuring the arrival time of the forward ranging signal sent by the master node from the slave node.

[0018] Based on T1 and T2, and combined with the pre-calibrated master node transmitting device delay t1, master node receiving device delay r1, slave node transmitting device delay t2, and slave node receiving device delay r2, calculate the clock difference between the master node and the slave node.

[0019] Preferably, calculate clock bias The process includes:

[0020]

[0021] Among them, t 12 t represents the total device delay incurred during the transmission of a signal from the autonomous node to the slave node; 21 This represents the total device delay that occurs as the signal travels from the node to the master node.

[0022] Preferably, the PL section adopts QPSK modulation, defining the I branch as the measurement branch for transmitting ranging and time comparison data, and defining the Q branch as the data transmission branch for transmitting user data; within the time slot, the signals of the measurement branch and the data transmission branch are transmitted simultaneously.

[0023] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0024] This invention achieves high-precision time synchronization in a distributed network by combining consistent hardware node units and master-slave software configuration with microwave bidirectional ranging and time-division multiple access technologies. This device effectively overcomes the limitations of traditional technologies, such as dependence on satellite signals and wired deployment. It eliminates clock errors through bidirectional measurement and achieves nanosecond-level synchronization accuracy in a wireless environment. Furthermore, its integrated channel design allows time synchronization, distance measurement, and data communication to be performed in parallel, offering significant advantages such as flexible networking, strong anti-interference capabilities, convenient deployment, and good scalability. Attached Figure Description

[0025] To more clearly illustrate the technical solution of the present invention, the drawings used in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the node unit structure according to an embodiment of the present invention;

[0027] Figure 2 This is a block diagram of the baseband signal processing hardware circuit according to an embodiment of the present invention;

[0028] Figure 3 This is a schematic diagram of the time slot frame structure according to an embodiment of the present invention;

[0029] Figure 4 This is a schematic diagram illustrating the bidirectional single-way pseudorange measurement principle of an embodiment of the present invention;

[0030] Figure 5 This is a schematic diagram of the system networking according to an embodiment of the present invention;

[0031] Figure 6 This is a block diagram of the baseband signal processing design according to an embodiment of the present invention;

[0032] Figure 7 This is a schematic diagram of the overall design architecture of the baseband processing software according to an embodiment of the present invention;

[0033] Figure 8 This is a block diagram illustrating the demodulation processing unit according to an embodiment of the present invention.

[0034] Figure 9This is a schematic diagram illustrating the digital down-conversion principle of an embodiment of the present invention;

[0035] Figure 10 This is a schematic diagram of the local carrier NCO unit according to an embodiment of the present invention;

[0036] Figure 11 This is a schematic representation of local carrier lookup in an embodiment of the present invention;

[0037] Figure 12 This is a schematic diagram of the fast acquisition module in an embodiment of the present invention;

[0038] Figure 13 This is a schematic diagram of the scheduling module flow according to an embodiment of the present invention;

[0039] Figure 14 This is a block diagram illustrating the basic principle of the tracking loop in an embodiment of the present invention.

[0040] Figure 15 This is a schematic diagram illustrating the time slot division time and number of bits in an embodiment of the present invention;

[0041] Figure 16 This is a schematic diagram illustrating the working principle of the data transmission tributary transmitter in an embodiment of the present invention.

[0042] Figure 17 This is a schematic diagram of the baseband data processing flow according to an embodiment of the present invention;

[0043] Figure 18 This is a block diagram of the time management module implementation in an embodiment of the present invention;

[0044] Figure 19 This is a schematic diagram of communication signal types according to an embodiment of the present invention. Detailed Implementation

[0045] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0046] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0047] This embodiment provides a distributed high-precision time synchronization device based on microwave bidirectional ranging and time division multiple access, which includes at least two or more node units with identical hardware structures to form a network; one of the node units is configured as the master node through software, and the rest are slave nodes.

[0048] The multi-node network's core mechanism involves each slave node exchanging high-precision, bidirectional time information and measuring clock deviation with the master node in the network. By fusing and processing the pairwise measurement data between master and slave nodes, the system can collaboratively calculate a unified global time, thereby achieving stable and reliable high-precision synchronization across the entire network, far exceeding point-to-point synchronization.

[0049] During network construction, both the master and slave nodes are equipped with transmitters and receivers, receiving each other's signals. Through pseudo-code and carrier phase tracking, the master and slave nodes obtain relative pseudoranges. Clock errors are eliminated through bidirectional measurement, enabling inter-station ranging, time synchronization, and data exchange. This embodiment uses an ASSAC module structure (connector model LRMS2-A135G2-B72T12R-T2 to the device backplane), with dimensions of 160mm × 233.4mm × 24mm (tolerances are 0 to -0.2mm). A schematic diagram of this embodiment is shown below. Figure 1 .

[0050] Each node unit includes an RF transceiver module and a baseband signal processing module. The baseband signal processing module is further divided into the PL (Power Line Transceiver) section and the PS (Power Switch) section of the SOC chip. The hardware circuit block diagram of the baseband signal processing is shown below. Figure 2 .

[0051] The RF transceiver module uses the AD9361 chip as the main chip. The AD9361 outputs two 12-bit digital intermediate frequency (IF) signals (I and Q) to the PL (Programmable Logic Controller) terminal of the SOC chip as IF signal inputs. Simultaneously, it outputs one clock signal to the FPGA chip (PL section) as a synchronization clock for digital signal processing. The AD9361 receives the two 12-bit IF signals (I and Q) from the PL section as the transmitted IF signals. The AD9361 receives configuration data from the PL section via the SPI interface.

[0052] The PL section: The core processing chip for the baseband signal is a System-on-a-Chip (SoC). In this embodiment, the Xilinx Zynq7Z045 is used, which has abundant logic resources and can complete all programmable logic work for baseband signal processing. The PL section receives the digital intermediate frequency (IF) signal, completes carrier and pseudocode signal acquisition, carrier and pseudocode signal tracking, despreading, demodulation, measurement, and outputs 1PPS signals. The PL section also implements the spread spectrum and modulation functions of the baseband signal from the transmitting section, generates local spreading codes and digital IF, and finally outputs a digital modulated signal.

[0053] PS Section: The SOC chip includes a PS section, which contains two ARM9 CPUs. The PS interacts with the PL via the AXI bus. The PS performs control and configuration operations on the baseband PL section, realizing functions such as flow control, function scheduling, information transmission and reception, and parsing. At the same time, the PS section also implements bidirectional ranging algorithms and interface data protocol packaging functions.

[0054] The wireless microwave links between nodes operate in Time Division Duplex (TDD) mode. The master and slave nodes are identical devices with identical hardware and software, switching between master and slave modes via command configuration to achieve interchangeability. The network employs a hybrid access method combining TDMA (Time Division Multiple Access) and CDMA (Code Division Multiple Access). Each device is configured with a unique ID number corresponding to its transmitted pseudo-random code Cx (x=1,2,3…n) for CDMA. Within the TDMA frame structure, CDMA code division is used to differentiate signals within each time slot to avoid interference.

[0055] The operating frequency band for the bidirectional wireless link can be selected from L, S, C, etc. Since a time-division multiplexing mode is used, transmission and reception operate on the same frequency. Based on link budget considerations, the most important principle in frequency band selection is to avoid interference from other frequency bands and to avoid interfering with other devices. Through environmental monitoring and comprehensive consideration, the 1.98 GHz frequency band with a bandwidth of 20 MHz was selected.

[0056] Based on the requirements, in addition to time synchronization, data communication is also required between nodes. Therefore, the microwave link in this embodiment adopts an integrated channel design for data transmission, ranging, and time synchronization. Bidirectional ranging, time comparison, and data transmission communication are multiplexed using code division multiple access and QPSK modulation. Specifically, the Q-branch is defined as the data transmission branch, used for user data communication transmission; the I-branch is defined as the measurement branch, used for ranging and time comparison, and can also transmit internal measurement data, such as time information and bidirectional measurement information.

[0057] In the QPSK modulation scheme, the Q branch is the data transmission branch, and the I branch is the measurement branch. To reduce the bit error rate of the communication link, improve the coding efficiency of the data transmission branch, and reduce the amount of encoded data, the data transmission branch data first undergoes CRC check, then RS(127,149) encoding, and finally block interleaving. This encoding method provides strong real-time error correction capability, introduces a certain coding gain, and prevents continuous burst errors from affecting the decoding at the receiver. The measurement branch, due to its high spreading gain, does not employ error correction coding; error detection is performed solely through CRC check.

[0058] The design of the time-slot frame structure, such as Figure 3The length of each time slot is tentatively set at 5ms, and the time slot period of N time slots is 5*N milliseconds. There are pre-protection time slots and post-protection time slots between consecutive time slots, and the pre-protection time slots are tentatively set at 100us.

[0059] The frame structure within each time slot includes a measurement branch and a data transmission branch. The measurement branch frame mainly includes a frame header, time information, bidirectional comparison data (service segment), status information, and other data (data segment). The data transmission branch mainly transmits user data. The tentative frame period is designed to be 0.38ms. Each time slot contains 10 frames. Each all-in-one device is allocated one time slot to transmit signals, and the remaining time slots are used to receive signals from other nodes.

[0060] Microwave dual one-way pseudorange measurement (DOWR) is a widely used ranging and time comparison method in modern aerospace telemetry and control. In this method, two nodes each install a transmitter and a receiver, receiving signals from each other. Through pseudocode and carrier phase tracking, each node obtains its relative pseudorange. Bidirectional measurement eliminates clock errors, enabling inter-station ranging, time synchronization, and data exchange. The principle of dual one-way pseudorange measurement is as follows: Figure 4 .

[0061] The master node (host) and slave nodes (slave devices) transmit forward ranging signals and reverse ranging signals respectively, using their own clocks as a reference. Due to the time discrepancy between the two sides, there is a clock difference between the ranging signal frames transmitted by both sides. At the master node, the time delay T1 between the synchronization of the forward ranging signal frame and the frame synchronization of the reverse ranging signal can be obtained by capturing and tracking the reverse ranging signal. This time delay includes not only the electromagnetic wave propagation delay τ between the slave and master antennas, but also the slave's transmitting equipment delay t2, the master's receiving equipment delay r1, and the clock difference between the slave and master. The relationship is as follows:

[0062] (1)

[0063] Similarly, the slave device can measure the time delay, and its time relationship is as follows:

[0064] (2)

[0065] Where r2 represents the receiving device delay of the slave device.

[0066] The actual distance D and clock difference between the master and slave can be obtained from the above two equations:

[0067] (3)

[0068] (4)

[0069] set up ,but:

[0070] (5)

[0071] (6)

[0072] Among them, t 12 t represents the total device delay incurred during the transmission of a signal from the autonomous node to the slave node; 21 This represents the total device delay that occurs during the transmission of the signal from the node to the master node; c represents the speed of light.

[0073] During operation, the measurement and data exchange processes of the master and slave are exactly the same. Taking the slave as an example, the pseudorange measurement value at the moment of receiving the transmission frame header from the master (actually calculated using the local delay measurement value T2 measured by the slave) is substituted into equation (1), and the pseudorange data within the service segment of the received master transmission frame (calculated using the local delay measurement value T1 measured by the master) is substituted into equation (2). Equations (5) and (6) give the formulas for calculating the distance between the master and slave and the clock difference between the master and slave.

[0074] During measurement, T1 and T2 can be extracted from the code tracking loops of the master and slave devices respectively and embedded into the service segment data area of ​​the transmission frame, and sent to each other via a bidirectional link; the one-way propagation delay t 12 and t 21 Accurate distance and time comparison measurements can be obtained through calibration, and then the local clock and local 1PPS pulse output time can be corrected using bidirectional single-way pseudorange measurements.

[0075] Example 2

[0076] The structure and operation of the device of the present invention will be described in detail below with reference to this embodiment and the accompanying drawings. The device of this embodiment includes several node units with identical hardware structures; one node unit is configured as a master node via software, and the rest are slave nodes; the node units adopt a multi-node networking method, such as... Figure 5 As shown. Each node unit includes an RF transceiver module and a baseband signal processing module.

[0077] The RF transceiver module uses an AD9361 as the main chip. The AD9361 supports two RF inputs and two RF outputs, enabling two-transmit and two-receive functionality. The AD9361 receives two RF signals, amplifies them, performs AGC control, generates a local oscillator signal, down-converts the signal via a mixer, applies a low-pass filter, performs ADC conversion, and outputs two digital intermediate frequency (IF) signals (I and Q channels). The RF transceiver board receives an external 20MHz clock input via an SMA interface, serving as the operating clock source for the various modules within the AD9361 transceiver. This 20MHz clock is used by a BPLL to generate the required clock frequencies for each internal module, ensuring stable and normal operation. The AD9361 supports two RF transmissions, baseband up-conversion and IF up-conversion, baseband signal filtering and RF signal filtering, transmit attenuation control, and transmit local oscillator frequency configuration.

[0078] The baseband signal processing module uses a Xilinx Zynq7 series SOC chip to implement the PL and PS functions. Peripherals also include storage and some interfaces. The digital processing circuit design adopts a mature SOC chip design scheme, which has been verified through actual testing in previous projects. The hardware design of the digital processing section is the core of the hardware design of this research scheme and serves as the carrier for the software operation. To reduce the chip layout area, this embodiment uses a Xilinx ZYNQ7 series SOC chip, integrating the CPU and FPGA into a single chip, specifically model xc7z045ffg676-2L. This chip includes both PS and PL components, and the design block diagram is shown below. Figure 6 .

[0079] The DDR chip used is LPDDR2, specifically the MT42L32M32D2AC-25. This chip supports a 400MHz clock speed, a 32-bit data bus, and 128MB of storage space, fully meeting the requirements of this solution. The Flash chip used is the N25Q256A13EF840E, which is used to store firmware code and configuration parameters.

[0080] All software functions for baseband signal processing are implemented on the PL+PS SOC chip platform, with data exchange between the PS and PL via the AXI bus. Specifically, modulation processing, demodulation processing, timing management, and interface processing are completed on the PL side; ranging calculation, communication protocol framing, and main software flow control are completed on the PS side. The overall architecture of the baseband processing software is as follows: Figure 7 .

[0081] (1) Demodulation processing unit

[0082] The PL section includes a demodulation processing unit, which is responsible for acquiring, tracking, synchronizing, and extracting messages from digital intermediate frequency signals. In time-division mode, it also performs functions such as time slot division and adjustment. A detailed block diagram is shown below. Figure 8 .

[0083] (2) Digital downconversion

[0084] The digital intermediate frequency (IF) design in the PL section uses an IQ complex signal, therefore employing a complex-pair quadrature down-conversion algorithm. This algorithm requires four multipliers and two adders to achieve its function. The baseband signal after complex-pair digital down-conversion contains no new frequency components other than Doppler. Its principle is as follows: Figure 9 .

[0085] (3) Local carrier generation

[0086] The PL section also includes a local carrier NCO unit, used to generate local sine (-sin) and cosine (cos) signals, implemented using a DDS method, the principle of which is as follows: Figure 10 .

[0087] The driving clock is consistent with the intermediate frequency data sampling clock, the input clock is 60MHz, the accumulator bit is 32 bits, the frequency resolution is 0.014Hz, and the local carrier waveform lookup table requires at least 3 bits of quantization to generate cosine and -sin.

[0088] a) The quantization period of cos is (-1 1 2 2 1 -1 -2 -2);

[0089] b) The quantization period of -sin is (2 2 1 -1 -2 -2 -1 1).

[0090] The high 3 bits of the accumulator are used as the address of the lookup table to obtain the local cosine and -sin values ​​for different phases. The lookup table is as follows: Figure 11 .

[0091] Since a digital intermediate frequency (IF) is used, neither D / A conversion nor LPF (Local Frequency Filter) is required. The frequency control word is 32 bits, consistent with the accumulator bit width. The frequency control word is obtained by adding the acquisition frequency control word and the carrier tracking loop output adjustment control word. The acquisition frequency control word is configured by the PS software through a write operation, and the adjustment control word is output from the carrier tracking loop.

[0092] (4) Local pseudocode generation

[0093] The local pseudocode has a code rate of 10.24MHz, a code length of 128 chips, and a code period of 12.5µs. The local pseudocode is generated from the codes of the G1 branch and the G2 branch, or by truncating them. The codes of the G1 and G2 branches are both generated by a 10-stage linear shift register.

[0094] When transitioning from capture to tracking, a code phase delay needs to be set. This delay is written by the PS (Power Sequencer) to determine the local pseudocode integration reset time. The code phase delay of the local pseudocode generation module is updated when the DUMP signal is valid, and this delay will be reflected in the next code cycle. To facilitate adjustment of the code correlator spacing, the spacing is adjusted via the sampling clock, with adjustments in units of one sampling clock cycle, a minimum of one sampling clock cycle, and a maximum of five sampling clock cycles. When the integration reset DUMP signal is valid, the value of the half-chip counter is cleared. When the 2x code clock pulse is valid, the half-chip counter is incremented by 1. At the TIC (Time Injection) moment, the half-chip counter is latched.

[0095] (5) Fast capture algorithm

[0096] Traditional acquisition methods utilize the sliding correlation algorithm, which involves serially searching for the code phase and Doppler frequency. This method is very slow and unsuitable for time-division multiplexing (TDM) signal acquisition. Currently, a faster PMF+FFT fast acquisition algorithm leverages the short-time partially matched characteristics of the pseudocode. It searches for the pseudocode phase using a massively parallel correlator, performs spectral analysis on the partially matched filter results using a small-point FFT, finds the maximum peak value, and compares it with a threshold to determine the captured pseudocode phase and carrier Doppler frequency.

[0097] The PL section includes a fast acquisition module, which is the core of the timing module. It uses a PMF+FFT fast acquisition algorithm, and the process is as follows: Figure 12 The time synchronization module is a hybrid module with the PL (Programmable Logic Controller) hardware circuitry at its core and controlled by the PS (Power Switch) software. The PL hardware circuitry receives clock difference data from the PS software; converts the clock difference into specific delay parameters (integer clock cycles and fractional cycles); uses a high-frequency clock (e.g., 200MHz) counter to achieve coarse delay (integer clock cycles); controls an external precision delay chip to achieve fine delay (11ps increments); and finally adjusts the output time of the local second pulse. The ARM processor in the PS section calculates the clock difference to be adjusted and sends this result to the time synchronization module on the PL side via the AXI bus for execution.

[0098] The PS section includes a scheduling module, which controls the fast acquisition module. Its simplified process is as follows: Figure 13 When the scheduling module is idle, it checks the working status of the fast acquisition module in the accumulated interrupt. If the fast acquisition module is idle, the scheduling module can start the fast acquisition operation.

[0099] 1) The scheduling module resets the fast acquisition module;

[0100] 2) The scheduling module configures the working parameters and mode of the fast capture module and starts the fast capture process;

[0101] 3) The scheduling module queries the fast acquisition status register in the accumulating interrupt to monitor the fast acquisition process;

[0102] 4) The scheduling module reads the results returned by the fast capture, performs the conversion, and then configures them into the tracking channel.

[0103] (6) Loop tracking algorithm

[0104] After acquisition, the carrier residual is within the carrier loop pulling range, and the pseudocode phase difference is within half a chip. However, it cannot yet track changes in the carrier Doppler frequency and phase, nor can it track changes in the upper code phase. Therefore, the role of loop tracking is to refine the acquired result and dynamically track changes in the input signal. Receivers typically have two tracking loops, and the basic principle block diagram is as follows: Figure 14 One is the carrier tracking loop, and the other is the code tracking loop. They track simultaneously, complement each other, and neither can be dispensed with. The carrier tracking loop tracks the carrier frequency and phase changes of the input signal, while the code tracking loop tracks the code phase changes of the input signal.

[0105] (7) Carrier tracking loop design

[0106] In this embodiment, the code period is 12.5us, and one pseudo-code period modulates 1 bit of data. Therefore, the carrier loop update rate is at least 80KHz. With such a high loop update rate, there is no need to consider the pull of the FLL-assisted PLL. A second-order phase-locked loop can be used alone to achieve carrier loop tracking under high dynamic conditions.

[0107] The bandwidth of the PLL's traction phase is selected based on the frequency resolution of the fast acquisition, with a bandwidth of 500Hz, and the loop parameters are calculated. Since the loop update rate is fast and the loop bandwidth is large, a second-order loop is sufficient to meet the dynamic performance requirements.

[0108] (8) Pseudocode tracking loop design

[0109] To improve the dynamic performance of the timing module, the code discriminator adopts a normalized lead envelope minus lag envelope method. The correlation interval is set by software and calculated using the formula (EL) / (E+L), where E and L are the lead envelope and lag envelope, respectively. In the logic module, the calculation follows this process:

[0110] Calculate the square of IE sequentially, then calculate the square of QE;

[0111] Calculate the sum of the squares of the two, and then calculate the square root to obtain the leading envelope E;

[0112] Calculate the square of IL sequentially, and then calculate the square of QL.

[0113] Calculate the sum of the squares of the two, and then calculate the square root to obtain the leading envelope L;

[0114] Calculate EL and E+L, and magnify EL by a factor of N, where N is a power of 2. Determine the value of N based on the required calculation precision; here, we tentatively set N=12.

[0115] Calculate (EL) / (E+L) using a divider.

[0116] Output the results and status signals and save them.

[0117] Code tracking typically employs a delay-locked loop. The design takes into account carrier assistance to reduce code loop dynamics, so a second-order code loop is sufficient to meet the dynamic requirements.

[0118] (9) Carrier ring auxiliary code ring

[0119] To eliminate the dynamic stress of the code loop in the line-of-sight direction, a carrier loop-assisted code loop method must be used to improve the robustness of the code loop. The principle of the carrier loop-assisted code tracking loop is to divide the Doppler frequency control word on the carrier by the carrier-assisted code loop coefficient to obtain an auxiliary value. This auxiliary value is directly added to the output of the code loop filter, and then directly used as the output of the code loop filter of the correlation channel. This output is then added to the frequency control word of the code NCO set during acquisition, serving as the closed-loop frequency control word of the code tracking NCO.

[0120] In time-division mode, the rapid convergence of the code ring and carrier ring is the key to the design. The code tracking ring and carrier tracking ring designed for this scheme are applied in actual work, and the discriminator output is acquired by online acquisition tools.

[0121] (10) Time slot division module

[0122] This module consists of a PL (Programming Logic) section and a PS (Power Switching) section. The PL section is responsible for the low-level, high-precision time slot timing and switching. The PS section is responsible for the high-level, overall TDMA frame structure management and scheduling.

[0123] When the code period is 12.5us, consider the number of nodes that can accommodate a 5ms time slot period:

[0124] 1) Since the 100µs guard time slots before and after have been removed, the total number of bits within 5ms is 384 bits;

[0125] 2) Within 5ms, the main information includes capture, tracking, synchronization, data, and verification.

[0126] The specific time and bit number divisions are as follows: Figure 15 As shown.

[0127] The allocated time for measurement data is 3500µs, and the I-branch can transmit 280 bits. Each node requires 32 bits of measurement data, so analysis shows that this can satisfy the network transmission needs of 8 nodes. If the time per bit is further reduced to 6.25µs, then at least 16 nodes can transmit measurements to each other. This requirement uses a 4-node network, so this design uses a code period of 12.5µs.

[0128] (11) Modulation processing unit

[0129] The PL section also includes a modulation processing unit. This unit uses QPSK modulation, with separate modulation for the I and Q branches. The I branch is used for microwave bidirectional measurement to achieve time synchronization, while the Q branch is used for data transmission communication. This includes baseband data processing, Q branch transmit pseudocode generation, spread spectrum modulation, and then alignment with the local transmit time of the I branch (i.e., the local second pulse time) to achieve QPSK modulation. The signal is then up-converted and transmitted via the RF chip. The working principle of the data transmission branch transmitter is as follows: Figure 16 .

[0130] The baseband data processing flow is as follows Figure 17 First, the host computer software sends user data to the PS software via serial port or Ethernet port. The data volume per second does not exceed 2000K bits, so the data volume of a 5ms time slot is 2000 * 0.005 = 10Kbps, or 1250 bytes. If it exceeds 1250 bytes, it is transmitted in two parts. The PS software adds a frame header, frame trailer, and byte length to a data packet and writes it into the first-level transmit buffer of the PL. Before the next PPS arrives, the PL checks whether there is a complete frame of data in the first-level transmit buffer. If so, it reads out a frame of data, processes it as baseband data, and stores it in the final-level transmit buffer. When the next PPS arrives, it spreads the data along with the I-branch measurement data and the local spreading code. Finally, the baseband data is directly output to the RF chip for QPSK modulation.

[0131] The PL's processing of baseband data includes generating CRC checksums, RS error correction coding, block interleaving, storing in the final-stage transmit buffer, reading and transmitting bit by bit. At the transmitting end, the data transmitter needs to generate local spreading pseudo-code for spread spectrum modulation. The local pseudo-code generation at the modulation unit and the demodulation unit uses the same format.

[0132] (12) Time Management Module

[0133] The timing management module is a hardware-software co-implemented module. Its core is located in the PL (Plug-in) section of the core processing chip—the Xilinx Zynq 7Z045 SoC. The main execution unit is implemented as hardware logic circuits in the PL (FPGA) section of the Zynq chip. The control and computing units are controlled and managed at a higher level by the PS (Power Switch) section of the Zynq chip. This is a hardware-software co-implemented module.

[0134] The time synchronization management module primarily receives the time difference value sent by the PS software and adjusts the output delay of the second pulse (PPS) signal generated by the time difference management module, thereby achieving time synchronization between the slave station and the master station. The specific implementation block diagram is as follows: Figure 18 .

[0135] exist Figure 18 In this process, the measured time difference is converted into the number of 5ns delay clock cycles and delay parameters within 5ns. The 5ns delay is achieved by counting with a 200MHz clock. The delay within 5ns is achieved by a precision delay chip with a step accuracy of 11ps, which can achieve 512 delay steps to meet the precision time delay requirements.

[0136] This embodiment employs pseudo-code tracking measurement technology to achieve high-precision measurement. The receiving channel locally reproduces the pseudo-code of the transmitted signal and accurately tracks the frequency and phase of the pseudo-code. Accurate pseudorange measurements are obtained through observation extraction techniques such as code period counting, half-chip counting, and code NCO fractional counting. The pseudorange measurements from both directions are then combined to remove path and system errors, thereby achieving high-precision ranging and clock error calculation. This embodiment uses a 10.24MHz pseudo-code, with a chip time accuracy close to 100ns. Loop tracking can be accurate to within at least 0.005 chips, achieving a measurement accuracy of 0.5ns.

[0137] (13) Data frame structure

[0138] Two-way communication management signals are used for information exchange between the host computer and the high-precision two-way communication time synchronization device module. They employ RS232 level, full-duplex communication. There are six types of two-way communication management signals, as follows: Figure 19 The clock difference reported by the high-precision bidirectional communication time synchronization device at the slave station to the host computer at the slave station is a key parameter for achieving time synchronization between the master and slave stations, while other information is auxiliary management information.

[0139] The high-precision bidirectional communication time synchronization device reports data commands with fixed cycles, which are further divided into 1Hz and 50Hz commands. The 50Hz slave communication time synchronization unit's clock difference parameter command needs to be reported in real time with priority (i.e., the sending priority is greater than that of the 1Hz command). The host computer sends commands at irregular intervals (generally when the device is powered on and initialized, but it can also be sent at any time thereafter, but the sending frequency is not higher than 1Hz).

[0140] The working process of the device in this embodiment is as follows:

[0141] After the slave node is powered on, it first quickly captures and locks the master node signal in the receiving state to obtain preliminary time synchronization.

[0142] All nodes receive signals from other nodes in the receive time slot and perform pseudorange measurements. The measurement values ​​are exchanged via data frames.

[0143] The slave node uses bidirectional measurements to calculate the clock difference with the master node according to relevant algorithms.

[0144] The slave node utilizes the clock difference with the master node to control the precision delay management module to adjust the local clock and 1PPS output, gradually reducing and eliminating the clock difference to achieve high-precision time synchronization.

[0145] The entire process simultaneously completed distance measurement and data communication (≥2Mbps) between nodes.

[0146] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made to the technical solutions of the present invention by those skilled in the art without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.

Claims

1. A distributed high-precision time synchronization device based on microwave two-way ranging and time division multiple access, characterized in that, The application relates to a network device, comprising: a plurality of node units with the same hardware structure; wherein one node unit is configured as a master node by software, and the rest are slave nodes; wherein, the node units adopt a multi-node networking mode, comprising: each slave node performs bidirectional ranging with a master node in a network; by fusing the two-way measurement data between the master and slave nodes, the device cooperatively calculates a unified global time.

2. The distributed high-precision time synchronization device based on microwave two-way ranging and time division multiple access according to claim 1, characterized in that, In the networking process, each slave node and the master node are installed with transmitters and receivers; each slave node and the master node receive signals from each other, and perform pseudo code and carrier phase tracking; the slave node and the master node respectively obtain relative pseudo ranges, eliminate clock differences through bidirectional ranging, realize inter-station ranging, time synchronization and data interaction. 3.The distributed high-precision time synchronization device based on microwave two-way ranging and time division multiple access of claim 1, wherein, Each node unit comprises a radio frequency transceiver module and a baseband signal processing module. The radio frequency transceiver module adopts an AD9361 chip as a main chip. The baseband signal processing module uses an SOC chip, comprising a PL part and a PS part.

4. The distributed high-precision time synchronization device based on microwave two-way ranging and time division multiple access according to claim 3, characterized in that, In the radio frequency transceiver module, the radio frequency transceiver board card receives external 20MHz clock input through an SMA interface, serving as a working clock source of each module in the AD9361 chip; the 20MHz clock generates clock frequencies required by each module through a BPLL.

5. The distributed high-precision time synchronization device based on microwave two-way ranging and time division multiple access according to claim 3, characterized in that, In the baseband signal processing module, the PL part receives a digital intermediate frequency signal, completes carrier and pseudo code signal capture, carrier and pseudo code signal tracking, despreading, demodulation, measurement and outputs a 1PPS signal; the PL part also realizes spreading and modulation functions of the baseband signal of the transmitting part, generates a local spreading code and a digital intermediate frequency, and finally outputs a digital modulation signal; The PS part contains two ARM9 CPUs, the PS exchanges information with the PL through an AXI bus, the PS completes control and configuration operations on the baseband PL part, realizes process control, function scheduling, information transceiving and analysis functions, and simultaneously, the PS part also realizes bidirectional ranging and interface data protocol packaging functions.

6. The distributed high-precision time synchronization device based on microwave two-way ranging and time division multiple access according to claim 5, characterized in that, The process of bidirectional ranging comprises: the master node measures the arrival time of a reverse ranging signal sent by the slave node, and obtains a first time delay measurement value T1; the slave node measures the arrival time of a forward ranging signal sent by the master node, and obtains a second time delay measurement value T2; according to T1 and T2, in combination with a pre-calibrated master node transmitting device time delay t1, a master node receiving device time delay r1, a slave node transmitting device time delay t2 and a slave node receiving device time delay r2, the clock difference between the master node and the slave node is calculated.

7. The distributed high-precision time synchronization device based on microwave two-way ranging and time division multiple access according to claim 6, characterized in that, Computing a clock difference The flow includes: where t 12 represents the total device delay incurred in the transmission of the signal from the master node to the slave node; t 21 represents the total device delay incurred in the transmission of the signal from the slave node to the master node.

8. The distributed high-precision time synchronization device based on microwave two-way ranging and time division multiple access according to claim 3, characterized in that, The PL part adopts a QPSK modulation mode, defines an I branch as a measurement branch for transmitting ranging and time comparison data, and defines a Q branch as a data transmission branch for transmitting user data; in a time slot, the signals of the measurement branch and the data transmission branch are simultaneously transmitted.

Images