Semiconductor device and method of manufacturing the same

Abstract

This application relates to a semiconductor device and a method for manufacturing the same, comprising: a substrate, a first dielectric layer, a first gate structure, and a second gate structure. An epitaxial layer is disposed within the substrate. The first gate structure is located within the substrate below the epitaxial layer and includes a first gate, a first gate dielectric layer, and a second gate dielectric layer. The second gate dielectric layer is located between the first gate and the epitaxial layer, and the first gate dielectric layer covers the sidewalls and bottom of the first gate. The second gate structure is located on the substrate, and the orthographic projection of the second gate structure onto the substrate surface partially coincides with the orthographic projection of the first gate structure onto the substrate surface. This application reduces the leakage current of the substrate, achieves precise control of the current and voltage of the semiconductor device, thereby improving the performance of the semiconductor device, effectively reducing the noise of the semiconductor device, and extending the bandwidth of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] The fully depleted silicon-on-insulator (FD-SOI) process addresses the body leakage problem by creating a buried oxide (BOX) layer, which allows the PN junction to remain on the buried oxide layer. As the size of FD-SOI devices is further reduced, the size of the PN junction and the gate linewidth of the metal gate (MG) are also reduced accordingly.

[0003] However, as the length of the metal gate decreases, the random roughness of the gate line increases accordingly, which is enough to make the uniformity of the gate line uncontrollable. At the same time, the presence of the thin-body region can easily lead to random dopant flux (RDF) of doped atoms. For example, when the channel length is too small, electrons between the source and drain may randomly enter the channel, causing changes in the channel concentration, which in turn makes the threshold voltage Vt of the semiconductor device uncontrollable. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor device and its manufacturing method to achieve precise control of the current and voltage of the semiconductor device and reduce leakage current.

[0005] This application provides a semiconductor device, including:

[0006] A substrate, wherein an epitaxial layer is disposed therein;

[0007] A first gate structure is located within the substrate, and the first gate structure is located below the epitaxial layer;

[0008] A second gate structure is located on the substrate, and the orthographic projection of the second gate structure toward the substrate surface partially coincides with the orthographic projection of the first gate structure toward the substrate surface.

[0009] The first gate structure includes a first gate, a first gate dielectric layer, and a second gate dielectric layer. The second gate dielectric layer is located between the first gate and the epitaxial layer, and the first gate dielectric layer covers the sidewalls and bottom of the first gate.

[0010] In one embodiment, the second gate structure includes:

[0011] A third gate dielectric layer is located on the substrate;

[0012] The second gate is located on the third gate dielectric layer, and the orthogonal projection of the second gate toward the substrate partially coincides with the orthogonal projection of the first gate toward the substrate.

[0013] A gate sidewall is located on the third gate dielectric layer and covers the sidewall of the second gate.

[0014] In one embodiment, the substrate further includes:

[0015] The well region is located within the epitaxial layer and the substrate on both sides of the epitaxial layer;

[0016] A shallow trench isolation structure extends through the well region and into the substrate beneath the well region;

[0017] The source region is located within the substrate on one side of the second gate structure;

[0018] The drain region is located within the substrate on the side of the second gate structure away from the source region.

[0019] In one embodiment, the semiconductor device further includes:

[0020] A metal silicide layer is located on top of the source region, the drain region, and the second gate;

[0021] An interlayer dielectric layer is located on the substrate, and the interlayer dielectric layer covers the second gate structure and the metal silicide layer;

[0022] An electrical connector extends through the interlayer dielectric layer and is respectively connected to the source region, the drain region, and the metal silicide layer at the top of the second gate structure;

[0023] A first gate connector extends through the interlayer dielectric layer, the second gate dielectric layer, and the portion of the substrate located between the interlayer dielectric layer and the second gate dielectric layer, and the first gate connector is connected to the first gate.

[0024] Accordingly, this application also provides a method for manufacturing a semiconductor device, comprising:

[0025] A substrate is provided in which a gate trench is formed, and a first gate dielectric layer is formed on the sidewalls and bottom of the gate trench;

[0026] A first gate is formed on the first gate dielectric layer, and the first gate is formed at the bottom of the gate trench;

[0027] A second gate dielectric layer is formed on the top surface of the first gate;

[0028] The portion of the first gate dielectric layer that is above the second gate dielectric layer is removed to expose the portion of the sidewall of the gate trench that is above the second gate dielectric layer, and a first gate structure is formed, the first gate structure including the first gate, the second gate dielectric layer and the remaining first gate dielectric layer;

[0029] An epitaxial layer is formed on the first gate structure, and the epitaxial layer fills the gate trench;

[0030] A second gate structure is formed on the substrate, and the orthogonal projection of the second gate structure toward the substrate partially coincides with the orthogonal projection of the first gate structure toward the substrate.

[0031] In one embodiment, after forming an epitaxial layer on the first gate structure and before forming a second gate structure on the substrate, the method of manufacturing the semiconductor device further includes:

[0032] A well region is formed in the epitaxial layer and in the substrate on both sides of the epitaxial layer;

[0033] A shallow trench isolation structure is formed within the substrate, the shallow trench isolation structure penetrating the well region and extending into the substrate below the well region.

[0034] In one embodiment, the formation process of the second gate structure includes:

[0035] A third gate dielectric layer is formed on the substrate;

[0036] A second gate is formed on the third gate dielectric layer, and the orthogonal projection of the second gate toward the substrate partially coincides with the orthogonal projection of the first gate toward the substrate.

[0037] A gate sidewall is formed on the sidewall of the second gate to form the second gate structure, and the second gate structure includes the third gate dielectric layer, the second gate and the gate sidewall.

[0038] In one embodiment, after forming a gate sidewall on the sidewall of the second gate, the method of manufacturing the semiconductor device further includes:

[0039] A source region and a drain region are formed in the substrate on both sides of the second gate structure, respectively;

[0040] A metal silicide layer is formed on top of the source region, the drain region, and the second gate;

[0041] An interlayer dielectric layer is formed on the substrate, the interlayer dielectric layer covering the second gate structure and the metal silicide layer;

[0042] An electrical connector and a first gate connector are formed within the interlayer dielectric layer. The electrical connector penetrates the interlayer dielectric layer and connects to the metal silicide layer at the top of the source region, the drain region, and the second gate, respectively. The first gate connector penetrates the interlayer dielectric layer, the second gate dielectric layer, and the portion of the substrate located between the interlayer dielectric layer and the second gate dielectric layer, and the first gate connector is connected to the first gate.

[0043] In one embodiment, after removing the portion of the first gate dielectric layer that extends above the second gate dielectric layer, the method of manufacturing the semiconductor device further includes:

[0044] A first rapid thermal treatment is performed to repair the second gate dielectric layer and the sidewalls of the gate trench;

[0045] After forming an epitaxial layer on the first gate structure, the method for manufacturing the semiconductor device further includes:

[0046] A second rapid thermal treatment is performed to repair the surface of the epitaxial layer and the interface between the epitaxial layer and the substrate.

[0047] Accordingly, this application also provides a semiconductor device manufactured using the semiconductor device manufacturing method described above.

[0048] The unexpected effect of this application is that by setting a first gate structure in the substrate and a second gate structure on the substrate, and making the orthographic projection of the first gate structure toward the substrate coincide with the orthographic projection of the second gate structure toward the substrate, the leakage current of the substrate is reduced, and precise control of the current and voltage of the semiconductor device is achieved, thereby improving the performance of the semiconductor device, effectively reducing the noise of the semiconductor device, and expanding the frequency band of the semiconductor device. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in one embodiment of this application.

[0051] Figure 2 This is a schematic diagram showing the location of the epitaxial layer in a semiconductor device according to one embodiment of this application.

[0052] Figure 3 This is a schematic diagram of the layout design of a semiconductor device provided in one embodiment of this application.

[0053] Figure 4 for Figure 3 A schematic diagram of the cross-sectional structure along the AB direction.

[0054] Figure 5 A flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of this application.

[0055] Figure 6 This is a schematic diagram of the structure corresponding to the step of providing a substrate in the manufacturing method of a semiconductor device provided in one embodiment of this application.

[0056] Figure 7 This is a schematic diagram of the structure corresponding to the step of forming a first gate dielectric layer in the gate trench in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0057] Figure 8 This is a schematic diagram of the structure corresponding to the step of filling the gate trench with gate material in the manufacturing method of a semiconductor device provided in one embodiment of this application.

[0058] Figure 9 This is a schematic diagram of the structure corresponding to the step of forming a first gate in a gate trench in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0059] Figure 10 This is a schematic diagram of the structure corresponding to the step of forming a second gate dielectric layer on a first gate in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0060] Figure 11 This is a schematic diagram of the structure corresponding to the step of removing a portion of the first gate dielectric layer and forming a first gate structure in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0061] Figure 12 This is a schematic diagram of the structure corresponding to the step of forming an epitaxial layer in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0062] Figure 13 This is a schematic diagram of the structure corresponding to the step of removing the first hard mask layer and the second hard mask layer in the manufacturing method of a semiconductor device provided in one embodiment of this application.

[0063] Figure 14 This is a schematic diagram of the structure corresponding to the step of forming a well region in a substrate in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0064] Figure 15 This is a schematic diagram of the structure corresponding to the step of forming a shallow trench isolation structure in a substrate in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0065] Figure 16 This is a schematic diagram of the structure corresponding to the step of forming a P-well in a substrate in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0066] Figure 17 This is a schematic diagram of the structure corresponding to the step of forming a third gate dielectric layer on a substrate in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0067] Figure 18 This is a schematic diagram of the structure corresponding to the step of forming a second gate and a first sidewall on a third gate dielectric layer in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0068] Figure 19 This is a schematic diagram of the structure corresponding to the step of forming a lightly doped region in the P-well in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0069] Figure 20 This is a schematic diagram of the structure corresponding to the step of forming a second sidewall, a source region, a drain region, and a metal silicide layer in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0070] Figure 21 This is a schematic diagram of the structure corresponding to the steps of forming an interlayer dielectric layer, an electrical connector, and a first gate connector in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0071] The reference numerals in the figures include: 100-substrate; 100a-first hard mask layer; 100b-second hard mask layer; 100c-protective layer; 100d-third hard mask layer; 100e-third photoresist layer; 101-gate trench; 102-epitaxy layer; 110-first gate structure; 111-first gate dielectric layer; 112-first gate; 113-second gate dielectric layer; 120-well region; 121-P-well; 122-N-well; 12 3-Shallow trench isolation structure; 130-Second gate structure; 131-Third gate dielectric layer; 132-Second gate; 133-Gate sidewall; 133a-First sidewall; 133b-Second sidewall; 140-Lightly doped region; 140a-Fifth photoresist layer; 141-Source region; 142-Drain region; 150-Metal silicide layer; 160-Interlayer dielectric layer; 170-Electrical connector; 171-First gate connector; 172-Metal layer. Detailed Implementation

[0072] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be more thorough and complete.

[0073] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0074] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0075] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0076] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0077] Typical gate structures are semiconductor structures composed of a high-k dielectric material layer and a metal gate (MG) (i.e., HKMG structure). When the gate oxide capacitance Cox of the HKMG structure is large enough, the subthreshold leakage current at the channel surface and the drain-induced barrier low (DIBL) leakage current should not be a problem. At this time, the main leakage current in the semiconductor device comes from the PN junction and the well region, which are far away from the channel surface.

[0078] With the rapid development of integrated circuits, 28nm and below process technologies have gradually given rise to the Fully Depleted Silicon-On-Insulator (FD-SOI) process. This process involves fabricating a buried oxide (BOX) layer, allowing the PN junction to remain on the buried oxide layer, thus solving the body leakage problem. As the size of FD-SOI devices is further reduced, for example to ultra-thin-body (UTB) FD-SOI devices, the size of the PN junction and the gate linewidth of the metal gate (MG) are also reduced accordingly.

[0079] However, as the length of the metal gate decreases, the random roughness of the gate linewidth increases accordingly, leading to uncontrollable gate linewidth uniformity. Simultaneously, the presence of the thin-body region easily causes random dopant flux (RDF) of doped atoms. For example, when the channel length is too small, electrons between the source and drain may randomly enter the channel, causing changes in the channel concentration and thus making the threshold voltage Vt of the semiconductor device uncontrollable.

[0080] Therefore, it is necessary to provide a semiconductor device and its manufacturing method to achieve precise control of the current and voltage of the semiconductor device and reduce leakage current.

[0081] Figure 1 and Figure 2 This is a schematic diagram of the structure of a semiconductor device provided in one embodiment of this application. See also... Figure 1 and Figure 2One embodiment of this application provides a semiconductor device including a substrate 100, a first gate structure 110, and a second gate structure 130. An epitaxial layer 102 is disposed within the substrate 100. The first gate structure 110 is located within the substrate 100 and below the epitaxial layer 102. The second gate structure 130 is located on the substrate 100, and the orthographic projection of the second gate structure 130 toward the surface of the substrate 100 partially coincides with the orthographic projection of the first gate structure 110 toward the surface of the substrate 100. The first gate structure 110 includes a first gate 112, a first gate dielectric layer 111, and a second gate dielectric layer 113. The second gate dielectric layer 113 is located between the first gate 112 and the epitaxial layer 102. The first gate dielectric layer 111 covers the sidewalls and bottom of the first gate 112.

[0082] The semiconductor device described above reduces the leakage current of the substrate by setting a first gate structure in the substrate and a second gate structure on the substrate, and making the orthogonal projection of the first gate structure toward the substrate coincide with the orthogonal projection of the second gate structure toward the substrate. This achieves precise control of the current and voltage of the semiconductor device, thereby improving the performance of the semiconductor device, effectively reducing the noise of the semiconductor device, and expanding the frequency band of the semiconductor device.

[0083] In one embodiment, the substrate and epitaxial layer are made of homogeneous silicon; the first gate dielectric layer and the second gate dielectric layer are both made of silicon oxide; and the first gate is made of polysilicon or other commonly used gate materials. In other embodiments of this application, the material selection and thickness parameters of different parts of the substrate, epitaxial layer, and first gate structure can be adjusted according to actual needs, and this application does not impose any limitations on this.

[0084] Continue reading Figure 1 and Figure 2 In one embodiment, the second gate structure 130 includes a third gate dielectric layer 131, a second gate 132, and a gate sidewall 133, wherein the third gate dielectric layer 131 is located on the substrate 100; the second gate 132 is located on the third gate dielectric layer 131, and the orthographic projection of the second gate 132 toward the substrate 100 partially coincides with the orthographic projection of the first gate 112 toward the substrate 100; the gate sidewall 133 is located on the third gate dielectric layer 131 and covers the sidewall of the second gate 132.

[0085] In one embodiment, the third gate dielectric layer 131 is made of silicon oxide; the second gate 132 is made of polysilicon or other commonly used gate materials; and the gate sidewall 133 is made of at least one of silicon oxide and silicon nitride. Optionally, the gate sidewall 133 includes a first sidewall 133a and a second sidewall 133b, wherein the first sidewall 133a covers the sidewall of the second gate 132, and the second sidewall 133b covers the sidewall of the first sidewall 133a away from the second gate 132. Optionally, both the first sidewall 133a and the second sidewall 133b include at least one silicon oxide layer and a silicon nitride layer; for example, both the first sidewall 133a and the second sidewall 133b are stacked structures formed by stacking silicon oxide and silicon nitride layers.

[0086] See Figure 1 and Figure 2 In one embodiment, the semiconductor device further includes a well region 120, which is located in the epitaxial layer 102 above the first gate structure 110 and in the substrate 100 on both sides of the epitaxial layer 102; wherein the well region 120 includes alternately arranged P-wells 121 and N-wells 122, and a shallow trench isolation structure 123 (STI) is provided between adjacent P-wells 121 and N-wells 122.

[0087] It should be noted that in most cases (e.g., when the semiconductor device includes a single NMOS structure, when the semiconductor device includes a single PMOS structure, and when the semiconductor device includes a complex circuit structure with both NMOS and PMOS), deep N-wells (DNWs) can be formed in the epitaxial layer and the substrates on both sides of the epitaxial layer; the morphology of deep N-wells can be found in [reference needed]. Figure 1 The middle well region (120) contains P-wells and N-wells spaced apart from each other within the deep N-well (the morphology of the P-wells and N-wells can be found in [reference]). Figure 1 The P-well 121 and N-well 122 are located in the deep N-well, and the depths of the P-well and N-well are both less than or equal to the depth of the deep N-well.

[0088] It is important to emphasize that in complex circuit structures where semiconductor devices include both NMOS and PMOS, the depth of the deep N-well must be greater than the depths of the individual N-wells and P-wells to ensure the proper functioning of the semiconductor device. However, in cases where the semiconductor device includes only a PMOS structure, the depth of the deep N-well can be the same as the depths of the individual N-wells and P-wells, which is equivalent to not having a deep N-well within the semiconductor device.

[0089] Continue reading Figure 1In one embodiment, the semiconductor device further includes a lightly doped region 140, which is located within the P-wells 121 on both sides of the second gate structure 130. Optionally, a source region 141 and a drain region 142 are disposed within the lightly doped region 140, wherein the source region 141 is located within the lightly doped region 140 on one side of the second gate structure 130, and the drain region 142 is located within the lightly doped region 140 on the side of the second gate structure 130 away from the source region 141.

[0090] Continue reading Figure 1 In one embodiment, the semiconductor device further includes a metal silicide layer 150, an interlayer dielectric layer 160, and an electrical connector 170. The metal silicide layer 150 is located on top of the source region 141, the drain region 142, and the second gate structure 130. The interlayer dielectric layer 160 is located on the substrate 100 and covers the second gate structure 130 and the metal silicide layer 150. The electrical connector 170 penetrates the interlayer dielectric layer 160 and is connected to the metal silicide layer 150 on top of the source region 141, the drain region 142, and the second gate structure 130, respectively. Optionally, the metal silicide layer 150 is made of nickel-platinum silicide (NiPtSi2), the interlayer dielectric layer 160 includes at least one of a silicon oxide layer and a silicon nitride layer, and the electrical connector 170 is made of tungsten.

[0091] Figure 3 for Figure 1 The schematic diagram of the layout design corresponding to the semiconductor device shown is as follows ( Figure 3 (Partial structure of the semiconductor device is not shown). Figure 4 for Figure 3 A schematic diagram of the cross-sectional structure along the AB direction. (See attached diagram.) Figure 1 , Figure 3 and Figure 4 In one embodiment, the first gate structure 110 and the second gate structure 130 partially overlap in a direction perpendicular to the substrate 100, and the semiconductor device further includes a first gate connector 171 penetrating the interlayer dielectric layer 160, the second gate dielectric layer 113, and a portion of the substrate 100, and the first gate connector 171 is used to lead out the first gate 112. Optionally, the material of the first gate connector 171 includes tungsten.

[0092] Continue reading Figure 1 and Figure 4 In one embodiment, the sidewalls and bottom of the electrical connector 170 and the first gate connector 171 are provided with a metal layer 172 to improve the adhesion between the electrical connector 170 and the first gate connector 171 and other film layers, thereby helping to improve the performance and stability of the semiconductor device. Optionally, the metal layer 172 includes a combination of a titanium (Ti) layer and a titanium nitride (TiN) layer.

[0093] Figure 5 This application provides a method for manufacturing a semiconductor device according to one embodiment. Accordingly, see [link to relevant documentation]. Figure 5 One embodiment of this application provides a method for manufacturing a semiconductor device, which includes the following steps S01 to S06.

[0094] Step S01: Provide a substrate in which a gate trench is formed, and form a first gate dielectric layer on the sidewalls and bottom of the gate trench.

[0095] Step S02: A first gate is formed on the first gate dielectric layer, and the first gate is formed at the bottom of the gate trench.

[0096] Step S03: Form a second gate dielectric layer on the top surface of the first gate.

[0097] Step S04: Remove the portion of the first gate dielectric layer that is above the second gate dielectric layer to expose the portion of the sidewall of the gate trench that is above the second gate dielectric layer, and form a first gate structure, the first gate structure including the first gate, the second gate dielectric layer and the remaining first gate dielectric layer.

[0098] It should be noted that since the first gate is formed at the bottom of the gate trench in step S02, the first gate structure is also formed at the bottom of the gate trench (which can also be understood as the first gate structure not filling the gate trench), so that an epitaxial layer can be formed on top of the first gate structure in subsequent process flows, so that the first gate structure is buried in the substrate, thereby helping to reduce leakage current in the substrate.

[0099] Step S05: An epitaxial layer is formed on the first gate structure, and the epitaxial layer fills the gate trench.

[0100] Step S06: A second gate structure is formed on the substrate, and the orthogonal projection of the second gate structure toward the substrate partially coincides with the orthogonal projection of the first gate structure toward the substrate.

[0101] The semiconductor device manufacturing method described above reduces the leakage current of the substrate by forming a first gate structure in the substrate, thereby achieving high control over the threshold voltage of the semiconductor device. By setting a second gate structure on the substrate and making the orthogonal projection of the first gate structure toward the substrate coincide with the orthogonal projection of the second gate structure toward the substrate, precise control over the current and voltage of the semiconductor device is achieved, thereby improving the performance of the semiconductor device, effectively reducing the noise of the semiconductor device, and expanding the frequency band of the semiconductor device.

[0102] Figures 6 to 21This is a schematic diagram showing the structure of some steps in the manufacturing method of a semiconductor device according to one embodiment of this application. The following is in conjunction with... Figures 6 to 21 This application provides a detailed description of the specific process of manufacturing the semiconductor device.

[0103] See Figure 6 and Figure 7 In step S01, a substrate 100 is provided, in which a gate trench 101 is formed, and a first gate dielectric layer 111 is formed on the sidewalls and bottom of the gate trench 101. Exemplarily, the specific formation process of the gate trench 101 and the first gate dielectric layer 111 includes: First, referring to... Figure 6 A substrate 100 is provided, on which a first hard mask layer 100a, a second hard mask layer 100b, and a patterned first photoresist layer (not shown) are sequentially formed. The patterned first photoresist layer is used to define the position and shape of the gate trench. Using the first photoresist layer as a mask, the second hard mask layer 100b, the first hard mask layer 100a, and the substrate 100 are sequentially etched to form a gate trench 101 within the substrate 100. Next, refer to... Figure 7 The first gate dielectric layer 111 is formed using an in-situ steam generation (ISSG) process within a furnace tube process or a rapid temperature processing (RTP) process. Optionally, the substrate 100 is made of silicon, for example, the first hard mask layer is made of silicon oxide, and the second hard mask layer is made of silicon nitride. Optionally, the first gate dielectric layer 111 is made of silicon oxide.

[0104] In one embodiment, the process of sequentially forming a first hard mask layer, a second hard mask layer, and a patterned first photoresist layer on a substrate includes: firstly, forming a first hard mask layer on the substrate using any one of thermal oxidation, furnace oxidation, or deposition processes; then, forming a second hard mask layer on the first hard mask layer using a deposition process; subsequently, forming a first photoresist layer on the second hard mask layer using a spin coating process, and exposing and developing the first photoresist layer to form a patterned first photoresist layer. Optionally, the first photoresist layer is a negative photoresist layer.

[0105] In one embodiment, a dry etching process is used to etch the second hard mask layer, the first hard mask layer, and the substrate to form a gate trench. Optionally, after forming the gate trench, an ashing process can be used to remove the first photoresist layer, followed by a wet cleaning process to remove residual polymers from the dry etching and ashing processes, in order to avoid the polymers generated during the etching process of the gate trench from negatively affecting subsequent process steps.

[0106] It should be noted that during the etching process of the gate trench, the etching depth usually needs to be greater than a set value, and this set value can be the sum of the implantation depth of the first hard mask layer, the second hard mask layer, and the subsequent well region formed in the substrate, so as to ensure that the final semiconductor device functions properly.

[0107] Meanwhile, it should be emphasized that by forming the first gate dielectric layer, the damage to the substrate caused by the etching process of the gate trench can be repaired, and the first gate dielectric layer can act as an isolation layer to isolate the substrate from the subsequently formed first gate, so as to ensure the normal operation of the semiconductor device.

[0108] See Figure 8 and Figure 9 In step S02, a first gate 112 is formed on the first gate dielectric layer 111, and the first gate 112 is formed at the bottom of the gate trench 101. Exemplarily, the specific formation process of the first gate structure 110 includes: (Refer to...) Figure 8 Gate material is deposited within gate trench 101, and the gate material is planarized to ensure that it precisely fills gate trench 101; subsequently, refer to... Figure 9 A portion of the gate material is removed to form a first gate 112 located at the bottom of the gate trench 101. Optionally, a dry etching process is used to remove a portion of the gate material. Optionally, the thickness of the first gate 112 ranges from 500 Å to 800 Å.

[0109] In one embodiment, a furnace-tube process is used to deposit gate material within the gate trench, and a chemical mechanical polishing (CMP) process is used to planarize the gate material. Optionally, end-point detection (EDP) technology can be used to determine the stopping point of the planarization process to ensure that the planarized gate material precisely fills the gate trench, and that the surface of the gate material is flush with the surface of the second hard mask layer. Optionally, the gate material includes polysilicon or other commonly used gate materials.

[0110] Next, refer to Figure 10Step S03 is executed to form a second gate dielectric layer 113 on the top surface of the first gate 112. In one embodiment, the second gate dielectric layer 113 can be formed using a rapid temperature processing (RTP) process. Optionally, the material of the second gate dielectric layer 113 includes silicon oxide. It is important to emphasize that using a rapid temperature processing method to form the second gate dielectric layer 113 can repair the etching damage caused to the first gate 112 during the dry etching process of the gate material, thereby improving the performance of the final semiconductor device.

[0111] It should be noted that the thickness of the second gate dielectric layer must be at least greater than the thickness of the first gate dielectric layer to prevent the second gate dielectric layer from being completely removed during the subsequent removal of the first gate dielectric layer, thereby ensuring the normal functioning of the semiconductor device.

[0112] Then refer to Figure 11 Step S04 is executed to remove the portion of the first gate dielectric layer 111 above the second gate dielectric layer 113, thereby exposing the portion of the sidewall of the gate trench 101 above the second gate dielectric layer 113, and forming a first gate structure 110. The first gate structure 110 includes a first gate 112, a second gate dielectric layer 113, and the remaining first gate dielectric layer 111. In one embodiment, a wet etching process is used to remove a portion of the first gate dielectric layer 111. Optionally, the etchant used in the wet etching process includes a DHF solution.

[0113] It should be noted that during the partial removal of the first gate dielectric layer, the surface of the second gate dielectric layer away from the first gate will also be etched, and the thickness of the second gate dielectric layer will decrease during the removal of part of the first gate dielectric layer. After the partial removal of the first gate dielectric layer is completed, the top surface of the first gate is still covered by the second gate dielectric layer. At this time, the remaining first gate dielectric layer, second gate dielectric layer and first gate constitute the first gate structure of the semiconductor device.

[0114] In one embodiment, after forming the first gate structure, the method for manufacturing the semiconductor device further includes performing a first rapid thermal process (RTP) to repair damage to the sidewalls of the second gate dielectric layer and the gate trench caused during the wet etching process. Optionally, the first rapid thermal process is performed in a vacuum atmosphere purged with nitrogen (N2).

[0115] See Figure 12In step S05, an epitaxial layer 102 is formed on the first gate structure 110, and the epitaxial layer 102 fills the gate trench 101. In one embodiment, the epitaxial layer 102 can be formed by laterally epitaxially processing the substrate 100 exposed above the first gate structure 110 using a single-crystal silicon epitaxial process.

[0116] In one embodiment, after forming the epitaxial layer, the method for manufacturing the semiconductor device further includes performing a second rapid thermal process (RTP) to repair the interface between the second gate dielectric layer and the epitaxial layer. Optionally, the second rapid thermal process is performed in a vacuum atmosphere purged with nitrogen (N2).

[0117] See Figure 12 and Figure 13 After forming the epitaxial layer 102, the semiconductor device manufacturing method further includes removing the first hard mask layer 100a and the second hard mask layer 100b. At this time, a first gate structure 110 and the epitaxial layer 102 are formed within the substrate 100. In one embodiment, a wet etching process can be used to remove the first hard mask layer 100a and the second hard mask layer 100b. Optionally, if the first hard mask layer 100a is a silicon oxide layer and the second hard mask layer 100b is a silicon nitride layer, the second hard mask layer 100b can be removed first using phosphoric acid, and then the first hard mask layer 100a can be removed using a DHF solution.

[0118] It should be emphasized that by forming a first gate structure in the substrate and forming an epitaxial layer on the first gate structure, the leakage current of the substrate can be effectively reduced, thereby helping to achieve high control of the threshold voltage of the semiconductor device.

[0119] See Figure 14 After forming the epitaxial layer 102, the semiconductor device manufacturing method further includes: forming a protective layer 100c on the surface of the substrate 100, and performing an ion implantation process on the substrate 100 to form well regions 120 in the epitaxial layer 102 and the substrate 100 on both sides of the epitaxial layer 102. In one embodiment, the protective layer 100c is formed using a furnace tube process, and the protective layer 100c is a silicon oxide layer to prevent damage to the surface of the substrate 100 during the ion implantation process of the well region 120. Optionally, the thickness of the protective layer 100c is, for example, 55 Å. Optionally, the well region 120 is a deep N-well (DNW).

[0120] Next, refer to Figure 15A shallow trench isolation structure 123 (STI) is formed that penetrates the protective layer 100c and extends into the substrate 100, and the shallow trench isolation structure 123 extends into the substrate 100 below the well region 120.

[0121] In one embodiment, the process of forming the shallow trench isolation structure 123 includes: forming a third hard mask layer 100d and a second photoresist layer (not shown in the figure) on the protective layer 100c, and patterning the second photoresist layer; then, etching the third hard mask layer 100d, the protective layer 100c and the substrate 100 using the patterned second photoresist layer as a mask to form an isolation trench (not shown in the figure); subsequently, removing the patterned second photoresist layer; and filling the isolation trench with an isolation layer to form the shallow trench isolation structure 123 including the isolation trench and the isolation layer.

[0122] In one embodiment, the material of the third hard mask layer includes silicon nitride; the second photoresist layer can be removed by a wet etching process, and the polymer remaining during the etching of the isolation trench can be removed by a wet cleaning process. Optionally, the wet cleaning process for the second photoresist layer and the wet cleaning process for the polymer remaining after etching the isolation trench can be combined into a single process to save costs and improve production efficiency.

[0123] In one embodiment, a deposition process can be used to fill the isolation trench with isolation material. After the deposition process is completed, an annealing process can be performed at a certain temperature to make the deposited isolation material more dense. Subsequently, the isolation material is planarized to form an isolation layer that exactly fills the isolation trench. Optionally, the isolation material used for the isolation layer includes an oxide material, for example, tetraethyl orthosilicate (TEOS). Optionally, a chemical mechanical polishing process is used to planarize the isolation material, and an endpoint detection method is used to control the timing of the planarization process to ensure that the surface of the isolation layer is flush with the surface of the third hard mask layer.

[0124] In one embodiment, after removing the second photoresist layer and before filling the isolation trench with an isolation layer, a rapid thermal treatment can be used to perform an oxidation repair treatment on the inner wall of the isolation trench to form a thin oxide layer (not shown in the figure) on the inner wall of the isolation trench, thereby repairing the etching damage to the substrate caused during the etching process of the isolation trench.

[0125] See Figure 16After forming the shallow trench isolation structure 123, the third hard mask layer 100d and the portion of the isolation layer above the protective layer 100c are removed. Next, a patterned third photoresist layer 100e is formed on the protective layer 100c and the shallow trench isolation structure 123. Using the third photoresist layer 100e as a mask, an ion implantation process is performed on the substrate 100 to form a P-well 121 within the well region 120. It should be noted that while forming the P-well 121, the portion of the well region 120 located below the third photoresist layer 100g is an N-well 122, and the P-well 121 and N-well 122 are separated by the shallow trench isolation structure 123 to ensure the normal operation of the semiconductor device.

[0126] In one embodiment, a wet etching process is used to remove the portion of the third hard mask layer 100d and the isolation layer above the protective layer 100c. Optionally, the etchant used in the wet etching process of the third hard mask layer 100d and the isolation layer includes phosphoric acid and DHF solution.

[0127] In one embodiment, the ions implanted in the ion implantation process of P-trap 121 include boron ions (B) and boron difluoride ions (BF2). It should be noted that, because boron ions are relatively light, ion implantation can be performed in four steps, with each implantation reaching a different depth, to form P-trap 121.

[0128] Then refer to Figure 17 After forming the P-well 121 and N-well 122, the third photoresist layer 100e and the protective layer 100c are removed, and a third gate dielectric layer 131 is formed on the substrate. In one embodiment, the third photoresist layer 100e is removed by an ashing process, and the protective layer 100c is removed by a wet etching process to expose the surface of the substrate 100.

[0129] In one embodiment, a third gate dielectric layer 131 is formed on the surface of substrate 100 using a furnace tube process or an in-situ steam generation (ISSG) process. When the semiconductor device is a low-voltage device, the thickness of the third gate dielectric layer 131 ranges from 15 Å to 30 Å. In other embodiments of this application, the specific thickness of the third gate dielectric layer can be adjusted according to the type of semiconductor device and actual process requirements, and this application does not impose any limitations on this.

[0130] Next, refer to Figure 18 A second gate 132 is formed on the third gate dielectric layer 131; a first sidewall 133a is formed on the sidewall of the second gate 132; and the portion of the third gate dielectric layer 131 not covered by the second gate 132 and the first sidewall 133a is removed.

[0131] In one embodiment, the process of forming the second gate 132 on the third gate dielectric layer 131 includes: forming a second gate material layer (not shown) on the third gate dielectric layer 131, and sequentially forming a fourth hard mask layer (not shown), an anti-reflection layer (not shown), and a patterned fourth photoresist layer (not shown) on the second gate material layer; etching the anti-reflection layer, the fourth hard mask layer, and the second gate material layer using the fourth photoresist layer as a mask to form the second gate 132; and removing the fourth photoresist layer, the anti-reflection layer, and at most a portion of the fourth hard mask layer. Optionally, the material of the second gate material layer includes polysilicon; the fourth hard mask layer includes a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a stacked structure composed of any combination thereof.

[0132] In one embodiment, after forming the second gate and removing up to a portion of the fourth hard mask layer, the remaining fourth hard mask layer on the second gate is a silicon oxide layer. Optionally, a wet etching process is used to remove a portion of the fourth hard mask layer, wherein the removed portion of the fourth hard mask layer includes silicon nitride, and the etchant of the fourth hard mask layer includes phosphoric acid.

[0133] In one embodiment, after the second gate is formed, a silicon oxide layer (not shown in the figure) is formed on the sidewall of the second gate using rapid thermal processing to repair the etching damage to the sidewall of the second gate caused during the etching of the second gate material layer and the formation of the second gate. At the same time, the silicon oxide layer formed on the sidewall of the second gate can also serve as part of the subsequently formed first sidewall to ensure the normal operation of the semiconductor device.

[0134] In one embodiment, after forming the second gate and removing up to a portion of the fourth hard mask layer, a first sidewall material layer is formed on the remaining fourth hard mask layer, and the first sidewall material layer covers the sidewall of the second gate and the third gate dielectric layer on both sides of the second gate; a dry etching process is used to remove a portion of the first sidewall material layer, the remaining fourth hard mask layer, and the portion of the third gate dielectric layer covered by the first sidewall material layer to form a first sidewall covering the sidewall of the second gate.

[0135] Then refer to Figure 19A fifth photoresist layer 140a is formed covering a portion of the substrate 100, and the fifth photoresist layer 140a exposes the portion of the P-well 121 not covered by the second gate 132 and the first sidewall 133a. Using the fifth photoresist layer 140a as a mask, an ion implantation process is performed to form a lightly doped region 140 in the exposed P-well 121. In one embodiment, at least one of germanium ions (Ge), carbon ions (C), boron ions (B), nitrogen ions (N), phosphorus ions (P), and arsenic ions (As) can be implanted sequentially to a certain depth to form an N-type lightly doped region 140 (LDD).

[0136] Next, refer to Figure 20 After forming the lightly doped region 140, the fifth photoresist layer 140a is removed; a second sidewall 133b is formed on the sidewall of the first sidewall 133a away from the second gate 132 to form a second gate structure 130. The second gate structure 130 includes a third gate dielectric layer 131, a second gate 132, and a gate sidewall 133 (the gate sidewall 133 includes the first sidewall 133a and the second sidewall 133b); then, a source region 141 and a drain region 142 are formed in the lightly doped regions 140 on both sides of the second gate structure 130, respectively; subsequently, a metal silicide layer 150 is formed on the second gate 132, the source region 141, and the drain region 142.

[0137] In one embodiment, the process of forming the second sidewall includes: forming a second sidewall material layer (not shown) on the substrate, the second gate, and the first sidewall, and removing the second sidewall material layer above the second gate and the substrate to form the second sidewall, wherein the second sidewall covers the sidewall of the first sidewall away from the second gate. Optionally, both the first and second sidewalls include at least one of a silicon oxide layer and a silicon nitride layer; for example, both the first and second sidewalls are stacked structures composed of a combination of silicon oxide layers and silicon nitride layers.

[0138] In one embodiment, after forming the second gate structure, ion implantation can be performed on the lightly doped regions on both sides of the second gate structure to form source and drain regions, respectively. Optionally, at least one of germanium ions (Ge), phosphorus ions (P), arsenic ions (As), and fluorine ions (F) can be implanted sequentially to a certain depth to form source and drain regions.

[0139] In one embodiment, after forming the source and drain regions, a spike annealing process can be performed to fix the implanted ions within the source and drain regions and restrict their movement within a certain area. Optionally, the process temperature for the spike annealing process can be 1050°C. In other embodiments of this application, the specific process temperature for the spike annealing process can be adjusted according to actual needs, and this application does not impose any limitations on this.

[0140] Continue reading Figure 20 In one embodiment, the process of forming a metal silicide layer 150 on the second gate 132, source region 141, and drain region 142 includes: forming a mask layer (not shown) on the substrate 100 and the second gate structure 130, exposing the second gate 132, source region 141, and drain region 142 and covering other portions of the substrate 100 and the second gate structure 130; and employing a silicon cobalt nickel pre-cleaning process (SiCoNi). Pre-cleaning removes the native oxide; then, a platinum nickel oxide layer (NiPt, not shown in the figure) is deposited, and a titanium nitride layer (TiN, not shown in the figure) is formed on the platinum nickel oxide layer; next, a first rapid thermal treatment is performed to form a high-resistivity metal silicide (e.g., Ni2PtSi) at the junction of the platinum nickel oxide layer and the second gate 132, source region 141 and drain region 142; then, a second rapid thermal treatment is performed to form a low-resistivity metal silicide (e.g., NiPtSi2); then, the portion of the platinum nickel oxide layer that has not been converted into a metal silicide layer is removed to form a metal silicide layer 150.

[0141] In one embodiment, the thickness of the platinum nickelate layer is, for example, 120 Å, and the thickness of the titanium nitride layer is, for example, 50 Å. Optionally, the first rapid thermal treatment process temperature is 290°C, and the process time is 30 s. In other embodiments of this application, the process methods, process parameters, and materials and thickness ranges of each film layer used in the formation of the metal silicide layer can be adjusted according to actual needs, and this application does not impose any limitations on them.

[0142] See Figure 21 After forming the metal silicide layer 150, an interlayer dielectric layer 160 is formed on the substrate 100, the metal silicide layer 150, and the second gate structure 130, and an electrical connection 170 is formed through the interlayer dielectric layer 160 and connected to the metal silicide layer 150. In one embodiment, the interlayer dielectric layer 160 includes a stacked structure of a silicon nitride layer (not shown) and a plurality of oxide layers (not shown), and the oxide layer material includes tetraethyl orthosilicate (TEOS). Optionally, the thickness of the silicon nitride layer in the interlayer dielectric layer 160 is, for example, 300 Å, and the total thickness of the plurality of oxide layers is 2700 Å.

[0143] In one embodiment, the formation process of the electrical connector includes: forming a patterned sixth photoresist layer on the interlayer dielectric layer; etching the interlayer dielectric layer using the patterned sixth photoresist layer as a mask to form a contact hole (CT) penetrating the interlayer dielectric layer, wherein the contact hole exposes a portion of the surface of the metal silicide layer above the second gate, source region, and drain region; then, removing residual polymer within the contact hole using a wet cleaning process; subsequently, forming the electrical connector within the contact hole. Optionally, the material of the electrical connector includes tungsten (W).

[0144] Figure 3 for Figure 21 The schematic diagram of the layout design corresponding to the semiconductor device shown is as follows ( Figure 3 (Part of the structure in the semiconductor device is not shown). Figure 4 for Figure 3 The diagram shows a cross-sectional view of the semiconductor device along the AB direction. (See attached image.) Figure 21 , Figure 3 and Figure 4 In one embodiment, during the formation of the electrical connector 170, a first gate connector 171 is also formed, penetrating the interlayer dielectric layer 160, the second gate dielectric layer 113, and a portion of the substrate 100. The formation process of the first gate connector 171 is the same as that of the electrical connector 170, and will not be elaborated further. Optionally, the material of the first gate connector 171 may include tungsten (W).

[0145] Continue reading Figure 21 and Figure 4 In one embodiment, after forming the contact hole and before forming the electrical connector and the first gate connector within the contact hole, a metal layer 172 may be formed on the inner wall and bottom of the contact hole to improve the connection performance between the electrical connector 170 and the metal silicide layer 150, and between the first gate connector 171 and the first gate 112. Optionally, the metal layer 172 is a stacked structure composed of a titanium (Ti) layer and a titanium nitride (TiN) layer, wherein the thickness of the titanium layer is 100 Å and the thickness of the titanium nitride layer is 50 Å. In other embodiments of this application, other materials may be used to prepare the metal layer, the first gate connector, and the electrical connector, and the specific structure and parameters of the metal layer may be adjusted according to actual needs, which is not limited in this application.

[0146] Comparative Reference Figure 21 and Figure 1 The method for manufacturing a semiconductor device provided in one embodiment of this application can be used to manufacture, for example, a semiconductor device. Figure 1The semiconductor device is shown. As can be seen, the semiconductor device manufacturing method described above reduces the leakage current of the substrate 100 by forming a first gate structure 110 within the substrate 100, achieving high control over the threshold voltage of the semiconductor device; by forming a second gate structure 130 on the substrate, a dual-gate MOS structure is formed, achieving precise control over the current and voltage of the semiconductor device, improving the performance of the semiconductor device, reducing noise, and extending the bandwidth. Furthermore, compared to conventional semiconductor devices, the dual-gate MOS structure manufactured by the semiconductor device manufacturing method provided in this application is more suitable for application in radio frequency and microwave circuits.

[0147] The unexpected effect of this application is that by setting a first gate structure in the substrate and a second gate structure on the substrate, and making the orthographic projection of the first gate structure toward the substrate coincide with the orthographic projection of the second gate structure toward the substrate, the leakage current of the substrate is reduced, and precise control of the current and voltage of the semiconductor device is achieved, thereby improving the performance of the semiconductor device, effectively reducing the noise of the semiconductor device, and expanding the frequency band of the semiconductor device.

[0148] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0149] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0150] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided in which a gate trench is formed, and a first gate dielectric layer is formed on the sidewalls and bottom of the gate trench; A first gate is formed on the first gate dielectric layer, and the first gate is formed at the bottom of the gate trench; A second gate dielectric layer is formed on the top surface of the first gate; The portion of the first gate dielectric layer that is above the second gate dielectric layer is removed to expose the portion of the sidewall of the gate trench that is above the second gate dielectric layer, and a first gate structure is formed, the first gate structure including the first gate, the second gate dielectric layer and the remaining first gate dielectric layer; An epitaxial layer is formed on the first gate structure, and the epitaxial layer fills the gate trench; A second gate structure is formed on the substrate, and the orthogonal projection of the second gate structure toward the substrate partially coincides with the orthogonal projection of the first gate structure toward the substrate.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, After forming an epitaxial layer on the first gate structure and before forming a second gate structure on the substrate, the method for manufacturing the semiconductor device further includes: A well region is formed in the epitaxial layer and in the substrate on both sides of the epitaxial layer; A shallow trench isolation structure is formed within the substrate, the shallow trench isolation structure penetrating the well region and extending into the substrate below the well region.

3. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The formation process of the second gate structure includes: A third gate dielectric layer is formed on the substrate; A second gate is formed on the third gate dielectric layer, and the orthogonal projection of the second gate toward the substrate partially coincides with the orthogonal projection of the first gate toward the substrate. A gate sidewall is formed on the sidewall of the second gate to form the second gate structure, and the second gate structure includes the third gate dielectric layer, the second gate and the gate sidewall.

4. The method for manufacturing a semiconductor device according to claim 3, characterized in that, After forming a gate sidewall on the sidewall of the second gate, the method for manufacturing the semiconductor device further includes: A source region and a drain region are formed in the substrate on both sides of the second gate structure, respectively; A metal silicide layer is formed on top of the source region, the drain region, and the second gate; An interlayer dielectric layer is formed on the substrate, the interlayer dielectric layer covering the second gate structure and the metal silicide layer; An electrical connector and a first gate connector are formed within the interlayer dielectric layer. The electrical connector penetrates the interlayer dielectric layer and connects to the metal silicide layer at the top of the source region, the drain region, and the second gate, respectively. The first gate connector penetrates the interlayer dielectric layer, the second gate dielectric layer, and the portion of the substrate located between the interlayer dielectric layer and the second gate dielectric layer, and the first gate connector is connected to the first gate.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that, After removing the portion of the first gate dielectric layer that extends above the second gate dielectric layer, the method of manufacturing the semiconductor device further includes: A first rapid thermal treatment is performed to repair the second gate dielectric layer and the sidewalls of the gate trench; After forming an epitaxial layer on the first gate structure, the method for manufacturing the semiconductor device further includes: A second rapid thermal treatment is performed to repair the surface of the epitaxial layer and the interface between the epitaxial layer and the substrate.

6. A semiconductor device, characterized in that, The semiconductor device is manufactured using the semiconductor device manufacturing method as described in any one of claims 1 to 5.

7. The semiconductor device according to claim 6, characterized in that, include: A substrate, wherein an epitaxial layer is disposed therein; A first gate structure is located within the substrate, and the first gate structure is located below the epitaxial layer; A second gate structure is located on the substrate, and the orthographic projection of the second gate structure toward the substrate surface partially coincides with the orthographic projection of the first gate structure toward the substrate surface. The first gate structure includes a first gate, a first gate dielectric layer, and a second gate dielectric layer. The second gate dielectric layer is located between the first gate and the epitaxial layer, and the first gate dielectric layer covers the sidewalls and bottom of the first gate.

8. The semiconductor device according to claim 7, characterized in that, The second gate structure includes: A third gate dielectric layer is located on the substrate; The second gate is located on the third gate dielectric layer, and the orthogonal projection of the second gate toward the substrate partially coincides with the orthogonal projection of the first gate toward the substrate. A gate sidewall is located on the third gate dielectric layer and covers the sidewall of the second gate.

9. The semiconductor device according to claim 8, characterized in that, The substrate further includes: The well region is located within the epitaxial layer and the substrate on both sides of the epitaxial layer; A shallow trench isolation structure extends through the well region and into the substrate beneath the well region; The source region is located within the substrate on one side of the second gate structure; The drain region is located within the substrate on the side of the second gate structure away from the source region.

10. The semiconductor device according to claim 9, characterized in that, The semiconductor device further includes: A metal silicide layer is located on top of the source region, the drain region, and the second gate; An interlayer dielectric layer is located on the substrate, and the interlayer dielectric layer covers the second gate structure and the metal silicide layer; An electrical connector extends through the interlayer dielectric layer and is respectively connected to the source region, the drain region, and the metal silicide layer at the top of the second gate structure; A first gate connector extends through the interlayer dielectric layer, the second gate dielectric layer, and the portion of the substrate located between the interlayer dielectric layer and the second gate dielectric layer, and the first gate connector is connected to the first gate.

Images