CIS chip packaging method

Abstract

According to the CIS chip packaging method provided by the embodiment of the invention, the shading substrate is made of the non-light-transmitting material, so that global shading of the back surface and the side surface of the chip is realized; a plurality of conductive columns penetrating through the thickness of a shading substrate are formed on the shading substrate, and through holes of the shading substrate are adopted to replace TSVs, so that the process difficulty and cost are reduced; by forming the light-transmitting dielectric layer wrapping the photosensitive chip in the groove, sealing of the photosensitive chip is achieved, no cofferdam needs to be additionally arranged, and the risk that overflowing glue pollutes the photosensitive area of the chip is eliminated; the light-transmitting dielectric layer and the light-transmitting rewiring layer are adopted to replace thick glass in the prior art, the optical path is shortened, interface reflection is inhibited, glare is weakened, and the imaging quality is optimized; the light-transmitting insulating layer is formed on the light-transmitting rewiring layer and is used as a solder mask with light-transmitting and scratch-resistant characteristics, so that the reliability of the photosensitive chip packaging structure is improved; the light shielding layer and the light-proof light shielding substrate wrap the non-optical functional area, so that the whole-area light shielding integrity is ensured.

Description

Technical Field

[0001] This disclosure pertains to the field of semiconductor packaging technology, specifically relating to a CIS chip packaging method. Background Technology

[0002] CIS (CMOS image sensor) is a photoelectric sensor device based on CMOS technology. Its working principle is to convert incident light into electrical signals by utilizing the photoelectric effect of pixel arrays. The core structure of CIS packaging includes: substrate (mechanical support and circuit wiring), photosensitive chip (pixel array that carries photoelectric conversion), electrical interconnection structure (such as leads / solder balls, to connect the chip to the substrate), and glass cover (bonded to the photosensitive surface of the chip, providing optical path and physical protection for the chip).

[0003] Existing CIS packaging forms include: 1) Substrate-level packaging: Due to the need for additional structures to avoid arc height limitations and the increase in pixel count depends on the increase in chip area, it contradicts the miniaturization requirements of the module.

[0004] 2) Wafer-level packaging (Fan-in / Fan-out): This overcomes size limitations and resolves the conflict between miniaturization and high pixel count, but relies on TSV / TMV processes. Fan-in uses an in-chip TSV to guide electrical signals to the wiring on the back of the chip (area ≤ chip edge), while Fan-out uses an in-chip TSV or a TMV within the package to guide electrical signals to the wiring on the back of the package (extending beyond the chip's projected area). However, TSV deep silicon etching and copper filling processes are difficult and costly; the dam sealing of the chip's periphery can lead to the defect of colloids breaking through the boundary and contaminating the central photosensitive area.

[0005] To address the aforementioned issues, it is necessary to propose a CIS chip packaging method that is both rationally designed and effectively solves these problems. Summary of the Invention

[0006] The present disclosure aims to at least solve one of the technical problems existing in the prior art and provide a CIS chip packaging method.

[0007] One aspect of this disclosure provides a CIS chip packaging method, the method comprising:

[0008] A light-shielding substrate is provided, and a plurality of conductive pillars extending through its thickness are formed on the light-shielding substrate;

[0009] Multiple grooves are formed on the first surface of the light-shielding substrate, and multiple photosensitive chips are fixed with their back sides facing down in the corresponding grooves, wherein the orthogonal projection of the photosensitive chip in the groove falls inside the groove;

[0010] A light-transmitting dielectric layer is formed within the groove to encapsulate the photosensitive chip;

[0011] A light-transmitting redistribution layer is formed on the surface of the light-transmitting dielectric layer and on the first surface of the light-shielding substrate, and the light-transmitting redistribution layer is electrically connected to the photosensitive chip and the conductive pillar, respectively.

[0012] A light-transmitting insulating layer is formed on the light-transmitting redistribution layer;

[0013] A light-shielding layer with multiple openings is formed on the light-transmitting insulating layer, the openings corresponding to the photosensitive areas of the photosensitive chip;

[0014] A signal output layer electrically connected to the conductive pillar is formed on the second surface of the light-shielding substrate;

[0015] The chips are cut according to packaging requirements to form multiple independent CIS chip packaging structures.

[0016] Optionally, the method further includes:

[0017] A first square panel is provided, the light-shielding substrate is fixed to the first square panel, and the conductive pillars are formed on the light-shielding substrate; wherein...

[0018] After forming the light-shielding layer, the method further includes removing the first square panel.

[0019] Optionally, forming a plurality of conductive pillars penetrating the thickness of the light-shielding substrate includes:

[0020] Multiple through holes penetrating the thickness of the light-shielding substrate are formed on the substrate.

[0021] The through-hole is filled with conductive material to form the conductive pillar.

[0022] Optionally, the method further includes:

[0023] Before filling the through-hole with conductive material, a plurality of grooves are formed on the light-shielding substrate.

[0024] Optionally, forming a light-transmitting dielectric layer encapsulating the photosensitive chip within the groove includes:

[0025] A light-transmitting dielectric layer encapsulating the photosensitive chip is formed within the groove using spin coating or spray coating processes.

[0026] The transparent dielectric layer is thinned by grinding to expose the conductive bumps of the photosensitive chip.

[0027] Optionally, the surface of the formed light-transmitting dielectric layer is flush with the first surface of the light-shielding substrate.

[0028] Optionally, forming a light-transmitting redistribution layer on the surface of the light-transmitting dielectric layer and on the first surface of the light-shielding substrate includes:

[0029] A first metal layer is formed on the surface of the light-transmitting dielectric layer and on the first surface of the light-shielding substrate, and the first metal layer is electrically connected to the photosensitive chip and the conductive pillar, respectively.

[0030] A first dielectric layer is formed on the first metal layer, and the first dielectric layer is made of a light-transmitting material.

[0031] Optionally, forming a light-shielding layer with multiple openings on the light-transmitting insulating layer includes:

[0032] The light-shielding layer is formed on the light-transmitting insulating layer by spin coating or spray coating process;

[0033] The light-shielding layer is patterned to form multiple windows on the light-shielding layer, the windows corresponding to the photosensitive areas of the photosensitive chip.

[0034] Optionally, after forming the light-shielding layer, the method further includes:

[0035] A second square panel is provided, and the second square panel is fixed to the light-shielding layer;

[0036] After forming the signal output layer, the method further includes:

[0037] Remove the second square panel.

[0038] Optionally, a signal output layer electrically connected to the conductive pillar is formed on the second surface of the light-shielding substrate, including:

[0039] A redistribution layer is formed on the second surface of the light-shielding substrate, and the redistribution layer is electrically connected to the conductive pillar.

[0040] A solder resist layer is formed on the redistribution layer;

[0041] Solder balls are formed on the solder mask layer to form a plurality of solder balls that are electrically connected to the redistribution layer.

[0042] The CIS chip packaging method of this disclosure uses a non-transparent material as the light-shielding substrate to achieve full light shielding on the back and sides of the chip. By forming multiple conductive pillars penetrating the thickness of the light-shielding substrate and using through-holes in the light-shielding substrate instead of TSVs, the process difficulty and cost are reduced. By forming a transparent dielectric layer that wraps the photosensitive chip in the groove, the photosensitive chip is sealed without the need for additional dikes, eliminating the risk of adhesive overflow contaminating the photosensitive area of ​​the chip. The transparent dielectric layer and the transparent redistribution layer replace the thick glass in the prior art, shortening the optical path, suppressing interface reflection to reduce glare, and optimizing image quality. The transparent insulating layer formed on the transparent redistribution layer serves as a solder resist layer with light transmission and scratch resistance properties, improving the reliability of the photosensitive chip packaging structure. The light-shielding layer and the non-transparent light-shielding substrate wrap the non-optical functional areas to ensure the integrity of full light shielding. Attached Figure Description

[0043] Figure 1 This is a schematic flowchart of a CIS chip packaging method according to one embodiment of the present disclosure;

[0044] Figures 2 to 14 This is a schematic diagram of a CIS chip packaging method according to another embodiment of this disclosure. Detailed Implementation

[0045] To enable those skilled in the art to better understand the technical solutions of the embodiments of this disclosure, the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0046] like Figure 1 As shown, this disclosure presents an inventive method S100 for packaging a CIS chip, which specifically includes:

[0047] S110, Provide a light-shielding substrate and form a plurality of conductive pillars extending through its thickness on the light-shielding substrate.

[0048] Specifically, such as Figure 2 As shown, a light-shielding substrate 101 and a first square panel 103 are provided. The shape of the light-shielding substrate 101 matches the shape of the first square panel 103, and the light-shielding substrate 101 is also square. The light-shielding substrate 101 is attached and fixed to the first square panel 103 with temporary bonding adhesive 102.

[0049] The light-shielding substrate 101 is made of a non-transparent material. Preferably, in this embodiment, the light-shielding substrate 101 is made of a resin material, such as FR4 or BT resin. The specific material of the light-shielding substrate 101 is not specifically limited and can be selected according to actual needs. The first square panel 103 can be made of a material that matches the CTE of the light-shielding substrate 101, such as resin or metal. In this embodiment, the specific material of the first square panel 103 is not limited and can be selected according to actual needs.

[0050] In this embodiment, the light-shielding substrate 101 is made of a non-transparent material, which can achieve light protection on the back and sides of the photosensitive chip.

[0051] In step S110, the specific process of forming a plurality of conductive pillars 106 penetrating the thickness of the light-shielding substrate 101 can be as follows:

[0052] like Figure 3 As shown, multiple through holes 104 penetrating the thickness of the light-shielding substrate 101 are formed on the substrate using processes such as laser drilling.

[0053] like Figure 4 As shown, conductive material is filled into the through-hole 104 using an electroplating process to form the conductive pillar 106. The conductive pillar 106 enables vertical interconnection of the photosensitive chip, reducing the package thickness.

[0054] In this embodiment, a through-hole in a light-shielding substrate is used instead of the existing TSV, reducing the difficulty and cost of the process.

[0055] S120. A plurality of grooves are formed on the first surface of the light-shielding substrate, and a plurality of photosensitive chips are fixed with their back sides facing down in the corresponding grooves, wherein the orthogonal projection of the photosensitive chip in the groove falls inside the groove.

[0056] like Figure 3 As shown, before filling the through hole 104 with conductive material, multiple grooves 105 are formed on the first surface of the light-shielding substrate 101 by means of laser ablation or etching.

[0057] like Figure 5 As shown, multiple photosensitive chips 107 are mounted and fixed with their back sides facing down in their corresponding grooves 105. In this embodiment, as... Figure 6 As shown, mounting and fixing multiple photosensitive chips 107 in their corresponding grooves 105 can reduce the overall package thickness.

[0058] Among them, such as Figure 5As shown, the orthographic projection of the photosensitive chip 107 within the groove 105 falls inside the groove 105. That is, there is a corresponding space between the outer wall of the photosensitive chip 107 and the inner wall of the groove 105. The front side of the photosensitive chip 107 has pads 1071, conductive bumps 1072 are disposed on the pads 1071, and a photosensitive area 1073 is disposed in the central region of the front side of the photosensitive chip 107. Figure 6 As shown, multiple photosensitive chips 107 are arrayed on a square light-shielding substrate 101, which can overcome the limitations of wafer size and achieve efficient mass assembly.

[0059] S130, A light-transmitting dielectric layer is formed in the groove to enclose the photosensitive chip.

[0060] Step S130 may specifically include:

[0061] like Figure 7 As shown, a light-transmitting dielectric layer 108 encapsulating the photosensitive chip 107 is formed within the groove 105 using a spin coating or spray coating process. The light-transmitting dielectric layer 108 can be a highly transparent photoresist, such as PS or PI. The specific material of the light-transmitting dielectric layer 108 is not specifically limited and can be selected according to actual needs.

[0062] like Figure 7 As shown, the light-transmitting dielectric layer 108 is ground and chemically mechanically polished to thin it out, thereby exposing the conductive bumps 1072 of the photosensitive chip 107. The surface of the thinned light-transmitting dielectric layer 108 is flush with the first surface of the light-shielding substrate 101 to facilitate subsequent wiring on both the first surface of the light-shielding substrate 101 and the surface of the light-transmitting dielectric layer 108.

[0063] In this embodiment, a transparent dielectric layer 108 is used to directly wrap the photosensitive chip 107 to achieve sealing, eliminating the need for a dike, thus eliminating the risk of adhesive overflow contaminating the photosensitive area of ​​the chip and improving the reliability of the photosensitive chip 107.

[0064] S140. A light-transmitting redistribution layer is formed on the surface of the light-transmitting dielectric layer and on the first surface of the light-shielding substrate. The light-transmitting redistribution layer is electrically connected to the photosensitive chip and the conductive pillar, respectively.

[0065] like Figure 8 As shown, the specific process of step S140 can be as follows:

[0066] First, a first metal layer is formed on the surface of the light-transmitting dielectric layer 108 and the first surface of the light-shielding substrate 101. The first metal layer is electrically connected to the photosensitive chip 107 and the conductive pillar 106, respectively.

[0067] Specifically, an electroplating process is used to form a plurality of first pads 109 on the conductive pillars 106 and the conductive bumps 1072 of the photosensitive chip 107. The first pads 109 are electrically connected to the photosensitive chip 107 and the conductive pillars 106, respectively.

[0068] Secondly, a first dielectric layer 110 is formed on the first metal layer using a spin coating or spray coating process. The first dielectric layer 110 is made of a light-transmitting material. For example, the first dielectric layer 110 can be made of a high-transmittance photoresist, such as PS or PI.

[0069] The first conductive via 111 is formed by patterning processes such as exposure, development, electroplating, and etching on the first dielectric layer 110.

[0070] A plurality of second pads 112 electrically connected to the first conductive via 111 are electroplated on the first dielectric layer 110. The first pads 109, the first conductive via 111, and the second pads 112 together form a first metal layer. The first metal layer and the first dielectric layer together form a light-transmitting redistribution layer. The number of light-transmitting redistribution layers is not limited and can be selected according to actual needs.

[0071] In this embodiment, the first transparent dielectric layer 110 in the transparent dielectric layer 108 and the transparent redistribution layer replaces the thick glass in the prior art, shortening the optical path, suppressing interface reflection to reduce glare, and optimizing imaging quality.

[0072] S150. A light-transmitting insulating layer is formed on the light-transmitting redistribution layer.

[0073] like Figure 9 As shown, a light-transmitting insulating layer 113 is deposited on the first dielectric layer 110 of the first rewiring using processes such as ALD or CVD. The light-transmitting insulating layer 113 can be a SiO2 / DLC composite coating, etc. The light-transmitting insulating layer 113 has both light-transmitting and scratch-resistant functions, and serves as a solder resist layer.

[0074] In this embodiment, the light-transmitting insulating layer 113 formed on the light-transmitting redistribution layer serves as a solder resist layer with light-transmitting and scratch-resistant properties, thereby improving the reliability of the photosensitive chip packaging structure.

[0075] S160. A light-shielding layer with multiple openings is formed on the light-transmitting insulating layer, the openings corresponding to the photosensitive areas of the photosensitive chip.

[0076] The specific process of step S160 can be as follows:

[0077] like Figure 10As shown, the light-shielding layer 114 is formed on the light-transmitting insulating layer 113 by spin coating or spray coating. The light-shielding layer 114 is patterned using processes such as exposure and development to form multiple windows 114a on the light-shielding layer 114. These windows 114a correspond to the photosensitive area 1073 of the photosensitive chip 107, thereby exposing the photosensitive area 1073 of the photosensitive chip 107. The light-shielding layer 114 can be a photoresist doped with a light-shielding agent, and its formation reduces light interference.

[0078] In this embodiment, the light-shielding layer 114 and the non-transparent light-shielding substrate 101 cover the non-optical functional area to ensure the integrity of light protection throughout the entire area.

[0079] like Figure 11 As shown, a second square panel 116 is provided. The second square panel 116 is fixed to the light-shielding layer 114 with temporary bonding adhesive 115. The second square panel 116 is flipped so that the first square panel 103 is facing upward. Then the first square panel 103 is debonded and removed.

[0080] S170, A signal output layer electrically connected to the conductive pillar is formed on the second surface of the light-shielding substrate.

[0081] Among them, such as Figure 12 As shown, the process of forming the signal output layer in step S170 is as follows:

[0082] First, a redistribution layer is formed on the second surface of the light-shielding substrate, and the redistribution layer is electrically connected to the conductive pillar.

[0083] Specifically, multiple third pads 117 are formed on the conductive pillar 106 using an electroplating process, and the third pads 117 are electrically connected to the conductive pillar 106. A second dielectric layer 118 is formed on the second metal layer using a spin coating or spray coating process. The second dielectric layer 118 can be made of a non-transparent material. Second conductive vias 119 are formed on the second dielectric layer 118 through patterning processes such as exposure, development, electroplating, and etching. Multiple fourth pads 120 electrically connected to the second conductive vias 119 are formed on the second dielectric layer 118 by electroplating. The third pads 117, the second conductive vias 119, and the fourth pads 120 together constitute the second metal layer. The number of redistribution layers is not limited and can be selected according to actual needs.

[0084] Next, a solder mask layer 121 is formed on the redistribution layer. Specifically, as shown... Figure 12 As shown, a solder resist layer 121 is formed on the second dielectric layer 118 using processes such as spin coating or spray coating.

[0085] Finally, solder balls are implanted on the solder mask layer 121 to form a plurality of solder balls 122 that are electrically connected to the redistribution layer.

[0086] Specifically, the solder mask layer 121 is subjected to processes such as exposure and development to form an opening to expose the third pad 117. For example... Figure 13 As shown, multiple solder balls 122 are formed on the exposed third solder pad 117 using a ball-planting process.

[0087] In this embodiment, the signal from the photosensitive chip is extracted through the signal output layer.

[0088] Among them, such as Figure 14 As shown, after the ball-planting process is completed, the second square panel 116 is debonded to remove it.

[0089] S180. Cut according to packaging requirements to form multiple independent CIS chip packaging structures.

[0090] The packaged body formed above is cut according to the packaging requirements to form multiple packages, such as... Figure 14 The independent CIS chip package structure 100 is shown.

[0091] The CIS chip packaging method of this disclosure uses a non-transparent material as the light-shielding substrate to achieve full light shielding on the back and sides of the chip. By forming multiple conductive pillars penetrating the thickness of the light-shielding substrate and using through-holes in the light-shielding substrate instead of TSVs, the process difficulty and cost are reduced. By forming a transparent dielectric layer that wraps the photosensitive chip in the groove, the photosensitive chip is sealed without the need for additional dikes, eliminating the risk of adhesive overflow contaminating the photosensitive area of ​​the chip. The transparent dielectric layer and the transparent redistribution layer replace the thick glass in the prior art, shortening the optical path, suppressing interface reflection to reduce glare, and optimizing image quality. The transparent insulating layer formed on the transparent redistribution layer serves as a solder resist layer with light transmission and scratch resistance properties, improving the reliability of the photosensitive chip packaging structure. The light-shielding layer and the non-transparent light-shielding substrate wrap the non-optical functional areas to ensure the integrity of full light shielding.

[0092] like Figure 14 As shown, the CIS chip packaging structure 100 formed by this CIS chip packaging method includes a light-shielding substrate 101, multiple photosensitive chips 107, a light-transmitting dielectric layer 108, a light-transmitting redistribution layer, a light-shielding layer 114, and a signal output layer.

[0093] The first surface of the light-shielding substrate 101 is provided with a plurality of grooves 105, and the light-shielding substrate 101 is provided with a plurality of conductive pillars 106 extending through its thickness. Vertical interconnection of the photosensitive chips is achieved through the conductive pillars 106, reducing the package thickness. The light-shielding substrate 101 can achieve light shielding on the back and sides of the photosensitive chips.

[0094] The light-shielding substrate 101 is made of a non-transparent material. Preferably, in this embodiment, the light-shielding substrate 101 is made of a resin material, such as FR4 or BT resin. The specific material of the light-shielding substrate 101 is not specifically limited and can be selected according to actual needs.

[0095] The back sides of the plurality of photosensitive chips 107 are fixedly in the corresponding grooves 105 with their back sides facing down. Specifically, the back sides of the photosensitive chips 107 can be adhesively fixed in the corresponding grooves 105.

[0096] The orthographic projection of the photosensitive chip 107 within the groove 105 falls inside the groove 105. That is, there is a corresponding space between the outer wall of the photosensitive chip 107 and the inner wall of the groove 105. The front side of the photosensitive chip 107 has pads 1071 with conductive bumps 1072, and a photosensitive area 1073 is located in the central region of the front side of the photosensitive chip 107.

[0097] A light-transmitting dielectric layer 108 is disposed in the groove 105 and encloses the photosensitive chip 107. By directly covering the photosensitive chip 107 with the light-transmitting dielectric layer 108, a seal is achieved without the need for a dike, eliminating the risk of adhesive overflow contaminating the photosensitive area of ​​the chip and improving the reliability of the photosensitive chip 107.

[0098] A light-transmitting redistribution layer is disposed on the surface of the light-transmitting dielectric layer 108 and the first surface of the light-shielding substrate 101, and is electrically connected to the conductive pillar 106 and the photosensitive chip 107, respectively.

[0099] A light-shielding layer 114 is insulatingly disposed on the light-transmitting redistribution layer, wherein the light-shielding layer 114 has a window 114a at the photosensitive area corresponding to the photosensitive chip 107. The photosensitive area 1073 of the photosensitive chip 107 is exposed through the window 114a, ensuring the normal operation of the photosensitive chip 107.

[0100] A signal output layer is disposed on the second surface of the light-shielding substrate 101 and is electrically connected to the conductive pillar 106. The signal from the photosensitive chip 107 is extracted through the signal output layer.

[0101] The CIS chip packaging structure of this disclosure achieves full light shielding on the back and sides of the chip via a light-shielding substrate. By forming multiple conductive pillars penetrating the thickness of the light-shielding substrate and using through-holes (TSVs) instead of TSVs, the process difficulty and cost are reduced. By setting a transparent dielectric layer that wraps the photosensitive chip in the groove, the photosensitive chip is sealed without the need for additional dikes, eliminating the risk of adhesive overflow contaminating the photosensitive area of ​​the chip. In particular, the use of a transparent dielectric layer and a transparent redistribution layer instead of the thick glass in the prior art shortens the optical path, suppresses interface reflection to reduce glare, and optimizes image quality. The light-shielding layer and the light-shielding substrate cover the non-optical functional areas, ensuring the integrity of full light shielding.

[0102] For example, such as Figure 14 As shown, the CIS chip package structure 100 also includes a light-transmitting insulating layer 113. The light-transmitting insulating layer 113 is disposed between the light-transmitting redistribution layer and the light-shielding layer 114.

[0103] In this embodiment, the light-transmitting insulating layer 113 can be a SiO2 / DLC composite coating. Of course, other composite coatings can also be used for the light-transmitting insulating layer 113, and the choice can be made according to actual needs. This embodiment does not make specific limitations.

[0104] In this embodiment, a light-transmitting insulating layer 113 is provided between the light-transmitting redistribution layer and the light-shielding layer 114. The light-transmitting insulating layer 113 serves as a solder resist layer with light-transmitting and scratch-resistant properties, thereby improving the reliability of the photosensitive chip packaging structure.

[0105] For example, such as Figure 14 As shown, the surface of the light-transmitting dielectric layer 108 is flush with the first surface of the light-shielding substrate 101 to facilitate subsequent wiring on the first surface of the light-shielding substrate 101 and the surface of the light-transmitting dielectric layer 108. The surface of the light-transmitting dielectric layer 108 exposes the conductive bumps 1072 of the photosensitive chip 107. The photosensitive chip 107 is electrically connected to the light-transmitting redistribution layer through the conductive bumps 1072.

[0106] For example, in this embodiment, the light-transmitting dielectric layer 108 can be formed using a high-transmittance photoresist material, such as PS or PI. The specific material of the light-transmitting dielectric layer 108 is not specifically limited and can be selected according to actual needs.

[0107] For example, the light-shielding substrate 101 is provided with a plurality of through holes penetrating its thickness, and the conductive pillar 106 is disposed in the through holes. In this embodiment, substrate through holes are used instead of the existing TSV, reducing the difficulty and cost of the process.

[0108] For example, such as Figure 14As shown, the light-transmitting redistribution layer includes a first dielectric layer 110 and a first metal layer. The first metal layer is disposed on the surface of the light-transmitting dielectric layer 108 and the first surface of the light-shielding substrate 101, and is electrically connected to the conductive pillar 106 and the conductive bump 1072 of the photosensitive chip 107, respectively.

[0109] The first dielectric layer 110 is disposed on the first metal layer. The first dielectric layer 110 is formed by using a light-transmitting material. For example, the first dielectric layer 110 can be made of a highly light-transmitting photoresist, such as PS or PI.

[0110] Specifically, the first metal layer includes a plurality of first pads 109, a plurality of first conductive vias 111, and a plurality of second pads 112. The plurality of first pads 109 are respectively disposed on the surface of the light-transmitting dielectric layer 108 and the first surface of the light-shielding substrate 101, and are electrically connected to the conductive pillars 106 and the conductive bumps 1072 of the photosensitive chip 107, respectively.

[0111] The first conductive via 111 passes through the first dielectric layer 110 and is electrically connected to the first pad 109. A plurality of second pads 112 are disposed on the first dielectric layer 110 and electrically connected to their corresponding first conductive vias 111. The number of light-transmitting redistribution layers is not limited and can be selected according to actual needs.

[0112] In this embodiment, the light-transmitting dielectric layer 108 and the light-transmitting redistribution layer replace the thick glass in the prior art, shortening the optical path, suppressing interface reflection to reduce glare, and optimizing imaging quality.

[0113] For example, the signal output layer includes a redistribution layer, a solder mask layer 121, and a plurality of solder balls 122. The redistribution layer is disposed on the second surface of the light-shielding substrate 101; the solder mask layer 121 is disposed on the redistribution layer; and the plurality of solder balls 122 are disposed on the redistribution layer and electrically connected to the redistribution layer.

[0114] like Figure 14 As shown, the redistribution layer includes a second metal layer and a second dielectric layer 118. The second metal layer includes a plurality of third pads 117, a plurality of second conductive vias 119, and a plurality of fourth pads 120. The plurality of third pads 117 are disposed on the second surface of the light-shielding substrate 101 and are electrically connected to the conductive pillars 106. The second conductive vias 119 pass through the second dielectric layer 118 and are electrically connected to the third pads 117. The plurality of fourth pads 120 are disposed on the second dielectric layer 118 and are electrically connected to the second conductive vias 119. In this embodiment, the second dielectric layer 118 may be made of a non-transparent material.

[0115] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the embodiments of this disclosure, and the embodiments of this disclosure are not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of this disclosure, and these modifications and improvements are also considered to be within the protection scope of the embodiments of this disclosure.

Claims

1. A CIS chip packaging method, characterized by, The method comprises: providing a light-shielding substrate and forming a plurality of conductive columns penetrating through the thickness of the light-shielding substrate; forming a plurality of grooves on the first surface of the light-shielding substrate, and fixing a plurality of back surfaces of photosensitive chips downward in the corresponding grooves, wherein the orthographic projection of the photosensitive chip in the groove falls inside the groove; forming a light-transmitting dielectric layer wrapping the photosensitive chip in the groove; forming a light-transmitting redistribution layer on the surface of the light-transmitting dielectric layer and the first surface of the light-shielding substrate, the light-transmitting redistribution layer being electrically connected with the photosensitive chip and the conductive column respectively; forming a light-transmitting insulating layer on the light-transmitting redistribution layer; forming a light-shielding layer with a plurality of windows on the light-transmitting insulating layer, the windows corresponding to the photosensitive area of the photosensitive chip; forming a signal output layer electrically connected with the conductive column on the second surface of the light-shielding substrate; cutting according to packaging requirements to form a plurality of independent CIS chip packaging structures.

2. The method of claim 1, wherein, The method further comprises: providing a first square panel, fixing the light-shielding substrate on the first square panel, and forming the conductive column on the light-shielding substrate; wherein, after forming the light-shielding layer, the method further comprises: removing the first square panel.

3. The method of claim 1, wherein, The method of forming a plurality of conductive columns penetrating through the thickness of the light-shielding substrate comprises: forming a plurality of through holes penetrating through the thickness of the light-shielding substrate on the light-shielding substrate; filling the through holes with conductive material to form the conductive column.

4. The method of claim 3, wherein, The method further comprises: forming a plurality of grooves on the light-shielding substrate before filling the through holes with conductive material.

5. The method according to any one of claims 1 to 4, characterized in that, The method of forming a light-transmitting dielectric layer wrapping the photosensitive chip in the groove comprises: adopting a spin coating or spraying process to form a light-transmitting dielectric layer wrapping the photosensitive chip in the groove; grinding and thinning the light-transmitting dielectric layer to expose the conductive bumps of the photosensitive chip.

6. The method of claim 5, wherein, The surface of the formed light-transmitting dielectric layer is flush with the first surface of the light-shielding substrate.

7. The method according to any one of claims 1 to 4, characterized in that, The method of forming a light-transmitting redistribution layer on the surface of the light-transmitting dielectric layer and the first surface of the light-shielding substrate comprises: forming a first metal layer on the surface of the light-transmitting dielectric layer and the first surface of the light-shielding substrate, the first metal layer being electrically connected with the photosensitive chip and the conductive column respectively; forming a first dielectric layer on the first metal layer, the first dielectric layer adopting a light-transmitting material.

8. The method according to any one of claims 1 to 4, characterized in that, The method of forming a light-shielding layer with a plurality of windows on the light-transmitting insulating layer comprises: forming the light-shielding layer on the light-transmitting insulating layer by a spin coating or spraying process; performing patterning on the light-shielding layer to form a plurality of windows on the light-shielding layer, the windows corresponding to the photosensitive area of the photosensitive chip.

9. The method according to any one of claims 1 to 4, characterized in that, After forming the light-shielding layer, the method further comprises: providing a second square panel, and fixing the second square panel on the light-shielding layer; After forming the signal output layer, the method further comprises: removing the second square panel.

10. The method according to any one of claims 1 to 4, characterized in that, The method of forming a signal output layer electrically connected with the conductive column on the second surface of the light-shielding substrate comprises: A redistribution layer is formed on the second surface of the light shielding substrate, and the redistribution layer is electrically connected with the conductive column; A solder resist layer is formed on the redistribution layer; Ball planting is performed on the solder resist layer to form a plurality of solder balls electrically connected with the redistribution layer.

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