Method for batch precision chip mounting

Abstract

The application provides a batch precise chip pasting method, comprising: pasting an integral piece of to-be-pasted chips on a base film, the base film being provided with a boss structure, and the top surface of the boss structure being provided with a first alignment mark; cutting the to-be-pasted chips based on the chip layout on a target wafer to form a plurality of independent chips on the base film; aligning the cut to-be-pasted chips with the target wafer, wherein the alignment is achieved by aligning the first alignment mark on the top surface of the boss structure of the base film with a second alignment mark on the target wafer; pasting the plurality of chips on the base film on the target wafer; and removing the base film. The application realizes super-high-precision optical alignment and solves the technical problem of direct alignment between thick chip wafers.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit design and manufacturing, and in particular relates to a method for batch and precise chip mounting. Background Technology

[0002] In the field of semiconductor chip packaging, especially in the manufacturing of magnetic sensing chips (such as Hall sensors), in order to improve the sensor's sensitivity and directional detection capabilities, such as reducing inter-axis crosstalk, it is usually necessary to precisely mount a magnet (which can be regarded as a functional chip) on the sensing chip. The positional accuracy of the magnet directly determines the sensor's performance indicators, such as Z-axis isolation.

[0003] However, even relatively sophisticated equipment can only achieve a positional accuracy of approximately ±10 micrometers in conventional semiconductor mounting processes, which is insufficient for more precise designs. For example, with the development of Hall effect technology, the design of magnets has become increasingly complex and precise, and product performance is more sensitive to mounting errors. To achieve good sensitivity and reduce crosstalk, the horizontal error requirement for the magnet mounting is ±2 micrometers. High-precision mounting equipment cannot meet this requirement, making it difficult to overcome the low device yield problem under traditional processes.

[0004] Therefore, there is an urgent need for a new method that can achieve high-precision and high-efficiency chip mounting at the wafer level without relying on improving the ultimate precision of single-chip mounting equipment.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for batch and precise chip mounting, which solves the problem that it is difficult to improve the chip mounting accuracy in the prior art.

[0007] To achieve the above and other related objectives, the present invention provides a method for batch precise chip mounting, the method comprising the steps of: attaching a whole chip to be mounted onto a substrate film, the substrate film having a protrusion structure and a first alignment mark on the top surface of the protrusion structure; cutting the chip to be mounted based on the chip layout on a target wafer to form multiple independent chips on the substrate film; aligning the cut chip to be mounted with the target wafer, wherein the alignment operation is achieved by aligning the first alignment mark on the top surface of the protrusion structure of the substrate film with a second alignment mark on the target wafer; mounting the multiple chips on the substrate film onto the target wafer; and removing the substrate film.

[0008] Optionally, the basement membrane is made of a rigid or semi-rigid material, or / and the basement membrane is made of a transparent or semi-transparent material.

[0009] Optionally, the height of the boss structure is equal to the thickness of the chip to be mounted, so that the first alignment mark and the second alignment mark are attached during alignment.

[0010] Alternatively, alignment can be performed under a microscope by observing the first alignment mark on the boss structure and the second alignment mark on the target wafer.

[0011] Optionally, the boss structure is integrally formed with the base membrane, or the boss structure is bonded to the base membrane with additional materials.

[0012] Optionally, the first alignment mark is formed on the top surface of the boss structure by one or more of photolithography, etching, printing and deposition processes.

[0013] Optionally, the chip to be mounted is cut using the first alignment mark as a position reference.

[0014] Optionally, cutting the chip to be mounted includes: cutting along a first direction to form a plurality of first cutting stripes; cutting along a second direction to form a plurality of second cutting stripes, so that the entire chip to be mounted is divided into a plurality of independent chips.

[0015] Optionally, the first direction and the second direction are perpendicular to each other, and after cutting, multiple rectangular or square chips are formed.

[0016] Optionally, the first direction and the second direction are not at a 90-degree angle, and after cutting, multiple rhomboid or parallelogram-shaped chips are formed.

[0017] Optionally, when cutting the chip to be mounted, the distance between two adjacent chips is defined by the thickness of the cutting blade, and the width of the chip is defined by the edge of the cutting position of two adjacent cutting blades.

[0018] Optionally, mounting multiple chips on a substrate film onto a target wafer includes: applying an adhesive layer to the surface of the target wafer before the alignment step; and after the alignment step, pressing the chips to be mounted on the substrate film onto the target wafer and curing the adhesive layer through a curing process.

[0019] Optionally, the adhesive layer is a strong adhesive liquid, and the curing method includes heat curing or ultraviolet light curing.

[0020] Optionally, removing the base film includes peeling off the base film by softening the adhesive layer between the base film and the chip through heating or chemical treatment.

[0021] Optionally, the entire chip to be mounted is a magnet chip wafer, and the target wafer is a Hall sensor wafer.

[0022] As described above, the method for batch precise chip placement of the present invention has the following beneficial effects:

[0023] This invention transforms the individual chip mounting process into whole-chip array mounting, shifting the alignment accuracy from relying on the mechanical movement precision of the pick-and-place machine to relying on the precision of wafer dicing and the optical alignment system. The recognition accuracy of optical alignment systems (such as microscopes) is far higher than that of mechanical positioning, thus fundamentally breaking through the precision bottleneck of traditional processes. This invention can significantly reduce mounting errors from the tens of micrometers level to the micrometer level.

[0024] Because the chips to be mounted (such as magnets) are typically thick (tens to hundreds of micrometers) and opaque, if the alignment marks are made on the chip itself, there will be a height difference between the marks and the target wafer during alignment, making it impossible to image them clearly simultaneously within the same microscope depth of field, resulting in alignment difficulties. This invention innovatively sets a raised structure on the substrate film at the same height as the chip, and fabricates the alignment marks on the surface of the raised structure. This allows the alignment marks of the two wafers to be on the same focal plane during alignment, enabling clear and synchronous observation, achieving ultra-high precision optical alignment, and solving the technical challenge of direct alignment between thick chip wafers.

[0025] This invention, by precisely controlling the thickness and feed spacing of the dicing blade, can directly dice chip arrays with specific dimensions and spacing onto a whole wafer. The thickness of the dicing blade determines the edge distance between adjacent chips, and the feed spacing determines the chip width and the center distance between adjacent chips. This ensures that the relative positions of all chips are determined during the dicing process, with accuracy guaranteed by the dicing machine's precision. This accuracy is far higher than the position repeatability precision of individual placement, thus guaranteeing the inherent precision of the chip spacing.

[0026] The materials (base film, etc.) and processes (such as spin coating, exposure, cutting, and lamination) used in this invention are compatible with standard semiconductor processes and are easy to integrate into existing production lines. Furthermore, full-surface mounting improves efficiency by tens to hundreds of times compared to single-chip mounting, making it particularly suitable for large-scale production. This invention combines high precision and high throughput, effectively reducing manufacturing costs. Attached Figure Description

[0027] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the embodiments of this application and to illustrate the implementation of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application.

[0028] Figure 1The diagram shows a step flow chart of a method for batch precise chip mounting according to an embodiment of the present invention.

[0029] Figures 2-9 The diagram shows the structural schematics of each step in the method for batch precise chip mounting according to an embodiment of the present invention.

[0030] Component labeling description: 10 Hall sensor, 11 base film, 111 boss structure, 112 first alignment mark, 12 magnet chip wafer, 121 magnet chip, 13 dicing blade, 131 dicing track, 14 Hall sensor wafer, steps S11~S15. Detailed Implementation

[0031] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0032] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0033] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0034] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0035] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0036] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0037] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0038] like Figures 1-9 As shown, this embodiment provides a method for batch precise chip mounting. In one embodiment, the method is illustrated using a magnetizing chip wafer 12 as the whole chip to be mounted and a Hall sensor wafer 14 as the target wafer. For the horizontal magnetic field detection of the Hall sensor, as... Figure 2 As shown, in the horizontal magnetic deflection design of the Hall sensor 10 pair, the corners of the two magnetic chips 121 shown are required to be adjacent to and coincide with the outer corners of the Hall sensor 10. Generally, the mounting of the magnetic chips 121 in the self-rotation direction can better ensure accuracy, so the Hall sensor can achieve high accuracy in the detection direction. However, due to limitations in mechanical precision and repeatability, the mounting position of the magnetic chips 121 will have an uncertainty of several micrometers to tens of micrometers, which will bring z-axis crosstalk, resulting in reduced z-axis isolation and increased signal error. The batch precision chip mounting method provided by this invention can reduce the positional error of the magnetic chips 121 to within micrometers, greatly improving z-axis isolation and reducing z-axis crosstalk. It should be noted that this method will also bring significant advantages in improving production efficiency and achieving high-precision mounting for the bonding of other types of chips on the entire wafer that require precise mounting, such as MEMS packaging and silicon photonics device packaging.

[0039] like Figures 1-9 As shown, the method for batch precise chip mounting in this embodiment includes the following steps:

[0040] like Figures 1-3 As shown, step S11 is performed first, where the entire chip to be mounted is attached to a base film 11. The base film 11 has a boss structure 111, and a first alignment mark 112 is provided on the top surface of the boss structure 111.

[0041] In one embodiment, the basement membrane 11 is made of a rigid or semi-rigid material, or / and the basement membrane 11 is made of a transparent or semi-transparent material.

[0042] In one embodiment, the height of the boss structure 111 is equal to the thickness of the chip to be mounted, so that the first alignment mark 112 and the second alignment mark are attached during alignment. Since the chip to be mounted (such as a magnet) is typically thick (tens to hundreds of micrometers) and opaque, if the alignment mark is made on the chip, there will be a height difference between the two marks when aligned with the target wafer, making it impossible to image clearly simultaneously within the same microscope depth of field, leading to alignment difficulties. This invention innovatively sets a boss structure 111 on the base film 11 with the same height as the chip, and fabricates the alignment mark on the surface of the boss structure 111, so that during alignment, the alignment marks of the two wafers can be in the same focal plane, thus allowing for clear and synchronous observation, achieving ultra-high precision optical alignment, and solving the technical problem of direct alignment between thick chip wafers.

[0043] In one embodiment, the boss structure 111 is integrally formed with the base membrane 11, or the boss structure 111 is bonded to the base membrane 11 by means of an additional material. The additional material may be the same as the base membrane 11, or it may be a different rigid or semi-rigid material. The boss structure 111 is preferably made of a transparent or semi-transparent material.

[0044] In one embodiment, the boss structure 111 can be arranged in a ring around the entire chip to be mounted, or it can be arranged in a columnar shape around the entire chip to be mounted.

[0045] In one embodiment, the first alignment mark 112 may be cross-shaped, star-shaped, L-shaped, square-shaped, etc., and is not limited to the examples listed herein. The first alignment mark 112 is preferably equal in shape and size to the second alignment mark on the target wafer, so as to ensure more precise alignment of the first alignment mark 112 and the second alignment mark.

[0046] In one embodiment, the first alignment mark 112 is formed on the top surface of the boss structure 111 by one or more of photolithography, etching, printing and deposition processes.

[0047] In a specific example, the entire chip to be mounted is a polymagnetic chip wafer 12. The material of the polymagnetic chip wafer 12 can be NiFe (permalloy), and its thickness can be 50 micrometers to 300 micrometers. The substrate film 11 can be a rigid transparent die-attach film (DAF), glass, polycarbonate, or a semi-rigid polyolefin film, etc., and its thickness can be, for example, 100 micrometers to 500 micrometers. A heat-release adhesive film is coated on the back of the polymagnetic chip wafer 12 and then attached to the transparent die-attach film (DAF). Of course, the material of the polymagnetic chip wafer 12 can also be FeSiAl, etc.

[0048] like Figure 1 and Figures 4-6As shown, then step S12 is performed, whereby the chip to be mounted is cut based on the chip layout on the target wafer to form multiple independent chips on the substrate film 11.

[0049] In one embodiment, the chip to be mounted is cut using the first alignment mark 112 as a position reference. This invention, by using the first alignment mark 112 as a position reference for cutting the chip to be mounted, can significantly improve cutting accuracy.

[0050] In one embodiment, cutting the chip to be mounted includes: cutting along a first direction to form a plurality of first cutting stripes; cutting along a second direction to form a plurality of second cutting stripes, so that the entire chip to be mounted is divided into a plurality of independent chips.

[0051] In one embodiment, the first direction and the second direction are perpendicular to each other, and after cutting, multiple rectangular or square chips are formed.

[0052] In one embodiment, the first direction and the second direction are not at a 90-degree angle, and after cutting, multiple rhomboid or parallelogram-shaped chips are formed.

[0053] In one embodiment, such as Figure 4 As shown, when cutting the chip to be mounted, the thickness of the cutting blade 13 defines the edge distance D1 between two adjacent chips, and the edge of the cutting position of two adjacent cutting blades 13 defines the chip width D2 and the distance D3 between the centers of two adjacent chips. D1 and D2 have an adjacent edge. Meanwhile, from... Figure 4 It can be seen that D3 = D1 + D2. For example, the material of the cutting blade 13 can be diamond, and the thickness of the cutting blade 13 can be 10 micrometers to 50 micrometers.

[0054] In some embodiments, the cutting depth of the dicing blade 13 is preferably equal to the thickness of the chip to be mounted, or slightly greater than the thickness of the chip to be mounted. For example, the cutting depth can be 1 micrometer to 5 micrometers greater than the thickness of the chip to be mounted, so as to ensure the strength of the base film 11 after cutting and prevent it from cracking.

[0055] In some embodiments, an air extraction or rinsing step may be added during the dicing process to reduce contamination of the wafer during dicing.

[0056] In a specific example, for rectangular and array-type magnetizers (chips), the main parameters are the length, width, and the spacing along the x and y axes. After determining these parameters according to the chip design, precise processing is performed using a dicing blade 13. The thickness of the dicing blade 13 can be selected to be equal to the edge distance between two adjacent chips, allowing the required edge distance to be cut in a single cut. If the required edge distance is large, it can be removed by two or more cuts to meet the edge distance requirement. After cutting in one direction, the magnetizer chip wafer 12 is rotated 90 degrees and then cut again using a dicing blade 13 with the same edge distance as the two adjacent chips in that direction to create a rectangular chip array of the specified size and edge distance.

[0057] In another specific instance, when an array of diamond-shaped chips is required, such as... Figure 5 As shown. Its process flow is basically the same as cutting a rectangular chip array. During cutting, simply adjust the cutting angle to the required design value. Additionally, it is worth noting that the utilization rate of the cut magnet chip 121 is only about half. For example... Figure 5 As shown, the magnetizing chips 121 with black dots in the middle are the required magnetizing chips, and the adjacent parts without black dots need to be removed. For example, magnetizing chips 121 that do not correspond to chips on the wafer can be removed using a pick-and-place machine. The result after removal is a matrix of magnetizing chips 121 arranged as shown in the dashed box, which corresponds to the chip (black dot) positions on the Hall sensor wafer 14.

[0058] In a specific example, after cutting in one direction with a spacing d between two adjacent dicing lines 131, the magnetizer chip wafer 12 is rotated 60 degrees, and cutting continues with a spacing d between two adjacent dicing lines 131. After completion, the resulting magnetizer is a rhombus with interior angles of 60 degrees and 120 degrees. The resulting array spacing ratio is 1: . Figure 5 The center-to-center distance between two adjacent magnet chips 121 in the x-direction is 2d, and the center-to-center distance in the y-direction is... The array of magnet chips 121 can be obtained by removing a row of magnet chips 121 at intervals.

[0059] like Figures 7-8 As shown, step S13 is then performed to align the cut chip to be mounted with the target wafer. The alignment operation is achieved by aligning the first alignment mark 112 on the top surface of the protrusion structure 111 of the substrate film 11 with the second alignment mark on the target wafer.

[0060] In one embodiment, alignment is performed under a microscope by observing the first alignment mark 112 on the boss structure 111 with the second alignment mark on the target wafer.

[0061] In one specific example, the cut magnet chip 121 and base film 11 assembly are flipped 180 degrees and placed upside down on top of the Hall sensor wafer 14. The position is adjusted by a precision workpiece stage, and under a microscope, the first alignment mark 112 on the protrusion of the base film 11 is precisely aligned with the corresponding second alignment mark on the Hall sensor wafer 14, with an alignment accuracy on the order of ±1 micrometer.

[0062] like Figures 7-8 As shown, then step S14 is performed to mount multiple chips on the base film 11 onto the target wafer;

[0063] In one embodiment, mounting multiple chips on the base film 11 onto a target wafer includes: before the alignment step, applying an adhesive layer to the surface of the target wafer; after the alignment step, pressing the chips to be mounted on the base film 11 onto the target wafer, and curing the adhesive layer through a curing process.

[0064] In one embodiment, the adhesive layer is a strong adhesive liquid, and the curing method includes heat curing or ultraviolet light curing.

[0065] like Figure 9 As shown, the final step is S15, in which the basement membrane 11 is removed.

[0066] In one embodiment, removing the base film 11 includes peeling off the base film 11 by softening the adhesive layer between the base film 11 and the chip through heating or chemical treatment.

[0067] For example, the entire assembly can be heated to above 100°C, causing the adhesive layer between the base film 11 and the magnet chip 121 to lose its adhesiveness, thereby peeling off the base film 11 and the protrusion structure 111. It should be noted that the adhesive layer between the target wafer and the magnet chip 121 is preferably a permanently adhesive material, or an adhesive material that requires heating to a higher temperature to lose its adhesiveness, to ensure that the adhesive layer loses its adhesiveness without affecting the adhesion between the target wafer and the magnet chip 121.

[0068] As described above, the method for batch precise chip placement of the present invention has the following beneficial effects:

[0069] This invention transforms the individual chip mounting process into whole-chip array mounting, shifting the alignment precision from relying on the mechanical movement precision of the pick-and-place machine to relying on the precision of wafer dicing and the optical alignment system. The recognition precision of the optical alignment system (such as a microscope) is far higher than that of the mechanical positioning precision, thus fundamentally breaking through the precision bottleneck of traditional processes. This invention can significantly reduce the mounting error from the ±10 micrometer range to the ±1 micrometer or even submicrometer range.

[0070] Since the chips to be mounted (such as magnets) are typically thick (tens to hundreds of micrometers) and opaque, if the alignment marks are made on the chip, there will be a height difference between the marks and the target wafer during alignment, making it impossible to image them clearly at the same microscope depth of field, resulting in alignment difficulties. This invention innovatively sets a protrusion structure 111 on the base film 11 at the same height as the chip, and fabricates the alignment marks on the surface of the protrusion structure 111. This allows the alignment marks of the two wafers to be on the same focal plane during alignment, enabling clear and synchronous observation, achieving ultra-high precision optical alignment, and solving the technical problem of direct alignment between thick chip wafers.

[0071] This invention, by precisely controlling the thickness and feed spacing of the dicing blade 13, can directly dice chip arrays with specific dimensions and spacing onto a whole wafer. The thickness of the dicing blade 13 determines the edge distance between two adjacent chips, and the feed spacing determines the chip width and the center distance between adjacent chips. This ensures that the relative positions of all chips are determined during the dicing process, with accuracy guaranteed by the dicing machine's precision. This accuracy is far higher than the position repeatability precision of individual placement, thus guaranteeing the inherent precision of the chip spacing.

[0072] The materials (base film 11, etc.) and processes (such as spin coating, exposure, cutting, and lamination) used in this invention are compatible with standard semiconductor processes and are easy to integrate into existing production lines. Furthermore, full-surface mounting improves efficiency by tens to hundreds of times compared to single-chip mounting, making it particularly suitable for large-scale production. This invention combines high precision and high throughput, effectively reducing manufacturing costs.

[0073] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0074] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for batch precise chip mounting, characterized in that, The method includes the following steps: The entire chip to be mounted is attached to a base film, the base film having a boss structure, and a first alignment mark is provided on the top surface of the boss structure; Based on the chip layout on the target wafer, the chip to be mounted is cut to form multiple independent chips on the substrate film; The cut chip to be mounted is aligned with the target wafer, wherein the alignment operation is achieved by aligning the first alignment mark on the top surface of the protrusion structure of the substrate film with the second alignment mark on the target wafer; Multiple chips on the base film are mounted onto the target wafer; as well as Remove the basement membrane; The height of the boss structure is equal to the thickness of the chip to be mounted, so that the first alignment mark and the second alignment mark are attached during alignment; the alignment is performed under a microscope, and alignment is achieved by observing the first alignment mark on the boss structure and the second alignment mark on the target wafer.

2. The method for batch precise chip mounting according to claim 1, characterized in that: The base membrane is made of a rigid or semi-rigid material, or / and the base membrane is made of a transparent or semi-transparent material.

3. The method for batch precise chip mounting according to claim 1, characterized in that: The boss structure is integrally formed with the base film, or the boss structure is bonded to the base film by additional materials; or / and the first alignment mark is formed on the top surface of the boss structure by one or more of photolithography, etching, printing and deposition processes.

4. The method for batch precise chip mounting according to claim 1, characterized in that: The chip to be mounted is cut using the first alignment mark as a position reference.

5. The method for batch precise chip mounting according to claim 1, characterized in that: Cutting the chip to be mounted includes: Multiple first cutting stripes are formed by cutting along a first direction; Multiple second cutting stripes are formed by cutting along the second direction, so that the entire chip to be mounted is divided into multiple independent chips; Wherein, the first direction and the second direction are perpendicular to each other, and after cutting, multiple rectangular chips are formed; or the first direction and the second direction are not at a 90-degree angle, and after cutting, multiple parallelogram chips are formed.

6. The method for batch precise chip mounting according to claim 1, characterized in that: When cutting the chip to be mounted, the distance between two adjacent chips is defined by the thickness of the cutting blade, and the width of the chip is defined by the edge of the cutting position of two adjacent cutting blades.

7. The method for batch precise chip mounting according to claim 1, characterized in that: Mounting multiple chips from a base film onto the target wafer includes: Prior to the alignment step, an adhesive layer is applied to the surface of the target wafer; After the alignment step, the chip to be mounted on the base film is pressed onto the target wafer, and the adhesive layer is cured by a curing process.

8. The method for batch precise chip mounting according to claim 7, characterized in that: The adhesive layer is a strong adhesive liquid, and the curing method includes heat curing or ultraviolet light curing; and / or removal of the base film includes softening the adhesive layer between the base film and the chip by heating or chemical treatment, thereby peeling off the base film.

9. The method for batch precise chip mounting according to claim 1, characterized in that: The entire chip to be mounted is a magnet chip wafer, and the target wafer is a Hall sensor wafer.

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