A stack-up and method of manufacture for large size package substrates

Abstract

The application discloses a kind of for large size package substrate's superstructure and manufacturing method, comprising: first core plate, first core plate upper and lower surface is provided with vertical spacer;Additional core plate is stacked on the first core plate, and the additional core plate is at least provided with one;First via hole is opened in the vertical direction of the intermediate core, and the first via hole is filled with insulating material;Second via hole is penetrated in the first via hole, additional core plate, vertical spacer and first core plate;Wherein, the vertical spacer thickness is greater than or equal to 50 μm;Additional core plate includes second core plate and / or third core plate, and second core plate and / or third core plate are stacked on the upper and lower surfaces of first core plate.The application is heterogeneous stacking by high-rigidity glass core plate and BT core plate, linear shrinkage of PP material is constrained during cooling process, and the design of vertical spacer thickness greater than or equal to 50 μm provides stress buffer interface, to reduce interlaminar shear force.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging substrate manufacturing technology, and in particular to a stacking and manufacturing method for large-size packaging substrates. Background Technology

[0002] In recent years, with the rapid development of semiconductor technology, especially the miniaturization of semiconductor manufacturing processes and the widespread application of artificial intelligence (AI) technology, the production of large chips has placed higher demands on packaging materials, processes, and the supply chain. However, a major challenge needs to be faced when developing fabrication processes for large-size packaging substrates:

[0003] Warpage control is difficult: Large-size carrier boards are prone to warpage during manufacturing due to material stress or temperature changes, which can affect assembly and signal transmission performance.

[0004] Therefore, this paper proposes a stacking and manufacturing method suitable for large-size packaging substrates, and combines material properties to solve the warpage problem of large-size substrates. Summary of the Invention

[0005] This invention proposes a stacked structure for large-size packaging substrates. By using multiple layers of high-hardness core boards, the overall hardness of the packaging substrate is enhanced, thus avoiding the problem of warping in large-size substrates.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] A stacked structure for large-size packaging substrates includes:

[0008] The first core board has vertical spacers spaced between its upper and lower surfaces.

[0009] An additional core board is stacked on the first core board, at least one of which is provided, and an intermediate core is provided at the middle position of the additional core board;

[0010] A first through hole is formed on the intermediate core and along the vertical direction of the intermediate core; the first through hole is filled with insulating material;

[0011] A second through hole that passes through the first through hole, the additional core plate, the vertical spacer, and the first core plate;

[0012] The thickness of the vertical spacer is ≥50μm.

[0013] The additional core board includes a second core board and / or a third core board, which are symmetrically stacked on the upper and lower sides of the first core board.

[0014] As a preferred embodiment of the stacked structure for large-size packaging substrates described in this invention, wherein:

[0015] The first core board is a copper-free BT core board, and the additional core board is a glass core substrate;

[0016] As a preferred embodiment of the stacked structure for large-size packaging substrates described in this invention, wherein:

[0017] The combination of the first core board and the additional core board includes, but is not limited to: solder ball connection, blind hole electroplating connection, copper pillar connection, and conductive connection.

[0018] As a preferred embodiment of the stacked structure for large-size packaging substrates described in this invention, wherein:

[0019] The number of layers in the first core board is greater than the number of layers in the additional core board;

[0020] As a preferred embodiment of the stacked structure for large-size packaging substrates described in this invention, wherein:

[0021] The line width and spacing in the first core board are less than the line width and spacing in the additional core board; the thickness of the circuit and solder pads in the first core board are less than the thickness of the circuit and solder pads in the additional core board.

[0022] As a preferred embodiment of the stacked structure for large-size packaging substrates described in this invention, wherein:

[0023] The thickness of the vertical spacer is 50~300μm.

[0024] As a preferred embodiment of the stacked structure for large-size packaging substrates described in this invention, wherein:

[0025] The diameter of the first through hole is larger than the diameter of the second through hole.

[0026] A method for manufacturing a stacked structure for a large-size packaging substrate, applied to the aforementioned stacked structure for a large-size packaging substrate, includes the following steps:

[0027] Step S1: Stack additional core boards on the first core board; wherein, the intermediate core of the additional core board is provided with a first through hole along the vertical direction of the intermediate core.

[0028] Step S2: Inject polypropylene into the first through hole;

[0029] Step S3: Drill holes along the central axis of the first through hole to form a second through hole, including the first through hole, the additional core plate, the vertical spacer, and the first core plate; wherein the diameter of the second through hole is smaller than the diameter of the first through hole.

[0030] Step S4: Insulating ink is injected into the second through hole, and chemical copper plating is performed;

[0031] Step S5: Etch the copper plate stacked on the surface of the additional core board and the first core board;

[0032] Step S6: Perform multiple ABF layering and SAP patterning on the surfaces of the additional core board and the first core board.

[0033] As a preferred embodiment of the manufacturing method for the stacked structure of large-size packaging substrates described in this invention, wherein:

[0034] In step S1, the additional core board is stacked on the upper and lower sides of the first core board, and the additional core board includes a second core board and / or a third core board.

[0035] As a preferred embodiment of the manufacturing method for the stacked structure of large-size packaging substrates described in this invention, wherein:

[0036] In step S1, when the second core board and the third core board are stacked on the first core board, the second core board is first laminated and its first through hole is filled, and then the third core board is laminated and its first through hole is filled.

[0037] The beneficial effects of this invention are:

[0038] 1. The present invention provides a stacked structure for large-size packaging substrates. By heterogeneously stacking a high-rigidity glass core substrate and a BT core board, the linear shrinkage of PP material during the cooling process is constrained. At the same time, the design of vertical spacer thickness ≥50μm provides a stress buffer interface, thereby reducing interlayer shear force.

[0039] 2. The present invention provides a stacked structure for large-size packaging substrates. In its manufacturing process, the sequence of filling the first through-hole (PP) and then drilling the second through-hole ensures that a complete copper plating layer is formed on the inner wall of the through-hole, preventing the chemical copper plating solution from seeping into the glass fiber. Simultaneously, for large-size substrates (e.g., 80mm × 80mm), the double-sided stacked three-core board structure can control the warpage to ≤0.15mm / m, thereby controlling the warpage of large-size substrates. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the structure of a first core board for a large-size packaging substrate according to an embodiment of the present invention;

[0041] Figure 2 This is a schematic diagram of the structure in step S1 of the stacking process for a large-size packaging substrate, provided in an embodiment of the present invention.

[0042] Figure 3 This is a schematic diagram of the structure in step S3 of the stacking process for a large-size packaging substrate, provided in an embodiment of the present invention.

[0043] Figure 4This is a schematic diagram of a stacked structure for a large-size packaging substrate provided in one embodiment of the present invention;

[0044] Figure 5 This is a schematic diagram of a stacked structure for a large-size packaging substrate, provided as another embodiment of the present invention.

[0045] Figure label:

[0046] 100. First core board; 200. Additional core board; 201. Intermediate core;

[0047] 210, First through hole; 220, Vertical spacer; 230, Second through hole; 240, Second core board; 250, Third core board. Detailed Implementation

[0048] To make the above-mentioned objectives, features, and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. It should be particularly noted that the process parameters, material types, and structural dimensions involved in the embodiments of the present invention are all based on actual mass production feasibility verification. Its core innovation lies in achieving stress synergistic control through the precise coupling design of heterogeneous material stacking (such as a combination of low CTE glass core board and BT core board with a specific CTE range) and through-hole size (especially the diameter difference between the first through-hole 210 and the second through-hole 230 and the vertical spacer 220 formed therein), effectively managing the interfacial stress caused by the difference in the coefficient of thermal expansion (CTE) of materials and curing shrinkage, rather than simply superimposing existing technologies.

[0049] In recent years, with the rapid development of semiconductor technology, especially the miniaturization of semiconductor processes (such as entering 5nm and below nodes) and the widespread application of artificial intelligence (AI) technologies (such as large-scale neural network training and inference), the demand for high computing power and high bandwidth has surged, directly driving a significant increase in chip size and substrate area. The production of large chips has placed higher demands on packaging materials, processes, and the supply chain. Taking AI accelerator cards as an example, their substrate size has generally exceeded 80mm×80mm (and is even developing towards 110mm×110mm). However, traditional FR-4 substrates at this size are limited by their high CTE (approximately 14-16ppm / ℃) and low modulus, and their warpage tolerance is only 0.25mm / m (measured according to IPC-TM-650 2.2.22 standard). This is far from meeting the stringent requirements of substrate coplanarity for high-precision flip chip bonding below 5μm, which can easily lead to fatal defects such as solder joint bridging or open circuits. However, developing fabrication processes for large-size packaging substrates presents a significant challenge: warpage control is difficult. During manufacturing (especially high-temperature processes such as lamination and curing), large-size substrates are prone to complex three-dimensional warpage deformations (such as protrusions, depressions, or twists) due to material stress (such as resin curing shrinkage stress, heterogeneous material CTE mismatch stress) or temperature changes (such as thermal cycling). This can affect the accuracy of subsequent die attach, the eutectic reliability of solder bumps, and the signal transmission performance of fine lines (such as signal integrity SI and power integrity PI). The root causes are: 1) Polypropylene (PP), as a commonly used prepreg, undergoes a significant volume shrinkage during its cooling process, transitioning from a molten state to a solid state. The shrinkage rate is as high as 1.8-2.5%. During lamination, it is constrained by a rigid core (such as glass), resulting in significant and anisotropic residual stress within the layers and at the interface with the core. 2) As the substrate size increases, the cumulative effect of thermal expansion behavior is amplified, leading to a sharp narrowing of the matching window for the overall coefficient of thermal expansion (CTE) of the substrate. When the CTE difference between the core (such as low-CTE glass) and the adjacent PP layer is greater than 8 ppm / ℃ (e.g., glass CTE = 3.8 ppm / ℃, PPCTE ≈ 50-70 ppm / ℃), the interface shear stress generated during temperature cycling will exceed the bonding strength of the material interface, and the delamination risk will increase exponentially.

[0050] Example 1: To address the difficulty in controlling the warpage of large-size substrates, refer to... Figures 1-4This invention provides a stacked structure for a large-size packaging substrate, comprising: a first core board 100 (the first core board 100 is a BT core board with a pure dielectric layer and no conductive layer, which has undergone special treatment to remove the surface copper foil, preferably with a thickness of 200±10μm, and its material formulation is optimized to ensure that it has a relatively low and stable CTE of 13-15ppm / ℃ in the XY plane direction (i.e., within the substrate plane); vertical spacers 220 are spaced apart on the upper and lower surfaces of the first core board 100 (the material of the vertical spacers 220 is selected low-shrinkage polypropylene Sabic PP-505P, melt index MFI=25g / 10min (230℃ / 2.16kg)), which ensures that it has good flowability during the melt injection stage to fully fill the vias, while its low linear shrinkage (about 1.5%) and specific yield strength (about 8MPa) are crucial for subsequent stress management); additional core boards 200 are stacked on the first core board 100, and at least one additional core board 200 is provided. Figure 2 In the middle, the additional core board 200 has its intermediate core 201 at its center; refer to Figures 2-3 A first through hole 210 is formed on the intermediate core 201 and along the vertical direction of the intermediate core 201 (for example, the diameter of the first through hole 210 is 120±5μm, formed by laser ablation or mechanical drilling, and the hole wall roughness Ra≤1.2μm to ensure good adhesion of subsequent material filling and coating); the first through hole 210 is filled with insulating material; a second through hole 230 penetrates the first through hole 210, the additional core plate 200, the vertical spacer 220 and the first core plate 100; wherein, the thickness of the vertical spacer 220 is ≥50μm (for example, the thickness can be maintained at 80 to 100μm to balance the stress buffering effect and process efficiency), and the diameter of the first through hole 210 is larger than the diameter of the second through hole 230. This is the core design feature to realize the innovation of subsequent drilling process and stress control function.

[0051] Specifically, refer to Figure 4 The additional core board 200 includes a second core board 240 and a third core board 250 (for example, the second core board 240 and the third core board 250 are both AGC EN-A1 type glass core boards with a thickness of 150±5μm, CTE=3.8ppm / ℃, and elastic modulus ≥72GPa). The second core board 240 and the third core board 250 are symmetrically stacked on the upper and lower sides of the first core board 100.

[0052] To optimize stress distribution, the upper and lower glass core sheets can be designed with different thicknesses: the lower core sheet is 100μm thick to suppress gravitational deformation, and the upper core sheet is 150μm thick to compensate for the asymmetric stress during the hot pressing process. This design ensures that the warpage of the 80mm×80mm substrate after thermal cycling test (-55℃↔125℃, 1000 times) is ≤0.02mm / m.

[0053] Specifically, to ensure that the vertical spacer 220 fully functions as a stress buffer, its thickness is 50~300μm. This range was determined through finite element simulation and experimental verification: when the thickness is <50μm, the PP layer cannot completely cover the inner wall of the glass through-hole (coverage <85%), leading to copper plating solution seepage and voids; when the thickness is >300μm, the PP cooling and curing time is extended by 40%, reducing production efficiency. The optimal thickness range is 80-150μm, at which point the interfacial shear strength can reach over 18MPa (test standard IPC-TM-650 2.4.8).

[0054] As described above, this application, through the setting of the vertical spacer 220, when the PP material cools and solidifies in the through hole, its radial shrinkage is constrained by the glass hole wall (the elastic modulus of glass is 72 GPa, which is much greater than the modulus of PP is 1.5 GPa), forcing the shrinkage force to be released axially.

[0055] Meanwhile, a PP layer with a thickness of ≥50μm can form a continuous buffer interface: when the substrate expands due to heat, the PP layer absorbs the CTE differential stress between the glass and BT through plastic deformation (yield strength 8MPa); when the substrate cools, the PP layer rebounds to compensate for shrinkage displacement. Furthermore, this effect increases the interfacial peel strength to 18.7N / cm, effectively preventing differential stress and improving the stability of the finished product.

[0056] Through the above technical solution, this application sets a specific dimensional relationship between the first through hole 210 and the second through hole 230, such that the diameter of the first through hole 210 is larger than the diameter of the second through hole 230. This design plays a key role in giving full play to the stress control advantage of this invention. Because traditional through hole designs (usually a single diameter through hole, or the diameter of the second through hole 230 is ≥ the diameter of the first through hole 210) require the drill bit to cut both glass and resin simultaneously during drilling, causing the stress and vibration generated during drilling to act directly on the brittle edge of the glass, which can easily lead to micro-cracks, becoming the starting point for failure under subsequent thermomechanical loads. Furthermore, this application innovatively reduces the diameter of the second through hole 230, ensuring that the cutting edge of the drill bit only contacts and cuts the PP layer in the central area when drilling the second through hole 230, completely avoiding the glass hole wall. This design brings three core advantages: 1) As a high molecular polymer, PP has a fracture toughness (KIC=3.5MPa·m / ²) that is 5 times that of brittle inorganic material glass (KIC=0.7MPa·m / ²). During drilling, it can absorb energy through greater plastic deformation, effectively inhibiting crack propagation and improving… 1) Drilling yield; 2) PP chips are continuous and ribbon-like due to their ductility, which are easily discharged by the drill bit's spiral groove or coolant, avoiding the generation of hard and brittle glass powder and clogging of the hole wall, thus ensuring the cleanliness of the hole wall and the quality of subsequent electroplating; 3) The smaller diameter second through hole 230 forms a higher aspect ratio under the same board thickness (for example, the diameter of the second through hole 230 = 70μm, the board thickness ≈ 490μm, and the aspect ratio ≈ 7:1). This high aspect ratio structure enhances the mechanical interlocking effect of the electroless copper plating layer on the inner wall of the hole, i.e., the anchoring effect, which significantly improves the bonding force between the copper plating layer and the hole wall (here, the PP layer) and its anti-peeling ability under thermal stress. Figure 3 In the diagram, Φ1 is the diameter of the first through hole 210, and Φ2 is the diameter of the second through hole 230.

[0057] In Example 1, the method for manufacturing the stacked structure of a large-size packaging substrate includes the following steps:

[0058] Step S1: An additional core board 200 is stacked on the upper and lower layers of the first core board 100; wherein, the middle core 201 of the additional core board 200 is provided with a first through hole 210 along its own vertical direction.

[0059] Lamination parameters: Pre-pressing stage 80℃ / 0.5MPa / 10min → Main pressing stage 180℃ / 0.8MPa / 30min → Cooling rate ≤3℃ / min; Key control points: Use a vacuum laminator (vacuum degree ≤10Pa) to remove air bubbles, and the interlayer alignment accuracy is ±15μm; (Among them, the additional core board 200 is pre-processed with a first through hole 210 (TGV) with a diameter of 120μm, and the hole position accuracy is ±5μm).

[0060] Step S2: Inject polypropylene into the first through hole 210;

[0061] Process details: PP melting temperature 210±5℃, viscosity control 850±50cP (Brookfield DV2T viscometer), air pressure injection (0.3MPa) to ensure pore filling rate >99%; curing procedure: first stage 120℃ / 20min to eliminate internal stress → second stage 150℃ / 30min for complete crystallization.

[0062] Step S3: Drill holes along the central axis of the first through hole 210, the additional core plate 200, the vertical spacer 220, and the first core plate 100 to form a second through hole 230; wherein the diameter of the second through hole 230 is smaller than the diameter of the first through hole 210.

[0063] Equipment parameters: Uses carbide drill bits (containing 8% cobalt), spindle speed 45,000±2,000 rpm, feed rate 1.2 m / min;

[0064] Hole diameter control: The diameter of the second through hole 230 is 70μm (tolerance ±3μm), and the concentricity deviation with the diameter of the first through hole 210 is ≤5μm; Innovative design: Because the diameter of the second through hole 230 is < the diameter of the first through hole 210, the drill bit only contacts the PP layer (hardness Shore D 70) and does not contact the glass hole wall, thus avoiding the generation of microcracks.

[0065] Step S4: Insulating ink is injected into the second through hole 230, and chemical copper plating is performed;

[0066] Material selection: electroless copper plating solution containing 25g / L copper sulfate; process parameters: copper deposition rate 1.2μm / min, plating thickness 8±0.5μm, hole inner wall coverage 100% (SEM detection).

[0067] Step S5: Etch the copper plates stacked on the surfaces of the additional core board 200 and the first core board 100;

[0068] Step S6: Perform multiple ABF layering and SAP patterning on the surfaces of the additional core board 200 and the first core board 100.

[0069] In step S1, the additional core plate 200 is stacked on the upper and lower surfaces of the first core plate 100, and the diameter of the first through hole 210 is [not specified]. The additional core plate 200 includes a second core plate 240 and a third core plate 250.

[0070] In step S1, when the second core board 240 and the third core board 250 are stacked on the first core board 100, the second core board 240 (upper layer) is laminated first and its first through-hole 210 is filled, and then the third core board 250 (lower layer) is laminated and its first through-hole 210 is filled. This sequential operation can avoid stress superposition caused by simultaneous curing of PP on both sides. The measured warpage of asymmetric substrates (such as the upper glass core board area being larger than the lower layer) is reduced by about 37% (compared to the synchronous lamination process).

[0071] Example 2, refer to Figures 1-3 ,as well as Figure 5 The difference in the technical solution provided is that the additional core board 200 includes a second core board or a third core board. In this embodiment, the additional core board is selected as the second core board 240. The second core board 240 is attached to the surface of the first core board 100 (set on both sides, suitable for heterogeneous packaging scenarios with limited space).

[0072] The following structural features have been expanded:

[0073] First core board 100: 250μm thick copper-free BT substrate (Panasonic R-5775);

[0074] Additional core board 200: is a glass core substrate (AGC EN-A1, thickness 180μm), with a pre-fabricated first through hole 210 having a diameter of 100μm;

[0075] Vertical spacer 220: PP filler layer thickness 120μm (Sabic PP-505P);

[0076] Second through hole 230: diameter is 50μm (satisfying that the diameter of the second through hole 230 is less than the diameter of the first through hole 210);

[0077] Special design: An ABF compensation layer (thickness = 110 ± 5% of the glass core thickness) is added on both sides to balance the thermal stress of the asymmetric structure.

[0078] The manufacturing method of the above embodiment two includes the following steps:

[0079] Step S1: An additional core board 200 is stacked on top of the first core board 100; wherein, the middle core 201 of the additional core board 200 is provided with a first through hole 210 along its own vertical direction.

[0080] Among them, the lamination process adjustment is as follows: a stepped heating program is adopted (80℃→120℃→160℃, each holding for 10min), with a heating rate ≤2℃ / min; anti-warping measures: after lamination, the product is immediately placed into a shaping fixture (flatness ±5μm) and cooled to room temperature.

[0081] Step S2: Inject polypropylene into the first through hole 210;

[0082] Process details: PP melting temperature 210±5℃, viscosity control 850±50cP (Brookfield DV2T viscometer), air pressure injection (0.3MPa) to ensure pore filling rate >99%; curing procedure: first stage 120℃ / 20min to eliminate internal stress → second stage 150℃ / 30min for complete crystallization.

[0083] Step S3: Drill holes along the central axis of the first through hole 210, the additional core plate 200, the vertical spacer 220, and the first core plate 100 to form a second through hole 230; wherein the diameter of the second through hole 230 is smaller than the diameter of the first through hole 210.

[0084] Equipment parameters: Uses carbide drill bits (containing 8% cobalt), spindle speed 45,000±2,000 rpm, feed rate 1.2 m / min;

[0085] Hole diameter control: The diameter of the second through hole 230 is 70μm (tolerance ±3μm), and the concentricity deviation with the diameter of the first through hole 210 is ≤5μm; Innovative design: Because the diameter of the second through hole 230 is < the diameter of the first through hole 210, the drill bit only contacts the PP layer (hardness Shore D 70) and does not contact the glass hole wall, thus avoiding the generation of microcracks.

[0086] Step S4: Insulating ink is injected into the second through hole 230, and chemical copper plating is performed;

[0087] Material selection: electroless copper plating solution containing 25g / L copper sulfate; process parameters: copper deposition rate 1.2μm / min, plating thickness 8±0.5μm, hole inner wall coverage 100% (SEM detection).

[0088] Step S5: Etch the copper plates stacked on the surfaces of the additional core board 200 and the first core board 100;

[0089] Step S6: Perform multiple ABF layering and SAP patterning on the surfaces of the additional core board 200 and the first core board 100.

[0090] Symmetrical thickening: Multiple layers of ABF are coated on both sides as needed, with a single layer thickness of 35μm; hot pressing parameters: 165℃ / 0.6MPa / 40min, so that the CTE of the ABF layer is close to that of the glass core board (ΔCTE≤2ppm / ℃).

[0091] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Red-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0092] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A stack-up for large size package substrates, characterized by, Comprise: A first core plate (100); a vertical spacer (220) is arranged between the upper and lower surfaces of the first core plate (100); An additional core plate (200) stacked on the first core plate (100), the additional core plate (200) is provided with at least one, and the middle part of the additional core plate (200) is provided with a middle core (201); A first through hole (210) is formed on the middle core (201) and in the vertical direction of the middle core (201); the first through hole (210) is filled with insulating material; A second through hole (230) penetrates the first through hole (210), the additional core plate (200), the vertical spacer (220) and the first core plate (100); Wherein, the thickness of the vertical spacer (220) is greater than or equal to 50μm; The additional core plate (200) comprises a second core plate (240) and / or a third core plate (250), and the second core plate (240) and / or the third core plate (250) are stacked on the upper and lower surfaces of the first core plate (100); The diameter of the first through hole (210) is greater than the diameter of the second through hole (230).

2. The structure for large-size packaging substrate according to claim 1, wherein: The first core plate (100) is a copper-free BT core plate; The additional core plate (200) is a glass core substrate.

3. The stack-up for large size package substrates of claim 1, wherein, The combination of the first core plate (100) and the additional core plate (200) includes tin ball connection, blind hole electroplating connection, copper column connection and through connection.

4. The structure for large-size packaging substrate according to claim 1, wherein: The number of layers of the first core plate (100) is greater than the number of layers of the additional core plate (200).

5. The stack-up for large size package substrates of claim 1, wherein, The line width and distance in the first core plate (100) are less than the line width and distance in the additional core plate (200); the thickness of the circuit and solder pad in the first core plate (100) is less than the thickness of the circuit and solder pad in the additional core plate (200).

6. The structure for large-size packaging substrate according to claim 1, wherein: The thickness of the vertical spacer (220) is 50-300μm.

7. A manufacturing method for a stack of large-size package substrates, applied to the stack of large-size package substrates according to any one of claims 1 to 6, characterized in that, The steps include: Step S1, stacking the additional core plate (200) on the first core plate (100); wherein the first through hole (210) is arranged on the middle core (201) of the additional core plate (200) in the vertical direction of the middle core (201); Step S2, injecting polypropylene into the first through hole (210); Step S3, drilling the first through hole (210), the additional core plate (200), the vertical spacer (220) and the first core plate (100) along the central axis direction of the first through hole (210) to form the second through hole (230); wherein the diameter of the second through hole (230) is less than the diameter of the first through hole (210); Step S4, injecting insulating ink into the second through hole (230) and performing chemical copper plating; Step S5, etching the copper plate stacked on the surface of the additional core plate (200); Step S6, performing multiple ABF layering and SAP patterning on the surface of the additional core plate (200) and the first core plate (100).

8. The manufacturing method of a stack for a large-size package substrate according to claim 7, wherein In step S1, the additional core boards (200) are stacked on both upper and lower surfaces of the first core board (100), and the additional core boards (200) include a second core board (240) and / or a third core board (250).

9. The manufacturing method of the stack for large-size package substrates according to claim 8, wherein, In step S1, when the second core board (240) and the third core board (250) are stacked on the first core board (100), the second core board (240) is laminated and the first through holes (210) thereof are filled first, and then the third core board (250) is laminated and the first through holes (210) thereof are filled.

Images