Display substrate and display device

Abstract

A display substrate includes a substrate (10), a plurality of light emitting element groups, and a plurality of pixel circuit groups. The at least one light-emitting element group comprises a plurality of first area light-emitting elements (31) which are arranged along the first direction and are positioned in the first display area (A1) and a plurality of second area light-emitting elements (32) which are positioned in the second display area (A2); and at least one pixel circuit group comprises a plurality of first type pixel circuits (41) and a plurality of second type pixel circuits (42) which are arranged at intervals along the first direction and are positioned in the second display area (A2). At least one first-type pixel circuit (41) in the ith pixel circuit group is connected to at least one first-region light-emitting element (31) in the jth light-emitting element group, and at least one second-type pixel circuit (42) in the ith pixel circuit group is connected to at least one second-region light-emitting element (32) in the jth light-emitting element group. The jth light-emitting element group is located on one side of the ith pixel circuit group in the second direction.

Description

Display substrate and display device Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. Under-display camera technology is a novel technology proposed to increase the screen-to-body ratio of display devices.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a display substrate and a display device.

[0006] In one aspect, embodiments of this disclosure provide a display substrate, comprising: a substrate, a plurality of light-emitting element groups, and a plurality of pixel circuit groups. The substrate includes a first display area and a second display area located at least one side of the first display area. At least one of the plurality of light-emitting element groups includes: a plurality of first-region light-emitting elements and a plurality of second-region light-emitting elements arranged along a first direction, wherein the plurality of first-region light-emitting elements are located in the first display area, and the plurality of second-region light-emitting elements are located in the second display area; at least one of the plurality of pixel circuit groups includes: a plurality of first-type pixel circuits and a plurality of second-type pixel circuits arranged at intervals along the first direction and located in the second display area; the plurality of light-emitting element groups are arranged along a second direction, and the plurality of pixel circuit groups are arranged along the second direction, wherein the second direction intersects the first direction. At least one first-type pixel circuit in the i-th pixel circuit group is connected to at least one first-region light-emitting element in the j-th light-emitting element group, and at least one second-type pixel circuit in the i-th pixel circuit group is connected to at least one second-region light-emitting element in the j-th light-emitting element group, wherein i and j are both integers greater than 0; the j-th light-emitting element group is located on one side of the i-th pixel circuit group along the second direction. For multiple first-area light-emitting elements that emit the same color light in the j-th light-emitting element group, the first type pixel circuit in the i-th pixel circuit group connected to the first-area light-emitting element close to the second display area, and the first type pixel circuit in the i-th pixel circuit group connected to the first-area light-emitting element far away from the second display area, are located on the side far away from the first display area.

[0007] In some exemplary embodiments, the first direction is a row direction and the second direction is a column direction; or, the first direction is a column direction and the second direction is a row direction.

[0008] In some exemplary embodiments, the orthographic projection of the plurality of second region light-emitting elements in the j-th light-emitting element group onto the substrate at least partially overlaps with the orthographic projection of the (i-1)-th pixel circuit group or the (i+1)-th pixel circuit group onto the substrate.

[0009] In some exemplary embodiments, at least one first-type pixel circuit in the i-th pixel circuit group is connected to at least one first-region light-emitting element in the j-th light-emitting element group via a conductive connection line. The conductive connection line includes: a main body segment extending along a first direction, a first connecting segment and a second connecting segment extending at least along a second direction, the main body segment being connected between the first connecting segment and the second connecting segment, the first connecting segment being connected to the first-type pixel circuit, and the second connecting segment being connected to the first-region light-emitting element. The first connecting segment and the second connecting segment of the conductive connection line are located on opposite sides of the main body segment along the second direction.

[0010] In some exemplary embodiments, the plurality of first-area light-emitting elements in the first display area include: a plurality of first light-emitting elements emitting a first color light, a plurality of second light-emitting elements emitting a second color light, and a plurality of third light-emitting elements emitting a third color light. The plurality of first-type pixel circuits in the second display area include: a plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of third pixel circuits. At least one of the plurality of first pixel circuits is connected to at least one of the plurality of first light-emitting elements via a first conductive connection line; at least one of the plurality of second pixel circuits is connected to at least one of the plurality of second light-emitting elements via a second conductive connection line; and at least one of the plurality of third pixel circuits is connected to at least one of the plurality of third light-emitting elements via a third conductive connection line. The plurality of third pixel circuits are located on the side of the plurality of first pixel circuits and the plurality of second pixel circuits closest to the first display area.

[0011] In some exemplary embodiments, the at least one third pixel circuit is connected to two adjacent third light-emitting elements via a third conductive connection line; the third conductive connection line is located on the side of the first conductive connection line and the second conductive connection line closer to the substrate.

[0012] In some exemplary embodiments, at least one third pixel circuit in the i-th pixel circuit group is connected to at least one third light-emitting element in the j-th light-emitting element group. At least one first light-emitting element in the j-th light-emitting element group is connected to at least one first pixel circuit in the (i-1)-th pixel circuit group, and at least one second light-emitting element in the j-th light-emitting element group is connected to at least one second pixel circuit in the (i-1)-th pixel circuit group; or, at least one first light-emitting element in the j-th light-emitting element group is connected to at least one first pixel circuit in the (i+1)-th pixel circuit group, and at least one second light-emitting element in the j-th light-emitting element group is connected to at least one second pixel circuit in the (i+1)-th pixel circuit group.

[0013] In some exemplary embodiments, the first color light is red light, the second color light is blue light, and the third color light is green light.

[0014] In some exemplary embodiments, the i-th pixel circuit group includes: a first sub-pixel circuit group and a second sub-pixel circuit group located on both sides of the first display area along the first direction; the light-emitting element group connected to the first sub-pixel circuit group and the light-emitting element group connected to the second sub-pixel circuit group are staggered in the first direction.

[0015] In some exemplary embodiments, the orthographic projection of the first sub-pixel circuit group onto the substrate at least partially overlaps with the orthographic projection of a plurality of second-region light-emitting elements in the j-th light-emitting element group onto the substrate; the orthographic projection of the second sub-pixel circuit group onto the substrate at least partially overlaps with the orthographic projection of a plurality of second-region light-emitting elements in the (j-1)th or (j+1)th light-emitting element group onto the substrate.

[0016] In some exemplary embodiments, the gate traces connected to the first sub-pixel circuit group of the i-th pixel circuit group are disconnected from the gate traces connected to the second sub-pixel circuit group.

[0017] On the other hand, embodiments of this disclosure provide a display device, including a display substrate as described above, and a sensor located on the non-display side of the display substrate, wherein the orthographic projection of the sensor on the display substrate at least partially overlaps with a first display area of ​​the display substrate.

[0018] In some exemplary embodiments, the sensor is a camera.

[0019] On the other hand, this embodiment provides a display substrate, including: a substrate, a plurality of light-emitting element groups, and a plurality of pixel circuit groups. The substrate includes a first display area and a second display area located at least one side of the first display area. At least one of the plurality of light-emitting element groups includes: a plurality of first-region light-emitting elements and a plurality of second-region light-emitting elements arranged along a first direction, wherein the plurality of first-region light-emitting elements are located in the first display area, and the plurality of second-region light-emitting elements are located in the second display area; at least one of the plurality of pixel circuit groups includes: a plurality of first-type pixel circuits and a plurality of second-type pixel circuits arranged at intervals along the first direction and located in the second display area; the plurality of light-emitting element groups are arranged along a second direction, and the plurality of pixel circuit groups are arranged along the second direction, wherein the second direction intersects the first direction. At least one first-type pixel circuit in the i-th pixel circuit group is connected to at least one first-area light-emitting element in the j-th light-emitting element group via a conductive connection line. At least one second-type pixel circuit in the i-th pixel circuit group is connected to at least one second-area light-emitting element in the j-th light-emitting element group, where i and j are both integers greater than 0. The orthographic projections of the plurality of second-area light-emitting elements in the j-th light-emitting element group onto the substrate at least partially overlap with the orthographic projections of the i-th pixel circuit group onto the substrate. At least one first-area light-emitting element in the j-th light-emitting element group is connected to the conductive connection line via a first adapter, which is offset from the i-th pixel circuit group in the first direction. For the first-area light-emitting elements in the j-th light-emitting element group that emit light of the same color, the first-type pixel circuit in the i-th pixel circuit group connected to the first-area light-emitting element closer to the second display area is on the side of the i-th pixel circuit group connected to the first-area light-emitting element farther from the first display area.

[0020] In some exemplary embodiments, the first adapter is aligned with the (i-1)th pixel circuit group or the (i+1)th pixel circuit group in the first direction.

[0021] In some exemplary embodiments, the plurality of first-area light-emitting elements include: a plurality of first light-emitting elements emitting a first color light, a plurality of second light-emitting elements emitting a second color light, and a plurality of third light-emitting elements emitting a third color light. The plurality of first-type pixel circuits in the second display area include: a plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of third pixel circuits; at least one of the plurality of first pixel circuits is connected to at least one of the plurality of first light-emitting elements via a first conductive connection line; at least one of the plurality of second pixel circuits is connected to at least one of the plurality of second light-emitting elements via a second conductive connection line; at least one of the plurality of third pixel circuits is connected to at least one of the plurality of third light-emitting elements via a third conductive connection line; the plurality of third pixel circuits are located on the side of the plurality of first pixel circuits and the plurality of second pixel circuits closest to the first display area.

[0022] In some exemplary embodiments, the at least one third pixel circuit is connected to two adjacent third light-emitting elements via a third conductive connection line.

[0023] In some exemplary embodiments, at least one first pixel circuit in the i-th pixel circuit group is connected to at least one first light-emitting element in the j-th light-emitting element group; at least one second pixel circuit in the i-th pixel circuit group is connected to at least one second light-emitting element in the j-th light-emitting element group; and at least one third light-emitting element in the j-th light-emitting element group is connected to at least one first pixel circuit in the (i-1)-th pixel circuit group or the (i+1)-th pixel circuit group.

[0024] In some exemplary embodiments, the first color light is red light, the second color light is blue light, and the third color light is green light.

[0025] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0026] Overview of the attached figures

[0027] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0028] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0029] Figure 2 is a schematic diagram of the planar structure of the display area of ​​a display substrate according to at least one embodiment of the present disclosure;

[0030] Figure 3 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0031] Figure 4 is a schematic diagram of the pixel circuit arrangement of the second display area of ​​the display substrate according to at least one embodiment of the present disclosure;

[0032] Figure 5 is a partial cross-sectional schematic diagram of a second display area of ​​a display substrate according to at least one embodiment of the present disclosure;

[0033] Figure 6A is a partial schematic diagram of the semiconductor layer and the first gate metal layer of the second display area according to at least one embodiment of the present disclosure;

[0034] Figure 6B is a partial schematic diagram of the second gate metal layer of the second display area according to at least one embodiment of the present disclosure;

[0035] Figure 6C is a partial schematic diagram of the first source / drain metal layer of the second display area according to at least one embodiment of the present disclosure;

[0036] Figure 6D is a schematic diagram of the second source / drain metal layer of the second display area according to at least one embodiment of the present disclosure;

[0037] Figure 6E is a schematic diagram of the third source / drain metal layer of the second display area according to at least one embodiment of the present disclosure;

[0038] Figure 7A is a schematic diagram showing the connection of pixel circuit and light-emitting element according to at least one embodiment of the present disclosure;

[0039] Figure 7B is a schematic diagram of the pixel circuit and conductive connection layer in Figure 7A;

[0040] Figure 7C is a schematic diagram of the light-emitting element and the conductive connection layer in Figure 7A;

[0041] Figure 8A is another connection diagram of the pixel circuit and light-emitting element according to at least one embodiment of the present disclosure;

[0042] Figure 8B is a schematic diagram of the pixel circuit and conductive connection layer in Figure 8A;

[0043] Figure 8C is a schematic diagram of the light-emitting element and the conductive connection layer in Figure 8A;

[0044] Figure 9A is another connection diagram of the pixel circuit and light-emitting element according to at least one embodiment of the present disclosure;

[0045] Figure 9B is a schematic diagram of the pixel circuit and conductive connection layer in Figure 9A;

[0046] Figure 9C is a schematic diagram of the light-emitting element and the conductive connection layer in Figure 9A;

[0047] Figure 10 is a schematic diagram comparing the maximum and minimum capacitance values ​​of the conductive connection lines in at least one embodiment of the present disclosure.

[0048] Figure 11 is a schematic diagram showing the connection between the first region light-emitting element and the first pixel circuit according to at least one embodiment of the present disclosure;

[0049] Figure 12A is another connection diagram of the pixel circuit and light-emitting element according to at least one embodiment of the present disclosure;

[0050] Figure 12B is a schematic diagram of the pixel circuit and conductive connection layer in Figure 12A;

[0051] Figure 13 is a schematic diagram of another arrangement of pixel circuits in the second display area of ​​a display substrate according to at least one embodiment of the present disclosure;

[0052] Figure 14A is another connection diagram of the pixel circuit and light-emitting element according to at least one embodiment of the present disclosure;

[0053] Figure 14B is a schematic diagram showing the connection between the pixel circuit and the light-emitting element in the first region in Figure 14A;

[0054] Figure 15A is another connection diagram of the pixel circuit and light-emitting element according to at least one embodiment of the present disclosure;

[0055] Figure 15B is a schematic diagram showing the connection between the pixel circuit and the light-emitting element in the first region in Figure 15A;

[0056] Figure 16A is another connection diagram of the pixel circuit and light-emitting element according to at least one embodiment of the present disclosure;

[0057] Figure 16B is a schematic diagram of the pixel circuit and conductive connection layer in Figure 16A;

[0058] Figure 16C is a schematic diagram of the light-emitting element and the conductive connection layer in Figure 16A;

[0059] Figure 17A is another schematic diagram showing the connection between the pixel circuit and the light-emitting element in at least one embodiment of the present disclosure;

[0060] Figure 17B is a schematic diagram of the pixel circuit and conductive connection layer in Figure 17A;

[0061] Figure 17C is a schematic diagram of the light-emitting element and the conductive connection layer in Figure 17A;

[0062] Figure 18A is another schematic diagram showing the connection between the pixel circuit and the light-emitting element in at least one embodiment of the present disclosure;

[0063] Figure 18B is a schematic diagram of the light-emitting element and conductive connection layer in Figure 18A;

[0064] Figure 19 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0065] Detailed Explanation

[0066] The embodiments of this application will now be described in detail with reference to the accompanying drawings. This application describes multiple embodiments, but these descriptions are exemplary and not restrictive, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0067] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0068] Furthermore, in describing representative embodiments, the specification may have presented the method or process as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims relating to the method or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0069] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0070] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise expressly defined.

[0071] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the meaning of the above terms in this application according to the circumstances.

[0072] In this application, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission of electrical signals between the connected constituent elements. Examples of "components having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0073] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0074] In this application, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain electrode terminal, drain region, or drain electrode) and its source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this application, the channel region refers to the region through which current primarily flows.

[0075] In this application, the first electrode can be the drain and the second electrode can be the source, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this application, the "source" and "drain" can be interchanged. Additionally, the gate can also be called the control electrode.

[0076] In this application, "parallel" refers to the state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore also includes the state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" refers to the state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore also includes the state where the angle is greater than 85° and less than 95°.

[0077] In this application, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, such as chamfers, curved edges, and other variations.

[0078] In this application, "light transmittance" refers to the ability of light to pass through a medium, which is the percentage of light flux passing through a transparent or translucent body relative to the incident light flux.

[0079] In this application, "approximately" and "roughly" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this application, "identical" can include situations where they are completely identical and substantially the same; "roughly the same" means that the values ​​differ by less than 10%.

[0080] In this application, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this application, "A extends along direction B" refers to "the main part of A extends along direction B."

[0081] With the continuous development of display technology, cameras are typically installed on display devices to meet the needs of photography or facial recognition. To maximize screen-to-body ratio, technologies such as notch displays, waterdrop displays, and punch-hole displays have emerged. These technologies reduce the area occupied by the camera by creating a hole in a portion of the display area and placing the camera below the hole, thereby increasing the screen-to-body ratio. However, these technologies require removing part of the display area, resulting in some areas of the screen being undisplayed and preventing further increases in screen-to-body ratio. To avoid punching holes in the display area and to make a true full-screen display possible while ensuring the practicality of the display substrate, external or internal pixel circuitry is typically used in the under-display camera area.

[0082] The external pixel circuit method refers to placing the pixel circuit connected to the light-emitting element in the under-display camera area within the normal display area. This separate arrangement of the light-emitting element and pixel circuit improves the light transmittance of the under-display camera area. Since the under-display camera area lacks pixel circuits and has no light-shielding layer other than the anode of the light-emitting element, it achieves high light transmittance. In this method, the pixel circuit and the light-emitting element are electrically connected via conductive wires, typically made of transparent conductive materials such as indium tin oxide (ITO). In some implementations, the light-emitting element in the under-display camera area is connected to the pixel circuit in the normal display area in a close-to-close manner; that is, the pixel circuit connected to the light-emitting element closer to the normal display area is located on the side of the pixel circuit connected to the light-emitting element farther from the normal display area that is closer to the under-display camera area. However, this connection method suffers from significant capacitance differences in the conductive wires, leading to situations where the light-emitting element in the under-display camera area fails to illuminate under high-frequency, low-grayscale conditions. For example, under high-frequency, low-grayscale conditions, the light-emitting element located at the edge of the under-display camera area illuminates, while the light-emitting element located in the center of the under-display camera area remains off.

[0083] This embodiment provides a display substrate and a display device, which can improve the wiring uniformity of conductive connection lines and ensure that the light-emitting elements can be turned on under high frequency and low grayscale conditions.

[0084] This embodiment provides a display substrate, including: a substrate, a plurality of light-emitting element groups and a plurality of pixel circuit groups located on one side of the substrate. The substrate includes a first display area and a second display area located on at least one side of the first display area. At least one light-emitting element group includes: a plurality of first-area light-emitting elements and a plurality of second-area light-emitting elements arranged along a first direction, wherein the plurality of first-area light-emitting elements are located in the first display area, and the plurality of second-area light-emitting elements are located in the second display area. At least one pixel circuit group includes: a plurality of first-type pixel circuits and a plurality of second-type pixel circuits arranged at intervals along the first direction and located in the second display area. The plurality of light-emitting element groups are arranged along a second direction, and the plurality of pixel circuit groups are arranged along the second direction. The second direction intersects the first direction; for example, the first direction may be perpendicular to the second direction. At least one first-type pixel circuit in the i-th pixel circuit group is connected to at least one first-area light-emitting element in the j-th light-emitting element group, and at least one second-type pixel circuit in the i-th pixel circuit group is connected to at least one second-area light-emitting element in the j-th light-emitting element group, where i and j are both integers greater than 0; the j-th light-emitting element group is located on one side of the i-th pixel circuit group along the second direction. For example, the j-th light-emitting element group and the i-th pixel circuit group are staggered along a first direction. For example, the orthographic projections of the j-th light-emitting element group and the i-th pixel circuit group onto the substrate may not overlap.

[0085] In some examples, for multiple first-area light-emitting elements emitting the same color light within the j-th light-emitting element group, the first-type pixel circuit in the i-th pixel circuit group connected to the first-area light-emitting element closer to the second display area is located on the side of the first-type pixel circuit in the i-th pixel circuit group connected to the first-area light-emitting element farther from the second display area, which is farther from the first display area. In this example, the first-area light-emitting elements and the first-type pixel circuits can be connected in a near-far connection manner, that is, the first-type pixel circuit connected to the first-area light-emitting element closer to the second display area is located on the side of the first-type pixel circuit connected to the first-area light-emitting element farther from the second display area, which is farther from the first display area.

[0086] In the display substrate provided in this embodiment, the i-th pixel circuit group drives the j-th light-emitting element group to emit light, and the j-th light-emitting element group is located on one side of the i-th pixel circuit group along the second direction. This can improve the wiring uniformity of the conductive connection lines connecting the light-emitting elements in the first region and the pixel circuit of the first type, and ensure that the light-emitting elements can be turned on under both high and low frequency grayscale.

[0087] In some exemplary embodiments, the first direction can be a row direction and the second direction can be a column direction. Alternatively, the first direction can be a column direction and the second direction can be a row direction. In some examples, the first direction can be a row direction and the second direction can be a column direction; a pixel circuit group can be a row of pixel circuits, a light-emitting element group can be a row of light-emitting elements, and a row of pixel circuits can be configured to drive another row of light-emitting elements (e.g., adjacent row light-emitting elements). In other examples, the first direction can be a column direction and the second direction can be a row direction; a pixel circuit group can be a column of pixel circuits, a light-emitting element group can be a column of light-emitting elements, and a column of pixel circuits can be configured to drive another column of light-emitting elements (e.g., adjacent column light-emitting elements). In some examples, the orthographic projection of the plurality of second-region light-emitting elements in the j-th light-emitting element group onto the substrate can at least partially overlap with the orthographic projection of the (i-1)-th or (i+1)-th pixel circuit group onto the substrate. This example, by using a staggered driving method for pixel circuit groups and light-emitting element groups, can reduce the ratio of the maximum capacitance to the minimum capacitance of conductive interconnects, thereby improving the wiring uniformity of conductive interconnects.

[0088] In some exemplary embodiments, at least one first-type pixel circuit in the i-th pixel circuit group is connected to at least one first-region light-emitting element in the j-th light-emitting element group via a conductive connection line. The conductive connection line may include: a main body segment extending along a first direction, a first connecting segment and a second connecting segment extending at least along a second direction, the main body segment connecting between the first connecting segment and the second connecting segment, the first connecting segment connecting to the first-type pixel circuit, and the second connecting segment connecting to the first-region light-emitting element. The first connecting segment and the second connecting segment of the conductive connection line are located on opposite sides of the main body segment along the second direction. The structure of the conductive connection line in this example can support the connection between the first-type pixel circuit in the pixel circuit group and the first-region light-emitting element in the light-emitting element group under a staggered driving mode.

[0089] The following examples illustrate the solution of this embodiment.

[0090] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, the display substrate may include a display area AA and a border area BB surrounding the display area AA. For example, the border area BB may include a first border area B1 located on one side of the display area AA, and border areas located on other sides of the display area AA (e.g., a second border area B2, a third border area B3, and a fourth border area B4). The first border area B1 may be the top border of the display substrate, the second border area B2 may be the bottom border of the display substrate, the third border area B3 may be the left border of the display substrate, and the fourth border area B4 may be the right border of the display substrate.

[0091] In some examples, the display area AA may include a first display area A1 and a second display area A2. The second display area A2 may at least partially surround the first display area A1. For example, the first display area A1 may be located at the top center of the display area AA, and the second display area A2 may surround the first display area A1. However, this embodiment is not limited to this. For example, the first display area A1 may be located at other positions such as the upper left or upper right corner of the display area AA, and the second display area A2 may surround at least one side of the first display area A1.

[0092] In some examples, as shown in Figure 1, the display area AA can be a rectangle, such as a rounded rectangle. The first display area A1 can be a circle or an ellipse. However, this embodiment is not limited to this. For example, the first display area A1 can be a rectangle, a semicircle, a pentagon, or other shapes.

[0093] In some examples, as shown in Figure 1, the first display area A1 can be a light-transmitting display area, also known as an under-display camera (FDC) area, configured for image display and light transmission; the second display area A2 can be a normal display area, configured for image display. For example, the orthographic projection of a sensor (e.g., a camera) onto the display substrate can be located within the first display area A1 of the display substrate. In some examples, as shown in Figure 1, the first display area A1 can be circular, and the size of the orthographic projection of the sensor onto the display substrate can be less than or equal to the size of the first display area A1. However, this embodiment is not limited to this. In other examples, the first display area A1 can be rectangular, and the size of the orthographic projection of the sensor onto the display substrate can be less than or equal to the size of the inscribed circle of the first display area A1.

[0094] In some examples, as shown in Figure 1, the pixel density of the first display area A1 may be less than or equal to the pixel density of the second display area A2. For example, the pixel density of the first display area A1 may be equal to the pixel density of the second display area A2. This embodiment is not limited in this respect.

[0095] In some examples, the ratio of the resolution of the first display area A1 to the resolution of the second display area A2 may be approximately 0.8 to 1.2. Alternatively, the resolution of the second display area A2 may be approximately the same as the resolution of the first display area A1. This embodiment is not limited in this respect.

[0096] Figure 2 is a schematic planar structure diagram of the display area of ​​a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 2, each pixel unit of the display area may include: a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and two third sub-pixels P31 and P32 emitting a third color light. Multiple pixel units can be arranged in an array within the display area AA. Within the second display area A2, the pixel circuits of multiple sub-pixels can be arranged in an array along the column direction Y and the row direction X. Within a single pixel unit, the light-emitting elements of four sub-pixels can be arranged in different columns along the row direction X, and the light-emitting elements of the four sub-pixels can be disposed in the same row; the pixel circuits of the four sub-pixels can be arranged sequentially along the row direction X. For example, the first sub-pixel P1, the third sub-pixel P31, the second sub-pixel P2, and the third sub-pixel P32 can be arranged sequentially along the row direction X, or the second sub-pixel P2, the third sub-pixel P32, the first sub-pixel P1, and the third sub-pixel P31 can be arranged sequentially along the row direction X.

[0097] In some examples, the first color light can be red, the second color light can be blue, and the third color light can be green. The first sub-pixel P1 can be a red sub-pixel (R), the second sub-pixel P2 can be a blue sub-pixel (B), and the third sub-pixels P31 and P32 can be green sub-pixels (G). For example, the third sub-pixel P31 can be the first green sub-pixel (G1), and the third sub-pixel P32 can be the second green sub-pixel (G2).

[0098] In some examples, as shown in Figure 2, multiple pixel units arranged along the row direction X can be considered a row of pixel units, and multiple pixel units arranged along the column direction Y can be considered a column of pixel units. Multiple pixel units can include multiple first pixel units Pa and multiple second pixel units Pb, and the arrangement order of the four sub-pixels within the first pixel unit Pa and the second pixel unit Pb can be different. For example, the pixel units in the e-th row can include: multiple first pixel units Pa arranged sequentially along the row direction X; the first sub-pixel P1, the third sub-pixel P31, the second sub-pixel P2, and the third sub-pixel P32 of the first pixel unit Pa are arranged sequentially along the row direction X. The pixel units in the (e+1)-th row can include: multiple second pixel units Pb arranged sequentially along the row direction X, and the second sub-pixel P2, the third sub-pixel P32, the first sub-pixel P1, and the third sub-pixel P31 of the second pixel unit Pb can be arranged sequentially along the row direction X. A column of pixel units can include: first pixel units Pa and second pixel units Pb alternately arranged along the column direction Y. Here, e can be an integer greater than 0. For example, the subpixels of odd-numbered rows of pixel units in the display area can be arranged in RG1BG2, and the subpixels of even-numbered rows of pixel units can be arranged in BG2RG1; or, the subpixels of odd-numbered rows of pixel units in the display area can be arranged in BG2RG1, and the subpixels of even-numbered rows of pixel units can be arranged in RG1BG2.

[0099] In some examples, multiple sub-pixels arranged along the column direction Y can constitute a column of sub-pixels. The k-th column of sub-pixels may include: a first sub-pixel P1 and a second sub-pixel P2 alternately arranged along the column direction Y; the (k+1)-th column of sub-pixels may include: a third sub-pixel P31 and a third sub-pixel P32 alternately arranged along the column direction Y. k can be an integer greater than 1. The pixel circuitry of each column of sub-pixels can be connected to the same data line. For example, the k-th column of sub-pixels can be connected to data line DLk, and the (k+1)-th column of sub-pixels can be connected to data line DLk+1. Data line DLk can provide data signals to the first sub-pixel P1 and the second sub-pixel P2 in a time-division manner, and data line DLk+1 can provide data signals to the third sub-pixels P31 and P32 in a time-division manner. For example, the data signals required by the third sub-pixels P31 and P32 can be the same.

[0100] In some examples, each sub-pixel may include a circuit unit and a light-emitting element. The circuit unit may include at least a pixel circuit, which is connected to a scan line, a data line, and a light-emitting control line, respectively. The pixel circuit may be configured to receive the data voltage transmitted by the data line and output a corresponding current to the light-emitting element under the control of the scan line and the light-emitting control line. The light-emitting element in at least one sub-pixel is connected to the pixel circuit of the sub-pixel, and the light-emitting element is configured to emit light of a corresponding brightness in response to the current output by the pixel circuit of the sub-pixel.

[0101] In some examples, a pixel circuit may include multiple transistors and at least one capacitor. For example, a pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In these circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0102] In some examples, the multiple transistors in the pixel circuit can be either P-type or N-type transistors. Using the same type of transistors in the pixel circuit simplifies the manufacturing process, reduces the complexity of the display substrate manufacturing, and improves product yield. In other examples, the multiple transistors in the pixel circuit can include both P-type and N-type transistors.

[0103] In some examples, the multiple transistors in the pixel circuit can be low-temperature polysilicon (LTPS) thin-film transistors (TFTs), oxide thin-film transistors (OPTs), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polysilicon (LTPS), while the active layer of the OPT TFT is made of oxide. LTPS TFTs offer advantages such as high mobility and fast charging, while OPTs offer advantages such as low leakage current. Integrating LTPS and OPTs onto a single display substrate—an LTPS+Oxide (LTPO) display substrate—leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0104] In some examples, the light-emitting element can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited in this respect.

[0105] In some examples, the shape of the light-emitting element can be rectangular, rhomboid, pentagonal, or hexagonal. The light-emitting elements of the four sub-pixels of a pixel unit can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited to this. In other examples, a pixel unit may include three sub-pixels, and the light-emitting elements of the three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement.

[0106] Figure 3 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. The pixel circuit of this exemplary embodiment is illustrated using a 7T1C structure as an example. In some examples, as shown in Figure 3, the pixel circuit of this example may include six switching transistors (T1, T2, T4 to T7), a driving transistor T3, and a storage capacitor Cst. The six switching transistors are a data writing transistor T4, a threshold compensation transistor T2, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a first reset transistor T1, and a second reset transistor T7. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode.

[0107] In some examples, as shown in Figure 3, the display substrate may include: a scan line GL, a data line DL, a first power line PL1, a second power line PL2, a light emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a first reset control line RST1, and a second reset control line RST2. In some examples, the first power line PL1 may be configured to provide a constant first voltage signal VDD to the pixel driving circuit, and the second power line PL2 may be configured to provide a constant second voltage signal VSS to the pixel driving circuit, wherein the first voltage signal VDD is greater than the second voltage signal VSS. The scan line GL may be configured to provide a scan signal SCAN to the pixel driving circuit, the data line DL may be configured to provide a data signal DATA to the pixel driving circuit, the light emission control line EML may be configured to provide a light emission control signal EM to the pixel driving circuit, the first reset control line RST1 may be configured to provide a first reset control signal RESET1 to the pixel driving circuit, and the second reset control line RST2 may be configured to provide a second reset control signal RESET2 to the pixel driving circuit. In some examples, in the nth row pixel driving circuit, the first reset control line RST1 can be electrically connected to the scan line GL of the (n-1)th row pixel driving circuit to be input to the scan signal SCAN(n-1), that is, the first reset control signal RESET1(n) is the same as the scan signal SCAN(n-1). The second reset control line RST2 can be electrically connected to the scan line GL of the nth row pixel driving circuit to be input to the scan signal SCAN(n), that is, the second reset control signal RESET2(n) is the same as the scan signal SCAN(n). In some examples, the second reset control line RST2 electrically connected to the nth row pixel driving circuit and the first reset control line RST1 electrically connected to the (n+1)th row pixel driving circuit can be a single structure. Here, n is an integer greater than 0. In this way, the signal lines of the display substrate can be reduced, realizing a narrow bezel design of the display substrate. However, this embodiment is not limited to this.

[0108] In some examples, the first initial signal line INIT1 can be configured to provide a first initial signal to the pixel driving circuit, and the second initial signal line INIT2 can be configured to provide a second initial signal to the pixel driving circuit. For example, the first initial signal may be different from the second initial signal. The first and second initial signals can be constant voltage signals, the magnitude of which may be, for example, between the first voltage signal VDD and the second voltage signal VSS, but are not limited thereto. In other examples, the first and second initial signals may be the same, and only the first initial signal line may be configured to provide the first initial signal.

[0109] In some examples, as shown in Figure 3, the driving transistor T3 is electrically connected to the light-emitting element EL, and outputs a driving current to drive the light-emitting element EL to emit light under the control of signals such as the scan signal SCAN, data signal DATA, first voltage signal VDD, and second voltage signal VSS. The gate of the data writing transistor T4 is electrically connected to the scan line GL, the first terminal of the data writing transistor T4 is electrically connected to the data line DL, and the second terminal of the data writing transistor T4 is electrically connected to the first terminal of the driving transistor T3. The gate of the threshold compensation transistor T2 is electrically connected to the scan line GL, the first terminal of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, and the second terminal of the threshold compensation transistor T2 is electrically connected to the second terminal of the driving transistor T3. The gate of the first light-emitting control transistor T5 is electrically connected to the light-emitting control line EML, the first terminal of the first light-emitting control transistor T5 is electrically connected to the first power supply line PL1, and the second terminal of the first light-emitting control transistor T5 is electrically connected to the first terminal of the driving transistor T3. The gate of the second light-emitting control transistor T6 is electrically connected to the light-emitting control line EML. The first terminal of the second light-emitting control transistor T6 is electrically connected to the second terminal of the driving transistor T3. The second terminal of the second light-emitting control transistor T6 is electrically connected to the anode of the light-emitting element EL. The first reset transistor T1 is electrically connected to the gate of the driving transistor T3 and is configured to reset the gate of the driving transistor T3. The second reset transistor T7 is electrically connected to the anode of the light-emitting element EL and is configured to reset the anode of the light-emitting element EL. The gate of the first reset transistor T1 is electrically connected to the first reset control line RST1. The first terminal of the first reset transistor T1 is electrically connected to the first initial signal line INIT1. The second terminal of the first reset transistor T1 is electrically connected to the gate of the driving transistor T3. The gate of the second reset transistor T7 is electrically connected to the second reset control line RST2. The first terminal of the second reset transistor T7 is electrically connected to the second initial signal line INIT2. The second terminal of the second reset transistor T7 is electrically connected to the anode of the light-emitting element EL. The first capacitor plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3, and the second capacitor plate of the storage capacitor Cst is electrically connected to the first power supply line PL1.

[0110] In this example, the first node N1 is the connection point of the storage capacitor Cst, the first reset transistor T1, the driving transistor T3, and the threshold compensation transistor T2; the second node N2 is the connection point of the first light-emitting control transistor T5, the data writing transistor T4, and the driving transistor T3; the third node N3 is the connection point of the driving transistor T3, the threshold compensation transistor T2, and the second light-emitting control transistor T6; and the fourth node N4 is the connection point of the second light-emitting control transistor T6, the second reset transistor T7, and the light-emitting element EL. The fourth node N4 is the anode connection node.

[0111] The operation of the pixel circuit illustrated in Figure 3 will be explained below. The explanation will take the example where all the transistors in the pixel circuit shown in Figure 3 are P-type transistors. In some examples, the operation of the pixel circuit during a single frame display period may include: a first stage, a second stage, and a third stage.

[0112] The first stage is called the reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, turning on the first reset transistor T1. The first initial signal provided by the first initial signal line INIT1 is provided to the first node N1 to initialize the first node N1 and clear the original data voltage in the storage capacitor Cst. The scan signal SCAN provided by the scan line GL is a high-level signal, and the light emission control signal EM provided by the light emission control line EML is a high-level signal, turning off the data writing transistor T4, the threshold compensation transistor T2, the first light emission control transistor T5, the second light emission control transistor T6, and the second reset transistor T7. During this stage, the light-emitting element EL does not emit light.

[0113] The second stage is called the data writing stage or threshold compensation stage. The scan signal SCAN provided by the scan line GL is a low-level signal, while the first reset control signal RESET1 provided by the first reset control line RST1 and the light emission control signal EM provided by the light emission control line EML are both high-level signals. The data line DL outputs the data signal DATA. During this stage, because the first capacitor plate of the storage capacitor Cst is low, the driving transistor T3 is turned on. The low-level scan signal SCAN turns on the threshold compensation transistor T2, the data writing transistor T4, and the second reset transistor T7. Threshold compensation transistor T2 and data write transistor T4 are turned on, allowing the data voltage Vdata output from data line DL to be supplied to first node N1 via second node N2, the turned-on drive transistor T3, third node N3, and the turned-on threshold compensation transistor T2. The difference between the data voltage Vdata output from data line DL and the threshold voltage of drive transistor T3 is charged into storage capacitor Cst. The voltage at the first capacitor plate of storage capacitor Cst (i.e., first node N1) is Vdata - |Vth|, where Vdata is the data voltage output from data line DL and Vth is the threshold voltage of drive transistor T3. Second reset transistor T7 is turned on, allowing the second initial signal provided by the second initial signal line INIT2 to be supplied to the anode of light-emitting element EL, initializing (resetting) the anode of light-emitting element EL, clearing its internal pre-stored voltage, completing the initialization, and ensuring that light-emitting element EL does not emit light. The first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, causing the first reset transistor T1 to turn off. The light emission control signal EM provided by the light emission control signal line EML is a high-level signal, which disconnects the first light emission control transistor T5 and the second light emission control transistor T6.

[0114] The third stage is called the light-emitting stage. The light-emitting control signal EM provided by the light-emitting control signal line EML is a low-level signal, while the scan signal SCAN provided by the scan line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals. When the light-emitting control signal EM provided by the light-emitting control signal line EML is low, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on. The first voltage signal VDD output from the first power supply line PL1 provides a driving voltage to the anode of the light-emitting element EL through the turned-on first light-emitting control transistor T5, driving transistor T3, and second light-emitting control transistor T6, driving the light-emitting element EL to emit light.

[0115] During the pixel circuit driving process, the driving current flowing through the driving transistor T3 is determined by the voltage difference between its gate and its first terminal. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the driving transistor T3 is:

[0116] I = K × (Vgs - Vth) 2 =K×[(VDD-Vdata+|Vth|)-Vth] 2 =K×[VDD-Vdata] 2 .

[0117] Where I is the driving current flowing through the driving transistor T3, which is also the driving current driving the light-emitting element EL, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the driving transistor T3, Vth is the threshold voltage of the driving transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first voltage signal output by the first power line PL1.

[0118] As can be seen from the above formula, the current flowing through the light-emitting element EL is independent of the threshold voltage of the driving transistor T3. Therefore, the pixel circuit of this embodiment can effectively compensate for the threshold voltage of the driving transistor T3.

[0119] In some examples, as shown in FIG1, the display substrate may include at least: a plurality of first region light-emitting elements 31 located in the first display area A1, a plurality of second region light-emitting elements 32 located in the second display area A2, a plurality of first type pixel circuits 41 and a plurality of second type pixel circuits 42.

[0120] In some examples, at least one second-type pixel circuit 42 within the second display area A2 can be connected to at least one second-region light-emitting element 32, configured to drive the at least one second-region light-emitting element 32 to emit light. For example, a plurality of second-region light-emitting elements 32 and a plurality of second-type pixel circuits 42 can be in a one-to-one relationship, that is, one second-type pixel circuit 42 can be electrically connected to one second-region light-emitting element 32, configured to drive the connected second-region light-emitting element 32 to emit light. For example, the orthographic projections of the second-region light-emitting element 32 and the connected second-type pixel circuit 42 onto the substrate can at least partially overlap, or may not overlap at all.

[0121] In some examples, at least one first-type pixel circuit 41 can be connected to at least one first-region light-emitting element 31 via a conductive connection line 51, configured to drive the at least one first-region light-emitting element 31 to emit light. For example, the plurality of first-region light-emitting elements 31 and the plurality of first-type pixel circuits 41 can have a one-to-one relationship, that is, one first-type pixel circuit 41 can be electrically connected to one first-region light-emitting element 31, configured to drive the connected first-region light-emitting element 31 to emit light. Alternatively, some of the plurality of first-type pixel circuits 41 can have a one-to-many relationship with the plurality of first-region light-emitting elements 31, while other parts of the first-type pixel circuits 41 can have a one-to-one relationship with the plurality of first-region light-emitting elements 31. For example, one first-type pixel circuit 41 can be electrically connected to a plurality of first-region light-emitting elements 31 that emit light of the same color, configured to drive the plurality of first-region light-emitting elements 31 that emit light of the same color to emit light. Since the first-region light-emitting elements 31 and the first-type pixel circuits 41 are located in different regions, the orthographic projection of at least one first-type pixel circuit 41 on the substrate and the orthographic projection of at least one first-region light-emitting element 31 on the substrate may not overlap. By placing the first type of pixel circuit 41 in the second display area A2, it is beneficial to improve the light transmittance of the first display area A1. In some examples, the conductive connecting line 51 can be made of a transparent conductive material (e.g., indium tin oxide (ITO)) to maximize the light transmittance of the first display area A1.

[0122] In some examples, since the second display area A2 is provided with not only a first-type pixel circuit 41 electrically connected to the first area light-emitting element 31, but also a second-type pixel circuit 42 electrically connected to the second area light-emitting element 32, the number of pixel circuits in the second display area A2 is greater than the number of second-type light-emitting elements 32. For example, the area for setting the newly added pixel circuit (including the first-type pixel circuit 41) can be obtained by reducing the size of the second-type pixel circuit 42 in the row direction X. For example, the size of the pixel circuit in the row direction X can be smaller than the size of the second-type light-emitting element 32 in the row direction X. In some examples, the original h columns of pixel circuits can be compressed along the row direction X to add space for the arrangement of one column of pixel circuits, and the space occupied by the h columns of pixel circuits before compression and the h+1 columns of pixel circuits after compression can be the same. Here, h can be an integer greater than 1.

[0123] Figure 4 is a schematic diagram of the pixel circuit arrangement of the second display area of ​​a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 4, h can be 4. Along the row direction X, four columns of second-type pixel circuits 42 can be arranged between two adjacent columns of first-type pixel circuits 41. In other words, a column of first-type pixel circuits 41 is inserted every four columns of second-type pixel circuits 42. However, this embodiment is not limited to this. In other examples, the value of h can be 2 or 3, etc.

[0124] Figure 5 is a partial cross-sectional schematic diagram of a second display area of ​​a display substrate according to at least one embodiment of the present disclosure. Figure 5 illustrates the structure of a sub-pixel of the second display area as an example. In this example, it is described that the multiple transistors in the pixel circuit are of the same type; for example, the multiple transistors in the pixel circuit may all be low-temperature polycrystalline silicon thin-film transistors (LTPS) or all be oxide thin-film transistors (OPS). In other examples, the multiple transistors in the pixel circuit may be both LPS and OPS.

[0125] In some examples, as shown in Figure 5, in a direction perpendicular to the display substrate, the second display area of ​​the display substrate may include: a substrate 10, and a circuit structure layer 11, a conductive connection layer 12, a light-emitting structure layer 13, and an encapsulation structure layer 14 sequentially disposed on the substrate 10. The circuit structure layer 11 may include at least: a plurality of first-type pixel circuits and a plurality of second-type pixel circuits, each pixel circuit including a plurality of transistors and at least one capacitor. The light-emitting structure layer 13 of the second display area may include at least: a plurality of second-region light-emitting elements.

[0126] In some examples, Figure 5 illustrates a thin-film transistor 21 and a capacitor 22 for each pixel circuit. In some examples, the circuit structure layer 11 of the second display area may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer disposed on the substrate 10. A first gate insulating layer 101 may be disposed between the semiconductor layer and the first gate metal layer; a second gate insulating layer 102 may be disposed between the first and second gate metal layers; an interlayer insulating layer 103 may be disposed between the second gate metal layer and the first source / drain metal layer; a passivation layer 104 and a first planarization layer 105 may be disposed between the first and second source / drain metal layers; a second planarization layer 106 may be disposed between the second and third source / drain metal layers; and a third planarization layer 107 may be disposed on the side of the third source / drain metal layer away from the substrate 10. In this embodiment, the first gate insulating layer 101, the second insulating layer 102, the interlayer insulating layer 103, and the passivation layer 104 can be inorganic insulating layers, while the first planarization layer 105, the second planarization layer 106, and the third planarization layer 107 can be organic insulating layers. However, this embodiment is not limited to these. In other examples, a buffer layer can be provided on the side of the semiconductor layer near the substrate. The buffer layer can prevent harmful substances in the substrate from penetrating into the interior of the display substrate and can also increase the adhesion of the film layers in the display substrate to the substrate. In other examples, a bottom shielding metal layer (BSM) can be provided on the side of the buffer layer near the substrate. The bottom shielding metal layer can be configured to at least partially cover the active layer of the thin-film transistor of the pixel circuit to avoid external light affecting the performance of the thin-film transistor. In other examples, the passivation layer can be omitted between the first source / drain metal layer and the second source / drain metal layer, and only the first planarization layer can be provided between the first source / drain metal layer and the second source / drain metal layer. In other examples, the circuit structure layer may omit the third source / drain metal layer, or the circuit structure layer may include a fourth source / drain metal layer located on the side of the third source / drain metal layer away from the substrate.

[0127] In some examples, as shown in Figure 5, the conductive connection layer 12 may include a first conductive connection layer, a second conductive connection layer, and a third conductive connection layer sequentially disposed along the direction of the substrate 10. A fourth planarization layer 108 may be disposed between the first and second conductive connection layers, a fifth planarization layer 109 may be disposed between the second and third conductive connection layers, and a sixth planarization layer 110 may be disposed on the side of the third conductive connection layer away from the substrate 10. The fourth planarization layer 108, the fifth planarization layer 109, and the sixth planarization layer 110 may be organic insulating layers. In some examples, the first, second, and third conductive connection layers may be made of transparent conductive materials, such as ITO.

[0128] In some examples, as shown in FIG5, the semiconductor layer of the second display area may include at least the active layer 210 of the thin-film transistor 21. The active layer 210 of the thin-film transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least the gate 213 of the thin-film transistor 21 and the first electrode 221 of the capacitor 22. The orthographic projection of the gate 213 of the thin-film transistor 21 onto the substrate 10 may cover the orthographic projection of the channel region 2100 of the active layer 210 onto the substrate 10. The second gate metal layer may include at least the second electrode 222 of the capacitor 22. The orthographic projections of the second electrode 222 and the first electrode 221 of the capacitor 22 onto the substrate 10 may at least partially overlap, for example, they may coincide. The first source-drain metal layer may include at least the source 211 and the drain 212 of the thin-film transistor 21. The interlayer insulating layer 103 may have multiple vias (e.g., including a first pixel via and a second pixel via) in the display area. The interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the first pixel via can be removed, exposing at least a portion of the surface of the first region 2101 of the active layer 210. The interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the second pixel via can be removed, exposing at least a portion of the surface of the second region 2102 of the active layer 210. The source 211 of the thin-film transistor 21 can be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the drain 212 can be electrically connected to the second region 2102 of the active layer 210 through the second pixel via. The second source-drain metal layer may include at least a first transition electrode 231. The first transition electrode 231 can be electrically connected to the drain 212 of the thin-film transistor 21 of the pixel circuit through a third pixel via formed by the passivation layer 104 and the first planarization layer 105. The third source-drain metal layer may include at least a second transition electrode 232, which can be connected to the first transition electrode 231 through a fourth pixel via formed by the second planarization layer 106. The first conductive connection layer may include at least a third transition electrode 233, which can be connected to the second transition electrode 232 through a fifth pixel via formed by the third planarization layer 107. The second conductive connection layer may include at least a fourth transition electrode 234, which can be connected to the third transition electrode 233 through a sixth pixel via formed by the fourth planarization layer 108. The third conductive connection layer may include at least a fifth transition electrode 235, which can be connected to the fourth transition electrode 234 through a seventh pixel via formed by the fifth planarization layer 109. In some examples, the orthographic projection of the fifth, sixth, and seventh pixel vias onto the substrate can be rectangular or circular, for example, a square with a side length of 3 micrometers.For example, the orthographic projections of the seventh pixel via and the fifth pixel via on the substrate may coincide, while the orthographic projections of the sixth pixel via and the seventh pixel via on the substrate may not coincide. This example can achieve the electrical connection between the pixel circuit and the light-emitting element through a second source / drain metal layer, a third source / drain metal layer, and three conductive connection layers. However, this embodiment is not limited to this. In other examples, the number of conductive connection layers may be one, two, or more.

[0129] In some examples, the orthographic projections of the third adapter electrode 233, the fourth adapter electrode 234, and the fifth adapter electrode 235 onto the substrate can be rectangular. The orthographic projections of the third adapter electrode 233, the fourth adapter electrode 234, and the fifth adapter electrode 235 onto the substrate can overlap and can partially overlap with the orthographic projection of the second adapter electrode 232 onto the substrate.

[0130] In some examples, as shown in FIG5, the light-emitting structure layer 13 of the display area may include: a pixel definition layer 304 and a plurality of light-emitting elements (e.g., a plurality of second-area light-emitting elements located in the second display area and a plurality of first-area light-emitting elements located in the first display area). For example, each light-emitting element may include: a stacked first electrode 301, an organic light-emitting layer 302, and a second electrode 303. The first electrode 301 of the light-emitting element may be an anode. For example, the first electrode 301 of the second-area light-emitting element located in the second display area may be disposed on the fifth planarization layer 110 and electrically connected to the fifth transition electrode 235 through an eighth pixel via formed in the fifth planarization layer 110. The pixel definition layer 304 is disposed on the first electrode 301 and the fifth planarization layer 110. The pixel definition layer 304 may have a plurality of pixel openings, and one pixel opening may expose at least a portion of the surface of a corresponding first electrode 301. At least a portion of the organic light-emitting layer 302 may be disposed within a pixel opening and connected to the corresponding first electrode 301. The second electrode 303 may be disposed on the organic light-emitting layer 302 and connected to the organic light-emitting layer 302. The organic light-emitting layer 302 can emit light of the corresponding color under the drive of the first electrode 301 and the second electrode 303. An isolation pillar layer can also be provided on the side of the pixel definition layer 304 away from the substrate 10, and the isolation pillar layer can include multiple isolation pillars (PS).

[0131] In some examples, the organic light-emitting layer 302 of the light-emitting element may include an emitting layer (EML) and one or more films selected from the following: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 301 and the second electrode 303, the light-emitting properties of the organic material can be utilized to emit light at the required grayscale.

[0132] In some examples, the light-emitting layers of different colored light-emitting elements can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be common layers, as can the electron injection layer and electron transport layer on the other side. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0133] In some examples, as shown in Figure 5, the encapsulation structure layer 14 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked together. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, while the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 may be disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to prevent external moisture from entering the light-emitting element. However, this embodiment is not limited to this. For example, the encapsulation structure layer may employ a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0134] The circuit structure layer of the second display area is illustrated below with an example. Figures 6A to 6E illustrate two rows (e.g., row d and row d+1) and five columns (e.g., columns f to f+4) of pixel circuits in the second display area. Columns f, f+1, f+3, and f+4 include multiple second-type pixel circuits, and column f+2 includes multiple first-type pixel circuits. Here, f and d are both integers greater than 0.

[0135] Figure 6A is a partial schematic diagram of the semiconductor layer and the first gate metal layer of the second display area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 6A, the semiconductor layer of the second display area may include: an active layer of a plurality of transistors of a first type pixel circuit (e.g., an active layer including the first transistor T11 to the seventh transistor T17), and an active layer of a plurality of transistors of a second type pixel circuit (e.g., an active layer including the first transistor T21 to the seventh transistor T27). The active layers of the first transistors T11 to the seventh transistor T17 of the first type pixel circuit may be an integral structure interconnected with each other, and the active layers of the first transistors T21 to the seventh transistor T27 of the second type pixel circuit may be an integral structure interconnected with each other.

[0136] In some examples, as shown in Figure 6A, the first gate metal layer of the second display area may include: gates of a plurality of transistors of a first type of pixel circuit (e.g., gates of first transistor T11 to seventh transistor T17), and gates of a plurality of transistors of a second type of pixel circuit (e.g., gates of first transistor T21 to seventh transistor T27), scan lines (e.g., GL(d), GL(d+1)), a first reset control line (e.g., RST1(d), RST1(d+1)), and light emission control lines (e.g., EML(d), EML(d+1)). The first reset control line RST1(d+1) connected to the pixel circuit of the (d+1)th row can serve as a second reset control line connected to the pixel circuit of the dth row. The scan line GL(d) and the gates of the second transistor T12, the fourth transistor T14, the second transistor T22, and the fourth transistor T24 of the first type of pixel circuit located in the dth row can be an integral structure interconnected with each other. The first reset control line RST1(d), the gate of the first transistor T11 of the first type pixel circuit located in row d, and the gate of the first transistor T21 of the second type pixel circuit can be interconnected as a single structure. The light emission control line EML(d), the gate of the fifth transistor T15 of the first type pixel circuit, the gate of the sixth transistor T16, the gate of the fifth transistor T25 of the second type pixel circuit, and the gate of the sixth transistor T26 located in row d can be interconnected as a single structure. The gate of the third transistor T13 can serve as the first plate of the storage capacitor of the first type pixel circuit, and the gate of the third transistor T23 can serve as the first plate of the storage capacitor of the second type pixel circuit.

[0137] Figure 6B is a partial schematic diagram of the second gate metal layer of the second display area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 6C, the second gate metal layer of the second display area may include: a first initial signal line (e.g., INIT1(d), INIT1(d+1)), a second initial signal line (e.g., INIT2(d), INIT2(d-1)), a second electrode plate of the storage capacitor of the first type pixel circuit, and a second electrode plate of the storage capacitor of the second type pixel circuit. The second electrodes of the storage capacitors of the multiple second type pixel circuits located in the same row and the second electrodes of the storage capacitors of the multiple first type pixel circuits can be an integral structure interconnected.

[0138] Figure 6C is a partial schematic diagram of the first source / drain metal layer of the second display area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 6C, the first source / drain metal layer of the second display area may include: a plurality of pixel connection electrodes (e.g., first pixel connection electrodes 271 to sixth pixel connection electrodes 276, eleventh pixel connection electrodes 281 to sixteenth pixel connection electrodes 286) and a plurality of first auxiliary connection lines 261. The first auxiliary connection lines 261 may be located between two adjacent rows of pixel circuits and extend along the row direction X. The active layer of the first transistor T11 of the first type pixel circuit can be connected to the first initial signal line (e.g., INIT1(d)) through the eleventh pixel connection electrode 281. The gate of the third transistor T13 can be connected to the active layer of the second transistor T12 through the twelfth pixel connection electrode 282. The active layer of the fourth transistor T14 can be connected to the thirteenth pixel connection electrode 283. The active layer of the fifth transistor T15 can be connected to the second plate of the storage capacitor of the first type pixel circuit through the fifteenth pixel connection electrode 285. The active layer of the sixth transistor T16 can be connected to the fourteenth pixel connection electrode 284. The active layer of the seventh transistor T17 can be connected to the second initial signal line (e.g., INIT2(d)) through the sixteenth pixel connection electrode 286. The active layer of the first transistor T21 of the second type pixel circuit can be connected to the first initial signal line (e.g., INIT1(d)) through the first pixel connection electrode 271. The gate of the third transistor T23 can be connected to the active layer of the second transistor T22 through the second pixel connection electrode 272. The active layer of the fourth transistor T24 can be connected to the third pixel connection electrode 273. The active layer of the fifth transistor T25 can be connected to the second plate of the storage capacitor of the second type pixel circuit through the fifth pixel connection electrode 275. The active layer of the sixth transistor T26 can be connected to the fourth pixel connection electrode 274. The active layer of the seventh transistor T27 can be connected to the second initial signal line (e.g., INIT2(d)) through the sixth pixel connection electrode 276.

[0139] Figure 6D is a schematic diagram of the second source-drain metal layer of the second display area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 6D, the second source-drain metal layer of the second display area may include: data lines (e.g., DL(f), DL(f+2)), first power lines (e.g., PL1(f), PL1(f+2)), and a plurality of first transition electrodes 231 and a plurality of sixth transition electrodes 241. The data line DL(f) may be connected to the active layer of the fourth transistor of a column of second-type pixel circuits, and the data line DL(f+2) may be connected to the active layer of the fourth transistor of a column of first-type pixel circuits. The first power line PL1(f) may be connected to the fifth transistor and storage capacitor of a column of second-type pixel circuits, and the first power line PL1(f+2) may be connected to the fifth transistor and storage capacitor of a column of first-type pixel circuits. The first transition electrode 231 may be connected to the active layer of the sixth transistor of the second-type pixel circuit through the fourth pixel connection electrode 274. The sixth transition electrode 241 can be connected to the active layer of the sixth transistor of the first type pixel circuit through the fourteenth pixel connection electrode 284.

[0140] Figure 6E is a schematic diagram of the third source / drain metal layer of the second display area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 6E, the third source / drain metal layer of the second display area may include: multiple second auxiliary connection lines 262, multiple second transition electrodes 232, and multiple seventh transition electrodes 242. The second transition electrodes 232 may be connected to the first transition electrode 231. The seventh transition electrode 242 may be connected to the sixth transition electrode 241. The second auxiliary connection lines 262 may extend along the column direction Y. The second auxiliary connection lines 262 may be located on one side of the data lines. The second auxiliary connection lines 262 may be connected to the corresponding data lines and the first auxiliary connection lines 261 to realize the routing of data lines along the row direction near the edge of the display substrate from a position away from the edge of the display substrate to the bezel area.

[0141] In some examples, the orthographic projection of the second region light-emitting element in the second display area onto the substrate may overlap with the orthographic projection of at least one second-type pixel circuit onto the substrate. For example, the second-type pixel circuit that overlaps with the orthographic projection of the second region light-emitting element onto the substrate may not be electrically connected to the second region light-emitting element. The orthographic projections of the second region light-emitting element and the connected second-type pixel circuit onto the substrate may not overlap.

[0142] Figure 7A is a schematic diagram of the connection between the pixel circuit and the light-emitting element according to at least one embodiment of the present disclosure. Figure 7B is a schematic diagram of the pixel circuit and the conductive connection layer in Figure 7A. Figure 7C is a schematic diagram of the light-emitting element and the conductive connection layer in Figure 7A. This example illustrates a conductive connection layer as an example. Figures 7A to 7C illustrate four rows of pixel circuits (e.g., rows i to i+3) and four rows of light-emitting elements (e.g., rows j+1 to j+4). Here, i and j are both integers greater than 0. In this example, one row of pixel circuits is a pixel circuit group, and one row of light-emitting elements is a light-emitting element group. The first direction is the row direction X, and the second direction is the column direction Y. In some examples, the number of rows of pixel circuits can be greater than the number of rows of light-emitting elements to satisfy the staggered driving method of the pixel circuits and light-emitting elements.

[0143] In some examples, as shown in Figures 7A to 7C, a row of light-emitting elements may include: a plurality of first-area light-emitting elements located in a first display area A1 and a plurality of second-area light-emitting elements located in a second display area A2. The plurality of first-area light-emitting elements and the plurality of second-area light-emitting elements in a row may be arranged along the row direction X. For example, the plurality of second-area light-emitting elements may be located on both sides of the plurality of first-area light-emitting elements along the row direction X.

[0144] In some examples, the plurality of first-area light-emitting elements may include: a first light-emitting element 311 emitting a first color light, a third light-emitting element 313a emitting a third color light, a second light-emitting element 312 emitting a second color light, and a third light-emitting element 313b emitting a third color light, arranged periodically along the row direction X. Within the first display area A1, the plurality of first light-emitting elements 311 and the plurality of second light-emitting elements 312 may be alternately arranged along the column direction Y; the plurality of third light-emitting elements 313a and the plurality of third light-emitting elements 313b may be alternately arranged along the column direction Y.

[0145] In some examples, the plurality of second-area light-emitting elements may include: a fourth light-emitting element 321 emitting a first color light, a sixth light-emitting element 323a emitting a third color light, a fifth light-emitting element 322 emitting a second color light, and a sixth light-emitting element 323b emitting a third color light, arranged periodically along the row direction X. Within the second display area A2, the plurality of fourth light-emitting elements 321 and the plurality of fifth light-emitting elements 322 may be alternately arranged along the column direction Y; the plurality of sixth light-emitting elements 323a and the plurality of sixth light-emitting elements 323b may also be alternately arranged along the column direction Y. For example, the first color light is red, the second color light is blue, and the third color light is green.

[0146] In some examples, as shown in Figures 7A and 7B, a row of pixel circuits in the second display area A2 may include first-type pixel circuits 41 and second-type pixel circuits 42 spaced apart along the row direction X. For example, a column of first-type pixel circuits 41 may be spaced apart every four columns of second-type pixel circuits 42.

[0147] In some examples, a row of pixel circuits is configured to drive a row of light-emitting elements. For example, the i-th row of pixel circuits can be configured to drive the j-th row of light-emitting elements, the (i+1)-th row of pixel circuits can be configured to drive the (j+1)-th row of light-emitting elements, the (i+2)-th row of pixel circuits can be configured to drive the (j+2)-th row of light-emitting elements, and the (i+3)-th row of pixel circuits can be configured to drive the (j+3)-th row of light-emitting elements. Here, i and j can be integers greater than 0. For example, at least one first-type pixel circuit 41 within the (i+1)-th row of pixel circuits can be connected to at least one first-area light-emitting element located in the first display area A1 within the (j+1)-th row of light-emitting elements, and at least one second-type pixel circuit 42 within the (i+1)-th row of pixel circuits can be connected to at least one second-area light-emitting element located in the second display area A2 within the (j+1)-th row of light-emitting elements.

[0148] In some examples, the orthographic projections of the second-region light-emitting element and the connected second-type pixel circuit 42 onto the substrate may not overlap, but may overlap with the orthographic projections of unconnected second-type pixel circuits 42 onto the substrate. For example, the orthographic projections of the i-th row pixel circuit overlap with those of multiple second-region light-emitting elements in the (j+1)-th row, the i+1-th row pixel circuit overlaps with those of multiple second-region light-emitting elements in the (j+2)-th row, the i+2-th row pixel circuit overlaps with those of multiple second-region light-emitting elements in the (j+3)-th row, and the i+3-th row pixel circuit overlaps with those of multiple second-region light-emitting elements in the (j+4)-th row. A row of light-emitting elements that overlaps with the orthographic projection of a row of pixel circuits is located on the opposite side of the row of light-emitting elements connected to that row of pixel circuits in the column direction Y.

[0149] In some examples, the first type of pixel circuit 41 connected to the first area light-emitting element near the second display area A2 within a row of light-emitting elements can be located on the side of the first type of pixel circuit 41 connected to the first area light-emitting element away from the second display area A2, away from the first display area A1. In other words, the first area light-emitting element near the boundary between the first display area A1 and the second display area A2 is connected to the first type of pixel circuit 41 away from the first display area A1, and the first area light-emitting element away from the boundary between the first display area A1 and the second display area A2 is connected to the first type of pixel circuit 41 near the first display area A1.

[0150] In some examples, the first light-emitting element 311 in the (j+1)th row of light-emitting elements, near the boundary of the first display area A1 and the second display area A2, can be connected to the fourth column of the first type pixel circuit 41 in the (i+1)th row of pixel circuits via the first conductive connection line 511; the third light-emitting element 313a in the (j+1)th row of light-emitting elements, near the boundary of the first display area A1 and the second display area A2, can be connected to the third column of the first type pixel circuit 41 in the (i+1)th row of pixel circuits via the third conductive connection line 513a; the second light-emitting element 312 in the (j+1)th row of light-emitting elements, near the boundary of the first display area A1 and the second display area A2, can be connected to the second column of the first type pixel circuit 41 in the (i+1)th row of pixel circuits via the second conductive connection line 512; and the third light-emitting element 313b in the (j+1)th row of light-emitting elements, near the boundary of the first display area A1 and the second display area A2, can be connected to the first column of the first type pixel circuit 41 in the (i+1)th row of pixel circuits via the third conductive connection line 513b. The first, second, third, and fourth columns of first-type pixel circuits 41 are arranged along a direction away from the first display area A1. This example only uses four columns of first-type pixel circuits as an example.

[0151] In some examples, the first conductive connection line 511, the second conductive connection line 512, and the third conductive connection lines 513a and 513b can be located on the same layer, for example, on the first conductive connection layer. Multiple conductive connection lines connecting multiple first region light-emitting elements within a row of light-emitting elements can be located on the same side of the row of light-emitting elements in the column direction Y, for example, they can all be located on the underside of the row of light-emitting elements.

[0152] In some examples, as shown in Figure 7B, taking the first conductive connection line 511 as an example, the first conductive connection line 511 may include: a main body segment 5110 extending along the row direction X, a first connecting segment 5111 and a second connecting segment 5112 extending at least along the column direction Y. The main body segment 5110 is connected between the first connecting segment 5111 and the second connecting segment 5112. The first connecting segment 5111 is connected to the first type pixel circuit 41, and the second connecting segment 5112 is connected to the anode of the first light-emitting element 311. The first connecting segment 5111 and the second connecting segment 5112 of the first conductive connection line 511 may be located on both sides of the main body segment 5110 along the column direction Y. The main body segment 5110, the first connecting segment 5111 and the second connecting segment 5112 of the first conductive connection line 511 may be an integral structure interconnected with each other. The structures of the second conductive connection line 512 and the third conductive connection lines 513a and 513b are similar to those of the first conductive connection line 511, and therefore will not be described in detail here. The structure of the conductive connection line in this example enables an electrical connection between a first type of pixel circuit that is not aligned in the X-direction and a first region light-emitting element.

[0153] In some examples, within the first display area A1, multiple first-area light-emitting elements can be connected to multiple conductive lines via multiple first adapters (e.g., first adapters 611, 612, 613a, and 613b). For example, a first light-emitting element 311 can be connected to a first conductive line 511 via first adapter 611, a second light-emitting element 312 can be connected to a second conductive line 512 via first adapter 612, a third light-emitting element 313a can be connected to a third conductive line 513a via first adapter 613a, and a third light-emitting element 313b can be connected to a third conductive line 513b via first adapter 613b. Multiple first adapters connected to a row of first-area light-emitting elements can be aligned along the row direction X. In some examples, the orthographic projection of the first adapter onto the substrate can be rectangular or rounded. Multiple first adapters can be located in the anode layer; for example, the anode of the first-area light-emitting element and the connected first adapter can be an integrally connected structure.

[0154] In some examples, within the second display area A2, multiple second-region light-emitting elements can be connected to multiple adapter electrodes via multiple second adapter lines (e.g., second adapter lines 721, 722, 723a, and 723b) and multiple second adapters (e.g., second adapters 711, 712, 713a, and 713b) to achieve connection with a second-type pixel circuit. For example, a fourth light-emitting element 321 can be connected to a second adapter 711 via second adapter line 721, and the second adapter 711 can be connected to a second-type pixel circuit; a fifth light-emitting element 322 can be connected to a second adapter 712 via second adapter line 722; a sixth light-emitting element 323a can be connected to a first adapter 713a via second adapter line 723a; and a third light-emitting element 323b can be connected to a second adapter 713b via second adapter line 723b. The orthographic projections of the multiple second adapters onto the substrate and the orthographic projections of the connected second-type pixel circuits onto the substrate can at least partially overlap.

[0155] In some examples, the orthographic projection of the second adapter onto the substrate can be rectangular or rounded. The second adapter line can be a broken line segment extending along the column direction Y. Multiple second adapters and multiple second adapter lines can be a co-layer structure, for example, located in the anode layer. The anode of the second region light-emitting element and the connected second adapter lines and second adapters can be an integral structure interconnected. For example, the second adapter wire 721 connected to the fourth light-emitting element 321 in the second region of the j+1 row can be located on the side opposite to the row direction X of the anode of the fifth light-emitting element 322 in the second region of the j+2 row; the second adapter wire 723a connected to the sixth light-emitting element 323a in the second region of the j+1 row can be located on the side opposite to the row direction X of the anode of the fifth light-emitting element 322 in the second region of the j+2 row; the second adapter wire 722 connected to the fifth light-emitting element 322 in the second region of the j+1 row can be located on the side opposite to the row direction X of the anode of the fourth light-emitting element 321 in the second region of the j+2 row; and the second adapter wire 723b connected to the sixth light-emitting element 323b in the second region of the j+1 row can be located on the side opposite to the row direction X of the anode of the fourth light-emitting element 321 in the second region of the j+2 row.

[0156] In some examples, multiple second adapters connected to the second region light-emitting elements in a row can be aligned along the row direction X and staggered with multiple first adapters connected to the first region light-emitting elements in the same row along the row direction X.

[0157] This example uses one row of pixel circuitry to drive another row of light-emitting elements, with the row of light-emitting elements driven by this row of pixel circuitry located on the opposite side of the column direction of this row of pixel circuitry. For example, the light-emitting elements in this row overlap with the orthographic projection of the previous row of pixel circuitry onto the substrate. This example can reduce the parasitic capacitance of conductive interconnects, making the ratio of the maximum capacitance to the minimum capacitance of multiple conductive interconnects close to 1, which is beneficial for improving the wiring uniformity of conductive interconnects.

[0158] Figure 8A is another schematic diagram of the connection between the pixel circuit and the light-emitting element according to at least one embodiment of the present disclosure. Figure 8B is a schematic diagram of the pixel circuit and the conductive connection layer in Figure 8A. Figure 8C is a schematic diagram of the light-emitting element and the conductive connection layer in Figure 8A. This example illustrates a conductive connection layer as an example. Figures 8A to 8C illustrate four rows of pixel circuits (e.g., rows i to i+3) and four rows of light-emitting elements (e.g., rows j-1 to j+2). Here, i and j are both integers greater than 0. In this example, one row of pixel circuits is a pixel circuit group, and one row of light-emitting elements is a light-emitting element group. The first direction is the row direction X, and the second direction is the column direction Y.

[0159] In some examples, as shown in Figures 8A to 8C, the pixel circuit in row i can be configured to drive the light-emitting element in row j, the pixel circuit in row i+1 can be configured to drive the light-emitting element in row j+1, the pixel circuit in row i+2 can be configured to drive the light-emitting element in row j+2, and the pixel circuit in row i+3 can be configured to drive the light-emitting element in row j+3. For example, a first type of pixel circuit in row i+1 can be connected to a first region light-emitting element in row j+1, and a second type of pixel circuit can be connected to a second region light-emitting element in row j+1.

[0160] In some examples, the orthographic projections of the pixel circuit in row i overlap with those of multiple second-region light-emitting elements in row j-1, row i+1, row j, row i+2, and row i+3, and row j+2, respectively. A row of light-emitting elements whose orthographic projections overlap with those of a row of pixel circuits is located on the Y-side of the row of pixel circuits connected to that row.

[0161] In some examples, the first type pixel circuit 41 connected to the first area light-emitting element in a row of light-emitting elements near the second display area A2 may be located on the side of the first type pixel circuit 41 connected to the first area light-emitting element away from the first display area A1.

[0162] This example utilizes a row of pixel circuits to drive another row of light-emitting elements, with the row of light-emitting elements driven by the pixel circuits located on one side of the row of pixel circuits in the column direction. For example, the light-emitting elements in this row overlap with the orthographic projection of the next row of pixel circuits onto the substrate. This example can reduce the parasitic capacitance of conductive interconnects, making the ratio of the maximum capacitance to the minimum capacitance of multiple conductive interconnects close to 1, which is beneficial for improving the wiring uniformity of conductive interconnects. Further description of the display substrate in this example can be found in the description of the foregoing embodiments, and therefore will not be repeated here.

[0163] Figure 9A is another schematic diagram showing the connection between the pixel circuit and the light-emitting element according to at least one embodiment of the present disclosure. Figure 9B is a schematic diagram of the pixel circuit and the conductive connection layer in Figure 9A. Figure 9C is a schematic diagram of the light-emitting element and the conductive connection layer in Figure 9A. This example illustrates two conductive connection layers (e.g., including a first conductive connection layer and a second conductive connection layer). Figures 9A to 9C illustrate four rows of pixel circuits (e.g., rows i to i+3) and four rows of light-emitting elements (e.g., rows j+1 to j+4). In this example, one row of pixel circuits is a pixel circuit group, and one row of light-emitting elements is a light-emitting element group. The first direction is the row direction X, and the second direction is the column direction Y.

[0164] In some examples, as shown in Figures 9A to 9C, the first type pixel circuit 41 connected to the third light-emitting elements 313a and 313b in a row of light-emitting elements can be located on the side of the first type pixel circuit 41 connected to the first light-emitting element 311 and the second light-emitting element 312 closer to the first display area A1. In other words, this example preferentially arranges the first type pixel circuits that drive the third light-emitting elements to emit a third color light (e.g., green light) to reduce the length of the third conductive connection lines 513a and 513b connected to the third light-emitting elements.

[0165] In some examples, the first conductive connection line 511 connected to the first light-emitting element 311 and the second conductive connection line 512 connected to the second light-emitting element 312 can be located in the same conductive layer, for example, in the first conductive connection layer; the multiple third conductive connection lines 513a and 513b connected to the multiple third light-emitting elements 313a and 313b can be located in the same conductive layer, for example, in the second conductive connection layer. The second conductive connection layer can be located on the side of the first conductive connection layer away from the substrate.

[0166] In some examples, the orthographic projections of the second-region light-emitting element and the connected second-type pixel circuit 42 on the substrate may not overlap, but may overlap with the orthographic projections of unconnected second-type pixel circuits 42 on the substrate. For example, the orthographic projections of the i-th row pixel circuit overlap with those of multiple second-region light-emitting elements in the (j+1)-th row, the i+1-th row pixel circuit overlaps with those of multiple second-region light-emitting elements in the (j+2)-th row, the i+2-th row pixel circuit overlaps with those of multiple second-region light-emitting elements in the (j+3)-th row, and the i+3-th row pixel circuit overlaps with those of multiple second-region light-emitting elements in the (j+4)-th row. A row of light-emitting elements that overlaps with the orthographic projection of a row of pixel circuits on the substrate is located on the opposite side of the row of pixel circuits connected to that row in the column direction Y. However, this embodiment is not limited to this. In other examples, a row of light-emitting elements that overlaps with the orthographic projection of a row of pixel circuits onto the substrate can be located on the Y-side of the row of pixel circuits to which the row of pixel circuits is connected.

[0167] The remaining description of the display substrate in this example can be found in the description of the embodiment shown in FIG7A, and therefore will not be repeated here.

[0168] Figure 10 is a schematic diagram comparing the maximum and minimum capacitance values ​​of the conductive connection lines according to at least one embodiment of this disclosure. In Figure 10, line L11 represents the capacitance change line of the first conductive connection line after adopting the misaligned driving method shown in Figure 9A, line L12 represents the capacitance change line of the second conductive connection line after adopting the misaligned driving method shown in Figure 9A, and line L13 represents the capacitance change line of the third conductive connection line after adopting the misaligned driving method shown in Figure 9A. In some conventional implementations, the first region light-emitting element and the first type pixel circuit adopt a close-to-close driving method, and the pixel circuit of the same row can drive the light-emitting elements of the same row whose orthogonal projections on the substrate overlap. Line L01 represents the capacitance change line of the first conductive connection line using a conventional scheme, line L02 represents the capacitance change line of the second conductive connection line using a conventional scheme, and line L03 represents the capacitance change line of the third conductive connection line using a conventional scheme.

[0169] In some examples, as shown in Figure 10, after adopting the staggered driving method shown in Figure 9A, the maximum capacitance of the conductive connection line is significantly reduced, and the ratio of the maximum capacitance to the minimum capacitance of the conductive connection line decreases substantially, with the trend of change becoming more gradual. The maximum capacitance of the first, second, and third conductive connection lines is reduced by about 1 / 3, and the ratio of the maximum capacitance to the minimum capacitance is closer to 1. This embodiment allows different light-emitting elements to be illuminated under high-frequency, low-grayscale conditions (e.g., 120Hz 5nitL32), with more uniform illumination.

[0170] Figure 11 is a schematic diagram showing the connection between a first-area light-emitting element and a first pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 11, a plurality of first-type pixel circuits may include: a plurality of first pixel circuits 411, a plurality of second pixel circuits 412, and a plurality of third pixel circuits 413. At least one first pixel circuit 411 is connected to at least one first light-emitting element 311 via a first conductive connection line 511, at least one second pixel circuit 412 is connected to at least one second light-emitting element 312 via a second conductive connection line 512, and at least one third pixel circuit 413 is connected to at least two third light-emitting elements 313a and 313b via a third conductive connection line 513. For example, the first pixel circuit 411 and the first light-emitting element 311 are connected in a one-to-one relationship, the second pixel circuit 412 and the second light-emitting element 312 are connected in a one-to-one relationship, and the third pixel circuit 413 and the third light-emitting elements 313a and 313b are connected in a one-to-two relationship. The plurality of third pixel circuits 413 may be located on the side of the plurality of first pixel circuits 411 and the plurality of second pixel circuits 412 near the first display area A1.

[0171] In some examples, as shown in Figure 11, the second display area A2 may include, along a direction away from the first display area A1, a transition area A20, a first sub-area A21, a second sub-area A22, a third sub-area A23, and a fourth sub-area A24. The transition area A20 may be provided with multiple second invalid pixel circuits 415. The second invalid pixel circuits 415 may not be connected to the first area light-emitting element. The first sub-area A21 may be provided with multiple columns of third pixel circuits 413. The second sub-area A22 and the third sub-area A23 may be provided with multiple first pixel circuits 411 and multiple second pixel circuits 412. A column of first-type pixel circuits within the second sub-area A22 and the third sub-area A23 may include alternating first pixel circuits 411 and second pixel circuits 412 along the column direction Y. The fourth sub-area A24 may be provided with multiple first invalid pixel circuits 414. The first invalid pixel circuits 414 may not be connected to the first area light-emitting element.

[0172] In some examples, as shown in Figure 11, the third conductive connection line 513 connected to the third pixel circuit 413 in the first sub-region A21 can be located in the first conductive connection layer; the first conductive connection line 511 connected to the first pixel circuit 411 and the second conductive connection line 512 connected to the second pixel circuit 412 in the second sub-region A22 can be located in the second conductive connection layer; and the first conductive connection line 511 connected to the first pixel circuit 411 and the second conductive connection line 512 connected to the second pixel circuit 412 in the third sub-region A23 can be located in the third conductive connection layer. The first conductive connection layer, the second conductive connection layer, and the third conductive connection layer can be arranged sequentially along a direction away from the substrate.

[0173] In some examples, one row of pixel circuitry can drive another row of light-emitting elements; for example, one row of pixel circuitry can drive either the previous row or the next row of light-emitting elements. The misalignment driving method in this example can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0174] Figure 12A is another schematic diagram of the connection between the pixel circuit and the light-emitting element according to at least one embodiment of the present disclosure. Figure 12B is a schematic diagram of the pixel circuit and the conductive connection layer in Figure 12A. In some examples, as shown in Figures 12A and 12B, the first display area A1 may include: a first region A11 and a second region A12 arranged along the row direction X; the second display area A2 may include: a first side region A2a and a second side region A2b located on both sides of the first display area A1 along the row direction X. A row of pixel circuits in the second display area A2 may include: two sub-pixel circuit groups located in the first side region A2a and the second side region A2b. For example, the i-th row of pixel circuits may include: a first sub-pixel circuit group located in the first side region A2a and a second sub-pixel circuit group located in the second side region A2b. The light-emitting elements connected to the first sub-pixel circuit group and the light-emitting elements connected to the second sub-pixel circuit group are staggered in the row direction X, for example, located in different rows. For example, the first sub-pixel circuit group of the i-th row of pixel circuits drives the light-emitting elements of the previous row (e.g., the second light-emitting element located in the first side region A2a and the first light-emitting element located in the first region A11 within the j-th row of light-emitting elements), and the second sub-pixel circuit group drives the light-emitting elements of the next row (e.g., the second light-emitting element located in the second side region A2b and the first light-emitting element located in the second region A12 within the (j-1)-th row of light-emitting elements). However, this embodiment is not limited to this. In other examples, the first sub-pixel circuit group can drive the light-emitting elements of the next row, and the second sub-pixel circuit group can drive the light-emitting elements of the previous row. The misalignment driving method of this example can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0175] In some examples, the gate traces connected to the first sub-pixel circuit group in the i-th row pixel circuit are disconnected from the gate traces connected to the second sub-pixel circuit group to avoid signal crosstalk caused by the different driving methods of the pixel circuits on both sides of the first display area A1.

[0176] Figure 13 is a schematic diagram of another arrangement of pixel circuits in the second display area of ​​a display substrate according to at least one embodiment of the present disclosure. In some examples, the area for setting the newly added pixel circuits (including the first type pixel circuits 41) can be obtained by reducing the size of the second type pixel circuits 42 in the column direction Y. For example, the size of the pixel circuits in the column direction Y can be smaller than the size of the second region light-emitting element 32 in the column direction Y. In some examples, the original h rows of pixel circuits can be compressed along the column direction Y to add a row of pixel circuit arrangement space, and the space occupied by the h rows of pixel circuits before compression and the h+1 rows of pixel circuits after compression can be the same. Here, h can be an integer greater than 1. As shown in Figure 13, four rows of second type pixel circuits 42 can be arranged between two adjacent rows of first type pixel circuits 41 along the column direction Y. In other words, a row of first type pixel circuits 41 is inserted every four rows of second type pixel circuits 42.

[0177] Figure 14A is another schematic diagram showing the connection between the pixel circuit and the light-emitting element according to at least one embodiment of the present disclosure. Figure 14B is a schematic diagram showing the connection between the pixel circuit and the light-emitting element in the first region in Figure 14A. Figures 14A and 14B are illustrated using multiple columns of pixel circuits (e.g., including columns i to i+3) and multiple columns of light-emitting elements as examples. In this example, one column of pixel circuits is a pixel circuit group, and one column of light-emitting elements is a light-emitting element group. The first direction is the column direction Y, and the second direction is the row direction X. In some examples, the number of columns of pixel circuits can be greater than the number of columns of light-emitting elements to satisfy the staggered driving mode of pixel circuits and light-emitting elements.

[0178] In some examples, as shown in Figures 14A and 14B, a column of light-emitting elements may include: a plurality of first-area light-emitting elements located in the first display area A1 and a plurality of second-area light-emitting elements located in the second display area A2. For example, the i-th column of light-emitting elements may include: a fourth light-emitting element 321 and a fifth light-emitting element 322 located in the second display area A2 and alternately arranged along the column direction Y, and a first light-emitting element 311 and a second light-emitting element 312 located in the first display area A1 and alternately arranged along the column direction Y; the (i+1)-th column of light-emitting elements may include: a sixth light-emitting element 323a and 323b located in the second display area A2 and alternately arranged along the column direction Y, and a third light-emitting element 313a and 313b located in the first display area A1 and alternately arranged along the column direction Y.

[0179] In some examples, a column of pixel circuits can be configured to drive a column of light-emitting elements. For example, the i-th column of pixel circuits can be configured to drive the leftmost column (e.g., the j-th column) of light-emitting elements. A first type of pixel circuit within the i-th column of pixel circuits can be connected to a first region light-emitting element within the j-th column of light-emitting elements via conductive connecting lines, and a second type of pixel circuit within the i-th column of pixel circuits can be connected to a second region light-emitting element within the j-th column of light-emitting elements.

[0180] In some examples, the orthographic projections of the second region light-emitting element and the connected second type pixel circuit on the substrate may not overlap, but may overlap with the orthographic projections of the unconnected second type pixel circuits on the substrate. A column of light-emitting elements that overlaps with the orthographic projections of a column of pixel circuits on the substrate may be located on the opposite side of the column of light-emitting elements connected to that column of pixel circuits in the row direction X.

[0181] In some examples, the first type of pixel circuit 41 connected to the first area light-emitting element near the second display area A2 within a column of light-emitting elements can be located on the side of the first type of pixel circuit 41 connected to the first area light-emitting element away from the second display area A2, away from the first display area A1. In other words, the first area light-emitting element near the boundary between the first display area A1 and the second display area A2 is connected to the first type of pixel circuit 41 away from the first display area A1, and the first area light-emitting element away from the boundary between the first display area A1 and the second display area A2 is connected to the first type of pixel circuit 41 near the first display area A1.

[0182] This example utilizes a column of pixel circuits to drive another column of light-emitting elements, with the column of light-emitting elements driven by the pixel circuits located on the opposite side of the row direction of the pixel circuits. This example can reduce the parasitic capacitance of conductive connection lines, making the ratio of the maximum capacitance value to the minimum capacitance value of multiple conductive connection lines close to 1, which is beneficial to improving the wiring uniformity of conductive connection lines. Further descriptions of this example can be found in the foregoing embodiments and will not be repeated here.

[0183] Figure 15A is another schematic diagram showing the connection between the pixel circuit and the light-emitting element according to at least one embodiment of the present disclosure. Figure 15B is a schematic diagram showing the connection between the pixel circuit and the light-emitting element in the first region in Figure 15A. Figures 15A and 15B are illustrated using multiple columns of pixel circuits (e.g., including columns i to i+3) and multiple columns of light-emitting elements as examples. In this example, one column of pixel circuits is a pixel circuit group, and one column of light-emitting elements is a light-emitting element group. The first direction is the column direction Y, and the second direction is the row direction X.

[0184] In some examples, as shown in Figures 15A and 15B, a column of pixel circuits can be configured to drive a column of light-emitting elements. For example, the i-th column of pixel circuits can be configured to drive the rightmost column (e.g., the j-th column) of light-emitting elements. A first type of pixel circuit within the i-th column of pixel circuits can be connected to a first region light-emitting element within the j-th column of light-emitting elements via conductive connecting lines, and a second type of pixel circuit within the i-th column of pixel circuits can be connected to a second region light-emitting element within the j-th column of light-emitting elements.

[0185] In some examples, the orthographic projections of the second region light-emitting element and the connected second type pixel circuit on the substrate may not overlap, but may overlap with the orthographic projections of the unconnected second type pixel circuits on the substrate. A column of light-emitting elements that overlaps with the orthographic projections of a column of pixel circuits on the substrate may be located on one side of the column of light-emitting elements connected to that column of pixel circuits in the row direction X.

[0186] This example utilizes a column of pixel circuits to drive another column of light-emitting elements, with the column of light-emitting elements driven by the pixel circuits located on one side of the column of pixel circuits in the row direction. This example can reduce the parasitic capacitance of conductive connection lines, making the ratio of the maximum capacitance value to the minimum capacitance value of multiple conductive connection lines close to 1, which is beneficial to improving the wiring uniformity of conductive connection lines. Further descriptions of this example can be found in the description of the embodiment shown in FIG14A, and will not be repeated here.

[0187] Figure 16A is another schematic diagram showing the connection between the pixel circuit and the light-emitting element according to at least one embodiment of the present disclosure. Figure 16B is a schematic diagram of the pixel circuit and the conductive connection layer in Figure 16A. Figure 16C is a schematic diagram of the light-emitting element and the conductive connection layer in Figure 16A. This example uses a conductive connection layer as an example for illustration. Figures 16A to 16C illustrate four rows of pixel circuits (e.g., rows i to i+3) and four rows of light-emitting elements (e.g., rows i to i+3). In this example, one row of pixel circuits is a pixel circuit group, and one row of light-emitting elements is a light-emitting element group. The first direction is the row direction X, and the second direction is the column direction Y.

[0188] In some examples, as shown in Figures 16A to 16C, a row of pixel circuitry is configured to drive a row of light-emitting elements. For example, the i-th row of pixel circuitry is configured to drive the i-th row of light-emitting elements, the (i+1)-th row of pixel circuitry is configured to drive the (i+1)-th row of light-emitting elements, and the (i+2)-th row of pixel circuitry is configured to drive the (i+2)-th row of light-emitting elements. The orthographic projections of the plurality of second-region light-emitting elements within the i-th row of light-emitting elements onto the substrate at least partially overlap with the orthographic projections of the i-th row of pixel circuitry onto the substrate.

[0189] In some examples, the i+2 row pixel circuit drives the i+2 row light-emitting element. Multiple second-region light-emitting elements within the i+2 row are electrically connected to a second-type pixel circuit 42 of the i+2 row pixel circuit. For example, one second-type pixel circuit 42 drives one second-region light-emitting element, and the orthographic projection of the second-type pixel circuit 42 onto the substrate and the orthographic projection of the driven second-region light-emitting element onto the substrate may partially overlap. Multiple first-region light-emitting elements within the i+2 row can be connected to multiple first-type pixel circuits 41 of the i+2 row pixel circuit via multiple first adapters, multiple first adapter lines, and multiple conductive connection lines. For example, the first adapters connected to the multiple first-region light-emitting elements within the i+2 row can be misaligned with the i+2 row pixel circuit in the row direction X. For example, the multiple first adapters connected to the i+2 row light-emitting elements can be aligned with the i+1 row pixel circuit.

[0190] In some examples, the plurality of first-area light-emitting elements may include: a plurality of first light-emitting elements 311, a plurality of second light-emitting elements 312, and a plurality of third light-emitting elements 313a and 313b. The first light-emitting element 311 can be connected to a first conductive connection line 511 via a first adapter 611 and a first adapter wire 621, the first conductive connection line 511 extending to the second display area A2 and connecting to the first pixel circuit. The second light-emitting element 312 can be connected to the second conductive connection line 512 via a first adapter 612 and a first adapter wire 622, the second conductive connection line 512 extending to the second display area A2 and connecting to the second pixel circuit. The third light-emitting element 313a can be connected to the third conductive connection line 513a via a first adapter 613a and a first adapter wire 623a, the third conductive connection line 513a extending to the second display area A2 and connecting to the third pixel circuit. The third light-emitting element 313b can be connected to the third conductive connection line 513b through the first adapter 613b and the first adapter line 623b. The third conductive connection line 513b can extend to the second display area A2 and be connected to the third pixel circuit.

[0191] In some examples, the plurality of first adapters connected to the plurality of first region light-emitting elements within the (i+2)th row of light-emitting elements may include: first adapter 611, first adapter 612, and first adapters 613a and 613b. The plurality of first adapters connected to the plurality of first region light-emitting elements within the (i+2)th row of light-emitting elements may be arranged sequentially along the row direction X and aligned with the pixel circuit of the (i+1)th row. For example, the plurality of first adapters may be located in the anode layer, and the first adapters and the anodes of the connected first region light-emitting elements may be an integral structure interconnected. However, this embodiment is not limited to this. In other examples, the plurality of first adapters may be located in a conductive connection layer.

[0192] In some examples, within the first display area A1, multiple first-area light-emitting elements can be connected to multiple conductive connection lines via multiple first adapter lines (e.g., first adapter lines 621, 622, 623a, and 623b) and multiple first adapters (e.g., first adapters 611, 612, 613a, and 613b). For example, a first light-emitting element 311 can be connected to a first adapter 611 via first adapter line 621, a second light-emitting element 312 can be connected to a first adapter 612 via first adapter line 622, a third light-emitting element 313a can be connected to a first adapter 613a via first adapter line 623a, and a third light-emitting element 313b can be connected to a first adapter 613b via first adapter line 623b. In some examples, the orthographic projection of the first adapter onto the substrate can be rectangular or rounded, and the first adapter line can be a broken line segment extending along the column direction Y. The multiple first adapters and multiple first adapter lines can be a co-layer structure, for example, located in the anode layer. The anode of the light-emitting element in the first region and the connected first adapter and first adapter cable can be an integrated structure that is interconnected.

[0193] In some examples, within the second display area A2, multiple second-region light-emitting elements can be connected to multiple adapter electrodes via multiple second adapters (e.g., second adapters 711, 712, 713a, and 713b) to achieve connection with a second type of pixel circuit. For example, the anode of the fourth light-emitting element 321 is connected to the second adapter 711, the anode of the fifth light-emitting element 322 is connected to the second adapter 712, the anode of the sixth light-emitting element 323a is connected to the second adapter 713a, and the anode of the sixth light-emitting element 323b is connected to the second adapter 713b. Multiple second adapters connected to a row of second-region light-emitting elements can be aligned along the row direction X. In some examples, the orthographic projection of the second adapter onto the substrate can be rectangular or rounded. Multiple second adapters can be located in the anode layer; for example, the anode of the second-region light-emitting element and the connected second adapter can be an integrally connected structure.

[0194] In some examples, multiple second adapters connected to a row of second-area light-emitting elements can be aligned along the row direction X and staggered with multiple first adapters connected to the first-area light-emitting elements in the same row in the row direction X, for example, aligned with multiple first adapters connected to the first-area light-emitting elements in adjacent rows in the row direction X.

[0195] In this example, multiple first-area light-emitting elements are connected to multiple conductive connecting lines via multiple first adapters and multiple first adapter cables, achieving a staggered driving effect between the first-area light-emitting elements and the first-type pixel circuit. This example can reduce the parasitic capacitance of the conductive connecting lines, making the ratio of the maximum capacitance value to the minimum capacitance value of multiple conductive connecting lines close to 1, which is beneficial to improving the wiring uniformity of the conductive connecting lines.

[0196] Figure 17A is another schematic diagram of the connection between the pixel circuit and the light-emitting element according to at least one embodiment of the present disclosure. Figure 17B is a schematic diagram of the pixel circuit and the conductive connection layer in Figure 17A. Figure 17C is a schematic diagram of the light-emitting element and the conductive connection layer in Figure 17A. This example illustrates a conductive connection layer as an example. Figures 17A to 17C illustrate four rows of pixel circuits (e.g., rows i to i+3) and four rows of light-emitting elements (e.g., rows i to i+3). In this example, one row of pixel circuits is a pixel circuit group, and one row of light-emitting elements is a light-emitting element group. The first direction is the row direction, and the second direction is the column direction.

[0197] In some examples, as shown in Figures 17A to 17C, a row of pixel circuitry is configured to drive a row of light-emitting elements. For example, the i-th row of pixel circuitry is configured to drive the i-th row of light-emitting elements, wherein the orthographic projection of a plurality of second-region light-emitting elements within the i-th row of light-emitting elements onto the substrate at least partially overlaps with the orthographic projection of the i-th row of pixel circuitry onto the substrate.

[0198] In some examples, the plurality of first-area light-emitting elements may include: a plurality of first light-emitting elements 311, a plurality of second light-emitting elements 312, and a plurality of third light-emitting elements 313a and 313b. The first light-emitting element 311 can be connected to a first conductive connection line 511 via a first adapter 611 and a first adapter wire 621, the first conductive connection line 511 extending to the second display area A2 and connecting to the first pixel circuit. The second light-emitting element 312 can be connected to the second conductive connection line 512 via a first adapter 612 and a first adapter wire 622, the second conductive connection line 512 extending to the second display area A2 and connecting to the second pixel circuit. Adjacent third light-emitting elements 313a and 313b can be connected to the third conductive connection line 513 via a first adapter 613 and a first adapter wire 623, the third conductive connection line 513 extending to the second display area A2 and connecting to the third pixel circuit. In this example, one third pixel circuit can be configured to drive two adjacent third light-emitting elements.

[0199] In some examples, multiple first adapters connected to multiple first region light-emitting elements within a row of light-emitting elements can be arranged sequentially along the row direction X and aligned with the adjacent row of pixel circuits.

[0200] In some examples, the first adapter lines 621 and 622 can be broken line segments extending along the column direction Y. The first adapter line 623 can include a first broken line segment extending along the column direction Y and a second broken line segment extending along the row direction X. The first broken line segment can be connected between the anode of the third light-emitting element 313a and the first adapter 613, and the second broken line segment can be connected between the anode of the third light-emitting element 313b and the first broken line segment. The first broken line segment and the second broken line segment can be an integral structure that is interconnected.

[0201] The third pixel circuit in this example is configured to drive two adjacent third light-emitting elements. This helps to reduce the maximum capacitance value of the third conductive connection line, and makes the ratio of the maximum capacitance value to the minimum capacitance value of multiple conductive connection lines close to 1, which helps to improve the wiring uniformity of the conductive connection lines. Further descriptions of the display substrate in this example can be found in the description of the embodiment shown in FIG16A, and will not be repeated here.

[0202] Figure 18A is another schematic diagram of the connection between the pixel circuit and the light-emitting element according to at least one embodiment of the present disclosure. Figure 18B is a schematic diagram of the light-emitting element and the conductive connection layer in Figure 18A. This example illustrates a conductive connection layer as an example. Figures 18A and 18B illustrate four rows of pixel circuits (e.g., rows i to i+3) and four rows of light-emitting elements (e.g., rows i to i+3). In this example, one row of pixel circuits is a pixel circuit group, and one row of light-emitting elements is a light-emitting element group. The first direction is the row direction X, and the second direction is the column direction Y.

[0203] In some examples, as shown in Figures 18A and 18B, the first-type pixel circuits 41 connected to multiple third light-emitting elements 313a and 313b within a row of light-emitting elements can be located in different rows from the first-type pixel circuits 41 connected to multiple first light-emitting elements 311 and multiple second light-emitting elements 312. For example, the first-type pixel circuits 41 connected to multiple third light-emitting elements 313a and 313b within the (i+1)th row of light-emitting elements can be located in the (i+2)th row of pixel circuits, and the first-type pixel circuits 41 connected to multiple first light-emitting elements 311 and multiple second light-emitting elements 312 can be located in the (i+1)th row of pixel circuits. For example, the first light-emitting element 311 can be connected to the first conductive connection line 511 via the first adapter 611 and the first adapter wire 621, and the second light-emitting element 312 can be connected to the second conductive connection line 512 via the first adapter 612 and the first adapter wire 622. The first adapters connected to the first light-emitting elements 311 and 312 within the (i+1)th row of light-emitting elements can be aligned with the pixel circuits in the (i)th row. The third light-emitting element 313a can be connected to the first adapter 613a, and the third light-emitting element 313b can be directly connected to the first adapter 613b. The first adapter connected to the third light-emitting element in the (i+1)th row of light-emitting elements is not aligned with the first adapter connected to the first light-emitting element and the second light-emitting element. For example, the first adapter connected to the third light-emitting element in the (i+1)th row of light-emitting elements is aligned with the pixel circuit in the (i+1)th row.

[0204] In some examples, the second type of pixel circuits connected to multiple second-region light-emitting elements within a row of light-emitting elements can be located in the same row. For example, multiple second-region light-emitting elements within the (i+1)th row of light-emitting elements are driven by multiple second-type pixel circuits within the (i+1)th row of pixel circuits. The orthographic projections of the multiple second-region light-emitting elements within the (i+1)th row of light-emitting elements onto the substrate at least partially overlap with the orthographic projections of the (i+1)th row of pixel circuits onto the substrate.

[0205] In this example, the first and second light-emitting elements can be driven by a first-type pixel circuit in the same row, and the third light-emitting element can be driven by a first-type pixel circuit arranged across rows. This avoids the reduction in light transmittance caused by arranging more first adapters in the anode layer in the first display area. Further descriptions of the display substrate in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0206] The display substrate provided in this embodiment can use one row of pixel circuits to drive another row of light-emitting elements to achieve staggered driving. Alternatively, a first adapter and a first adapter line can be set in the first display area to realize cross-row driving of the light-emitting elements in the first area by the first type of pixel circuit. This can reduce the parasitic capacitance of the conductive connection lines, thereby facilitating the uniform arrangement of the conductive connection lines.

[0207] In some examples, the connection between the gate traces and the pixel circuits can be adjusted to accommodate the connection relationship between the pixel circuits and the light-emitting elements. For example, starting with the first row of pixel circuits including the first type of pixel circuits, the gate traces and multiple rows of pixel circuits can be connected across rows; or, starting with the last row of pixel circuits including the first type of pixel circuits, the gate traces and multiple rows of pixel circuits can be connected across rows; or, starting with the first row of pixel circuits in the display area, the gate traces and multiple rows of pixel circuits can be connected across rows; or, using the central axis of the first display area as the dividing line, different cross-row connection methods can be used for the multiple rows of pixel circuits on both sides of the central axis.

[0208] On the other hand, this embodiment provides a display substrate, including: a substrate, a plurality of light-emitting element groups, and a plurality of pixel circuit groups. The substrate includes a first display area and a second display area located at least one side of the first display area. At least one of the plurality of light-emitting element groups includes: a plurality of first-region light-emitting elements and a plurality of second-region light-emitting elements arranged along a first direction, wherein the plurality of first-region light-emitting elements are located in the first display area, and the plurality of second-region light-emitting elements are located in the second display area; at least one of the plurality of pixel circuit groups includes: a plurality of first-type pixel circuits and a plurality of second-type pixel circuits arranged at intervals along the first direction and located in the second display area; the plurality of light-emitting element groups are arranged along a second direction, and the plurality of pixel circuit groups are arranged along the second direction, wherein the second direction intersects the first direction. At least one first-type pixel circuit in the i-th pixel circuit group is connected to at least one first-area light-emitting element in the j-th light-emitting element group via a conductive connection line. At least one second-type pixel circuit in the i-th pixel circuit group is connected to at least one second-area light-emitting element in the j-th light-emitting element group, where i and j are both integers greater than 0. The orthographic projections of the plurality of second-area light-emitting elements in the j-th light-emitting element group onto the substrate at least partially overlap with the orthographic projections of the i-th pixel circuit group onto the substrate. At least one first-area light-emitting element in the j-th light-emitting element group is connected to the conductive connection line via a first adapter, which is offset from the i-th pixel circuit group in the first direction. For the first-area light-emitting elements in the j-th light-emitting element group that emit light of the same color, the first-type pixel circuit in the i-th pixel circuit group connected to the first-area light-emitting element closer to the second display area is on the side of the i-th pixel circuit group connected to the first-area light-emitting element farther from the first display area.

[0209] The display substrate provided in this embodiment can be configured with a first adapter in the first display area to enable the first type of pixel circuit to drive the light-emitting element in the first area across rows, which can reduce the parasitic capacitance of the conductive connection lines and thus help to achieve a uniform arrangement of the conductive connection lines.

[0210] In some exemplary embodiments, the first adapter is aligned with the (i-1)th pixel circuit group or the (i+1)th pixel circuit group in the first direction.

[0211] In some exemplary embodiments, the plurality of first-area light-emitting elements include: a plurality of first light-emitting elements emitting a first color light, a plurality of second light-emitting elements emitting a second color light, and a plurality of third light-emitting elements emitting a third color light. The plurality of first-type pixel circuits in the second display area include: a plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of third pixel circuits; at least one of the plurality of first pixel circuits is connected to at least one of the plurality of first light-emitting elements via a first conductive connection line; at least one of the plurality of second pixel circuits is connected to at least one of the plurality of second light-emitting elements via a second conductive connection line; at least one of the plurality of third pixel circuits is connected to at least one of the plurality of third light-emitting elements via a third conductive connection line; the plurality of third pixel circuits are located on the side of the plurality of first pixel circuits and the plurality of second pixel circuits closest to the first display area.

[0212] In some exemplary embodiments, the at least one third pixel circuit is connected to two adjacent third light-emitting elements via a third conductive connection line.

[0213] In some exemplary embodiments, at least one first pixel circuit in the i-th pixel circuit group is connected to at least one first light-emitting element in the j-th light-emitting element group; at least one second pixel circuit in the i-th pixel circuit group is connected to at least one second light-emitting element in the j-th light-emitting element group; and at least one third light-emitting element in the j-th light-emitting element group is connected to at least one first pixel circuit in the (i-1)-th pixel circuit group or the (i+1)-th pixel circuit group.

[0214] In some exemplary embodiments, the first color light is red light, the second color light is blue light, and the third color light is green light.

[0215] The relevant description of this example can be found in the foregoing embodiments, and therefore will not be repeated here.

[0216] Figure 19 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in Figure 19, this embodiment provides a display device including: a display substrate 91 and a sensor 92 located on the light-emitting side of a light-emitting structure layer away from the display substrate 91. The sensor 92 may be located on the non-display surface side of the display substrate 91. The orthographic projection of the sensor 92 on the display substrate 91 may at least partially overlap with a first display area A1. For example, the orthographic projection of the sensor 92 on the display substrate 91 may be located within the range of the first display area A1. In some examples, the sensor 92 may be a camera.

[0217] In some examples, the display substrate 91 can be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device can be a product with image (including still images or moving images, where the moving images can be video) display capabilities. For example, the display device can be any of the following: monitor, television set, billboard, digital photo frame, laser printer with display function, telephone, mobile phone, drawing screen, personal digital assistant (PDA), digital camera, portable camcorder, viewfinder, navigator, vehicle, large-area wall, information query equipment (such as business query equipment for e-government, banks, hospitals, power companies, etc.), monitor, etc. Furthermore, the display device can also be any of the following: microdisplay, VR device or AR device containing a microdisplay, etc.

[0218] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "some examples," etc., indicate that a feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the described features, structures, materials, or characteristics may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0219] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A display substrate, comprising: The substrate includes a first display area and a second display area located at least one side of the first display area; The system comprises multiple groups of light-emitting elements and multiple groups of pixel circuits. At least one of the multiple groups of light-emitting elements includes: multiple first-region light-emitting elements and multiple second-region light-emitting elements arranged along a first direction, wherein the multiple first-region light-emitting elements are located in a first display area and the multiple second-region light-emitting elements are located in a second display area. At least one of the multiple groups of pixel circuits includes: multiple first-type pixel circuits and multiple second-type pixel circuits arranged at intervals along the first direction and located in the second display area. The multiple groups of light-emitting elements are arranged along a second direction, and the multiple groups of pixel circuits are arranged along the second direction, wherein the second direction intersects the first direction. At least one first-type pixel circuit in the i-th pixel circuit group is connected to at least one first-region light-emitting element in the j-th light-emitting element group, and at least one second-type pixel circuit in the i-th pixel circuit group is connected to at least one second-region light-emitting element in the j-th light-emitting element group, where i and j are both integers greater than 0; the j-th light-emitting element group is located on one side of the i-th pixel circuit group along the second direction. For the multiple first-area light-emitting elements that emit the same color light in the j-th light-emitting element group, the first type pixel circuit in the i-th pixel circuit group connected to the first-area light-emitting element close to the second display area, and the first type pixel circuit in the i-th pixel circuit group connected to the first-area light-emitting element far away from the second display area, are located on the side far away from the first display area.

2. The display substrate according to claim 1, wherein, The first direction is the row direction, and the second direction is the column direction; or, the first direction is the column direction, and the second direction is the row direction.

3. The display substrate according to claim 1, wherein, The orthographic projection of the plurality of second-region light-emitting elements in the j-th light-emitting element group onto the substrate at least partially overlaps with the orthographic projection of the (i-1)-th pixel circuit group or the (i+1)-th pixel circuit group onto the substrate.

4. The display substrate according to claim 1, wherein, At least one first-type pixel circuit in the i-th pixel circuit group is connected to at least one first-region light-emitting element in the j-th light-emitting element group via a conductive connection line. The conductive connection line includes: a main body segment extending along the first direction, a first connection segment and a second connection segment extending at least along the second direction, the main body segment being connected between the first connection segment and the second connection segment, the first connection segment being connected to the first type of pixel circuit, and the second connection segment being connected to the first region light-emitting element; The first and second connecting segments of the conductive connecting wire are located on both sides of the main body segment along the second direction.

5. The display substrate according to claim 1, wherein, The first display area includes multiple first light-emitting elements that emit first color light, multiple second light-emitting elements that emit second color light, and multiple third light-emitting elements that emit third color light; The plurality of first-type pixel circuits in the second display area include: a plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of third pixel circuits; At least one of the plurality of first pixel circuits is connected to at least one of the plurality of first light-emitting elements through a first conductive connection line; at least one of the plurality of second pixel circuits is connected to at least one of the plurality of second light-emitting elements through a second conductive connection line; and at least one of the plurality of third pixel circuits is connected to at least one of the plurality of third light-emitting elements through a third conductive connection line. The plurality of third pixel circuits are located near the plurality of first pixel circuits and the plurality of second pixel circuits. One side of a display area.

6. The display substrate according to claim 5, wherein, The at least one third pixel circuit is connected to two adjacent third light-emitting elements via a third conductive connection line; the third conductive connection line is located on the side of the first conductive connection line and the second conductive connection line closer to the substrate.

7. The display substrate according to claim 5, wherein, At least one third pixel circuit in the i-th pixel circuit group is connected to at least one third light-emitting element in the j-th light-emitting element group; At least one first light-emitting element in the j-th light-emitting element group is connected to at least one first pixel circuit in the (i-1)-th pixel circuit group, and at least one second light-emitting element in the j-th light-emitting element group is connected to at least one second pixel circuit in the (i-1)-th pixel circuit group. Alternatively, at least one first light-emitting element in the j-th light-emitting element group is connected to at least one first pixel circuit in the (i+1)-th pixel circuit group, and at least one second light-emitting element in the j-th light-emitting element group is connected to at least one second pixel circuit in the (i+1)-th pixel circuit group.

8. The display substrate according to any one of claims 5 to 7, wherein, The first color light is red light, the second color light is blue light, and the third color light is green light.

9. The display substrate according to claim 1, wherein, The i-th pixel circuit group includes: a first sub-pixel circuit group and a second sub-pixel circuit group located on both sides of the first display area along the first direction; The light-emitting element group connected to the first sub-pixel circuit group and the light-emitting element group connected to the second sub-pixel circuit group are offset in the first direction.

10. The display substrate according to claim 9, wherein, The orthographic projection of the first sub-pixel circuit group onto the substrate at least partially overlaps with the orthographic projection of the plurality of second region light-emitting elements in the j-th light-emitting element group onto the substrate; The orthographic projection of the second sub-pixel circuit group onto the substrate at least partially overlaps with the orthographic projection of the plurality of second region light-emitting elements in the (j-1)th or (j+1)th light-emitting element group onto the substrate.

11. The display substrate according to claim 9, wherein, The gate traces connected to the first sub-pixel circuit group of the i-th pixel circuit group are disconnected from the gate traces connected to the second sub-pixel circuit group.

12. A display device comprising a display substrate as claimed in any one of claims 1 to 11, and a sensor located on a non-display side of the display substrate, wherein the orthographic projection of the sensor onto the display substrate at least partially overlaps with a first display area of ​​the display substrate.

13. The display device according to claim 12, wherein, The sensor is a camera.

14. A display substrate, comprising: The substrate includes a first display area and a second display area located at least one side of the first display area; The system comprises multiple groups of light-emitting elements and multiple groups of pixel circuits. At least one of the multiple groups of light-emitting elements includes: multiple first-region light-emitting elements and multiple second-region light-emitting elements arranged along a first direction, wherein the multiple first-region light-emitting elements are located in a first display area and the multiple second-region light-emitting elements are located in a second display area. At least one of the multiple groups of pixel circuits includes: multiple first-type pixel circuits and multiple second-type pixel circuits arranged at intervals along the first direction and located in the second display area. The multiple groups of light-emitting elements are arranged along a second direction, and the multiple groups of pixel circuits are arranged along the second direction, wherein the second direction intersects the first direction. At least one first-type pixel circuit in the i-th pixel circuit group is connected to at least one first-region light-emitting element in the j-th light-emitting element group via a conductive connection line; at least one second-type pixel circuit in the i-th pixel circuit group is connected to at least one second-region light-emitting element in the j-th light-emitting element group; i and j are both integers greater than 0; the orthographic projection of the plurality of second-region light-emitting elements in the j-th light-emitting element group onto the substrate at least partially overlaps with the orthographic projection of the i-th pixel circuit group onto the substrate; At least one first region light-emitting element in the j-th light-emitting element group is connected to the conductive connection line through a first adapter, and the first adapter is offset from the i-th pixel circuit group in the first direction; For the first region light-emitting element that emits light of the same color in the j-th light-emitting element group, the first type pixel circuit in the i-th pixel circuit group connected to the first region light-emitting element close to the second display area, and the side of the first type pixel circuit in the i-th pixel circuit group connected to the first region light-emitting element far away from the second display area that is far away from the first display area.

15. The display substrate according to claim 14, wherein, The first adapter is aligned with the (i-1)th pixel circuit group or the (i+1)th pixel circuit group in the first direction.

16. The display substrate according to claim 14, wherein, The plurality of first-region light-emitting elements include: a plurality of first light-emitting elements emitting first-color light, a plurality of second light-emitting elements emitting second-color light, and a plurality of third light-emitting elements emitting third-color light; The plurality of first-type pixel circuits in the second display area include: a plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of third pixel circuits; At least one of the plurality of first pixel circuits is connected to at least one of the plurality of first light-emitting elements through a first conductive connection line; at least one of the plurality of second pixel circuits is connected to at least one of the plurality of second light-emitting elements through a second conductive connection line; and at least one of the plurality of third pixel circuits is connected to at least one of the plurality of third light-emitting elements through a third conductive connection line. The plurality of third pixel circuits are located on the side of the plurality of first pixel circuits and the plurality of second pixel circuits that are close to the first display area.

17. The display substrate according to claim 16, wherein, The at least one third pixel circuit is connected to two adjacent third light-emitting elements via a third conductive connection line.

18. The display substrate according to claim 16, wherein, At least one first pixel circuit in the i-th pixel circuit group is connected to at least one first light-emitting element in the j-th light-emitting element group; At least one second pixel circuit in the i-th pixel circuit group is connected to at least one second light-emitting element in the j-th light-emitting element group; At least one third light-emitting element in the j-th light-emitting element group is connected to at least one first pixel circuit in the (i-1)-th pixel circuit group or the (i+1)-th pixel circuit group.

19. The display substrate according to any one of claims 16 to 18, wherein, The first color light is red light, the second color light is blue light, and the third color light is green light.

Images