Controller, system and method for controlling output driver

Abstract

The invention provides a controller, a system and a method for controlling an output driver. For i = 1,..., M, where M is a positive integer, the controller is configured to form a first non-infinite impedance between an output node (i) of the output driver (i) and a first voltage source (e.g., VDD) during a first time period, where the output node (i) is at a first logic value that is a digitized value of a second voltage source (e.g., ground). For example, the controller may maintain the number 0 on the output node (i) without causing the analog voltage on the output (i) to be pulled down to the analog ground, and / or may maintain the number 1 on the output node (i) without causing the analog voltage on the output (i) to be pulled up to the positive supply voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to a controller, system, and method for controlling an output driver. BACKGROUND

[0002] IO (input / output) drivers and transmitters can be used for high speed data communications. IO drivers can incorporate equalization techniques such as pre-emphasis and de-emphasis. These techniques can help mitigate signal degradation and improve signal integrity at the receiver end.

[0003] De-emphasis is a technique to boost high frequencies of a signal while attenuating low frequency content to compensate for signal loss caused by the transmission channel. For example, in a voltage mode driver, a de-emphasis circuit can use a voltage divider network at the output stage of the driver to control the voltage swing for high frequency components and low frequency components. The voltage divider network can have resistors and transistors that can be turned on or off by a control signal. The level of de-emphasis can be adjusted by changing the number of switching elements of the resistors and capacitors.

[0004] For example, when the IO driver transmits a sequential order of binary "01" or "10" that is considered a high frequency data pattern, the driver de-emphasis circuit adjusts for a small driver impedance to generate a high swing output. When the IO driver transmits a continuous binary "11" or "00" that is considered a low frequency data pattern, the driver de-emphasis circuit adjusts for a low swing output by using a higher driver impedance. In short, conventional implementations of IO driver de-emphasis use a high driver impedance for low frequency data patterns and a low driver impedance for high frequency data patterns. Static de-emphasis circuits at the receiver end of the transmission channel and / or the transmitter end of the transmission channel have been implemented. Here, the word "static" in the context of a de-emphasis circuit means that the de-emphasis circuit does not change based on the signal being transmitted through the transmission channel. SUMMARY

[0005] A controller is disclosed herein. For i = 1,..., M, where M is a positive integer, the controller is configured to form a first non-infinite impedance between an output node (i) of an output driver i and a same first voltage source in a first time period, wherein the output node i is at a first logic value during the first time period, the first logic value being a digitized value of a same second voltage source.

[0006] In an aspect, the controller is configured to form a second non-infinite impedance between the output node (i) and the second voltage source in a second time period, wherein the output node i is at a second logic value during the second time period, the second logic value being a digitized value of the first voltage source.

[0007] In an aspect, the first voltage source is an operating voltage for input / output, and the second voltage source is ground.

[0008] In an aspect, M > 1.

[0009] In an aspect, the first time period includes: (A) a high frequency time period for data on the output node (i), and (B) a low frequency time period for data on the output node (i) immediately after the high frequency time period, and the controller is configured to form the first non-infinite impedance in the low frequency time period.

[0010] In an aspect, the controller is configured to form an infinite impedance between the output node (i) and the first voltage source throughout the high frequency time period.

[0011] In an aspect, the controller is configured to form a sixth non-infinite impedance between the output node (i) and the first voltage source in the high frequency time period.

[0012] In an aspect, the first time period includes: (A) a high frequency time period for data on the output node (i), and (B) a low frequency time period for data on the output node (i) immediately after the high frequency time period. The controller is configured to: (A) form a third impedance between the output node (i) and the second voltage source in the high frequency time period, and (B) form a fourth impedance between the output node (i) and the second voltage source in the low frequency time period. The third impedance is lower than the fourth impedance.

[0013] In an aspect, the controller is configured to form the fourth impedance throughout the low frequency time period.

[0014] In an aspect, the low frequency time period includes (A) a fifth time period, and (B) a sixth time period immediately after the fifth time period. The controller is configured to: (A) form the fourth impedance in the fifth time period, and (B) form a fifth impedance between the output node (i) and the second voltage source in the sixth time period. The fourth impedance is lower than the fifth impedance.

[0015] In an aspect, the first time period includes: (A) a high frequency time period for data on the output node (i), and (B) a low frequency time period for data on the output node (i) immediately after the high frequency time period, and the controller is configured to form a third impedance between the output node (i) and the second voltage source in both the high frequency time period and the low frequency time period.

[0016] In an aspect, for each value of i, the output driver (i) comprises: (A) Ki PMOS transistors electrically coupled to and between the output node (i) and the first voltage source; and (B) Ki NMOS transistors electrically coupled to and between the output node (i) and the second voltage source. The controller is configured to control ON / OFF states of the Ki PMOS transistors, thereby controlling an impedance between the output node (i) and the first voltage source. The controller is configured to control ON / OFF states of the Ki NMOS transistors, thereby controlling an impedance between the output node (i) and the second voltage source. Ki (i = 1,..., M) is an integer greater than 1.

[0017] In an aspect, Ki (i = 1,..., M) is the same.

[0018] In an aspect, for each value of i, and for j = 1,..., Ki, the controller comprises a sub-controller (i, j) configured to generate 2 control signals that respectively control (A) an ON / OFF state of a PMOS transistor (i, j) of the Ki PMOS transistors of the output driver (i), and (B) an ON / OFF state of an NMOS transistor (i, j) of the Ki NMOS transistors of the output driver (i).

[0019] In an aspect, the first time period comprises: (A) a high frequency time period for data on the output node (i), and (B) a low frequency time period for data on the output node (i) immediately after the high frequency time period, and the controller is configured to generate the control signal (i) indicating the high frequency time period or the low frequency time period for data on the output node (i).

[0020] Disclosed herein is a system comprising any of the above controllers. The system is a solid state drive (SSD), a flash drive, a motherboard, a processor, a computer, a server, a gaming device, or a mobile device.

[0021] Disclosed herein is a method of using any of the above controllers. The method comprises, for i = 1,..., M, using the controller to form a first non-infinite impedance between an output node (i) of an output driver (i) and a first voltage source in a first time period, wherein the output node (i) is at a first logic value during the first time period, the first logic value being a digitized value of the second voltage source.

[0022] In an aspect, the method further comprises forming, with the controller, a second non-infinite impedance between the output node (i) and a second voltage source during a second time period, wherein the output node (i) is at the second logic value during the second time period, the second logic value being a digitized value of the first voltage source.

[0023] In an aspect, the first time period comprises (A) a high frequency time period for data on the output node (i), and (B) a low frequency time period for data on the output node (i) immediately following the high frequency time period, and the controller forms the first non-infinite impedance during the low frequency time period.

[0024] In an aspect, the controller forms an infinite impedance between the output node (i) and the first voltage source during the entire high frequency time period.

[0025] In an aspect, the controller forms a sixth non-infinite impedance between the output node (i) and the first voltage source during the high frequency time period.

[0026] In an aspect, the first time period comprises (A) a high frequency time period for data on the output node (i), and (B) a low frequency time period for data on the output node (i) immediately following the high frequency time period. The method further comprises (A) forming, with the controller, a third impedance between the output node (i) and a second voltage source during the high frequency time period, and (B) forming, with the controller, a fourth impedance between the output node (i) and the second voltage source during the low frequency time period. The third impedance is lower than the fourth impedance.

[0027] The controllers and methods disclosed herein can allow for dynamic de-emphasis, particularly at the transmitter end of a transmission channel. Here, the word "dynamic" in the context of a de-emphasis circuit means that the de-emphasis circuit can change the de-emphasis based on the signal being transmitted through the transmission channel. For example, the controllers and methods disclosed herein can change the strength of the de-emphasis or turn the de-emphasis on or off based on the signal being transmitted. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 An output driver system including a controller and a plurality of output drivers according to an embodiment is schematically illustrated.

[0029] Figure 2 A micro driver of an output driver system according to an embodiment is schematically illustrated.

[0030] Figure 3 A sub-controller of a controller according to an embodiment is schematically illustrated.

[0031] Figures 4A to 4D A signal diagram for generating a control signal for a micro driver according to an embodiment is illustrated.

[0032] Figure 5 A flowchart showing the operation of the summary output driver system according to an embodiment is shown. DETAILED DESCRIPTION

[0033] Output driver system 100

[0034] Figure 1 An output driver system 100 according to an embodiment is schematically shown. The output driver system 100 can include a controller 110 and M output drivers 120.1, 120.2,..., where M is a positive integer (e.g., M = 8, as shown). Figure 1 The M output drivers can each be individually referred to as an “output driver 120”. The M output drivers can also be collectively referred to as “output drivers 120”.

[0035] In an embodiment, the output driver system 100 can be part of a solid state drive (SSD), a flash drive, a motherboard, a processor, a computer, a server, a gaming device, or a mobile device (not shown).

[0036] Controller 110

[0037] In an embodiment, referring to Figure 1 , the controller 110 can receive, as inputs, (A) data signals (e.g., Data_in.1, Data_in.2,..., and Data_in.8, or simply Data_in.1 to Data_in.8) and (B) control signals (e.g., Driver_Control, DE_Control, and Special_Control), as shown. Figure 1 The controller 110 can generate, as outputs, a plurality of control signals (e.g., 96 control signals, namely Data_P.11, Data_N.11,..., Data_P.86, and Data_N.86) for controlling the operation of the 8 output drivers 120.1 to 120.8, as shown in Figure 1

[0038] Output driver 120

[0039] In an embodiment, referring to Figure 1 , each output driver 120 of the output driver system 100 can include K micro-drivers (e.g., K = 6, as shown in Figure 1 For example, the output driver 120.1 can include 6 micro-drivers 122.11 to 122.16. Each of the K micro-drivers can be individually referred to as a “micro-driver 122”. The K micro-drivers can also be collectively referred to as “micro-drivers 122”.​

[0040] The number of micro-drivers 122 of an output driver 120 is not necessarily the same. For example, output driver 120.1 can have 6 micro-drivers 122, while output driver 120.8 can have 10 micro-drivers 122.

[0041] Micro-drivers 122

[0042] In an embodiment, with reference to Figure 1 Each micro-driver 122 of output driver system 100 can receive 2 control signals Data_P and Data_N as inputs from controller 110. For example, micro-driver 122.11 can receive 2 control signals Data_P.11 and Data_N.11 as inputs from controller 110.

[0043] In an embodiment, all micro-drivers 122 of each output driver 120 can be electrically connected to the same output node of the output driver 120. For example, all 6 micro-drivers 122.11 to 122.16 of output driver 120.1 can be electrically connected to the same output node 125.1 that carries data output signal Data_out.1. The function of output driver system 100 includes setting Data_out.i to the digital value of Data_in.i, where i = 1,..., 8.

[0044] In an embodiment, with reference to Figure 1 and Figure 2 Each of the 48 micro-drivers 122 of output driver system 100 can include (A) a level shifter, (B) a pre-driver, and (C) a main driver. For example, with reference to Figure 2 Micro-driver 122.11 of output driver 120.1 can include (A) level shifter 210.11, (B) pre-driver 220.11, and (C) main driver 230.11.

[0045] Level shifter 210 and pre-driver 220

[0046] In an embodiment, with reference to Figure 1 and Figure 2 The operation of micro-driver 122.11 can be as follows. The 2 control signals Data_P.11 and Data_N.11 from controller 110 can first enter level shifter 210.11 to transform its voltage level from the core voltage domain to the input / output voltage domain (VDD_IO).

[0047] In this embodiment, the two control signals can be further passed through a pre-driver 220.11, which may include a set of logic gates (not shown) to further fine-tune the strength and slew rate of the micro-driver 122.11. The two output signals P_Drive.11 and N_Drive.11 of the pre-driver 220.11 can be electrically connected to the main driver 230.11 for operational control.

[0048] Main drive 230

[0049] In the embodiment, reference Figure 1 and Figure 2 The main driver 230.11 may include a PMOS (p-channel metal-oxide-semiconductor) transistor 232p.11, which is connected to a resistor 234p.11 (such as...). Figure 2 The PMOS transistor 232p.11 is electrically coupled between (A) the input / output operating voltage VDD_IO and (B) the output node 125.1 of the output driver 120.1. Another suitable device can be used to replace the PMOS transistor 232p.11.

[0050] In an embodiment, the main driver 230.11 may further include an NMOS (n-channel metal-oxide-semiconductor) transistor 232n.11, which is connected to a resistor 234n.11 (such as...). Figure 2 (As shown) Electrical coupling is present between (A) ground and (B) output node 125.1 of output driver 120.1. Another suitable device can be used to replace NMOS transistor 232n.11.

[0051] In the embodiment, the two output signals P_Drive.11 and N_Drive.11 of the pre-driver 220.11 can turn on and off the PMOS transistor 232p.11 and the NMOS transistor 232n.11, respectively.

[0052] In an embodiment, the remaining 47 microdrivers 122.12 to 122.86 of the output driver system 100 may be structurally and functionally similar to microdriver 122.11.

[0053] For the output driver 120.i (i=1, ..., 8), six PMOS transistors 232p.i1 to 232p.i6 are electrically coupled in parallel between VDD_IO and output node 125.i, and six NMOS transistors 232n.i1 to 232n.i6 are electrically coupled in parallel between ground and output node 125.i.

[0054] Data_P and Data_N are used to control the micro driver 122.

[0055] In an embodiment, referring to Figures 1 to 3 , the control signals Data_P.11 and Data_N.11 for controlling the micro-driver 122.11 can be generated by a sub-controller 110.11 of the controller 110 as follows. Figure 3

[0056] The control signals Special_Control.111 and DE_Control.111 can first enter two multiplexers MUX_1.111 and MUX_2.111 of the sub-controller 110.11, where the multiplexer selection signal is Data_in.1.

[0057] When Data_in.1 is a logic “1” (or simply, Data_in.1 = 1), the Data_P.11 path can select DE_Control.111 and the Data_N.11 path can select Special_Control.111.

[0058] When Data_in.1 is a logic “0” (or simply, Data_in.1 = 0), the Data_P.11 path can select Special_Control.111 and the Data_N.11 path can select DE_Control.111.

[0059] Two additional multiplexers MUX_3.111 and MUX_4.111 of the sub-controller 110.11 can enable various pullback levels when transmitting low frequency data of Data_in.1 (i.e., consecutive zeros and consecutive ones). The two output signals of the multiplexers MUX_3.111 and MUX_4.111 can be Data_P.11 and Data_N.11, respectively.

[0060] The dynamic control signal DE.1 can be used as the multiplexer selection signal for the multiplexers MUX_3.111 and MUX_4.111.

[0061] When Data_in.1 is (A) consecutive or adjacent zeros (e.g., 00 in two adjacent clock periods) or (B) consecutive or adjacent 1s (e.g., 11 in two adjacent clock periods), DE.1 can be set to 1, thereby selecting the data signal from the outputs of the multiplexers MUX_1.111 and MUX_2.111.

[0062] When Data_in.1 changes from 0 to 1 or from 1 to 0 between two adjacent clock periods, DE.1 can be set to 0, thereby selecting the alternative path controlled by Driver_Control.111. ​

[0063] In an embodiment, DE.1 can be generated by an XNOR gate (not shown) that receives as inputs the current value of Data_in.1 and the previous value of Data_in.1. Thus, DE.1 is 1 when the previous and current values of Data_in.1 are 00 or 11 (low frequency change); and DE.1 is 0 when the previous and current values of Data_in.1 are 01 or 10 (high frequency change).

[0064] In an embodiment, controller 110 can include 47 other sub-controllers (not shown) for controlling the 47 micro-drivers 122.12 to 122.86, respectively. The 47 other sub-controllers can be similar in structure and function to sub-controller 110.11.

[0065] In short, controller 110 can individually control the ON / OFF states of the 48 PMOS transistors 232p and the 48 NMOS transistors 232n of output driver system 100, respectively.

[0066] A high frequency time period for a data signal (e.g., Data_in.1, Data_out.1, Data_in.8, Data_out.8, etc.) consists of a clock period in which the data signal changes from 0 to 1 or from 1 to 0 (in digital or logic values). For example, referring to Figure 4A Clock period C01 is a high frequency time period for Data_in.1 (and also for Data_out.1 because Data_out.1 = Data_in.1). Clock period C04 is another high frequency time period for Data_in.1. Clock period C07 is yet another high frequency time period for Data_in.1. Clock period C08 is yet another high frequency time period for Data_in.1.

[0067] A low frequency time period for a data signal (e.g., Data_in.1, Data_out.1, Data_in.8, Data_out.8, etc.) consists of one or more consecutive clock periods in which each clock period is not a high frequency time period. For example, referring to Figure 4A Clock periods C02 to C03 are low frequency time periods for Data_in.1 (and also for Data_out.1 because Data_out.1 = Data_in.1). Clock periods C05 to C06 are another low frequency time period for Data_in.1. Clock period C09 is yet another low frequency time period for Data_in.1.

[0068] Operation of output driver system 100

[0069] In an embodiment, with reference to Figures 1 to 4A , output driver 120.1 of output driver system 100 can operate as follows.

[0070] Data_in.1 changes from 1 to 0

[0071] Assume that for clock period COl, Data_in.1 changes from 1 to 0 (as shown in Figure 4A ). In response, in an embodiment, controller 110 can cause N0 of K=6 NMOS transistors 232n.11 through 232n.16 of output driver 120.1 to be ON (turned on) (i.e., the remaining (K-N0) of the K=6 NMOS transistors to be OFF (turned off)). In other words, for clock period COl, NMOS ON = N0 (as shown in Figure 4A ). In an embodiment, N0 can be a positive integer no more than K=6 (e.g., N0=5).

[0072] Additionally, in an embodiment, controller 110 can also cause all K=6 PMOS transistors 232p.11 through 232p.16 of output driver 120.1 to be OFF. In other words, the number of PMOS transistors 232p of output driver 120.1 that are ON is 0 (i.e., for clock period COl, PMOS ON = 0 or "OFF") as shown in Figure 4A .

[0073] The fact that for the high frequency time period COl, the 6 NMOS transistors 232n.11 through 232n.16 of output driver 120.1 are not all OFF (specifically, N0 of them are ON) results in a "non-infinite impedance" between output node 125.1 and ground, resulting in a primary force to pull down output node 125.1 of output driver 120.1 to ground, while the fact that the 6 PMOS transistors 232p.11 through 232p.16 of output driver 120.1 are all OFF results in an "infinite impedance" between output node 125.1 and VDD IO, resulting in no pullback force to pull up output node 125.1 of output driver 120.1 to VDD IO.

[0074] As a result, the primary force, without any pullback force, pulls down output node 125.1 of output driver 120.1 to ground, resulting in Data_out.1 = Data_in.1 = 0 for clock period COl.

[0075] The primary force is the force that pulls the output node 125.1 toward a voltage potential (VDD_IO or ground) so that Data_out.1 = Data_in.1. Conversely, the pull-back force is the force that pulls the output node 125.1 in the opposite direction of the primary force.

[0076] Data_in.1 remains at 0.

[0077] For the next clock cycle C02 to C03, assume Data_in.1 remains at 0 (e.g.) Figure 4A (As shown). In response, in an embodiment, controller 110 can turn N1 of the six NMOS transistors 232n.11 to 232n.16 of output driver 120.1 ON. In other words, for clock cycles C02 to C03, NMOS ON = N1 (as shown). Figure 4A (As shown). In an embodiment, N1 can be a positive integer less than N0 (e.g., N0=5 and N1=3).

[0078] Additionally, in this embodiment, the controller 110 can also turn ON P2 of the six PMOS transistors 232p.11 to 232p.16 of the output driver 120.1. In other words, for clock cycles C02 to C03, PMOS ON = P2 (e.g., ...). Figure 4A (As shown). In an embodiment, P2 can be a positive integer less than N1 (e.g., N1 = 3 and P2 = 2).

[0079] During the low-frequency time period C02 to C03 for Data_in.1 (and also for Data_out.1), not all of the six NMOS transistors 232n.11 to 232n.16 of the output driver 120.1 are OFF (specifically, N1 of them are ON), creating a non-infinite impedance between the output node 125.1 and ground, thus generating a primary force that pulls the output node 125.1 of the output driver 120.1 down to ground. Meanwhile, not all of the six PMOS transistors 232p.11 to 232p.16 of the output driver 120.1 are OFF (specifically, P2 of them are ON), creating a non-infinite impedance between the output node 125.1 and VDD_IO, thus generating a pull-back force that pulls the output node 125.1 of the output driver 120.1 up to VDD_IO.

[0080] As a result, when the impedance between output node 125.1 and ground is less than the impedance between output node 125.1 and VDD_IO (because N1=3>P2=2), the primary force overcomes the pull-back force, thus making Data_out.1=Data_in.1=0 for clock cycles C02 to C03.

[0081] Data_in.1 changes from 0 to 1 and remains at 1

[0082] In embodiments, the operation of output driver 120.1 when Data_in.1 changes from 0 to 1 (e.g., for high frequency time period C04) and then remains at 1 (e.g., for low frequency time periods C05-C06) can be similar to the operation of output driver 120.1 described above when Data_in.1 changes from 1 to 0 (for high frequency time period C01) and then remains at 0 (for low frequency time periods C02-C03).

[0083] In embodiments, the operation of the remaining 7 output drivers 120.2-120.8 of output driver system 100 can be similar to the operation of output driver 120.1 described above.

[0084] Operation Overview

[0085] In summary, with reference to Figures 1 to 4A , controller 110 (A) forms a first non-infinite impedance (resulting from PMOS ON = P2) between output node 125.1 of output driver 120.1 and first voltage source VDD IO during first time period C01-C03, where output node 125.1 is at a first logic value of “0” (i.e., Data_out.1 = 0) during this first time period C01-C03, which first logic value of “0” is a digitized value of second voltage source “ground,” and (B) forms a second non-infinite impedance (resulting from NMOS ON = N2) between output node 125.1 of output driver 120.1 and second voltage source “ground” during second time period C04-C06, where output node 125.1 is at a second logic value of “1” (i.e., Data_out.1 = 1) during this second time period C04-C06, which second logic value of “1” is a digitized value of first voltage source VDD IO.

[0086] Other Embodiments

[0087] Pullback force in both high frequency time period and low frequency time period

[0088] In the above-described embodiments, with reference to Figures 1 to 4A , controller 110 forms an infinite impedance (PMOS ON = OFF) between output node 125.1 and VDD IO for high frequency time period C01 for Data_out.1 Figure 4A ). In alternative embodiments, with reference to Figure 4BIn the high frequency time period C01 for Data_out.1, controller 110 can form a non-infinite impedance PMOS ON = P3 (where P3 is a positive integer less than N0) between output node 125.1 and VDD IO.

[0089] Same primary force in both high frequency time period and low frequency time period

[0090] In the above embodiment, with reference to Figure 4A , controller 110 causes (A) NMOS ON = N0 for high frequency time period C01, and (B) NMOS ON = N1 for low frequency time periods C02 to C03, where N1 < N0. In an alternative embodiment, N1 can be the same as N0 (e.g., N0 = N1 = 5). In other words, controller 110 forms the same impedance (e.g., NMOS ON = N0) between output node 125.1 and ground in both high frequency time period C01 for Data_out.1 and low frequency time periods C02 to C03 for Data_out.1 (as shown in Figure 4C .

[0091] Two different primary forces in low frequency time period

[0092] In the above embodiment, with reference to Figures 4A to 4C , there is no more than one primary force in low frequency time periods C02 to C03 for Data_in.1. In an alternative embodiment, there can be at least 2 different primary forces in low frequency time periods C02 to C03 for Data_in.1. For example, with reference to Figure 4D , there can be 2 different primary forces in low frequency time periods C02 to C03 for Data_in.1 (NMOS = N1 in C02, and NMOS = N3 in C03).

[0093] In an embodiment, N3 can be a positive integer less than N1. Thus, the impedance between output node 125.1 and ground in C02 (resulting from NMOS ON = N1) is lower than the impedance between output node 125.1 and ground in C03 (resulting from NMOS ON = N3).

[0094] Flowchart summarizing operation of output driver system 100

[0095] Figure 5 A flowchart 500 summarizing operation of output driver system 100 according to an embodiment is shown. Figure 1

[0096] ​In step S510, the operations can comprise, for i = 1,..., M, forming, with the controller, a first non-infinite impedance between the output node (i) of the output driver (i) and the first voltage source in a first time period, wherein the output node (i) is at a first logic value which is a digitized value of the second voltage source during said first time period.

[0097] For example, in the above embodiments, with reference to Figures 1 to 4A , the controller 110 forms a first non-infinite impedance (resulting from PMOS ON = P2) between the output node 125.1 of the output driver 120.1 and the first voltage source VDD IO in the first time periods C01 to C03, wherein the output node 125.1 is at a first logic value “0” (i.e., Data out.1 = 0) which is a digitized value of the second voltage source “ground” during the first time periods C01 to C03.

[0098] While various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for purposes of illustration and are not intended to be limiting, with the true scope and spirit being indicated by the appended claims.

Claims

1. A controller, wherein, for i = 1,..., M, the controller is configured to form a first non-infinite impedance between an output node (i) of an output driver (i) and a same first voltage source in a first time period, wherein the output node (i) is at a first logic value during the first time period, the first logic value being a digitized value of a same second voltage source, wherein M is a positive integer.

2. The controller of claim 1, wherein, the controller is configured to form a second non-infinite impedance between the output node (i) and the second voltage source in a second time period, wherein the output node (i) is at a second logic value during the second time period, the second logic value being a digitized value of the first voltage source.

3. The controller of claim 1, wherein the first voltage source is an operating voltage for input / output, and wherein the second voltage source is ground.

4. The controller of claim 1, wherein, M>1。 5. The controller of claim 1, wherein the first time period includes: (A) a high frequency time period for data on the output node (i), and (B) a low frequency time period for data on the output node (i) immediately after the high frequency time period, and wherein the controller is configured to form the first non-infinite impedance in the low frequency time period.

6. The controller of claim 5, wherein, the controller is configured to form an infinite impedance between the output node (i) and the first voltage source throughout the high frequency time period.

7. The controller of claim 5, wherein, the controller is configured to form a sixth non-infinite impedance between the output node (i) and the first voltage source in the high frequency time period.

8. The controller of claim 1, wherein the first time period includes: (A) a high frequency time period for data on the output node (i), and (B) a low frequency time period for data on the output node (i) immediately after the high frequency time period, wherein the controller is configured to: (A) form a third impedance between the output node (i) and the second voltage source in the high frequency time period, and (B) form a fourth impedance between the output node (i) and the second voltage source in the low frequency time period, and wherein the third impedance is lower than the fourth impedance.

9. The controller of claim 8, wherein, the controller is configured to form the fourth impedance throughout the low frequency time period.

10. The controller of claim 8, wherein the low frequency time period includes: (A) a fifth time period, and (B) a sixth time period immediately after the fifth time period, wherein the controller is configured to: (A) form the fourth impedance in the fifth time period, and (B) form a fifth impedance between the output node (i) and the second voltage source in the sixth time period, and wherein the fourth impedance is lower than the fifth impedance.

11. The controller of claim 1, wherein, the first time period includes: (A) a high frequency time period for data on the output node (i), and (B) a low frequency time period for data on the output node (i) immediately after the high frequency time period, and wherein the controller is configured to form a third impedance between the output node (i) and the second voltage source in both the high-frequency time period and the low-frequency time period.

12. The controller of claim 1, wherein for each value of i, the output driver (i) comprises: (A) Ki PMOS transistors electrically coupled to and between the output node (i) and the first voltage source; and (B) Ki NMOS transistors electrically coupled to and between the output node (i) and the second voltage source, wherein the controller is configured to control on / off states of the Ki PMOS transistors to thereby control an impedance between the output node (i) and the first voltage source, wherein the controller is configured to control on / off states of the Ki NMOS transistors to thereby control an impedance between the output node (i) and the second voltage source, and wherein Ki is an integer greater than 1, where i = 1,..., M.

13. The controller of claim 12, wherein, Ki is the same, where i = 1,..., M.

14. The controller of claim 12, wherein, for each value of i, and for j = 1,..., Ki, the controller comprises a sub-controller (i,j) configured to generate 2 control signals that control on / off states of (A) a PMOS transistor (i,j) of the Ki PMOS transistors of the output driver (i) and (B) an NMOS transistor (i,j) of the Ki NMOS transistors of the output driver (i), respectively.

15. The controller of claim 12, wherein the first time period comprises: (A) a high-frequency time period for data on the output node (i), and (B) a low-frequency time period for data on the output node (i) immediately after the high-frequency time period, and wherein the controller is configured to generate a control signal (i) that indicates the high-frequency time period or the low-frequency time period for data on the output node (i).

16. An output driver system comprising the controller of claim 1, wherein, the output driver system is a solid state drive (SSD), a flash drive, a motherboard, a processor, a computer, a server, a gaming device, or a mobile device.

17. A method of using the controller of claim 1, comprising: for i = 1,..., M, the controller forms the first non-infinite impedance between the output node (i) of the output driver (i) and the first voltage source in the first time period, where the output node (i) is at the first logic value during the first time period, the first logic value being a digitized value of the second voltage source.

18. The method of claim 17, further comprising: the controller forms a second non-infinite impedance between the output node (i) and the second voltage source in a second time period, where the output node (i) is at a second logic value during the second time period, the second logic value being a digitized value of the first voltage source.

19. The method of claim 17, wherein The first time period includes: (A) a high-frequency time period for data on the output node (i), and (B) a low-frequency time period for data on the output node (i) immediately after the high-frequency time period, and wherein the controller forms the first non-infinite impedance in the low-frequency time period.

20. The method of claim 19, wherein, The controller forms an infinite impedance between the output node (i) and the first voltage source throughout the high-frequency time period.

21. The method of claim 19, wherein, The controller forms a sixth non-infinite impedance between the output node (i) and the first voltage source in the high-frequency time period.

22. The method of claim 17, wherein The first time period includes: (A) a high-frequency time period for data on the output node (i), and (B) a low-frequency time period for data on the output node (i) immediately after the high-frequency time period, wherein the method further comprises: (A) forming, with the controller, a third impedance between the output node (i) and the second voltage source in the high-frequency time period, and (B) forming, with the controller, a fourth impedance between the output node (i) and the second voltage source in the low-frequency time period, and wherein the third impedance is lower than the fourth impedance.

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