Instruction fetch unit, instruction fetch method, processor and electronic devices of a processor

Abstract

This application provides an instruction fetch unit, an instruction fetch method, a processor, and an electronic device. The instruction fetch unit includes an instruction supply subunit, a buffer subunit, and an arbitration subunit. The instruction supply subunit is configured to read instruction data according to a given memory address and output the instruction data to a first input terminal of the arbitration subunit and an input terminal of the buffer subunit through its output terminal. The buffer subunit is configured to receive and store the instruction data output by the output terminal of the instruction supply subunit and output the instruction data through its output terminal. The arbitration subunit is configured to determine whether the output of the buffer subunit is valid. If the output of the buffer subunit is valid, the instruction data output by the buffer subunit is transmitted to a decoding unit. If the output of the buffer subunit is invalid, the instruction data output by the output terminal of the instruction supply subunit is transmitted to the decoding unit.

Description

Technical Field

[0001] This application relates to the field of processor technology, and in particular to a processor's instruction fetch unit, instruction fetch method, processor, and electronic device. Background Technology

[0002] In modern processor design, the instruction fetch unit is responsible for reading instruction data from the address provided by the program counter or branch predictor and reliably providing it to the subsequent decoding unit. The stability of the instruction fetch unit's operation is crucial to the overall processor performance. To improve the stability of the instruction fetch unit, a common design is to place an instruction buffer queue before the decoding unit. The core function of this buffer queue is to decouple the preceding and following pipeline stages. When the subsequent decoding unit is blocked for some reason (such as resource conflicts, complex instruction decoding, etc.), the preceding instruction fetch unit can continue its instruction fetching operation and temporarily store the fetched instructions in the buffer queue, thereby avoiding interruption of the instruction fetch unit's operation and maintaining its stability. However, this design of introducing an instruction buffer also brings significant performance drawbacks. Before the instruction enters the decoding unit, it needs to be completely written to the buffer queue and then read from the queue in a subsequent cycle before being delivered to the decoding unit. This process increases the time required for instruction data to travel from the instruction fetch unit to the decoding unit, causing additional transmission latency. Summary of the Invention

[0003] In view of this, embodiments of this application provide an instruction fetching unit, an instruction fetching method, a processor, and an electronic device to solve or at least alleviate the above-mentioned problems.

[0004] According to a first aspect of the embodiments of this application, an instruction fetch unit for a processor is provided, comprising: an instruction supply subunit, a buffer subunit, and an arbitration subunit; the output terminal of the instruction supply subunit is connected to a first input terminal of the arbitration subunit and an input terminal of the buffer subunit, the output terminal of the buffer subunit is connected to a second input terminal of the arbitration subunit, and the output terminal of the arbitration subunit is connected to a decoding unit of the processor; wherein, the instruction supply subunit is configured to read instruction data according to a given memory address, and to send the instruction data to the first input terminal of the arbitration subunit through the output terminal of the instruction supply subunit. The instruction data is output from the input terminal of the buffer subunit; the buffer subunit is configured to receive and store the instruction data output from the output terminal of the instruction supply subunit, and output the instruction data through the output terminal of the buffer subunit; the arbitration subunit is configured to determine whether the output terminal of the buffer subunit is valid. If the output terminal of the buffer subunit is valid, the instruction data output from the output terminal of the buffer subunit is transmitted to the decoding unit; if the output terminal of the buffer subunit is invalid, the instruction data output from the output terminal of the instruction supply subunit is transmitted to the decoding unit.

[0005] According to a second aspect of the embodiments of this application, a method for fetching instructions for a processor is provided. The processor includes an instruction supply subunit, a buffer subunit, and an arbitration subunit. The output terminal of the instruction supply subunit is connected to a first input terminal of the arbitration subunit and an input terminal of the buffer subunit, respectively. The output terminal of the buffer subunit is connected to a second input terminal of the arbitration subunit, and the output terminal of the arbitration subunit is connected to a decoding unit of the processor. The method for fetching instructions includes: reading instruction data according to a given memory address through the instruction supply subunit, and sending instruction data to the second input terminal of the arbitration subunit through the output terminal of the instruction supply subunit. The instruction data is output from an input terminal and the input terminal of the buffer subunit; the instruction data output from the output terminal of the instruction supply subunit is received and stored through the buffer subunit, and the instruction data is output through the output terminal of the buffer subunit; the output of the buffer subunit is determined by the arbitration subunit to determine whether the output of the buffer subunit is valid. If the output of the buffer subunit is valid, the instruction data output from the output terminal of the buffer subunit is transmitted to the decoding unit of the processor. If the output of the buffer subunit is invalid, the instruction data output from the output terminal of the instruction supply subunit is transmitted to the decoding unit.

[0006] According to a third aspect of the embodiments of this application, a processor is provided, including the instruction fetch unit described in any of the above embodiments.

[0007] According to a fourth aspect of the embodiments of this application, an electronic device is provided, including the processor described in any of the above embodiments.

[0008] In this embodiment, the instruction supply subunit can read instruction data according to a given storage address and output the instruction data to the arbitration subunit and the buffer subunit through its output terminal. The buffer subunit can receive and store the instruction data output by the output terminal of the instruction supply subunit and output the instruction data through its output terminal. The arbitration subunit is configured to determine whether the output terminal of the buffer subunit is valid, and when the output terminal of the buffer subunit is valid, transmit the instruction data output by the output terminal of the buffer subunit to the decoding unit; when the output terminal of the buffer subunit is invalid, transmit the instruction data output by the output terminal of the instruction supply subunit to the decoding unit. This allows for automatic switching to the output terminal of the instruction supply subunit to retrieve instruction data when the output terminal of the buffer subunit is invalid, without waiting for the instruction data to be written to the buffer subunit, thus saving the time required for instruction data to travel from the instruction fetch unit to the decoding unit and reducing additional transmission latency. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0010] Figure 1 This is a schematic diagram of the instruction fetching unit in some optional embodiments of this application.

[0011] Figure 2 This is a schematic diagram of the instruction fetching unit in some other optional embodiments of this application.

[0012] Figure 3 This is a schematic diagram of the instruction fetching unit in some optional embodiments of this application.

[0013] Figure 4 This is a schematic diagram of the instruction fetching unit in some optional embodiments of this application.

[0014] Figure 5 This is a schematic diagram of the instruction fetching unit in some optional embodiments of this application.

[0015] Figure 6 This is a flowchart of the steps of an instruction fetching method in some optional embodiments of this application.

[0016] Figure 7 This is a schematic diagram of the processor structure in some optional embodiments of this application.

[0017] Figure label:

[0018] 10. Processor; 100. Instruction Fetch Unit; 110. Instruction Feed Subunit; 111. Instruction Cache Subunit; 120. Buffer Subunit; 121. Receive Subunit; 1211. Receive Register; 1212. Enable Subunit; 122. Cache Subunit; 130. Arbitration Subunit; 140. Branch Prediction Subunit; 150. Address Cache Subunit; 200. Decode Unit; 300. Execution Unit. Detailed Implementation

[0019] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the essence of the present application, well-known methods, processes, and flows are not described in detail. Furthermore, the accompanying drawings are not necessarily drawn to scale.

[0020] First, some nouns or terms that appear in the description of the embodiments of this application shall be interpreted as follows.

[0021] Instruction fetch unit: Responsible for fetching the instructions that the processor will execute.

[0022] Decoding unit: Responsible for translating the instruction data obtained from the instruction fetch unit into micro-operations or control signals that the processor's underlying hardware can directly understand and execute.

[0023] Execution unit: Used to receive micro-operation or control signals output from the decoding unit and perform actual arithmetic operations.

[0024] Branch prediction is a technique that proactively predicts the execution path of branch instructions (such as if-else and loops) before the processor determines the instructions to be executed in a program, and obtains the memory address of the data of the instructions on that path based on the predicted execution path.

[0025] A register is a high-speed storage component inside the processor used to temporarily store instructions, data, and addresses. It is usually composed of flip-flops or latches.

[0026] Instruction fetch unit:

[0027] This application provides an instruction fetch unit 100 for a processor. The processor may be a CPU (Central Processing Unit), a SOC (System on Chip), or an Application Specific Integrated Circuit (ASIC). The instruction fetch unit 100 is used to at least partially solve the transmission delay caused by the use of instruction buffers when the processor executes instructions.

[0028] Figure 1 This is a schematic diagram of the instruction fetch unit of a processor according to one embodiment of this application. Figure 1 As shown, the instruction fetch unit 100 of the processor 10 includes: an instruction supply subunit 110, a buffer subunit 120, and an arbitration subunit 130; the output terminal of the instruction supply subunit 110 is connected to the first input terminal of the arbitration subunit 130 and the input terminal of the buffer subunit 120, respectively; the output terminal of the buffer subunit 120 is connected to the second input terminal of the arbitration subunit 130; and the output terminal of the arbitration subunit 130 is connected to the decoding unit 200 of the processor 10.

[0029] The instruction supply subunit 110 is configured to read instruction data according to a given storage address, and output the instruction data to the first input of the arbitration subunit 130 and the input of the buffer subunit 120 through the output of the instruction supply subunit 110.

[0030] The given memory address can be a memory address provided by the processor 10 through branch prediction, or a memory address provided by the processor 10's program counter. The memory space pointed to by the memory address stores instruction data. It should be understood that instruction data refers to data consisting of computer instructions that can be executed by the processor 10, which at least includes the code of the computer instructions. The instruction supply subunit 110 can read the corresponding instruction data according to the memory address. After reading the instruction data, the instruction supply subunit 110 can output the instruction data to the arbitration subunit 130 and the buffer subunit 120 respectively through its output terminal. The instruction supply subunit 110 may include a microcontroller or control circuit, thereby performing the related operations of reading instruction data according to the given memory address and outputting instruction data through the microcontroller or control circuit.

[0031] Buffer subunit 120 is configured to receive and store instruction data output from the output terminal of instruction supply subunit 110, and output instruction data through the output terminal of buffer subunit 120. Buffer subunit 120 may include memory or registers to store instruction data. Buffer subunit 120 may include an instruction buffer queue to store multiple instruction data entries, thus buffering the transmission of instruction data. The instruction buffer queue may consist of memory or multiple registers; this embodiment does not limit the implementation method of the instruction buffer queue. The memory involved in this application may include RAM (Random Access Memory) or other suitable memory, such as SRAM (Static Random-Access Memory), DRAM (Dynamic Random-Access Memory), non-volatile memory, or NAND Flash Memory, etc., which will not be elaborated further below.

[0032] Arbitration subunit 130 is configured to determine whether the output of buffer subunit 120 is valid. If the output of buffer subunit 120 is valid, the instruction data output by buffer subunit 120 is transmitted to decoding subunit 200. If the output of buffer subunit 120 is invalid, the instruction data output by instruction supply subunit 110 is transmitted to decoding subunit 200.

[0033] The second input terminal of the arbitration subunit 130 is connected to the output terminal of the buffer unit, thereby receiving instruction data output from the output terminal of the buffer subunit 120 through the second input terminal. Optionally, the arbitration subunit 130 can determine whether the output terminal of the buffer subunit 120 is valid based on whether the output terminal of the buffer subunit 120 outputs instruction data. That is, when the output terminal of the buffer subunit 120 outputs instruction data, the arbitration subunit 130 can determine that the output terminal of the buffer subunit 120 is valid; when the output terminal of the buffer subunit 120 does not output instruction data, the arbitration subunit 130 can determine that the output terminal of the buffer subunit 120 is invalid. Of course, the arbitration subunit 130 can also determine whether the output terminal of the buffer subunit 120 is valid in other ways. For example, when the buffer subunit 120 outputs instruction data to the arbitration subunit 130, it can simultaneously output an indication signal indicating whether the instruction data is valid. The arbitration subunit 130 can then determine whether the output terminal of the buffer subunit 120 is valid based on the indication signal. Arbitration subunit 130 may include a hardware structure composed of logic circuits, through which the above operations are performed. Arbitration subunit 130 may also include a microcontroller, through which the above judgment operations are performed. The hardware implementation of arbitration subunit 130 can refer to relevant technologies, and will not be described in detail here.

[0034] In scenarios where instructions are cleared due to branch prediction error recovery, it is necessary to clear the buffer subunit 120. At this time, the output of the buffer subunit 120 is empty, that is, the output of the buffer subunit 120 is invalid. The arbitration unit can directly transmit the instruction data newly read by the instruction supply subunit 110 to the decoding unit 200, thereby saving the time required for the buffer subunit 120 to cache instruction data, reducing the penalty for branch prediction errors, and shortening the recovery time of the processor 10.

[0035] In this embodiment, the instruction supply subunit 110 can read instruction data according to a given storage address and output the instruction data to the arbitration subunit 130 and the buffer subunit 120 through its output terminal. The buffer subunit 120 can receive and store the instruction data output by the output terminal of the instruction supply subunit 110 and output the instruction data through its output terminal. The arbitration subunit 130 is configured to determine whether the output terminal of the buffer subunit 120 is valid, and when the output terminal of the buffer subunit 120 is valid, transmit the instruction data output by the output terminal of the buffer subunit 120 to the decoding unit 200; when the output terminal of the buffer subunit 120 is invalid, transmit the instruction data output by the output terminal of the instruction supply subunit 110 to the decoding unit 200. When the output terminal of the buffer subunit 120 is invalid, the system can automatically switch to the output terminal of the instruction supply subunit 110 to obtain instruction data, without having to wait for the instruction data to be written to the buffer subunit 120, thus saving the time required for the instruction data to travel from the instruction fetch unit 100 to the decoding unit 200 and reducing additional transmission delay.

[0036] like Figure 2 As shown, in some optional embodiments, the second input terminal of the arbitration subunit 130 may include a first sub-input terminal and a second sub-input terminal, and the buffer subunit 120 includes a receiving subunit 121 and a buffer subunit 122. The input terminal of the receiving subunit 121 is connected to the input terminal of the buffer subunit 120, the first output terminal of the receiving subunit 121 is connected to the first sub-input terminal, the second output terminal of the receiving subunit 121 is connected to the input terminal of the buffer subunit 122, and the output terminal of the buffer subunit 122 is connected to the second sub-input terminal.

[0037] The receiving subunit 121 is configured to receive instruction data output from the output terminal of the instruction supply subunit 110, and output the instruction data through its first and second output terminals respectively. The buffer subunit 122 is configured to store the instruction data output from the second output terminal of the receiving subunit 121, and output the instruction data through its output terminal according to the storage order of the instruction data. The buffer subunit 122 may include an instruction buffer queue, thereby storing the instruction data through the instruction buffer queue.

[0038] Arbitration subunit 130 is configured to determine whether the output of buffer subunit 122 is valid. If the output of buffer subunit 122 is valid, the instruction data output by buffer subunit 122 is transmitted to decoding subunit 200. If the output of buffer subunit 122 is invalid, the arbitration subunit 130 determines whether the output of the first output of receiving subunit 121 is valid. If the output of the first output of receiving subunit 121 is valid, the instruction data output by the first output of receiving subunit 121 is transmitted to decoding subunit 200. If the output of the first output of receiving subunit 121 is invalid, the instruction data output by the output of instruction supply subunit 110 is transmitted to decoding subunit 200.

[0039] Similar to the above embodiments, the arbitration subunit 130 can determine whether the output of the buffer subunit 122 is valid based on whether instruction data is output at its output terminal. Similarly, the arbitration subunit 130 can determine whether the output of the first output terminal of the receiving subunit 121 is valid based on whether instruction data is output at its first output terminal. Further details are omitted here. It should be understood that when the arbitration subunit 130 determines that both the output of the buffer subunit 122 and the first output terminal of the receiving subunit 121 are invalid, the output of the buffer subunit 120 is invalid. Conversely, when the arbitration subunit 130 determines that either the output of the buffer subunit 122 or the first output terminal of the receiving subunit 121 is valid, the output of the buffer subunit 120 is valid.

[0040] In this implementation, the buffer subunit 120 includes a receiving subunit 121 and a buffer subunit 122. After receiving instruction data from the output terminal of the instruction supply subunit 110, the receiving subunit 121 can output the instruction data to the first sub-input terminal of the arbitration subunit 130 through its first output terminal and to the buffer subunit 122 through its second output terminal, thus extending the instruction data transmission path. The arbitration subunit 130 can determine whether the output of the buffer subunit 122 is valid based on the connection between its second sub-input terminal and the output terminal of the buffer subunit 122. When the output of the buffer subunit 122 is valid, the instruction data output by the buffer subunit 122 is transmitted to the decoding unit 200. When the output of the buffer subunit 122 is invalid, it is determined whether the output of the first output terminal of the receiving subunit 121 is valid. If the output of the first output terminal of the receiving subunit 121 is valid, the instruction data output by the first output terminal of the receiving subunit 121 is transmitted to the decoding unit 200. If the output of the first output terminal of the receiving subunit 121 is invalid, the instruction data output by the output terminal of the instruction supply subunit 110 is transmitted to the decoding unit 200. By establishing a connection between the receiving subunit 121 and the arbitration unit, a direct path for instruction data from the buffer subunit 120 to the arbitration unit is added, forming an intermediate bypass channel. This ensures that when the output of the buffer subunit 122 is invalid, the entire output of the buffer subunit 120 is not directly determined to be invalid. Instead, the system continues to check whether the output of the first output terminal of the receiving subunit 121 is invalid. This allows the arbitration unit to receive the instruction data output from the first output terminal of the receiving subunit 121 when the output of the buffer subunit 122 is invalid but new instruction data has arrived at the receiving subunit 121, thus obtaining the instruction data to be transmitted to the decoding unit 200 without waiting for the instruction data to be written to the buffer subunit 122 first. This reduces the latency of instruction data transmission and avoids missing instruction data that has arrived at the receiving subunit 121, thereby optimizing instruction data transmission without disrupting the instruction order.

[0041] like Figure 3As shown, in some optional embodiments, the receiving subunit 121 includes a receiving register 1211 and an enabling subunit 1212. The receiving subunit 121 is configured to receive instruction data output from the output terminal of the instruction supply subunit 110, store the received instruction data in the receiving register 1211, and generate a storage enable signal in the enabling subunit 1212. The instruction data stored in the receiving register 1211 is output to the arbitration subunit 130 through the first output terminal of the receiving subunit 121, and the instruction data stored in the receiving register 1211 and the storage enable signal are output to the buffer subunit 122 through the second output terminal of the receiving subunit 121. The buffer subunit 122 is configured to store the instruction data output from the second output terminal of the receiving subunit 121 in response to the storage enable signal; wherein the storage space of the buffer subunit 122 is larger than that of the receiving register 1211. In this embodiment, the receive register 1211 can be used as temporary storage before the instruction enters the cache subunit 122. Combined with the storage enable signal generated by the enable subunit 1212, precise control of the write operation of the cache subunit 122 is realized, which enables the instruction data to be stably written to the cache subunit 122. The two-level cache structure formed by the receive register 1211 and the larger capacity cache subunit 122 can improve the flexibility of buffering instruction data.

[0042] In some optional embodiments, the receiving subunit 121 can be configured to generate a storage pause signal by enabling subunit 1212 when the arbitration subunit 130 transmits the instruction data output from the output terminal of the instruction supply subunit 110 to the decoding unit 200, and output the storage pause signal to the buffer subunit 122 through the second output terminal of the receiving subunit 121. Optionally, when the arbitration subunit 130 transmits the instruction data output from the output terminal of the instruction supply subunit 110 to the decoding unit 200, it can send a first feedback signal to the receiving subunit 121. Upon receiving the first feedback signal, the receiving subunit 121 can generate a storage pause signal by enabling subunit 1212, and output the storage pause signal to the buffer subunit 122 through the second output terminal of the receiving subunit 121. Alternatively, the receiving subunit 121 can be configured to generate a storage pause signal through the enabling subunit 1212 when the arbitration subunit 130 transmits the instruction data output from the first output terminal of the receiving subunit 121 to the decoding unit 200, and output the storage pause signal to the buffer subunit 122 through the second output terminal of the receiving subunit 121. Optionally, when the arbitration subunit 130 transmits the instruction data output from the first output terminal of the receiving subunit 121 to the decoding unit 200, it can send a second feedback signal to the receiving subunit 121. Upon receiving the second feedback signal, the receiving subunit 121 can generate a storage pause signal through the enabling subunit 1212, and output the storage pause signal to the buffer subunit 122 through the second output terminal of the receiving subunit 121. Alternatively, the receiving subunit 121 can be configured to generate a storage pause signal through the enabling subunit 1212 and output the storage pause signal to the buffer subunit 122 through the second output terminal of the receiving subunit 121 when the arbitration subunit 130 transmits the instruction data output from the instruction supply subunit 110 to the decoding subunit 200, and when the arbitration subunit 130 transmits the instruction data output from the first output terminal of the receiving subunit 121 to the decoding subunit 200. The receiving subunit 121 can also generate a storage pause signal through the enabling subunit 1212 and output the storage pause signal to the buffer subunit 122 through the second output terminal of the receiving subunit 121 upon receiving either the first feedback signal or the second feedback signal.

[0043] The cache subunit 122 can be configured to stop storing instruction data output from the second output terminal of the receiving subunit 121 in response to a storage pause signal. Optionally, the storage enable signal and the storage pause signal can be a high-level signal indicating logic 1 and a low-level signal indicating logic 0, respectively. The enable subunit 1212 can adjust its output result by adjusting the level of its generated signal.

[0044] In this embodiment, the receiving subunit 121 can transmit the instruction data output from the output terminal of the instruction supply subunit 110 to the decoding unit 200 when the arbitration subunit 130 transmits the instruction data output from the first output terminal of the receiving subunit 121 to the decoding unit 200, and when the arbitration subunit 130 transmits the instruction data output from the first output terminal of the receiving subunit 121 to the decoding unit 200. By generating a storage pause signal, the cache subunit 122 can be controlled to pause the storage of instruction data. This can effectively avoid redundant write operations of the cache subunit 122, reduce the power consumption of the cache subunit 122, and free up storage space for subsequent instruction data that actually needs to be cached, thereby optimizing the performance of the cache subunit 122.

[0045] In some alternative embodiments, the arbitration subunit 130 may be configured to send a third feedback signal to the buffer subunit 122 when it transmits instruction data output from the output of the instruction supply subunit 110 to the decoding unit 200. Alternatively, the arbitration subunit 130 may be configured to send a third feedback signal to the buffer subunit 122 when it transmits instruction data output from the first output of the receiving subunit 121 to the decoding unit 200. Alternatively, the arbitration subunit 130 may be configured to send a third feedback signal to the buffer subunit 122 when transmitting instruction data output from the output of the instruction supply subunit 110 to the decoding unit 200, and when transmitting instruction data output from the first output of the receiving subunit 121 to the decoding unit 200. The buffer subunit 122 may be configured to stop storing instruction data output from the second output of the receiving subunit 121 in response to the third feedback signal.

[0046] In this embodiment, the arbitration subunit 130 can be configured to send a third feedback signal to the cache subunit 122 when it transmits the instruction data output from the output terminal of the instruction supply subunit 110 to the decoding unit 200, and when it transmits the instruction data output from the first output terminal of the receiving subunit 121 to the decoding unit 200. This feedback signal, together with the storage pause signal output by the receiving subunit 121 to the cache subunit 122, can control the cache subunit 122 to pause the storage operation, thereby further ensuring that the cache subunit 122 can pause the storage of instruction data and avoid redundant write operations of the cache subunit 122.

[0047] like Figure 4As shown, in some optional embodiments, the instruction supply subunit 110 may include an instruction cache subunit 111, which is used to store historical instruction data. The instruction supply subunit 110 is configured to read instruction data from the instruction cache subunit 111 according to a given storage address; if instruction data is not read from the instruction cache subunit 111, then instruction data is read from an instruction storage unit according to a given storage address, wherein the instruction storage unit is used to store all instruction data.

[0048] Historical instruction data refers to instruction data that the processor 10 has used. The instruction cache subunit 111 may include an instruction cache (iCache) to store recently used historical instruction data of the processor 10. The amount of historical instruction data stored in the instruction cache subunit 111 can be determined by its storage space; when its storage space is insufficient, older historical instruction data can be deleted when storing newer historical instruction data. The instruction storage unit can be a pre-determined memory for storing instruction data, and all instruction data of the processor 10 can be stored in the instruction storage unit. The given storage address may include a virtual address. The instruction supply subunit 110 can look up the physical address corresponding to the virtual address from the page table indicating the mapping relationship between virtual and physical addresses, and read the instruction data from the iCache based on the virtual address and the physical address. If the instruction data is read from the iCache, it can be output through its first and second output terminals. If the instruction data is not read from the iCache, the instruction supply subunit 110 can read the instruction data from the instruction storage unit based on the physical address. It should be understood that the physical address corresponding to the virtual address is the physical address of the storage space of the instruction storage unit. Of course, the given storage address can include both virtual and physical addresses. In this case, the instruction supply subunit 110 can directly read instruction data from the iCache based on the virtual and physical addresses.

[0049] In this embodiment, when the processor 10 needs to fetch instructions, the instruction supply subunit 110 can prioritize searching for the most recent historical instruction data from the instruction cache subunit 111, which has a smaller data volume. This leverages the small data volume and fast response speed of the cache subunit to achieve rapid instruction data retrieval. In the event of a cache miss, it can seamlessly switch to the instruction storage unit, which stores all instruction data, to ensure that instruction data can be retrieved. The instruction cache subunit 111 can reuse its stored high-frequency historical instruction data, reducing the average latency of instruction fetching, minimizing waiting time caused by slow access to the instruction storage unit, and improving the efficiency of the instruction fetch unit 100.

[0050] like Figure 5As shown, in some optional embodiments, the instruction fetch unit 100 further includes a branch prediction subunit 140, which is configured to obtain a memory address by performing branch prediction, thereby providing a given memory address to the instruction supply subunit 110. The branch prediction subunit 140 can be directly or indirectly connected to the instruction supply subunit 110, and this embodiment does not limit its connection method.

[0051] Branch prediction subunit 140 can predict the execution path of branch instructions (such as if-else statements and loops) through branch prediction, and obtain the memory address where the instruction data on that path is located based on the predicted execution path, so as to obtain the instruction data based on that memory address. Optionally, branch prediction subunit 140 can adopt an existing branch prediction unit (BPU), and details can be found in relevant technologies, which will not be elaborated here.

[0052] In this embodiment, by setting a branch prediction subunit 140, the instruction fetch unit 100 is equipped with the ability to predict the storage address of instruction data. This allows the instruction fetch unit 100 to obtain the next possible instruction data before the current instruction sequence is completed, ensuring the efficiency and continuity of instruction supply and laying the foundation for improving the parallel efficiency of the processor 10.

[0053] like Figure 5 As shown, in some optional embodiments, the instruction fetch unit 100 further includes an address cache subunit 150, which is connected between the branch prediction subunit 140 and the instruction supply subunit 110. The address cache subunit 150 is configured to receive and store the memory address predicted by the branch prediction subunit 140, and output the stored memory address to the instruction supply subunit 110.

[0054] After the branch prediction subunit 140 predicts the memory address, it can output the memory address to the address cache subunit 150. The address cache subunit 150 may include a fetch address queue (FTQ). After receiving the memory address output by the branch prediction subunit 140, the address cache subunit 150 can store the memory address in the fetch address queue. Multiple memory addresses are stored in the fetch address queue, and the memory addresses are sequentially output to the instruction supply subunit 110.

[0055] In this embodiment, by setting an address cache subunit 150, an intermediate unit for buffering memory addresses can be established between the branch prediction subunit 140 and the instruction supply subunit 110, enabling partial decoupling and parallel execution of "memory address generation" and "instruction data reading". The address cache subunit 150 can smooth the memory addresses generated by the branch prediction unit, providing a stable and continuous supply of memory addresses for the instruction supply subunit 110. Simultaneously, it allows the branch prediction unit to make predictions more flexibly, without being limited by the speed at which the instruction supply subunit 110 reads instruction data, effectively improving the efficiency of the instruction fetch unit 100 in transmitting instruction data.

[0056] Fetching method:

[0057] This application also provides an instruction fetching method for a processor. The processor may include the instruction fetching unit of any of the above embodiments, and the instruction fetching method of this embodiment is used for the instruction fetching unit included in the processor. Optionally, the processor may include an instruction supply subunit, a buffer subunit, and an arbitration subunit. The output terminal of the instruction supply subunit is connected to the first input terminal of the arbitration subunit and the input terminal of the buffer subunit, respectively. The output terminal of the buffer subunit is connected to the second input terminal of the arbitration subunit, and the output terminal of the arbitration subunit is connected to the decoding unit of the processor. Figure 6 As shown, the instruction fetching methods include:

[0058] S610. The instruction supply subunit reads instruction data according to the given storage address, and outputs the instruction data to the first input of the arbitration subunit and the input of the buffer subunit respectively through the output of the instruction supply subunit.

[0059] S620: Receives and stores instruction data output from the output terminal of the instruction supply subunit through the buffer subunit, and outputs instruction data through the output terminal of the buffer subunit.

[0060] S630: Determine whether the output of the buffer subunit is valid by using the arbitration subunit.

[0061] S631. If the output of the buffer subunit is valid, the instruction data output by the buffer subunit is transmitted to the processor's decoding unit.

[0062] S632. If the output of the buffer subunit is invalid, the instruction data output by the instruction supply subunit is transmitted to the decoding unit.

[0063] The instruction fetching method in this embodiment is based on the same inventive concept as the aforementioned instruction fetching unit 100 embodiment, and is used to implement the corresponding cache management methods in the above-mentioned instruction fetching method embodiments, and has the beneficial effects of the corresponding instruction fetching method embodiments, which will not be repeated here. The implementation of each step in the cache instruction fetching method of this embodiment can refer to the description of the corresponding module or unit in the aforementioned instruction fetching method embodiments, which will also not be repeated here.

[0064] processor:

[0065] This application also provides a processor 10, including the instruction fetch unit 100 described in any of the above embodiments.

[0066] like Figure 7 As shown, in some optional embodiments, the processor 10 may further include a decoding unit 200 and an execution unit 300. The decoding unit 200 translates the instruction data obtained by the instruction fetch unit 100 into corresponding micro-operation or control signals, and the execution unit 300 executes the corresponding arithmetic operations based on the micro-operation or control signals translated by the decoding unit 200.

[0067] Electronic devices:

[0068] This application also provides an electronic device, including the processor 10 described in the above embodiments.

[0069] It should be noted that the user-related information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to sample data used for training the model, data used for analysis, stored data, displayed data, etc.) involved in the embodiments of this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0070] It should be noted that, depending on the implementation needs, the various components / steps described in the embodiments of this application can be broken down into more components / steps, or two or more components / steps or parts of the operation of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of this application.

[0071] The methods described in the embodiments of this application can be implemented in hardware, firmware, or as software or computer code that can be stored in a recording medium (such as a CD-ROM, RAM, floppy disk, hard disk, or magneto-optical disk), or as computer code downloaded over a network that is originally stored in a remote recording medium or a non-transitory machine-readable medium and will be stored in a local recording medium. Thus, the methods described herein can be processed by software stored on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as an ASIC or FPGA). It is understood that the computer, processor, microprocessor controller, or programmable hardware includes storage components (e.g., RAM, ROM, flash memory, etc.) capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods described herein. Furthermore, when a general-purpose computer accesses code used to implement the methods shown herein, the execution of the code transforms the general-purpose computer into a dedicated computer for executing the methods shown herein.

[0072] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application.

[0073] The above embodiments are only used to illustrate the embodiments of this application, and are not intended to limit the embodiments of this application. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of this application. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of this application, and the patent protection scope of the embodiments of this application should be defined by the claims.

Claims

1. An instruction fetch unit for a processor, wherein, The instruction fetch unit includes: an instruction supply subunit, a buffer subunit, an arbitration subunit, and an instruction cache subunit; the output of the instruction supply subunit is connected to the first input of the arbitration subunit and the input of the buffer subunit, respectively; the output of the buffer subunit is connected to the second input of the arbitration subunit; and the output of the arbitration subunit is connected to the decoding unit of the processor. The instruction cache subunit is configured to store historical instruction data; The instruction supply subunit is configured to read instruction data from the instruction cache subunit according to a given storage address; if the instruction data is not read from the instruction cache subunit, then the instruction data is read from the instruction storage unit according to the given storage address, wherein the given storage address is a storage address given by branch prediction, and the instruction storage unit is used to store all instruction data; the instruction data is output from the output terminal of the instruction supply subunit to the first input terminal of the arbitration subunit and the input terminal of the buffer subunit, respectively. The buffer subunit is configured to receive and store the instruction data output from the output terminal of the instruction supply subunit, and output the instruction data through the output terminal of the buffer subunit, so as to buffer the transmission of the instruction data. The arbitration subunit is configured to determine whether the output of the buffer subunit is valid. When the output of the buffer subunit outputs the instruction data, the arbitration subunit determines that the output of the buffer subunit is valid. When the buffer subunit is cleared, the output of the buffer subunit is empty, and the arbitration subunit determines that the output of the buffer subunit is invalid. If the output of the buffer subunit is valid, the instruction data output by the buffer subunit is transmitted to the decoding unit. If the output of the buffer subunit is invalid, the instruction data output by the instruction supply subunit is transmitted to the decoding unit without waiting for the buffer subunit to write the instruction data.

2. The instruction fetching unit according to claim 1, wherein, The second input terminal of the arbitration subunit includes a first sub-input terminal and a second sub-input terminal; the buffer subunit includes a receiving subunit and a buffer subunit; the input terminal of the receiving subunit is connected to the input terminal of the buffer subunit, the first output terminal of the receiving subunit is connected to the first sub-input terminal, the second output terminal of the receiving subunit is connected to the input terminal of the buffer subunit, and the output terminal of the buffer subunit is connected to the second sub-input terminal. The receiving subunit is configured to receive the instruction data output by the output terminal of the instruction supply subunit, and output the instruction data through the first output terminal and the second output terminal of the receiving subunit respectively; The cache subunit is configured to store the instruction data output from the second output terminal of the receiving subunit, and to output the instruction data through the output terminal of the cache subunit according to the storage order of the instruction data; The arbitration subunit is configured to determine whether the output of the cache subunit is valid. If the output of the cache subunit is valid, the instruction data output by the cache subunit is transmitted to the decoding unit. If the output of the buffer subunit is invalid, then it is determined whether the output of the first output terminal of the receiving subunit is valid. If the output of the first output terminal of the receiving subunit is valid, then the instruction data output by the first output terminal of the receiving subunit is transmitted to the decoding unit. If the output of the first output terminal of the receiving subunit is invalid, then the instruction data output by the output terminal of the instruction supply subunit is transmitted to the decoding unit.

3. The instruction fetching unit according to claim 2, wherein, The receiving subunit includes a receiving register and an enabling subunit. The receiving subunit is configured to receive the instruction data output by the output terminal of the instruction supply subunit, store the received instruction data through the receiving register, and generate a storage enabling signal through the enabling subunit. The instruction data stored in the receiving register is output to the arbitration subunit through the first output terminal of the receiving subunit, and the instruction data stored in the receiving register and the storage enable signal are output to the cache subunit through the second output terminal of the receiving subunit. The cache subunit is configured to, in response to the storage enable signal, store the instruction data output from the second output terminal of the receiving subunit; wherein the storage space of the cache subunit is larger than that of the receiving register.

4. The instruction fetching unit according to claim 3, wherein, The receiving subunit is configured to generate a storage pause signal through the enabling subunit and output the storage pause signal to the buffer subunit through the second output terminal of the receiving subunit when the arbitration subunit transmits the instruction data output from the first output terminal of the receiving subunit to the decoding unit. The cache subunit is configured to stop storing the instruction data output by the second output terminal of the receiving subunit in response to the storage pause signal.

5. The instruction fetching unit according to any one of claims 1-4, wherein, The instruction fetching unit further includes a branch prediction subunit, which is configured to obtain the storage address by performing branch prediction.

6. The instruction fetching unit according to claim 5, wherein, The instruction fetch unit further includes an address cache subunit, which is connected between the branch prediction subunit and the instruction supply subunit. The address cache subunit is configured to receive and store the storage address predicted by the branch prediction subunit, and output the stored storage address to the instruction supply subunit.

7. A method for fetching instructions for a processor, wherein, The processor includes an instruction supply subunit, a buffer subunit, an arbitration subunit, and an instruction cache subunit; the output of the instruction supply subunit is connected to the first input of the arbitration subunit and the input of the buffer subunit, respectively; the output of the buffer subunit is connected to the second input of the arbitration subunit; the output of the arbitration subunit is connected to the decoding unit of the processor; and the instruction cache subunit is configured to store historical instruction data. The instruction fetching method includes: The instruction supply subunit reads instruction data from the instruction cache subunit according to a given storage address. If the instruction data is not found in the instruction cache subunit, it reads the instruction data from the instruction storage unit according to the given storage address. The given storage address is a storage address given by branch prediction. The instruction storage unit is used to store all instruction data. The instruction data is output from the output terminal of the instruction supply subunit to the first input terminal of the arbitration subunit and the input terminal of the buffer subunit, respectively. The buffer subunit receives and stores the instruction data output from the output terminal of the instruction supply subunit, and outputs the instruction data through the output terminal of the buffer subunit, so as to buffer the transmission of the instruction data. The arbitration subunit determines whether the output of the buffer subunit is valid. Specifically, when the buffer subunit outputs the instruction data, the arbitration subunit determines the output of the buffer subunit is valid; when the buffer subunit is cleared, the output of the buffer subunit is empty, and the arbitration subunit determines the output of the buffer subunit is invalid. If the output of the buffer subunit is valid, the instruction data output by the buffer subunit is transmitted to the processor's decoding unit. If the output of the buffer subunit is invalid, it is not necessary to wait for the buffer subunit to write the instruction data output by the instruction supply subunit; instead, the instruction data output by the instruction supply subunit is transmitted to the decoding unit.

8. A processor comprising the instruction fetch unit according to any one of claims 1-6.

9. An electronic device comprising the processor of claim 8.

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