Interrupt processing method, chip, electronic device, medium and product

Abstract

This application provides an interrupt handling method, chip, electronic device, medium, and product. The method includes: receiving an interrupt request; in response to the interrupt event type corresponding to the interrupt request being a fast interrupt type, determining the instruction state of each instruction in the instruction pipeline; in response to all the instruction states being a first state, canceling the execution of all the instructions and executing the interrupt routine corresponding to the interrupt request, wherein the first state indicates that the instruction can be canceled. This application aims to improve the timeliness of interrupt response.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to an interrupt handling method, chip, electronic device, medium, and product. Background Technology

[0002] An interrupt is a mechanism by which a processor responds to external asynchronous events. When an external device needs processing from the Central Processing Unit (CPU), the external device sends an interrupt request to the CPU. The CPU suspends the currently executing program flow and executes an interrupt service routine (ISR) to handle the interrupt event before returning to the original program to continue execution.

[0003] In related technologies, in order to return to the original program after the interrupt service routine (ISR) has finished executing, the CPU must ensure that all instructions in the current pipeline have been executed before entering the ISR. This significantly impacts the interrupt response speed and drastically reduces the system's real-time performance. How to improve the timeliness of interrupt response is a problem that urgently needs to be discussed and solved. Summary of the Invention

[0004] This application provides an interrupt handling method, chip, electronic device, medium, and product, aiming to improve the timeliness of interrupt response.

[0005] In a first aspect, embodiments of this application provide an interrupt handling method, the method comprising: receiving an interrupt request; in response to the interrupt event type corresponding to the interrupt request being a fast interrupt type, determining the instruction state of each instruction in the instruction pipeline; in response to all the instruction states being a first state, canceling the execution of all the instructions, and executing the interrupt routine corresponding to the interrupt request, wherein the first state indicates that the instruction can be canceled.

[0006] Secondly, embodiments of this application provide a chip, the chip including a processor and a data interface, the processor reading instructions stored in a memory through the data interface and executing the interrupt handling method as described in the first aspect.

[0007] Thirdly, embodiments of this application provide an electronic device, including: at least one processor; at least one memory for storing at least one program; and implementing the interrupt handling method as described in the first aspect when at least one of the programs is executed by at least one of the processors.

[0008] Fourthly, embodiments of this application provide a computer-readable storage medium, characterized in that the computer-readable storage medium stores computer-executable instructions for performing the interrupt handling method as described in the first aspect.

[0009] Fifthly, embodiments of this application provide a computer program product, including a computer program or computer instructions, characterized in that the computer program or computer instructions are stored in a computer-readable storage medium, a processor of a computer device reads the computer program or computer instructions from the computer-readable storage medium, and the processor executes the computer program or computer instructions, causing the computer device to perform the interrupt handling method as described in the first aspect.

[0010] In this embodiment, upon receiving an interrupt request, if the interrupt event type corresponding to the interrupt request is a fast interrupt type, a fast interrupt procedure is triggered. During the fast interrupt procedure, the instruction status of each instruction in the instruction pipeline is identified. When the instruction status of all instructions is in the first state, it is determined that all instructions in the instruction pipeline can be cancelled, thus cancelling the execution of all instructions and directly responding to the interrupt request to execute the interrupt routine. This achieves immediate interrupt response and execution of the interrupt routine without waiting for all instructions in the instruction pipeline to retire, improving the timeliness of interrupt response and enhancing system real-time performance.

[0011] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the description, claims and drawings. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of an interruption handling scenario for an application interruption handling method provided in one embodiment of this application;

[0013] Figure 2 A flowchart illustrating an interrupt handling method provided in an embodiment of this application;

[0014] Figure 3 A schematic diagram of an interrupt handling process provided as an example of this application;

[0015] Figure 4 A comparative illustration of enabling fast interrupts (left) and disabling fast interrupts (right) in a first scenario provided as an example of this application;

[0016] Figure 5 A comparative illustration of enabling fast interrupts (left) and disabling fast interrupts (right) in a second scenario provided as an example of this application;

[0017] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0019] It should be noted that although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first," "second," etc., in the specification, claims, and the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0020] In the description of the embodiments of this application, unless otherwise expressly limited, terms such as setting, installing, and connecting should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in the embodiments of this application in combination with the specific content of the technical solution.

[0021] In this application, the terms "furthermore," "exemplarily," or "optionally" are used as examples, illustrations, or descriptions and should not be construed as being more preferred or advantageous than other embodiments or designs. The use of terms such as "furthermore," "exemplarily," or "optionally" is intended to present the relevant concepts in a specific manner.

[0022] In related technologies, an interrupt is a mechanism for a processor to respond to external asynchronous events. When an external device needs processing from the Central Processing Unit (CPU), the external device sends an interrupt request to the CPU. The CPU suspends the currently executing program flow and executes an interrupt service routine (ISR). After handling the interrupt event, it returns to the original program to continue execution.

[0023] When an interrupt occurs and is responded to by the CPU, the hardware and software will operate according to the following process:

[0024] (1) Automatic hardware response

[0025] ① Complete the current instruction: In order to return to the original program after the interrupt service routine is completed, the CPU must ensure that all instructions in the current pipeline have been executed before proceeding to the next step.

[0026] ② Save the current state to specific registers: The hardware automatically stores key information into a series of control status registers; including but not limited to:

[0027] PC (Program Counter): Stores the address of the next instruction to be executed (as the return address after an interrupt is completed);

[0028] cause (Cause Register): Stores the interrupt cause number;

[0029] status (Status Register): Stores current status information such as the global interrupt enable bit.

[0030] ③ Jump to the interrupt handler entry point: The CPU jumps to the corresponding interrupt service routine based on the base address of the interrupt vector table set in the register to begin execution.

[0031] (2) Software processing (interrupt service routine)

[0032] ① Save context: The interrupt service routine first needs to push the general-purpose registers that the current task may use onto the stack to prevent the original task's execution environment from being corrupted.

[0033] ② Investigate the cause and identify the interrupt source: Read the cause register to determine which specific interrupt source triggered this interrupt.

[0034] ③ Execute interrupt handling logic: If it is a timer interrupt, the operating system scheduler is called, which may perform task switching; if it is an external interrupt, the interrupt controller needs to be queried to determine which specific device it is and then handle it.

[0035] ④ Clear the interrupt source: After processing is complete, you need to notify the interrupt controller or the device itself that "the interrupt has been processed"; otherwise, the interrupt will continue to be triggered.

[0036] ⑤ Restore context: Restore the general-purpose registers that were previously pushed onto the stack.

[0037] (3) Interruption return

[0038] ① Execute the *RET instruction: This is a privileged instruction. The hardware will respond to it and: restore the program counter from the PC register, that is, jump back to the original interrupted instruction stream; restore the values ​​of some fields in the status register.

[0039] Normally, to ensure execution can return to the original program after an interrupt service routine has finished executing, the CPU responds to interrupts only after all instructions in the pipeline have retired. If the CPU executes multi-cycle instructions or instructions with unpredictable delays, the interrupt response speed is significantly impacted because it has to wait for all instructions to retire, drastically reducing system real-time performance. However, many critical systems have strict time constraints for interrupt response. The time from the interrupt signal being issued to entering the interrupt service routine must be as short as possible; otherwise, system failure or a sharp performance degradation may occur. Improving the timeliness of interrupt response is a problem that urgently needs to be discussed and solved.

[0040] Based on this, embodiments of this application provide an interrupt handling method, chip, electronic device, medium, and product. Upon receiving an interrupt request, the interrupt event type corresponding to the interrupt request is identified. If the interrupt event type corresponding to the interrupt request is a fast interrupt type, a fast interrupt procedure is triggered. In the fast interrupt procedure, the instruction status of each instruction in the instruction pipeline is identified. When the instruction status of all instructions is in the first state, it is determined that all instructions in the instruction pipeline can be cancelled, thereby cancelling the execution of all instructions and directly responding to the interrupt request to execute the interrupt routine. This achieves immediate interrupt response and execution of the interrupt routine without waiting for all instructions in the instruction pipeline to retire, improving the timeliness of interrupt response and enhancing system real-time performance.

[0041] The embodiments of this application will be further described below with reference to the accompanying drawings.

[0042] Figure 1 This is a schematic diagram of an interruption handling scenario provided by an embodiment of the application interruption handling method.

[0043] For example, such as Figure 1 As shown, when an interrupt source initiates an interrupt, the interrupt controller captures the interrupt and sends an interrupt request to the processor. Upon receiving the interrupt request, the processor identifies the interrupt event type corresponding to the interrupt request. If the interrupt event type corresponding to the interrupt request is a fast interrupt type, the processor determines the relevant instructions in the instruction pipeline (such as...) Figure 1 The processor responds when all instruction states are in the first state, where the first state indicates that the instruction can be cancelled. After confirming that all instructions in the current instruction pipeline are cancelable, the processor cancels the execution of all instructions and executes the interrupt routine corresponding to the interrupt request.

[0044] In the example above, when the processor receives an interrupt request, it identifies the interrupt event type corresponding to the interrupt request. If the interrupt event type is a fast interrupt, a fast interrupt procedure is triggered. In the fast interrupt procedure, the state of each instruction in the instruction pipeline is used to determine whether an instruction can be cancelled. If it is confirmed that all instructions can be cancelled, the execution of all instructions is directly cancelled, and the interrupt request is responded to immediately by executing the interrupt routine. This achieves immediate interrupt response and execution of the interrupt routine without waiting for all instructions in the instruction pipeline to retire, improving the timeliness of interrupt response and enhancing system real-time performance.

[0045] Figure 2 This is a flowchart illustrating an interrupt handling method provided in an embodiment of this application. Figure 2 As shown, this interrupt handling method can be applied to, but is not limited to, processors, for example... Figure 1 The processor shown. This interrupt handling method includes, but is not limited to:

[0046] Step 210: An interrupt request is received;

[0047] Step 220: In response to the interrupt event type corresponding to the interrupt request being a fast interrupt type, determine the instruction status of each instruction in the instruction pipeline;

[0048] Step 230: In response to all instruction states being in the first state, cancel the execution of all instructions and execute the interrupt routine corresponding to the interrupt request. The first state indicates that the instruction can be canceled.

[0049] In step 210, an interrupt request refers to a request sent by an external hardware device or software program to the processor (such as the CPU) to notify the processor that a sudden event has occurred and requires preferential processing. For example, an interrupt request may be generated by an interrupt controller that has captured an interrupt event.

[0050] In step 220, the interrupt event type is an identifier indicating whether the corresponding interrupt request requires fast response for interrupt handling. For example, interrupt event types include fast interrupt types and normal interrupt types. The fast interrupt type indicates that the corresponding interrupt requires urgent handling, such as watchdog interrupts, high-speed I / O (Input / Output) device interrupts, memory error interrupts, and other interrupt events related to core system functions.

[0051] An instruction pipeline is a hardware module in a processor that can break down the execution of a single instruction into multiple independent stages, allowing for the parallel processing of different stages of multiple different instructions. Instruction status indicates whether the corresponding instruction can be canceled or not.

[0052] In step 230, instruction cancellation is a process that stops the current execution of instructions in the pipeline that have not started retirement or have not completed retirement, cleans up the corresponding temporary data (if any), and releases the corresponding hardware resources.

[0053] An instruction that can be cancelled means that when an interrupt occurs, the instruction can respond to the interrupt immediately without waiting to retire; it can simply be re-executed when the interrupt returns. An instruction that cannot be cancelled means that when an interrupt occurs, the instruction must retire before it can enter the interrupt service routine. For example, whether an instruction is cancelable or non-cancellable can be configured in advance through preset methods; alternatively, the decision of whether an instruction can be cancelled can be determined based on the current business logic and the instruction's impact on the system.

[0054] An interrupt routine refers to an interrupt service routine (ISR) that corresponds to an interrupt request. For example, each interrupt request is bound to a dedicated interrupt service routine. In some scenarios, such as for low-priority interrupt requests, multiple interrupt requests may share a single interrupt service routine. No specific limitations are imposed here.

[0055] In the embodiments of steps 210 to 230 above, upon receiving an interrupt request, the interrupt event type corresponding to the interrupt request is identified. If the interrupt event type corresponding to the interrupt request is a fast interrupt type, a fast interrupt procedure is triggered. In the fast interrupt procedure, the instruction status of each instruction in the instruction pipeline is identified. When the instruction status of all instructions is in the first state, it is determined that all instructions in the instruction pipeline can be cancelled, thereby cancelling the execution of all instructions and directly responding to the interrupt request to execute the interrupt routine. This achieves immediate interrupt response and execution of the interrupt routine without waiting for all instructions in the instruction pipeline to retire, improving the timeliness of interrupt response and enhancing system real-time performance.

[0056] The above is a general description of steps 210 to 230. The following is a detailed description of the specific implementation process of steps 210 to 230.

[0057] In one embodiment, after step 210, the method further includes: responding to the interrupt event type corresponding to the interrupt request being a normal interrupt type, and waiting for all instructions in the instruction pipeline to retire before executing the interrupt routine corresponding to the interrupt request. Here, a normal interrupt type indicates an interrupt that does not require urgent handling, such as non-critical sensors, modulation interfaces, or other interrupt events that are weakly related to the core functions of the system.

[0058] In this embodiment, since the interrupt event type corresponding to the interrupt request is a normal interrupt type, such as interrupts to non-critical sensors or debugging interfaces, no emergency handling is required. Therefore, a normal interrupt response process is directly adopted. That is, after all instructions in the instruction pipeline retire, i.e., after the instruction pipeline is cleared, the interrupt service routine is entered to execute the interrupt routine corresponding to the interrupt request. By flexibly selecting between a fast interrupt process and a normal interrupt response process based on the normal interrupt type and fast interrupt type corresponding to the interrupt request, the interference of interrupts on the original program execution efficiency is minimized without affecting the critical functions of the system. This avoids the additional overhead of pipeline flushing and context switching, ensures program state consistency, and balances interrupt response with system throughput.

[0059] In one embodiment, a status register can be configured to store the instruction status of each instruction in the instruction pipeline. Each bit in the status register corresponds one-to-one with each instruction in the instruction pipeline, so that the status register can be used to indicate whether each instruction can be canceled.

[0060] For example, a status register with a corresponding bit width is allocated according to the total number of instructions that can be stored in the instruction pipeline. For instance, if the number of instructions that can exist in the instruction pipeline at the same time is N, then the corresponding register that stores whether the instruction can be canceled, i.e., the status register, also has a bit width (number of bits) of N.

[0061] For example, for each instruction in the instruction pipeline, the status register stores the instruction state in the first state by default, meaning that the stored instruction can be cancelled by default. The status register can be written to by each execution unit and retirement unit, and the state of the instruction stored in it can be changed according to the writing by each execution unit and retirement unit.

[0062] The above embodiments enable the processor to quickly identify whether each instruction in the instruction pipeline can be canceled when an interrupt occurs by using the instruction status stored in the status register, thereby improving the system's response efficiency and operating efficiency.

[0063] In one embodiment, after configuring the status register, each instruction in the instruction pipeline can be identified as either cancelable or non-cancellable, and the identification result (i.e., instruction status) can be written into the corresponding bit of the status register. Specifically: based on the type of each instruction in the instruction pipeline and the execution stage of each instruction, it is determined whether each instruction in the instruction pipeline can be canceled; when an instruction can be canceled, the value of the bit corresponding to the instruction in the status register is set to the first value; when an instruction cannot be canceled, the value of the bit corresponding to the instruction in the status register is set to the second value.

[0064] In this embodiment, the instruction type indicates the function type corresponding to the instruction, such as logical operation type, control flow type, data transfer type, input / output type, system-level management type, etc. The execution stage of the instruction refers to the stage in the instruction pipeline during which the instruction is executed.

[0065] For example, the instruction status can be represented by 0 or 1 in the status register. For instance, when the instruction status is in the first state, the corresponding bit in the status register is 0 (i.e., the first value), which means the instruction can be cancelled; when the instruction status is in the second state, the corresponding bit in the status register is 1 (i.e., the second value), which means the instruction cannot be cancelled.

[0066] For example, instructions such as ordinary logical operation instructions, which can be executed multiple times without affecting the processor as a whole, can be identified as cancelable instructions, and their corresponding values ​​in the status register are set to 0. For some I / O load / store instructions involving interaction with external devices, or some system instructions that require modification of processor permissions, these instructions have a greater impact on the system and can be classified as non-cancellable instructions, with their corresponding values ​​in the status register set to 1.

[0067] For example, during instruction execution in the instruction pipeline, when an instruction is non-cancellable and its execution is partially complete and cannot be cancelled, the corresponding bit in the status register is set to 1. When the instruction retires, the corresponding bit in the status register is set to 0. It should be noted that when an interrupt occurs, if an instruction has retired, whether or not it can be cancelled will not affect the interrupt response; therefore, the corresponding bit in the status register is set to 0, treating its instruction status as equivalent to that of a cancelable instruction.

[0068] For example, when the instruction is a regular logical operation instruction, the instruction unit will not operate on the corresponding status register. Since the status register defaults to the first state (i.e., the value is 0), the instruction unit will not operate on the status register, meaning the value remains 0, indicating that the logical operation instruction is cancelable. When the instruction is an I / O type load / store instruction and has started execution, the corresponding arithmetic unit will set the corresponding bit in the status register to 1, indicating that the instruction is not cancelable. When the instruction completes its retirement, the corresponding bit in the status register will be set back to 0.

[0069] For example, let's continue with the example of non-cancellable I / O load / store instructions. If the I / O load / store instruction has already started executing in the corresponding execution unit, then the execution unit will set the corresponding bit in the status register to 1, indicating that the instruction is no longer cancelable. If the I / O load / store instruction has only been assigned to the corresponding execution unit and is waiting in the queue to be executed (i.e., it has not actually been executed), then the execution unit will not set the corresponding bit in the status register at this time, and the value of that bit in the status register will remain 0 (initially the default value is 0).

[0070] For example, when an interrupt arrives, the processor prevents new instructions from entering. If the entire status register is empty (i.e., all instructions are cancelable or have been retired), then the interrupt service routine can be entered. If at least one non-cancellable instruction remains in the status register, the interrupt service routine can only be entered after that non-cancellable instruction has been retired.

[0071] In the above embodiments, the ability to cancel each instruction is determined based on its type and execution stage in the instruction pipeline. Besides the instruction type, it also takes into account that even if an instruction's type has a significant impact on the system and should be considered non-cancellable, it may not have started execution at certain stages, in which case its state should be cancelable. By combining the instruction type and its execution stage, the system can more flexibly and accurately determine the instruction's state. It can also respond promptly when a change in the execution stage leads to a change in the instruction's state, further improving the system's responsiveness.

[0072] In one embodiment, all instructions correspond one-to-one with bits in the status register. Step 220 includes: determining the instruction status of each instruction in the instruction pipeline based on the values ​​of each bit in the status register.

[0073] Specifically, for each bit in the status register, if the value is the first value, the instruction status of the corresponding instruction is determined to be the first state.

[0074] For each bit in the status register, if it takes the second value, the instruction status of the corresponding instruction is determined to be the second state; the second state indicates that the instruction cannot be canceled.

[0075] In this embodiment, "all instructions" refers to all instructions in the instruction pipeline. The processor can quickly determine whether the instruction corresponding to each bit can be canceled by checking the value of each bit in the status register, i.e., 0 or 1. For example, if the value of the first bit is 0, it means that the instruction corresponding to that bit can be canceled.

[0076] The above embodiments utilize status registers to quickly determine the instruction status of all instructions in the pipeline, further improving the timeliness of interrupt response.

[0077] In one embodiment, determining the instruction state of each instruction in the instruction pipeline includes: performing an OR operation on the values ​​of all bits in the status register to obtain a third value; and in response to the third value being a first preset value, determining that the instruction state of all instructions in the instruction pipeline is a first state.

[0078] In this embodiment, a bitwise OR operation is performed on all bits in the status register to obtain a total value that indicates whether all values ​​in the status register are 0, i.e., the third value. When all values ​​in the status register are 0, that is, when all instructions in the instruction pipeline are in the first state, the third value obtained by the OR operation is also 0, i.e., the first preset value.

[0079] For example, when an interrupt arrives, if the total value of the status register is 0, it means that all instructions in the entire instruction pipeline can be canceled. In this case, the interrupt will be responded to immediately, all instructions will stop executing, the PC will be stored as the memory address of the oldest non-retired instruction in the instruction pipeline, and the interrupt service routine will be entered according to the interrupt handling process. After the process is completed, the interrupt service routine will be returned to the previous instruction pipeline.

[0080] The above embodiment obtains a third value by performing an OR operation on all values ​​in the status register. Therefore, only one judgment is needed to determine whether all instructions can be cancelled, without having to judge each bit in the status register individually, thus further improving the timeliness of interrupt response.

[0081] In another embodiment, determining the instruction state of each instruction in the instruction pipeline includes:

[0082] The fourth value is obtained by performing an OR operation on all the bits in the status register;

[0083] In response to the fourth value being the second preset value, it is determined that among all instructions in the instruction pipeline, at least one instruction has an instruction state of the second state; wherein, the second state indicates that the instruction cannot be canceled.

[0084] In this embodiment, a bitwise OR operation is performed on all bits in the status register to obtain a total value that indicates whether there is a 1 in the status register, i.e., the fourth value. When there is at least one "1" value among all the values ​​in the status register, that is, when there is at least one instruction in the instruction pipeline whose instruction state is the second state, the fourth value obtained by the OR operation is 1, which is the second preset value.

[0085] For example, when an interrupt arrives, if the total value of the status register is 1, it means that there are non-cancellable instructions in the instruction pipeline. The interrupt will remain pending and will not be responded to immediately, waiting for the instructions to retire sequentially. Once an instruction retires, the value in the status register for that instruction is set to 0. When the total value of the status register reaches 0, meaning all non-cancellable instructions have retired, the interrupt will be responded to immediately. The remaining non-retired instructions will stop executing, the program counter (PC) will be stored as the memory address of the oldest non-retired instruction in the instruction pipeline, and the interrupt service routine will be entered according to the interrupt handling flow. After processing, the interrupt will return to the previous instruction pipeline. In some examples, the change in the total value of the status register from 1 to 0 can be determined by periodic polling; alternatively, when the total value of the status register changes from 1 to 0, a relevant command can be directly generated to notify the processor.

[0086] The above embodiment obtains the fourth value by performing an OR operation on all values ​​in the status register. This allows the determination of whether there are still instructions that cannot be canceled and have not been retired by simply judging the total value corresponding to the status register, reducing the complexity of the judgment and improving the timeliness of interrupt response.

[0087] It should be noted that the third and fourth values ​​actually refer to the total value obtained after performing an OR operation on all bits of the status register. The third and fourth values ​​are only used to distinguish the names in different implementation scenarios.

[0088] It should be noted that in the aforementioned embodiments, the value "0" in the status register represents the first state (cancellable) and "1" represents the second state (cannot be cancelled). Therefore, when calculating the total value corresponding to all bits of the status register, an OR operation is used. This way, when at least one "1" exists, the total value will be "1," indicating that at least one instruction cannot be cancelled. However, in other embodiments, a value of "0" can be set to represent the second state (cannot be cancelled) and a value of "1" to represent the first state (cancellable). In this case, when calculating the total value corresponding to all bits of the status register, an AND operation is required. This way, the total value is 1 only when all bits are 1, i.e., all instructions are in the first state. When at least one bit is 0, i.e., at least one instruction is in the second state, the total value is 0, indicating that at least one instruction cannot be cancelled. That is, in the embodiments of this application, the first and second values ​​being 0 or 1 can be set according to requirements, and other related content can be adjusted accordingly. The actual principle is the same and will not be elaborated further here.

[0089] In one embodiment, after step 220, the interrupt handling method further includes: responding to the existence of at least one instruction state in the second state among all instruction states, waiting for the instruction in the instruction pipeline in the second state to retire, canceling the execution of the remaining instructions, and executing the interrupt routine corresponding to the interrupt request. In this embodiment, when the interrupt event type of the received interrupt request is a fast interrupt type, directly canceling all instructions in the instruction pipeline to respond to the interrupt would pose a risk of system anomalies. Therefore, in the fast interrupt process, the instruction state of each instruction in the instruction pipeline is first determined. When a second state exists, i.e., an instruction that cannot be canceled exists, the execution of other cancelable instructions after the non-cancellable instruction is stopped (if there are multiple non-cancellable instructions, the execution of other cancelable instructions after the last non-cancellable instruction based on logical order is stopped), waiting for the non-cancellable instruction to retire, canceling the remaining cancelable instructions, and responding to the interrupt by executing the corresponding interrupt routine. Through the above method, both the stable operation of the system and the timeliness of interrupt response can be guaranteed.

[0090] In one embodiment, in response to an interrupt request, the execution of all instructions is canceled, and the memory address of the oldest non-retired instruction in the instruction pipeline is stored in the program counter. In this embodiment, "oldest" refers to the first instruction in the instruction pipeline arranged sequentially in the program. The memory address of the oldest non-retired instruction in the instruction pipeline is the address of the first instruction that is logically not yet completed when the interrupt service routine is executed.

[0091] In response to an interrupt request, the above embodiments cancel the execution of all instructions and store the memory address of the oldest non-retired instruction in the instruction pipeline into the program counter. This ensures that after the interrupt is handled, the processor can fetch the instruction again from this address, ensuring that the program can seamlessly resume from the breakpoint without missing or repeating instructions.

[0092] In one embodiment, the interrupt event type in the above embodiments is determined based on the interrupt type and priority of the interrupt request. In this embodiment, the interrupt type is used to indicate the event / device corresponding to the interrupt request, allowing the processor to determine which device / event initiated the interrupt based on the interrupt type. The priority is used to characterize the urgency of the interrupt request.

[0093] For example, the interrupt type can be an interrupt ID (identifier) ​​pre-assigned by the interrupt controller. When an external device or software (interrupt source) needs to trigger an interrupt, it sends the corresponding interrupt request to the interrupt controller module. The interrupt controller assigns an interrupt ID to each interrupt event and determines the priority order of the interrupt events. In some examples, the interrupt controller can determine whether the interrupt needs to configure the register to enable fast interrupts to enter the fast interrupt process based on the different interrupt priorities and IDs. That is, the interrupt controller can determine whether the interrupt event type corresponding to the interrupt is a fast interrupt or a normal interrupt based on the interrupt ID and priority of the interrupt request, and send it to the processor along with the interrupt request. In other examples, the processor can also directly determine whether the corresponding interrupt is a fast interrupt based on the interrupt ID and priority sent by the interrupt controller.

[0094] In some examples, a mapping can be constructed between the interrupt ID corresponding to the interrupt and its interrupt event type. The processor can determine whether the interrupt request is a fast interrupt type based on the interrupt ID corresponding to the received interrupt request, and then determine whether to enable the fast interrupt process.

[0095] The above embodiments determine the interrupt event type by the interrupt type and priority of the interrupt request, so that the subsequent processor can determine whether to enter the fast interrupt procedure based on the indication of the interrupt event type. This ensures that when a relatively urgent interrupt occurs, it can be responded to in a timely manner through the fast interrupt procedure, thereby improving system timeliness.

[0096] The interrupt handling method of this application will be described in general detail below through examples. It should be understood that the following embodiments are for better illustration of the interrupt handling method of this application and are not intended to limit it.

[0097] Example 1:

[0098] Figure 3 This is a schematic diagram illustrating an example of an interrupt handling process provided in this application. For example, as shown... Figure 3 As shown, when an interrupt source sends an interrupt, the interrupt controller captures it. The interrupt controller then determines, based on the interrupt ID, interrupt type, and other information, whether the corresponding interrupt event type needs to be configured as a fast interrupt. By default, the processor does not enter the fast interrupt handling process; that is, fast interrupt enable is disabled by default. When the interrupt event type is a fast interrupt and a fast interrupt process is needed for a quick response, fast interrupt enable can be enabled through the configuration register.

[0099] When fast interrupts are not enabled, when an interrupt arrives (i.e., the processor receives an interrupt request), the instructions in the instruction pipeline are paused until all instructions in the current instruction pipeline have retired, at which point the interrupt request is responded to and the interrupt service routine is entered.

[0100] With fast interrupt enabled, the processor (e.g., individual execution units) determines whether an instruction can be cancelled based on its type and the stage of execution it has reached. By default, instructions can be cancelled, meaning the corresponding bit (not_cancel bit) in the status register is 0. When the processor determines that an instruction cannot be cancelled as long as it exists in the pipeline, it sets the not_cancel bit to 1. When the processor determines that the instruction has been partially executed, but cancellation would have no impact on the system, the not_cancel bit remains 0. When the processor determines that the instruction has been partially executed and cancellation would affect the system, meaning the instruction must continue execution until retirement, the not_cancel bit is set to 1. When the instruction completes execution and retires normally, the not_cancel bit is set to 0.

[0101] Assuming all instructions in the instruction pipeline are cancelable (i.e., all bits in the status register are 0), instruction execution in the entire pipeline will stop, an interrupt will be immediately triggered, and the program counter (PC) will be saved as the address of the oldest non-retired instruction in the current pipeline. The system will enter the interrupt service routine, complete the interrupt event, exit the interrupt service routine, and then re-execute the instruction at the address saved by the PC.

[0102] Suppose that among all instructions in the instruction pipeline, there is an instruction that cannot be canceled, meaning that at least one bit of the not_cancel register is set to 1. An interrupt can only be responded to after this non-cancelable instruction and all instructions preceding it have been submitted for retirement. Once this non-cancelable instruction and all instructions preceding it have been submitted for retirement, execution of the remaining instructions stops, the program counter (PC) is saved as the address of the instruction following the latest non-cancelable instruction, the interrupt service routine is entered, and after exiting the interrupt service routine, the instruction at the address saved by the PC is re-executed.

[0103] In the example above, upon receiving an interrupt request, the interrupt event type corresponding to the interrupt request is identified. If the interrupt event type is a fast interrupt, a fast interrupt procedure is triggered. In the fast interrupt procedure, the instruction state of each instruction in the instruction pipeline is identified. When the instruction state of all instructions is in the first state, it is determined that all instructions in the instruction pipeline can be cancelled, thus cancelling the execution of all instructions and directly responding to the interrupt request to execute the interrupt routine. This achieves immediate interrupt response and execution of the interrupt routine without waiting for all instructions in the instruction pipeline to retire, improving the timeliness of interrupt response and enhancing system real-time performance.

[0104] Example 2:

[0105] By using the interrupt handling methods provided in the above embodiments of this application, and by classifying instructions into cancelable and non-cancellable instructions, users can distinguish which instructions can be canceled according to their needs and interrupt priorities. When the interrupt event type corresponding to the interrupt request is a fast interrupt type, if all instructions in the instruction pipeline are cancelable, the interrupt can be responded to and the interrupt service routine can be entered without completely emptying the instruction pipeline.

[0106] For example, Figure 4 This is a comparative illustration of a first scenario provided as an example of this application, showing the difference between enabling fast interrupts (left) and disabling fast interrupts (right). Figure 4 As shown, assuming there are a total of 32 instructions in the instruction pipeline, the cancelability register (i.e., the status register) is also 32 bits. In the first scenario, it is assumed that all 32 instructions in the instruction pipeline can be canceled, that is, the value of each bit in the cancelability register is 0, and none of the instructions have been retired (as shown in the "Instruction Retirement Status" column, all are "N", where "N" represents no).

[0107] When an interrupt arrives, that is, when the processor receives an interrupt request, if fast interrupt procedure is enabled, since all instructions can be canceled and the processor directly enters the interrupt service routine, the interrupt service routine can be entered at time t0. Figure 4 The table on the left shows the highlighted text in gray. If fast interrupts are not enabled, it's necessary to wait until all instructions in the instruction pipeline retire. Since the last instruction, 31, has not yet retired at time t31, it's necessary to wait until it retires, i.e., at time t32, before entering the interrupt service routine. Figure 4 The table on the right is highlighted in gray.

[0108] In summary, enabling the fast interrupt procedure saves Δt = (t32 - t0) time in entering the interrupt service compared to not enabling fast interrupt.

[0109] For example, Figure 5 This is a comparative illustration of a second scenario provided as an example of this application, showing the difference between enabling fast interrupts (left) and disabling fast interrupts (right). Figure 5 As shown, assuming there are a total of 32 instructions in the instruction pipeline, the cancelability register (i.e., the status register) also has 32 bits. In the second scenario, consider another extreme case: the last instruction in the instruction pipeline is non-cancellable, meaning the last bit in the cancelability register is 1, and all instructions are not retired (as shown in the "Instruction Retirement Status" column, all are "N", where "N" represents no), while any of the other instructions in between are in any state.

[0110] When an interrupt arrives, that is, when the processor receives an interrupt request, if the fast interrupt procedure is enabled, due to the presence of non-cancellable instructions, the interrupt can only be responded to after all non-cancellable instructions and all preceding instructions have been committed and retired. In other words, the time to enter the interrupt service routine is at time t32. Figure 5 The table on the left shows the highlighted text in gray. If fast interrupts are not enabled, the interrupt service routine cannot be entered until all instructions in the instruction pipeline retire, i.e., at time t32. Figure 5 The table on the right is highlighted in gray.

[0111] Figure 4 and Figure 5 For two extreme scenarios, Figure 4 and Figure 5 From the examples, it can be concluded that by adopting the interrupt handling methods of the above embodiments of this application, entering the interrupt service routine can save 0~(tn-t0) time compared with related technologies, where n refers to the total number of instructions that can exist in the instruction pipeline.

[0112] It should be noted that, Figure 5 This is merely an extreme scenario example illustrating the minimum time threshold that can be saved by adopting the method of this application, and is not a specific limitation; given the randomness of the instructions and mathematical statistics, Figure 5 The scenario shown has an extremely low probability of occurring.

[0113] The comparison between enabling and disabling the fast interrupt procedure in the above examples confirms that the interrupt handling method of this application can indeed reduce the time to enter the interrupt service routine, improve the timeliness of interrupt response, and improve the real-time performance of the system.

[0114] One embodiment of this application also provides a chip, which includes a processor and a data interface. The processor reads instructions stored in a memory through the data interface and executes the interrupt handling method provided in any of the above embodiments.

[0115] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. For example... Figure 6 As shown, the electronic device 2000 includes a memory 2100 and a processor 2200. The number of memory 2100 and processor 2200 can be one or more. Figure 6 Taking a memory 2101 and a processor 2201 as an example; the memory 2101 and processor 2201 in the network device can be connected via a bus or other means. Figure 6 Taking the example of a connection between China and Israel via a bus.

[0116] The memory 2101, as a computer-readable storage medium, can be used to store software programs, computer-executable programs, and modules, such as program instructions / modules corresponding to the methods provided in any embodiment of this application. The processor 2201 implements the interrupt handling method provided in any of the above embodiments by running the software programs, instructions, and modules stored in the memory 2101.

[0117] Memory 2101 may primarily include a program storage area and a data storage area, wherein the program storage area may store the operating system and application programs required for at least one function. Furthermore, memory 2101 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some instances, memory 2101 further includes memory remotely located relative to processor 2201, and this remote memory can be connected to the device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0118] One embodiment of this application also provides a computer-readable storage medium storing computer-executable instructions for performing an interrupt handling method as provided in any embodiment of this application.

[0119] An embodiment of this application also provides a computer program product, including a computer program or computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer program or computer instructions from the computer-readable storage medium and executes the computer program or computer instructions, causing the computer device to perform an interrupt handling method as provided in any embodiment of this application.

[0120] The system architecture and application scenarios described in this application are intended to more clearly illustrate the technical solutions of this application and do not constitute a limitation on the technical solutions provided in this application. Those skilled in the art will understand that as system architectures evolve and new application scenarios emerge, the technical solutions provided in this application are also applicable to similar technical problems.

[0121] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or appropriate combinations thereof.

[0122] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0123] The terms “component,” “module,” “system,” etc., used in this specification are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, or a computer. As illustrated, applications running on computing devices and computing devices can both be components. One or more components may reside in a process or execution thread, and components may be located on a single computer or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, or a network, such as the Internet interacting with other systems via signals).

[0124] The above description, with reference to the accompanying drawings, illustrates some embodiments of this application, but does not limit the scope of this application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and spirit of this application shall be within the scope of this application.

Claims

1. An interrupt handling method, characterized in that, The method includes: An interrupt request has been received; In response to the interrupt event type corresponding to the interrupt request being a fast interrupt type, the instruction status of each instruction in the instruction pipeline is determined. In response to all of the instruction states being in the first state, the execution of all the instructions is cancelled, and the interrupt routine corresponding to the interrupt request is executed, wherein the first state indicates that the instruction can be cancelled; In response to the existence of at least one instruction state in the second state among all the instruction states, after waiting for the instruction in the instruction pipeline in the second state to retire, the execution of the remaining instructions is cancelled, and the interrupt routine corresponding to the interrupt request is executed. The second state indicates that the instruction cannot be cancelled.

2. The interrupt handling method according to claim 1, characterized in that, All the aforementioned instructions correspond one-to-one with the bits in the status register, and determining the instruction status of each instruction in the instruction pipeline includes: The instruction status of each instruction in the instruction pipeline is determined based on the value of each bit in the status register.

3. The interrupt handling method according to claim 2, characterized in that, Determining the instruction state of each instruction in the instruction pipeline based on the values ​​of each bit in the status register includes: For each bit in the status register, if the value is the first value, the instruction status of the corresponding instruction is determined to be the first status.

4. The interrupt handling method according to claim 2, characterized in that, Determining the instruction state of each instruction in the instruction pipeline based on the values ​​of each bit in the status register includes: For each bit in the status register, if it takes the second value, the instruction status of the corresponding instruction is determined to be the second state.

5. The interrupt handling method according to claim 2, characterized in that, Determining the instruction state of each instruction in the instruction pipeline includes: A third value is obtained by performing an OR operation on the values ​​of all the bits in the status register; In response to the third value being the first preset value, it is determined that the instruction state of all instructions in the instruction pipeline is the first state.

6. The interrupt handling method according to claim 2, characterized in that, Determining the instruction state of each instruction in the instruction pipeline includes: The fourth value is obtained by performing an OR operation on all the bits in the status register; In response to the fourth value being the second preset value, it is determined that among all the instructions in the instruction pipeline, at least one instruction has an instruction state of the second state; wherein the second state indicates that the instruction cannot be cancelled.

7. The interrupt handling method according to claim 1, characterized in that, All the aforementioned instructions correspond one-to-one with the bits in the status register, and the method further includes: Based on the type of each instruction in the instruction pipeline and the execution stage of each instruction, determine whether each instruction in the instruction pipeline can be cancelled; When the instruction can be cancelled, the value of the bit corresponding to the instruction in the status register is set to the first value; If the instruction cannot be cancelled, the value of the bit corresponding to the instruction in the status register is set to the second value.

8. The interrupt handling method according to claim 1, characterized in that, The interrupt event type is determined based on the interrupt type and priority of the interrupt request.

9. The interrupt handling method according to claim 1, characterized in that, The method further includes: If the interrupt event type corresponding to the interrupt request is a normal interrupt type, the interrupt routine corresponding to the interrupt request will be executed after all the instructions in the instruction pipeline have retired.

10. The interrupt handling method according to claim 1, characterized in that, The method further includes: Store the memory address of the oldest non-retired instruction in the instruction pipeline into the program counter.

11. A chip, characterized in that, The chip includes a processor and a data interface. The processor reads instructions stored in the memory through the data interface and executes the method as described in any one of claims 1 to 10.

12. An electronic device, characterized in that, include: At least one processor; At least one memory for storing at least one program; The method as described in any one of claims 1 to 10 is implemented when at least one of the programs is executed by at least one of the processors.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions for performing the method as described in any one of claims 1 to 10.

14. A computer program product, comprising a computer program or computer instructions, characterized in that, The computer program or the computer instructions are stored in a computer-readable storage medium, and the processor of the computer device reads the computer program or the computer instructions from the computer-readable storage medium. The processor executes the computer program or the computer instructions, causing the computer device to perform the method as described in any one of claims 1 to 10.

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