Managing data placement in memory subsystem

Abstract

The invention relates to managing data placement in a memory subsystem. A system includes a memory device and a memory subsystem controller operably coupled with the memory device, the memory subsystem controller to perform operations including: receiving a memory access command having one or more associated parameters from a host system; determining, using a hardware component of the memory subsystem controller, whether the one or more associated parameters conform to a current flexible data placement (FDP) configuration of the system; and in response to determining that the one or more associated parameters conform to the current FDP configuration of the system, executing the memory access command on an identified segment of the memory device.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to a memory subsystem, and more specifically, to managing the placement of data within a memory subsystem. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, the host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] According to one aspect of this disclosure, a system is provided. The system includes: a memory device; and a memory subsystem controller operatively coupled to the memory device, the memory subsystem controller being configured to perform operations including: receiving a memory access command from a host system having one or more associated parameters; determining, using hardware components of the memory subsystem controller, whether the one or more associated parameters conform to a current Flexible Data Placement (FDP) configuration of the system; and, in response to determining that the one or more associated parameters conform to the current FDP configuration of the system, executing the memory access command on an identified segment of the memory device.

[0004] According to another aspect of this disclosure, a method is provided. The method includes: receiving a memory access command having one or more associated parameters from a host system at a memory subsystem; determining, using hardware components of a memory subsystem controller of the memory subsystem, whether the one or more associated parameters conform to a current Flexible Data Placement (FDP) configuration of the memory subsystem; and, in response to determining that the one or more associated parameters conform to the current FDP configuration of the memory subsystem, executing the memory access command on an identified segment of a memory device in the memory subsystem.

[0005] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is provided. The non-transitory computer-readable storage medium stores instructions, when executed by a processing device, to cause the processing device to perform operations including: receiving a memory access command having one or more associated parameters from a host system at a memory subsystem; determining, using hardware components of a memory subsystem controller of the memory subsystem, whether the one or more associated parameters conform to the current Flexible Data Placement (FDP) configuration of the memory subsystem; and, in response to determining that the one or more associated parameters conform to the current FDP configuration of the memory subsystem, executing the memory access command on an identified segment of a memory device in the memory subsystem. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are merely for explanation and understanding.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This describes an instance virtualization internal management component included in a memory subsystem according to some embodiments of the present disclosure.

[0009] Figure 3 This is a diagram illustrating different instances of FDP configurations that can be implemented by a memory subsystem controller according to some embodiments of the present disclosure.

[0010] Figure 4 This is a flowchart illustrating an example of a method for implementing a data placement in a memory subsystem according to some embodiments of the present disclosure.

[0011] Figure 5 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0012] This disclosure relates to aspects of managing data placement in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components such as memory devices for storing data. The host system can provide data stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0013] The memory subsystem may include high-density non-volatile memory devices where it is desirable to retain data when no power is supplied to the memory device. An example of a non-volatile memory device is a NAND flash memory device. (The following section combines...) Figure 1Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die contains one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane contains a set of physical blocks. Each block contains a set of pages. Each page contains a set of memory cells. A memory cell is an electronic circuit that stores information. Depending on the type of memory cell, a memory cell may store one or more bits of binary information and has various logic states related to the number of bits stored. Logic states may be represented by binary values ​​such as "0" and "1" or combinations of such values.

[0014] Memory access operations can be performed by the memory subsystem. These operations can be host-initiated. For example, the host system can initiate memory access operations (e.g., write, read, erase, etc.) on the memory subsystem. The host system can send memory access commands (e.g., write commands, read commands) to the memory subsystem, for example, to store data in and / or read data from the memory devices of the memory subsystem. The memory subsystem controller can receive memory access commands from a host system externally connected to the memory subsystem, for example, via a Non-Volatile Memory Fast (NVMe) interface on the Peripheral Component Interconnect Fast (PCIe) communication bus. The memory subsystem can execute the memory access commands to perform the memory access operation and return the result of executing the memory access commands to the host system via the host interface.

[0015] The host system uses a logical address space to access memory devices. A logical address space identifies logical units, such as logical blocks. For some types of memory devices, a logical block is the smallest unit of write / read. For example, depending on the specifications of the memory device, the size of data in a logical block can be 512 bytes, 4096 bytes (4KB), etc. In some memory devices, a logical block can be a group of logical pages. A logical page is an abstraction of a physical page. The memory subsystem can define a logical page as a specific unit equal to a physical storage device (e.g., a physical page, a physical block, etc.). The logical block address (LBA) is the identifier of a logical block. In the logical block addressing scheme, integer indices are used to locate logical blocks, where the first block is LBA 0, the second block is LBA 1, and so on.

[0016] Translation units (TUs) can be used to manage logical address spaces. For some memory devices, a TU is the basic granularity of data managed by the memory device. A TU can contain a predefined number of logical units (e.g., logical pages, logical blocks, etc.). In some instances, a TU is predefined to contain a single logical block, so the size of the TU is equal to the size of the logical block. In some instances, a TU is predefined to contain multiple logical blocks. In that case, the size of the TU is a multiple of the size of the logical blocks.

[0017] In one instance, a TU can be predefined as containing a 512-byte logical block, so the size of the TU is 512 bytes. In another instance, a TU can be predefined as containing a 4KB logical block, so the size of the TU is 4KB. In yet another instance, a TU can be predefined as containing eight 512-byte logical blocks, for a total size of (8*512) bytes or 4096 bytes (4KB). In the previous instance, the size of the TU was 4KB. Several TUs (e.g., TUs of size 4KB) can be used to divide the logical address space, where each TU can contain eight logical blocks. In one addressing scheme for TUs, integer indices can be used to locate TUs, where the first TU is TU0, the second TU is TU1, and so on. In the example, TU0 can contain eight LBAs starting at LBA 0 and ending at LBA 7. TU1 can contain the next eight LBAs starting at LBA 8 and ending at LBA 15, and so on. The start and end addresses of logical units (e.g., logical blocks, logical pages, etc.) define the boundaries of a TU.

[0018] When the host system requests access to data (e.g., to read or write data), it can send a memory access command to the memory device pointing to a logical address space. For example, the host system can provide logical address information (e.g., logical block address (LBA), namespace) that identifies the location where data will be stored or read. Since the data from the host system will ultimately be stored at a physical address within the memory device, the memory subsystem controller can translate the logical address information into a corresponding TU. The memory subsystem controller maintains a logic-to-physical (L2P) translation map or table to identify the physical location where data corresponding to each logical address resides. The L2P table may contain several L2P entries. Each entry in the L2P table identifies the physical location corresponding to a specific TU. The L2P table tracks the TUs by maintaining the physical addresses that have been written to each TU in the memory device. For example, an L2P entry may contain an index of the TU (e.g., TU 0, TU 1, etc.), a corresponding range of physical addresses, and some metadata (e.g., a flag indicating whether the data at the address is valid or invalid). The L2P table may be maintained by the firmware of the memory subsystem controller and stored on one or more non-volatile memory devices of the memory subsystem. The L2P table may be cached at least partially by one or more volatile memory devices of the memory subsystem.

[0019] In some memory devices, the logical address space of the memory device is divided into namespaces that allow for more efficient data management. Each namespace can map to multiple logical blocks. For example, one or more LBAs can map to a specific namespace. Each namespace can be referenced using a namespace identifier. Each namespace can contain namespace data structures (e.g., tables) that are created, updated, or deleted, for example, using namespace management and namespace attachment commands defined by the NVMeTPAR-4146 specification. Namespace data structures can indicate capabilities and settings specific to a particular namespace.

[0020] The memory subsystem can present one or more physical functions to the host system via a PCIe interface. A physical function can represent a partitioned portion of the memory subsystem associated with a given host system. Multiple physical functions can be used to partition the memory subsystem into multiple parts. In some systems, the memory subsystem utilizes specifications that allow the isolation of PCIe resources among various hardware functions for manageability and performance reasons, while also allowing the sharing of a single physical PCIe device in a virtual environment. Physical functions allow for the enumeration of several virtual functions. The host system can then assign those virtual functions to one or more virtual machines running on the host system via a hypervisor. Therefore, this virtual environment abstracts physical components into logical objects to allow various software modules, such as, for example, multiple operating systems, to run concurrently and in isolation from other software modules on one or more interconnected physical computer systems. Nevertheless, in a virtual environment, some media management is required to better present the performance of the memory subsystem.

[0021] For example, the memory subsystem controller can perform media management operations, such as wear leveling, flushing, obsolete collection, and wiping, on blocks containing some pages with valid data and the remaining pages with invalid data. To avoid waiting for a threshold number of pages in a block to contain invalid data before erasing and reusing the block, the memory subsystem controller can perform obsolete collection to allow the block to be erased and released as a free block for subsequent write operations. Obsolete collection is the process of restoring free space by relocating pages with data to a new block and erasing the old block. Specifically, a block may contain valid data pages and data pages that are no longer needed (e.g., obsolete pages). Obsolete collection typically involves copying only valid data pages from the source block to the destination block and then erasing the source block to free up space. Thus, the number of blocks that have been erased can be increased, making more blocks available for storing subsequent data from the host system. This additional rewriting of valid data in a data block during obsolete collection can cause write amplification. Write amplification manifests as a multiple of the amount of physical data to be written to the storage medium compared to the amount of logical data manipulated by the host. Write amplification can reduce the operational lifespan of a memory subsystem and affect its performance.

[0022] In a virtual environment, the collection and write amplification of obsolete items can cause data associated with a virtual machine to be scattered across multiple blocks, resulting in data from different virtual machines being mixed together. For example, this data placement dispersion can adversely affect the performance and quality of service (QoS) of the memory devices associated with the virtual machine (e.g., bandwidth, operations per second (IOPS)).

[0023] Flexible Data Placement (FDP) is a set of NVM commands defined by the NVMe TPAR-4146 specification. FDP can be used to reduce write amplification. Specifically, FDP enables host-booted data placement to allow data to be referenced by a specific placement identifier, which in turn points to a Reclaimable Unit (RU). An RU is a unit of physical non-volatile storage that can be programmed, read, erased, reused, and / or recycled without interfering with each other. The specific placement identifier pointing to an RU may contain a Reclaimable Unit Handle (RUH). The host system can use the RUH to mark write commands to identify the RU to which the data specified in the write command should be written.

[0024] The firmware component of the memory subsystem controller can create multiple namespaces by allocating a set of superblocks (e.g., reclaim groups) to each namespace and assigning corresponding handles (e.g., reclaim unit handles) to each namespace. Since a superblock is a physically isolated portion of a memory device, namespaces mapped to superblocks provide physically isolated data placement for virtual machines. When the firmware component receives a command from a virtual machine running on the host system to perform a write operation associated with a namespace, the firmware component can identify segments of the memory device based on the handles assigned to the namespaces and perform operations on those segments.

[0025] In some devices, one or more RUs can form a reclamation group (RG), where RG corresponds to a namespace. Thus, an RU can be an addressable data storage unit containing a predefined number of smaller addressable data storage units of a lower order than RG, and therefore RG can refer to a higher-order data storage unit, while RU can refer to a lower-order data storage unit. In some instances, an RU can have a predefined number of block granularities and can be a superblock, and an RG can be a set of superblocks containing a predefined number of RUs. For example, an RU can be a single superblock, and an RG can be a set of superblocks containing one available superblock from each plane on a set of dies of the memory device. Each superblock can be located on a separate plane having independent circuitry that allows parallel operation on the set of superblocks. RGs can be physically isolated from each other to minimize performance interference. For example, a first RG is allocated in a first set of dies (e.g., dies 1 to dies 8), and a second RG is allocated in a second set of dies (e.g., dies 9 to dies 16), where the first and second sets of dies are physically isolated from each other.

[0026] In some memory subsystems, the firmware component of the memory subsystem controller can receive and process requests to create namespaces. Therefore, the memory subsystem controller can create namespaces by assigning RGs to them. Specifically, the memory subsystem controller can assign RGs by selecting a set of RUs, where the number of RUs in the set is predetermined (e.g., has a default value) or determined when the virtual machine is created. After the memory subsystem controller creates one or more namespaces, it can assign a RUH to each namespace. An RUH is unique for a given namespace, and a given namespace can only have one RUH. Although RUHs are used here, other forms of handles, tags, etc., can be used instead of RUHs to reference namespaces. The memory subsystem controller can store the RUHs assigned to a namespace, the namespace identifier, the set of RUs, and / or the assignments between RGs in a data structure. The memory subsystem controller can use the identifier of the RUH to identify a set of RUs in the RGs assigned to a given namespace. This identifier may be referred to as a Placement Handle Identifier (PHI).

[0027] When a virtual machine sends a request to the memory subsystem controller to perform a memory access operation associated with a namespace, the firmware component of the memory subsystem controller can use the PHI included in the request to identify the RUH, where the RUH can be further used to identify the RG. The memory subsystem controller can then perform the requested memory access operation on the identified RG. However, by having the firmware component determine the corresponding RG associated with the PHI for each memory access command received from the host system, system performance may be impacted due to the increased time and resource consumption typically required by the memory subsystem to process and execute memory access commands.

[0028] This disclosure addresses the aforementioned and other shortcomings by using hardware components (e.g., hardware automation components) of the memory subsystem controller to manage data placement within the memory subsystem. Instead of having the firmware components determine the corresponding RG associated with the PHI for each memory access command received from the host system, the determination of the corresponding RG associated with the PHI can be automated by hardware components (e.g., hardware automation components). This improves system performance by automating the determination of the corresponding RG associated with the PHI for each memory access command without involving the firmware. Furthermore, FDP can provide several different configurations for various parameters of the memory subsystem, which can be selected by the host system according to a specific implementation. For example, each configuration may include different combinations of the maximum number of namespaces supported in FDP mode (i.e., NS_max), the maximum number of placement handle identifiers supported in FDP mode (i.e., PHI_max), and the maximum number of reclamation groups supported in FDP mode (i.e., RG_max). The storage provided by the memory subsystem may have practical limitations, such that increasing one parameter may require decreasing another. Therefore, the host system can influence the configuration of the memory subsystem in FDP mode to best suit its needs. Upon receiving a memory access request, the hardware automation component can ensure that the request conforms to the selected configuration, and if so, process the request accordingly. If the memory access request does not conform to the selected configuration, the hardware automation component can pass the request to the memory subsystem controller firmware, which can modify the request as needed.

[0029] By automating the determination of the corresponding RG associated with PHI by the hardware components of the memory subsystem controller, the advantages of this disclosure include improved performance through reduced write amplification and improved memory device system performance. Furthermore, the configurability of the memory subsystem parameters for FDP mode improves the quality of service of the host system.

[0030] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0031] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0032] The computing system 100 may be a computing device such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transportation), device with Internet of Things (IoT) capability, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked commercial device), or such computing device containing memory and processing device.

[0033] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediary component), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0034] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110 to, for example, write data to and read data from memory subsystem 110. Host system 120 may include one or more commit queues 123A to 123N. Each commit queue 123A to 123N may be a data structure (e.g., a table) with one or more entries, where each entry stores a memory access command. Host system 120 may include one or more completion queues 121A to 121N. Each completion queue 121A to 121N may be a data structure (e.g., a table) with one or more entries, where each entry stores a notification of completion of the execution of a memory access command. One or more submission queues 123A to 123N and / or one or more completion queues 121A to 121N may be coupled to host system 120 and / or otherwise accessible to host system 120.

[0035] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect Fast (PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Double Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), and Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM slot interfaces supporting Double Data Rate (DDR)). The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM Fast (NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Typically, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or combinations of communication connections.

[0036] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (such as memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0037] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-situ write memory, such as a three-dimensional cross-point (“3D cross-point”) memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory cells can perform bit storage based on volume resistance variations combined with a stackable cross-grid data access array. Furthermore, in contrast to many flash memory-based memories, cross-point non-volatile memory can perform in-situ write operations, whereby the non-volatile memory cells can be programmed without previously erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0038] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell (e.g., a single-level memory cell (SLC)) may store one bit per memory cell. Other types of memory cells, such as multi-level memory cells (MLC), three-level memory cells (TLC), four-level memory cells (QLC), and five-level cells (PLC), may store multiple bits per memory cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include SLC portions and MLC portions, TLC portions, QLC portions, or PLC portions of memory cells. The memory cells of the memory device 130 may be grouped into pages, where a page may refer to a logical unit of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0039] Although non-volatile memory components such as 3D cross-point arrays of non-volatile memory cells and NAND flash memories (e.g., 2D NAND, 3D NAND) have been described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0040] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0041] The memory subsystem controller 115 may include processing means configured to execute instructions stored in local memory 119, which includes one or more processors (e.g., processor 117). In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0042] In some embodiments, local memory 119 may include memory registers storing memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although already... Figure 1 The instance memory subsystem 110 is described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0043] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to implement desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, discarded item collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions for accessing the memory device 130 and translate responses associated with the memory device 130 into information for the host system 120.

[0044] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0045] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 130 is a managed memory device, which is the original memory device 130 having on-die control logic (e.g., local controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0046] According to embodiments of this disclosure, a memory subsystem 110 includes a data placement management component 113 for implementing management of data placement within the memory subsystem. The data placement management component 113 may include a firmware component 113a and a hardware component 113b. The hardware component 113b may be a circuitry of a memory subsystem controller 115 for transmitting and receiving data to and from memory devices 130, 140 of the memory subsystem 110. The firmware component 113a may be firmware of the memory subsystem controller 115 that provides some control to the hardware component 113b of the memory subsystem controller 115. In some embodiments, the memory subsystem controller 115 includes at least a portion of the data placement management component 113. In some embodiments, the data placement management component 113 is part of a host system 120, an application, or an operating system. In other embodiments, a local media controller 135 includes at least a portion of the data placement management component 113 and is configured to perform the functionality described herein. References are made herein. Figures 2 to 5 This describes further details regarding the implementation of command completion notification pacing in the managed memory subsystem.

[0047] Those skilled in the art should understand that additional circuitry and signals can be provided, and that the process has been simplified. Figure 1 Components. It should be recognized that references... Figure 1 The functionality of the various block components described need not be separated into different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 1 The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1 The functionality of a single block component.

[0048] Figure 2This description illustrates virtualization internal management components in a memory subsystem according to some embodiments of this disclosure. System 200 may include a host system 120, one or more memory devices (not shown), and a controller 115 operatively coupled to the memory devices. In one embodiment, the controller 115 of the memory subsystem 110 is connected to the host system 120 via a physical host interface (e.g., PCIe bus 210). The controller 115 may expose different portions of the memory devices to virtual machines using various techniques, including Single Root Input / Output Virtualization (SrIOV), Multiple Physical Functions (MPF), and Scalable I / O Virtualization (sIOV or Scalable IOV). Using these techniques, the controller 115 may present two or more Physical or Virtual Functions (PF / VF) or Assignable Device Interfaces (ADI) to the host system 120 via interconnects (e.g., PCIe interfaces). The host system 120 may assign each of the PF / VF / ADI to an individual application, virtual machine, or the like. The host system 120 may request several PF / VF / ADIs as needed. In some embodiments, each of PF / VF / ADI corresponds to a virtual memory controller associated with a different portion of the memory device.

[0049] For example, controller 115 can manage several physical functions (PFs). A physical function is a full-featured PCIe function that can be discovered, managed, and manipulated like any other PCIe device, and is therefore used to configure and control PCIe devices. Each physical function is a PCIe function that supports virtualization capabilities, and therefore each physical function can allow enumeration of several virtual functions (VFs). Controller 115 can also manage virtual functions, virtual controllers, or the like to present themselves as physical functions and physical controllers to other devices, such as host system 120, connected to the PCIe bus 210 via physical functions. A virtual function can be a lightweight PCIe function that shares one or more resources with a physical function and the virtual functions associated with said physical function. For example, the PCI configuration space of each virtual function can be accessed via the physical function's bus, device, and function (BDF) number. Each virtual function can have a PCI memory space used to map its register set. The virtual function device driver operates on the register set to enable its functionality, and the virtual function behaves as an actual PCIe device that can be accessed by the host system 120 via the PCIe bus 210.

[0050] Controller 115 can create a set of namespaces by assigning physically separate memory segments to different namespaces. In other words, namespaces are created such that operations performed on namespaces will interfere with each other to a minimum. In some implementations, reclaimable units (RUs) in Flexible Data Placement (FDP) are used. An RU is a unit of a physically non-volatile memory device that can be programmed, read, erased, reused, or recycled without interfering with each other. Specifically, controller 115 can select a set of RUs for each namespace to form a reclamation group (RG) and map the RG to the namespace. For example, a first set of RUs is located in die 1, and a second set of RUs is located in die 2; controller 115 can select the first set of RUs to form a first RG and map the first RG to namespace 1, and controller 115 can select the second set of RUs to form a second RG and map the second RG to namespace 2. In some embodiments, the number of namespaces can be pre-configured at manufacturing time based on offline testing and media characterization of the memory device. In some embodiments, the number of sets of RUs that can be mapped to namespaces can be pre-configured at manufacturing time based on offline testing and media characterization of the memory device.

[0051] After controller 115 creates one or more namespaces, controller 115 may assign a recycling unit handle (RUH) to each namespace. The RUH can be used to point to an RG mapped to the namespace, thereby pointing to a set of RUs within the RG. The RUH is unique for a given namespace, and a given namespace can only have one RUH. Although RUHs are used here, other forms of handles, tags, etc., can be used instead of RUHs. For example, a cursor identifier can be used for referencing functions.

[0052] In some embodiments, controller 115 may store the assignment of RUHs to namespaces (e.g., identified by Placement Handle Identifiers (PHIs)) in a data structure. The data structure may also contain a mapping of each RU or a set of RUs to a specific PHI. In some embodiments, the data structure contains one or more entries containing a PHI, a RUH, a set of RUs (e.g., identified by physical addresses), an RG (e.g., identified by physical addresses), an RU granularity (e.g., represented by size), and the size of the RG. An RUH may be used to identify the namespace to which it is assigned. A PHI may be used to identify a specific set of RUs to which a namespace is mapped. An RU granularity may identify the size of an RU. In some embodiments, each namespace may have an RU granularity of a different size than another namespace. In some embodiments, each namespace may have an RU granularity of the same size as another namespace or every namespace. The size of the RG may represent the memory size provided by the namespace. In some embodiments, the size of the RG may be up to the drive capacity of the memory device. In some embodiments, the size of the RG is defined by the host system of the memory subsystem. In some embodiments, the size of the RG is pre-configured at manufacturing time based on offline testing and media characterization of the memory device. The set of RUs can be used to identify segments of a memory device for performing operations. Specifically, controller 115 can retrieve RUHs corresponding to a specific PHI (e.g., from entries in a data structure). For example, controller 115 can identify entries in a data structure that store a specific PHI, and in response to identifying an entry storing a specific PHI, controller 115 can identify the corresponding RUH stored in the entry. In response to identifying the corresponding RUH stored in the entry, controller 115 can identify a set of corresponding RUs and / or RGs including the set of RUs stored in the entry. Controller 115 can perform operations at the physical addresses located by the set of RUs and / or RGs.

[0053] In one embodiment, the FDP configuration implemented by controller 115 can be configured via negotiation with host system 120. For example, host system 120 can specify a particular configuration to be implemented by controller 115, wherein each configuration may include different combinations of parameter values. Figure 3Figure 300 illustrates different instances of FDP configurations that can be implemented by controller 115 according to some embodiments of this disclosure. In the illustrated embodiments, parameters include the maximum number of namespaces supported in FDP mode (i.e., NS_max), the maximum number of reclamation groups supported in FDP mode (i.e., RG_max), and the maximum number of placement handle identifiers supported in FDP mode (i.e., PHI_max). Storage provided by the memory subsystem may have practical limitations, such that if one parameter is increased, another parameter may need to be decreased. Note that in Figure 300, parameter values ​​all start from zero (i.e., a value of 0 represents 1, a value of 15 represents 16, etc.). For example, if host system 120 requests a maximum number of namespaces of 256, then there are options to either set the maximum number of reclamation groups to 1 and the maximum number of placement handle identifiers to 8 (i.e., FDP configuration 1), or set the maximum number of reclamation groups to 2 and the maximum number of placement handle identifiers to 4 (i.e., FDP configuration 2). Similarly, if the host system 120 requests a maximum of 8 namespaces, then the following options exist: make the maximum number of reclaim groups 8 and the maximum number of place handle identifiers 32 (i.e., FDP configuration 15), make the maximum number of reclaim groups 16 and the maximum number of place handle identifiers 16 (i.e., FDP configuration 16), or make the maximum number of reclaim groups 32 and the maximum number of place handle identifiers 8 (i.e., FDP configuration 17).

[0054] Refer again Figure 2 Once the FDP configuration is set, controller 115 can receive commands (e.g., data access requests) from host system 120 via PCIe bus 210, including requests to read, write, or erase data in a portion of a memory device (e.g., memory device 130). The commands may (e.g., using PHI) specify the namespace in which the read, write, or erase operations will be performed. In response to the command received by controller 115 from host system 120, data placement management component 113 (e.g., hardware component) can identify the RUH assigned to the namespace specified by the command. The RUH can be used to point to an RG mapped to the namespace, thereby pointing to a set of RUs within the RG namespace. Data placement management component 113 can use the RUH to identify the RG, and the RG represents a segment of the memory device in which the write, read, or erase operations will be performed.

[0055] The controller 115 can perform operations specified by commands on segments of the memory device. In some embodiments, the controller 115 can identify a specific RU within the RG to perform an operation. For example, the controller 115 can identify a specific RU as the last write location in the RG and continue writing on that specific RU to perform a write operation.

[0056] like Figure 2 In the example shown, controller 115 creates namespace 1 by assigning reclaim group 1, where reclaim group 1 contains reclaim units 202-1, 202-2, ... 202-x; controller 115 creates namespace 2 by assigning reclaim group 2, where reclaim group 2 contains reclaim units 204-1, 204-2, ... 204-y; controller 115 creates namespace n by assigning reclaim group n, where reclaim group n contains reclaim units 206-1, 206-2, ... 206-z. Controller 115 assigns RUH 1 to namespace 1, RUH 2 to namespace 2, and RUH n to namespace n. Controller 115 can receive commands from host system 120 via PCIe bus 210 to write data to a portion of a memory device, wherein the commands can specify namespace 1, and data placement management component 113 can identify RUH 1 assigned to namespace 1, where RUH 1 points to reclaim group 1. The controller can determine a specific location in reclaim group 1 to write the data specified in the command. Similarly, the controller 115 can receive a command from the host system 120 via the PCIe bus 210 to write data to a portion of the memory device, wherein the command can specify namespace 2, and the data placement management component 113 can identify RUH 2 assigned to namespace 2, wherein RUH 2 points to reclaim group 2.

[0057] Figure 4 This is a flowchart illustrating an example method 400 for placing data in a memory subsystem according to some embodiments of the present disclosure. Method 400 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1 The data placement management component 113 executes. Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0058] At operation 410, the processing logic resides in the memory subsystem controller (e.g., Figure 1 The memory access command is received from the memory subsystem controller 115. In some embodiments, the memory access command is a write command. The processing logic may receive a memory access command from the host device (e.g., Figure 1The host system 120 receives memory access commands. For example, memory access commands may be received via an interface port coupled to the memory subsystem controller and the host device. Examples of interface ports include Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect Fast (PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), etc. When the memory subsystem is coupled to the host device via a PCIe interface, the host device may further utilize an NVM Fast (NVMe) interface to access the memory subsystem controller. The interface port provides an interface for passing control, address, data, and other signals between the memory subsystem and the host device. The memory subsystem may contain multiple interface ports. In some embodiments, processing logic may retrieve memory access commands from entries of a data structure, such as a table (e.g., a submission queue) storing memory access commands from the host device in each entry. In some embodiments, the data structure may be as follows: Figure 1 The commit queues 123A to 123N are described in the diagram. In some embodiments, a memory access command may be associated with one or more parameters, including, for example, a Place Handle Identifier (PHI) and / or a segment identifier. For example, one or more parameters may indicate the namespace, PHI, and reclaim group to which the memory access command points. The segment identifier may correspond to a namespace in a set of namespaces of the memory device. (See also: Regarding...) Figure 2 Each described namespace may contain a reclamation group, where each reclamation group contains a set of reclamation units. In some embodiments, each namespace may be (e.g., by the memory subsystem controller and / or firmware components) assigned to a reclamation unit handle, wherein the reclamation unit handle is unique for the namespace, and the namespace is unique for the reclamation unit handle. In some embodiments, a segment identifier may correspond to a cursor identifier in a set of cursor identifiers for the memory device. Each cursor identifier may be associated with a corresponding function of the memory device. In some embodiments, based on the configuration settings of the memory device, the segment identifier may correspond to a namespace or a cursor identifier. In some embodiments, the configuration settings may be a static configuration set during the design phase of the memory device based on offline testing and media characterization.

[0059] At operation 420, the processing logic identifies a segment of the memory device based on the segment identifier received at operation 410. In some embodiments, hardware components of the memory subsystem controller (e.g., Figure 1The hardware automation component and / or hardware component 113b) are used to identify segments of the memory device. In some embodiments, segment identification of the memory device is performed in response to determining that a configuration setting is enabled for identifying segments of the memory device using a hardware component. In some embodiments, determining whether a configuration setting is enabled may include reading one or more registers associated with the host device, wherein one or more registers store data specifying the configuration setting. In some embodiments, determining whether a configuration setting is enabled may include reading metadata associated with a memory access command received from the host device. In some embodiments, the configuration setting is specified by the host device and stored in one or more registers associated with the host device and accessible by the memory subsystem. In some embodiments, the configuration setting is pre-configured at manufacturing time based on device requirements / specifications and / or customer / business requirements. In some embodiments, identifying segments of the memory device based on segment identifiers may include using a data structure that maps the corresponding reclaim unit handle to the corresponding namespace (e.g., regarding...). Figure 2 A data structure is described to identify reclaim unit handles assigned to a specific namespace. In some embodiments, the data structure contains a set of entries, each of which maps a corresponding reclaim unit to a corresponding PHI and a set of corresponding reclaim units contained in a corresponding reclaim group (e.g., storage logical association). Processing logic may retrieve reclaim unit handles corresponding to segment identifiers (e.g., corresponding to a specific PHI) from the entries of the data structure, where the reclaim unit handle identifies a set of reclaim units contained in a reclaim group. For example, processing logic may identify an entry of a data structure storing a specific PHI. In response to identifying an entry storing a specific PHI, processing logic may identify a corresponding reclaim unit handle corresponding to the specific PHI (e.g., logically associated with the specific PHI). In response to identifying the reclaim unit handle, processing logic may identify a set of corresponding RUs and / or corresponding RGs stored in the entry and logically associated with the reclaim unit handles and PHIs in the data structure.

[0060] At operation 430, the processing logic determines whether one or more associated parameters conform to the current Flexible Data Placement (FDP) configuration of the memory subsystem 110. As described herein, the FDP configuration may have been previously set based on input from the host system 120 and may include, for example, the maximum number of namespaces supported in the memory subsystem 110, the maximum number of placement handle identifiers supported in the memory subsystem 110, and the maximum number of reclamation groups supported in the memory subsystem 110. To determine whether the one or more associated parameters from the memory access command conform to the current FDP configuration, the hardware components (e.g., Figure 1 The hardware automation component and / or hardware component 113b) can compare the values ​​of one or more associated parameters with the maximum values ​​defined in the FDP configuration.

[0061] In response to determining that one or more associated parameters conform to the current FDP configuration of memory subsystem 110, at operation 440, the processing logic executes the memory access command received at operation 410 on an identified segment (e.g., at the physical address located by a set of RUs and / or RGs identified at operation 420). In some embodiments, the processing logic uses firmware components of the memory subsystem controller (e.g., Figure 1 Firmware component 113a) and / or hardware components (e.g. Figure 1 Hardware component 113b) executes a memory access command. In some embodiments, executing a memory access command may include a logical block address identifying the memory access command. The logical block address may be identified using logical address information contained, for example, in metadata associated with the memory access command. Processing logic (e.g., hardware component) may translate the logical block address into one or more translation units (TUs). The processing logic may identify a pointer to each of the one or more TUs, wherein each pointer points to a location in the memory device of data identified by each TU. The pointer may point to a location of an identified segment in the memory device. The processing logic may execute a memory access command by executing each of the one or more TUs using the pointer of each TU. For example, the processing logic may write data identified by a particular TU to a location in the memory device identified by the pointer of that particular TU.

[0062] In some embodiments, the hardware component sends an identified segment of the memory device to the firmware component. In response to receiving the identified segment of the memory device, the firmware component can use the identified segment on which a memory access command is executed to update the corresponding entry in the logical-to-physical (L2P) table.

[0063] In some embodiments, the processing logic notifies the host device of the completion of execution of a memory access command. In some embodiments, notifying the host device of the completion of execution of the memory access command may include updating entries in data structures coupled to and / or otherwise associated with the host device. In some embodiments, updating entries in the data structures may include updating the entries with an identifier of the memory access command (e.g., logical address information of the memory access command). In some embodiments, the processing logic may send an interrupt message to the host device. In some embodiments, the interrupt message may include data indicating that an entry in the L2P table has been updated. In some embodiments, the interrupt message is an electrical signal that interrupts the host device. In some embodiments, an interrupt routine may be used to send the interrupt message.

[0064] In response to determining that one or more associated parameters do not conform to the current FDP configuration of memory subsystem 110, at operation 450, the processing logic sends the memory access command to a firmware component (e.g., firmware component 113a) of memory subsystem controller 115. The firmware component is configured to generate a modified memory access command and execute the modified memory access command on memory device 130. To modify the memory access command, the firmware component may adjust one or more of the associated parameters to conform to the current FDP configuration. For example, the firmware component may change PHI and recycling group to default parameters (e.g., 0). In one embodiment, when modifying the memory access command, the firmware component sends the modified memory access command back to hardware component 113b for execution.

[0065] Figure 5 The computer system 500 is described as an example machine, within which a set of instructions is executable to cause the machine to perform any or more of the methods discussed herein. In some embodiments, the computer system 500 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110, or may be used to perform controller operations (e.g., execute an operating system to perform operations corresponding to...). Figure 1 (The operation of the data placement management component 113). In an alternative embodiment, the machine may connect (e.g., network) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer-to-peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0066] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by said machine. Furthermore, while describing a single machine, the term "machine" should also be considered to include any collection of machines that individually or collectively execute a set (or more) of instructions to perform any or more of the methods discussed herein.

[0067] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or RDRAM)), a static memory 506 (e.g., flash memory, static random access memory (SRAM)), and a data storage system 518, which communicate with each other via a bus 530.

[0068] Processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or multiple processors implementing combinations of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 for communicating via network 520.

[0069] Data storage system 518 may include machine-readable storage medium 524 (also called computer-readable medium) on which one or more sets of instructions 526 or software embodying any or more of the methods or functions described herein are stored. During execution of instructions 526 by computer system 500, instructions 526 may also reside wholly or at least partially in main memory 504 and / or processing device 502, which also constitute machine-readable storage medium. Machine-readable storage medium 524, data storage system 518, and / or main memory 504 may correspond to... Figure 1 The memory subsystem 110.

[0070] In one embodiment, instruction 526 includes instructions for implementing a component (e.g., Figure 1 The data placement management component 113) provides functional instructions. Although the machine-readable storage medium 524 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0071] Certain portions of the foregoing detailed description have been presented based on algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the most effective way for those skilled in the art of data processing to communicate the essence of their work to others skilled in the art. Here and generally, an algorithm is considered a self-consistent sequence of operations that leads to a desired result. These operations are those that require physical manipulation of physical quantities. Usually, but not necessarily, these quantities are in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven convenient, and sometimes, for customary use, these signals are referred to in principle as bits, values, elements, symbols, characters, items, numbers, or the like.

[0072] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure may relate to the operation and processes of a computer system or similar electronic computing device that manipulate and transform data representing physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented in the memory or registers of the computer system or other such information storage systems.

[0073] This disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0074] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used in conjunction with the programs taught herein, or, as may prove convenient, more specialized devices can be constructed to execute the methods. The structures for various such systems will appear as stated in the description below. Furthermore, this disclosure is not described with reference to any particular programming language. It will be understood that various programming languages ​​can be used to implement the teachings of this disclosure as described herein.

[0075] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being used to program a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0076] In the foregoing description, embodiments thereof have been described with reference to specific examples of the present disclosure. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure set forth in the appended claims. Therefore, the description and drawings should be regarded in an illustrative rather than restrictive sense.

Claims

1. A system comprising: Memory devices; and A memory subsystem controller, operatively coupled to the memory device, the memory subsystem controller being configured to perform operations including: Receive a memory access command with one or more associated parameters from the host system; The hardware components of the memory subsystem controller are used to determine whether the one or more associated parameters conform to the current Flexible Data Placement (FDP) configuration of the system. and In response to determining that the one or more associated parameters conform to the current FDP configuration of the system, the memory access command is executed on the identified segment of the memory device.

2. The system of claim 1, wherein the one or more associated parameters correspond to the namespace of the memory device.

3. The system of claim 2, wherein the namespace includes a recycling group, wherein the recycling group includes a plurality of recycling units, wherein the namespace has an associated recycling unit handle, and wherein the recycling unit handle is unique for the namespace, and the namespace is unique for the recycling unit handle.

4. The system of claim 3, wherein the memory subsystem controller is configured to perform operations further including: Identifying the segment of the memory device, wherein identifying the segment includes retrieving a reclaim unit handle from a data structure, wherein the reclaim unit handle identifies a plurality of reclaim units, and wherein the data structure includes a plurality of entries, each entry mapping a corresponding reclaim unit to a corresponding namespace and a corresponding plurality of reclaim units.

5. The system of claim 1, wherein the memory subsystem controller is configured to perform operations further including: In response to determining that one or more associated parameters do not conform to the current FDP configuration of the system, the memory access command is sent to the firmware component of the memory subsystem controller, wherein the firmware component is configured to generate a modified memory access command and execute the modified memory access command on the memory device.

6. The system of claim 1, wherein the current FDP configuration of the memory subsystem includes the maximum number of namespaces supported in the memory subsystem, the maximum number of place handle identifiers supported in the memory subsystem, and the maximum number of reclaim groups supported in the memory subsystem.

7. The system of claim 1, wherein the current FDP configuration of the memory subsystem can be configured by the host system.

8. A method comprising: At the memory subsystem, a memory access command with one or more associated parameters is received from the host system. The hardware components of the memory subsystem controller of the memory subsystem are used to determine whether the one or more associated parameters conform to the current Flexible Data Placement (FDP) configuration of the memory subsystem; and In response to determining that one or more associated parameters conform to the current FDP configuration of the memory subsystem, the memory access command is executed on the identified segment of the memory device of the memory subsystem.

9. The method of claim 8, wherein the one or more associated parameters correspond to the namespace of the memory device.

10. The method of claim 9, wherein the namespace includes a reclamation group, wherein the reclamation group includes a plurality of reclamation units, wherein the namespace has an associated reclamation unit handle, and wherein the reclamation unit handle is unique for the namespace, and the namespace is unique for the reclamation unit handle.

11. The method of claim 10, further comprising: Identifying the segment of the memory device, wherein identifying the segment includes retrieving a reclaim unit handle from a data structure, wherein the reclaim unit handle identifies a plurality of reclaim units, and wherein the data structure includes a plurality of entries, each entry mapping a corresponding reclaim unit to a corresponding namespace and a corresponding plurality of reclaim units.

12. The method of claim 8, further comprising: In response to determining that one or more associated parameters do not conform to the current FDP configuration of the system, the memory access command is sent to the firmware component of the memory subsystem controller, wherein the firmware component is configured to generate a modified memory access command and execute the modified memory access command on the memory device.

13. The method of claim 8, wherein the current FDP configuration of the memory subsystem includes the maximum number of namespaces supported in the memory subsystem, the maximum number of place handle identifiers supported in the memory subsystem, and the maximum number of reclaim groups supported in the memory subsystem.

14. The method of claim 8, wherein the current FDP configuration of the memory subsystem can be configured by the host system.

15. A non-transitory computer-readable storage medium storing instructions that, when executed by a processing apparatus, cause the processing apparatus to perform operations including: At the memory subsystem, a memory access command with one or more associated parameters is received from the host system. The hardware components of the memory subsystem controller of the memory subsystem are used to determine whether the one or more associated parameters conform to the current Flexible Data Placement (FDP) configuration of the memory subsystem; and In response to determining that one or more associated parameters conform to the current FDP configuration of the memory subsystem, the memory access command is executed on the identified segment of the memory device of the memory subsystem.

16. The non-transitory computer-readable storage medium of claim 15, wherein one or more associated parameters correspond to the namespace of the memory device.

17. The non-transitory computer-readable storage medium of claim 16, wherein the namespace includes a reclamation group, wherein the reclamation group includes a plurality of reclamation units, wherein the namespace has an associated reclamation unit handle, and wherein the reclamation unit handle is unique for the namespace, and the namespace is unique for the reclamation unit handle.

18. The non-transitory computer-readable storage medium of claim 17, wherein the instructions cause the processing apparatus to perform operations further including: Identifying the segment of the memory device, wherein identifying the segment includes retrieving a reclaim unit handle from a data structure, wherein the reclaim unit handle identifies a plurality of reclaim units, and wherein the data structure includes a plurality of entries, each entry mapping a corresponding reclaim unit to a corresponding namespace and a corresponding plurality of reclaim units.

19. The non-transitory computer-readable storage medium of claim 15, wherein the instructions cause the processing apparatus to perform operations further including: In response to determining that one or more associated parameters do not conform to the current FDP configuration of the system, the memory access command is sent to the firmware component of the memory subsystem controller, wherein the firmware component is configured to generate a modified memory access command and execute the modified memory access command on the memory device.

20. The non-transitory computer-readable storage medium of claim 15, wherein the current FDP configuration of the memory subsystem includes a maximum number of namespaces supported in the memory subsystem, a maximum number of place handle identifiers supported in the memory subsystem, and a maximum number of reclaim groups supported in the memory subsystem.

Images