System on chip, method and device supporting timestamp capture and storage medium

Abstract

Disclosed are a system on chip, method and device supporting timestamp capture, and a storage medium, the system comprising: a communication controller for sending a data acquisition instruction to a target sensor; responding to sensor valid data and placeholder data transmitted by the target sensor and received by the first data buffer, and correspondingly generating a first starting signal and a second starting signal; the first DMA controller is used for reading sensor effective data from the first data buffer and writing the sensor effective data into the data buffer area in response to a first starting signal; in response to the second starting signal, reading and writing the current time value of the preset clock as a timestamp corresponding to effective data of the sensor into the data buffer area; transmitting a read interrupt signal to a processor; and the processor is used for reading the sensor valid data and the timestamp from the data buffer area in response to the read interrupt signal. According to the system, precise binding of the timestamp and effective data of the sensor can be realized on a hardware level.

Description

Technical Field

[0001] This disclosure relates to the field of timestamp capture technology, and more particularly to an on-chip system, method, device and storage medium that supports timestamp capture. Background Technology

[0002] In the field of system-on-a-chip, the timestamps of multiple sensors need to be strictly synchronized. This is the core prerequisite for ensuring the accurate fusion of multi-source data. Therefore, the accuracy of the timestamps of each sensor is crucial.

[0003] Taking the aforementioned multi-sensor system, including the target sensor, as an example, the timestamp capture of the target sensor needs to be implemented through application layer software or kernel Serial Peripheral Interface (SPI) driver layer software. However, this timestamp capture method is affected by system scheduling latency, which not only produces significant timestamp errors, but also worsens timestamp stability as the operating system scheduling pressure increases. This will lead to a decrease in the accuracy of multi-sensor data fusion. Summary of the Invention

[0004] Existing target sensor timestamp acquisition schemes suffer from large timestamp errors and poor stability due to system scheduling delays, which reduces the accuracy of multi-sensor data fusion.

[0005] To address the aforementioned technical problems, a first aspect of this disclosure provides a system-on-a-chip that supports timestamp capture, including a preset clock, a processor, a communication controller, and a first direct memory access controller; the communication controller includes a first data buffer corresponding to the first direct memory access controller;

[0006] A communication controller is used to send data acquisition commands to the target sensor; and to generate a first start signal in response to receiving valid sensor data transmitted by the target sensor from the first data buffer.

[0007] A first direct memory access controller is configured to, in response to a first start signal, read valid sensor data from a first data buffer and write the valid sensor data into a data buffer of a preset memory.

[0008] The communication controller is also configured to generate a second start signal in response to receiving placeholder data transmitted by the target sensor from the first data buffer;

[0009] The first direct memory access controller is also configured to, in response to the second start signal, read the current time value of a preset clock and write the current time value of the preset clock as the timestamp corresponding to the valid data of the sensor into the data buffer; and after writing the current time value into the data buffer, transmit a read interrupt signal to the processor.

[0010] The processor is used to read valid sensor data and the timestamp corresponding to the valid sensor data from the data buffer in response to a read interrupt signal.

[0011] A second aspect of this disclosure provides a timestamp capture method based on a system-on-a-chip (SoC), wherein the SoC includes a preset clock, a processor, a communication controller, and a first direct memory access controller; the communication controller includes a first data buffer corresponding to the first direct memory access controller; the method includes:

[0012] The communication controller sends data acquisition commands to the target sensor.

[0013] The communication controller receives valid sensor data transmitted by the target sensor through the first data buffer and generates a first start signal.

[0014] In response to the first start signal, the first direct memory access controller reads valid sensor data from the first data buffer and writes the valid sensor data into the data buffer of the preset memory.

[0015] The communication controller receives placeholder data transmitted by the target sensor through the first data buffer and generates a second start signal.

[0016] In response to the second start signal, the first direct memory access controller reads the current time value of the preset clock and writes the current time value of the preset clock as the timestamp corresponding to the valid data of the sensor into the data buffer; and after writing the current time value into the data buffer, it transmits a read interrupt signal to the processor.

[0017] The processor responds to the read interrupt signal and reads the valid sensor data and the timestamp corresponding to the valid sensor data from the data buffer.

[0018] A third aspect of this disclosure provides a vehicle that includes a target sensor and the system-on-a-chip provided in the first aspect.

[0019] The target sensor is used to collect valid sensor data and placeholder data in response to data acquisition commands, and to transmit the valid sensor data and placeholder data to the system on-chip; wherein, the data acquisition command is the command sent by the communication controller in the system on-chip to the target sensor;

[0020] The system-on-a-chip (SoC) is configured to: generate a first start signal in response to receiving valid sensor data from a first data buffer in the communication controller; read valid sensor data from the first data buffer in response to the first start signal and write the valid sensor data into a data buffer of a preset memory; generate a second start signal in response to receiving placeholder data from the first data buffer; read the current time value of a preset clock in response to the second start signal and write the current time value of the preset clock as the timestamp corresponding to the valid sensor data into the data buffer; and transmit a read interrupt signal to the processor in the SoC after writing the current time value into the data buffer; and, in response to the read interrupt signal, read the valid sensor data and the timestamp corresponding to the valid sensor data from the data buffer.

[0021] A fourth aspect of this disclosure provides an electronic device including the processor described above and a memory for storing processor-executable instructions; the processor is configured to read executable instructions from the memory and execute the instructions to implement the system-on-chip-based timestamp capture method of the second aspect described above.

[0022] A fifth aspect of this disclosure provides a computer-readable storage medium storing a computer program that, when executed by a processor, is used to implement the system-on-chip-based timestamp capture method provided in the second aspect above.

[0023] A sixth aspect of this disclosure provides a timestamp capture apparatus based on a system-on-a-chip, the apparatus comprising:

[0024] The transmitting module is used to send data acquisition commands to the target sensor via the communication controller;

[0025] The first generation module is used to generate a first start signal in response to receiving valid sensor data transmitted by the target sensor through the communication controller in response to the first data buffer.

[0026] The first transport module is used to read valid sensor data from the first data buffer and write the valid sensor data into the data buffer of the preset memory in response to the first start signal via the first direct memory access controller.

[0027] The second generation module is used to generate a second start signal in response to the first data buffer receiving placeholder data transmitted by the target sensor through the communication controller.

[0028] The second transport module is used to read the current time value of a preset clock in response to a second start signal via a first direct memory access controller, and write the current time value of the preset clock as the timestamp corresponding to the valid data of the sensor into a data buffer; and after writing the current time value into the data buffer, transmit a read interrupt signal to the processor.

[0029] The read module is used to read valid sensor data and the timestamp corresponding to the valid sensor data from the data buffer in response to a read interrupt signal by the processor.

[0030] A sixth aspect of this disclosure provides a computer program product that, when instructions in the computer program product are executed by a processor, performs the on-chip-based timestamp capture method provided in the second aspect above.

[0031] The on-chip system supporting timestamp capture provided in this disclosure, since the placeholder data is data transmitted from the target sensor to the first data buffer after the valid sensor data, allows the communication controller to respond to the placeholder data received by the first data buffer and trigger the first DMA controller to read the current time value of a preset clock. This enables accurate determination of the reception time of the valid sensor data, i.e., the timestamp corresponding to the valid sensor data, thereby achieving precise binding between the timestamp and the valid sensor data at the hardware level. This process is completely unaffected by system scheduling delays and interrupt response delays, giving the timestamp high stability and minimal error, thus improving the accuracy of multi-sensor data fusion.

[0032] Furthermore, when this target sensor timestamp capture scheme is applied to an intelligent driving system, it can prevent phenomena such as attitude drift, positioning inaccuracy, and redundancy verification failure in the intelligent driving system, thereby ensuring the functional safety of the intelligent driving system. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the structure of an on-chip system supporting timestamp capture provided by an exemplary embodiment of this disclosure.

[0034] Figure 2 This is a schematic diagram of another on-chip system supporting timestamp capture provided by an exemplary embodiment of this disclosure.

[0035] Figure 3 This is a flowchart illustrating an exemplary embodiment of a timestamp capture method based on a system-on-a-chip.

[0036] Figure 4 This is a flowchart illustrating another on-chip system-based timestamp capture method provided by an exemplary embodiment of this disclosure.

[0037] Figure 5This is a flowchart illustrating another system-on-chip-based timestamp capture method provided in an exemplary embodiment of this disclosure.

[0038] Figure 6 This is a flowchart illustrating another on-chip system-based timestamp capture method provided in an exemplary embodiment of this disclosure.

[0039] Figure 7 This is a flowchart illustrating another on-chip system-based timestamp capture method provided in an exemplary embodiment of this disclosure.

[0040] Figure 8 This is a schematic diagram of the structure of a system-on-a-chip-based timestamp capture device provided in an exemplary embodiment of this disclosure.

[0041] Figure 9 This is a schematic diagram of another system-on-chip-based timestamp capture device provided in an exemplary embodiment of this disclosure.

[0042] Figure 10 This is a schematic diagram of the structure of a vehicle provided in an exemplary embodiment of this disclosure.

[0043] Figure 11 This is a schematic diagram of the structure of an electronic device provided in an exemplary embodiment of the present disclosure. Detailed Implementation

[0044] To explain this disclosure, exemplary embodiments of the disclosure will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the disclosure, and not all of them. It should be understood that the disclosure is not limited to exemplary embodiments.

[0045] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0046] Application Overview

[0047] At the system-on-a-chip (SoC) level, the microsecond-level accuracy of timestamps from multiple sensors is the core foundation for achieving strict time alignment and ensuring accurate data fusion. Take, for example, a multi-sensor scenario in autonomous driving where the target sensor is an Inertial Measurement Unit (IMU). Only when the IMU achieves strict time alignment with asynchronous sensors such as cameras, LiDAR, and GNSS can fusion algorithms like Extended Kalman Filter (EKF) and Simultaneous Localization and Mapping (SLAM) perform accurate calculations based on state variables at the same physical moment. Conversely, time deviations caused by timestamp inaccuracies accumulate and amplify during high-frequency integration, leading to attitude drift, positioning errors, and control failures in autonomous driving scenarios. Therefore, the accuracy of timestamps from all sensors, including the IMU, is crucial.

[0048] However, current intelligent driving systems can only implement IMU timestamps in pure software, which has significant limitations. Specifically, after the application layer software obtains IMU data through the Serial Peripheral Interface (SPI) subsystem's application programming interface (API), the software program needs to complete the timestamp annotation. However, during the process of data transmission from the SPI controller, through the hardware driver, and the operating system's SPI subsystem to the application layer, the scheduling delay and interrupt response delay in the intermediate links directly lead to a large timestamp error. Moreover, under heavy operating system scheduling pressure, the stability problem of the timestamp becomes even more prominent.

[0049] Even if the timestamp generation logic is migrated from the application layer software to the kernel SPI driver layer, although the probability of large errors can be reduced to some extent, since it is still essentially a software timestamp, its generation process is still affected by system scheduling fluctuations, which can still lead to a decrease in the accuracy of multi-sensor data fusion. Consequently, in intelligent driving scenarios, this can still cause phenomena such as attitude drift, positioning inaccuracies, and redundancy check failures, directly affecting the functional safety of the intelligent driving system.

[0050] To address the aforementioned technical issues, this disclosure provides a system-on-a-chip (SoC) supporting timestamp capture. The SoC includes a preset clock, a processor, a communication controller, and a first direct memory access controller (DMI). The communication controller includes a first data buffer corresponding to the DMI. The communication controller sends a data acquisition command to a target sensor and, in response to the first data buffer, receives valid sensor data transmitted by the target sensor, generating a first start signal. Then, in response to the first start signal, the first DMI reads the valid sensor data from the first data buffer and writes it into a data buffer of a preset memory. Simultaneously, the communication controller generates a second start signal in response to the first data buffer receiving placeholder data transmitted by the target sensor. In response to the second start signal, the first DMI reads the current time value of the preset clock and writes the current time value of the preset clock as the timestamp corresponding to the valid sensor data into the data buffer. After writing the current time value into the data buffer, it transmits a read interrupt signal to the processor. Then, the processor, in response to the read interrupt signal, reads the valid sensor data and the timestamp corresponding to the valid sensor data from the data buffer.

[0051] In this on-chip system, since the placeholder data is the data transmitted from the target sensor to the first data buffer after the valid sensor data, the communication controller, in response to the placeholder data received by the first data buffer, triggers the first DMA controller to read the current time value of the preset clock. This allows for the accurate determination of the reception time of the valid sensor data, i.e., the timestamp corresponding to the valid sensor data, thus achieving precise binding between the timestamp and the valid sensor data at the hardware level. This process is completely unaffected by system scheduling delays and interrupt response delays, giving the timestamp high stability and minimal error, thereby improving the accuracy of multi-sensor data fusion.

[0052] Furthermore, when this target sensor timestamp capture scheme is applied to an intelligent driving system, it can prevent phenomena such as attitude drift, positioning inaccuracy, and redundancy check failure, thereby ensuring the functional safety of the intelligent driving system.

[0053] Exemplary System

[0054] Figure 1 This is a schematic diagram of the structure of an on-chip system supporting timestamp capture, provided by an exemplary embodiment of this disclosure. Figure 1As shown, the on-chip system 10 supporting timestamp capture may include a preset clock 101, a processor 102, a communication controller 103, and a first direct memory access (DMA) controller 104; the communication controller 103 includes a first data buffer 1031 corresponding to the first DMA controller 104;

[0055] The communication controller 103 is used to send a data acquisition command to the target sensor; and to generate a first start signal in response to receiving valid sensor data transmitted by the target sensor from the first data buffer.

[0056] The first DMA controller 104 is configured to, in response to the first start signal, read valid sensor data from the first data buffer and write the valid sensor data into the data buffer of a preset memory;

[0057] The communication controller 103 is also configured to generate a second start signal in response to receiving placeholder data transmitted by the target sensor from the first data buffer;

[0058] The first DMA controller 104 is also configured to, in response to the second start signal, read the current time value of the preset clock and write the current time value of the preset clock as the timestamp corresponding to the valid data of the sensor into the data buffer; and after writing the current time value into the data buffer, transmit a read interrupt signal to the processor 102.

[0059] The processor 102 is used to read valid sensor data and the timestamp corresponding to the valid sensor data from the data buffer in response to a read interrupt signal.

[0060] The preset clock can be the hardware clock of the system-on-chip 10 that supports DMA access and timestamp capture. In some examples, the preset clock may include the network interface card's (NIC) precise hardware clock (PHC).

[0061] The processor 102 may be a central processing unit (CPU) or a microprocessor (MCU).

[0062] The communication controller 103 is preferably a Serial Peripheral Interface (SPI) controller; the first data buffer 1031 is preferably a Receive First In First Out (RX FIFO) buffer of the SPI controller; the first DMA controller 104 is preferably a Receive Peripheral Direct Memory Access (RX PDMA) controller; and the target sensor is preferably an IMU.

[0063] The depth of the first data buffer 1031 is a fixed parameter preset according to the target application scenario (such as communication rate, typical data volume), and can be 8 bytes, 16 bytes, 32 bytes, etc. This embodiment of the disclosure takes a depth of 16 bytes for the first data buffer 1031 as an example for illustrative explanation.

[0064] Valid sensor data refers to the raw motion state measurement data generated and transmitted by the IMU in response to data acquisition commands, which conforms to preset acquisition rules and can be directly used for calculations by the autonomous driving system.

[0065] Taking the communication controller 103 as an SPI controller as an example, since the SPI protocol is a synchronous serial communication protocol, its core characteristic determines that the amount of data sent and received must be completely consistent. Therefore, when the SPI controller sends a data acquisition command to the target sensor, the total amount of data transmitted by the target sensor in response to the command is always completely consistent with the total amount of data received by the SPI controller when performing this data acquisition operation (the amount of data in the data acquisition command).

[0066] The data transmitted by the target sensor includes valid sensor data. Therefore, the amount of valid sensor data is directly related to the amount of data in the data acquisition command. This disclosure does not limit the size of the valid sensor data; however, it uses N bytes as an example for illustrative purposes.

[0067] Data acquisition commands can be commands for acquiring three-axis accelerometer and three-axis gyroscope data, and may include parameter configuration commands. Parameter configuration commands are used to configure acquisition rules; for example, they are used to configure key parameters such as sampling rate, range, and accuracy, and to specify the data output method and format.

[0068] Taking the data acquisition command not including the enable command of the target sensor as an example, the processor 102 of the system-on-a-chip 10 that supports timestamp capture can send an enable command to the target sensor through the communication controller 103 during the system initialization phase to activate the three-axis accelerometer and the three-axis gyroscope. When acquiring data from the target sensor, the processor 102 sends a data acquisition command to the target sensor through the communication controller 103 so that the controller can acquire data from the target sensor according to the configured acquisition rules.

[0069] In some examples, the specific composition of the data acquisition instructions can be flexibly adjusted according to the type of target sensor and acquisition requirements. This disclosure does not limit the specific composition of the data acquisition instructions.

[0070] The first start signal can be a prompt signal used to initiate the first DMA controller 104 to transfer valid sensor data. In some examples, the first start signal can be used to indicate that additional valid sensor data is needed, and may be referred to as a handshake signal or a DMA request signal. For example, the first start signal can be DREQ.

[0071] In different application scenarios, the communication controller 103 can send data acquisition commands to the target sensor in different ways. For example, in a sensor perception scenario in intelligent driving, the communication controller 103 can send data acquisition commands to the target sensor at a preset period; in a collision detection scenario, the communication controller 103 only sends data acquisition commands to the target sensor (non-periodicly) when the vehicle experiences abnormal vibration. This disclosure does not limit the method by which the communication controller 103 sends data acquisition commands to the target sensor; this disclosure exemplifies the method by which the communication controller 103 sends data acquisition commands to the target sensor at a preset period.

[0072] The preset period can be the period at which the target sensor collects data, and it can correspond to the period of the sensor data collected by the target sensor. Taking the target sensor as an IMU and the frequency of the IMU data as 100Hz as an example, the preset period can be 10ms.

[0073] The communication controller 103 can be connected to the target sensor. After the target sensor receives and parses the complete data acquisition command, it receives the valid sensor data transmitted by the target sensor through the first data buffer 1031, and generates a first start signal by detecting the valid sensor data in the first data buffer 1031.

[0074] In some examples, the communication controller 103 may generate a first start signal when the first data buffer 1031 is full of valid sensor data or when all valid sensor data has been received. If the amount of valid sensor data is greater than the depth of the first data buffer 1031, the communication controller 103 may generate at least two first start signals when receiving all valid sensor data through the first data buffer 1031. For example, if the amount of valid sensor data is 30 bytes and the depth of the first data buffer 1031 is 16 bytes, the communication controller 103 will generate a first start signal when the first data buffer 1031 is full of the first 16 bytes, and a second first start signal when the remaining 14 bytes (i.e., all 30 bytes of data) have been received.

[0075] Preset memory, for example but limited to Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM, or DDR for short), located outside the on-chip system.

[0076] The data buffer can be a dedicated memory region configured in DDR by the processor 102, implemented using kernel-mode coherent memory, and used to store data frames. Because this data buffer can use a circular structure to implement cyclic writing of data, it can also be called a circular buffer.

[0077] The total capacity of the data buffer can be greater than or equal to a preset number of bytes. This disclosure does not limit the total capacity of the data buffer; however, it uses an example where the total capacity of the data buffer is greater than or equal to 10,000 bytes for illustrative purposes. In some examples, the operating system kernel can request the storage space for the data buffer through the UIO driver when loading the Userspace Input / Output (UIO) driver.

[0078] Taking a scenario where the amount of valid sensor data is 30 bytes, the depth of the first data buffer 1031 is 16 bytes, and the communication controller 103 generates a first start signal and a second start signal when the first data buffer 1031 receives valid sensor data, the first DMA controller 104, which can be connected to the communication controller 103, receives and responds to the first start signal, reads the first 16 bytes of valid sensor data from the first data buffer 1031, and writes the first 16 bytes of valid sensor data into the data buffer of a preset memory. Subsequently, receiving and responding to the second start signal, it reads the remaining 14 bytes of valid sensor data from the first data buffer 1031 and writes the remaining 14 bytes of valid sensor data into the data buffer of the preset memory.

[0079] Placeholder data refers to invalid data that is added to meet data volume requirements but does not participate in data processing. In some examples, placeholder data can be data in hardware registers within the target sensor. These hardware registers include, but are not limited to, status registers, configuration registers, calibration registers, and device information registers.

[0080] The size of the placeholder data can be consistent with the size of the timestamp data corresponding to the valid sensor data. This embodiment does not limit the size of the placeholder data; however, it uses an example where both the placeholder data and the timestamp data corresponding to the valid sensor data are 4 bytes each.

[0081] Taking the communication controller 103 as an SPI controller as an example, if the placeholder data includes 4 bytes and the sensor valid data is 30 bytes, then the data volume of the data acquisition instruction is 34 bytes, which is equal to the sum of the sensor valid data and the placeholder data, which conforms to the characteristic of strict equivalence of data volume between the two communicating parties in the SPI protocol.

[0082] The second start signal can be a prompt signal used to initiate the first DMA controller 104 to move placeholder data. In some examples, the second start signal can be used to indicate that additional placeholder data is needed, and similar to the first start signal, it can also be called a handshake signal or a DMA request signal. For example, the second start signal can also be DREQ.

[0083] Understandably, after receiving and parsing the data acquisition command, the target sensor transmits valid sensor data to the first data buffer 1031 and then continues to transmit placeholder data.

[0084] Taking a first data buffer 1031 with a depth of 16 bytes and a placeholder data size of 4 bytes as an example, the first data buffer 1031 can continue to receive placeholder data after receiving complete valid sensor data. The communication controller 103 can generate a second start signal when it detects that the first data buffer 1031 has received complete placeholder data.

[0085] Understandably, the second DMA controller 104 can be connected to the CPU's interrupt handler to transmit read interrupt signals to the CPU through that connection.

[0086] Taking a placeholder data size of 4 bytes and a first data buffer 1031 depth of 16 bytes as an example, the first DMA controller 104 can respond to the second start signal by reading 4 bytes of the current time value from the time register corresponding to the preset clock 101, and writing the 4 bytes of the current time value as the timestamp corresponding to the valid sensor data into the data buffer all at once.

[0087] The read interrupt can be a transfer completion interrupt, i.e., a Direct Memory Access Block Done (DMA Block Done) interrupt. The processor 102 can enable the read interrupt during the initialization of the first DMA controller 104 by writing to a register, thus enabling the read interrupt. When the read interrupt is enabled, the first DMA controller 104 can trigger the read interrupt and generate a read interrupt signal after writing the 4-byte current time value to the data buffer, i.e., after the first DMA controller 104 completes the transfer operation of the valid sensor data and the timestamp corresponding to the valid sensor data.

[0088] The interrupt handler of processor 102 can be electrically connected to the first DMA controller 104 to transmit a read interrupt signal to processor 102 via this electrical connection. Then, in response to the read interrupt signal, processor 102 reads valid sensor data and the timestamp corresponding to the valid sensor data from the data buffer.

[0089] The on-chip system supporting timestamp capture provided in this disclosure, since the placeholder data is data transmitted from the target sensor to the first data buffer after the valid sensor data, allows the communication controller to respond to the placeholder data received by the first data buffer and trigger the first DMA controller to read the current time value of a preset clock. This enables accurate determination of the reception time of the valid sensor data, i.e., the timestamp corresponding to the valid sensor data, thereby achieving precise binding between the timestamp and the valid sensor data at the hardware level. This process is completely unaffected by system scheduling delays and interrupt response delays, resulting in high stability and minimal error in the timestamp. This not only improves the accuracy of multi-sensor data fusion but also avoids problems such as attitude drift, positioning inaccuracies, and redundancy check failures, thus enhancing the safety of intelligent driving.

[0090] Continue to refer to Figure 1 As shown, the first DMA controller 104 is specifically configured to, in response to the first start signal, read the first descriptor from the descriptor memory area of ​​the preset memory; read the valid sensor data from the first data buffer 1031 according to the first descriptor; and write the valid sensor data to a specified location in the data buffer according to the first descriptor.

[0091] The first descriptor is the first data transfer control parameter transmitted by the first direct memory access controller.

[0092] The first descriptor can be in the form of a scatter-gather (SG) node, serving as the core metadata structure for the first DMA controller 104 to perform sensor valid data transfer. It can include data transfer control parameters such as source address, destination address, and transfer length. The source address can point to the storage location of the data to be transferred, i.e., the physical address of the first data buffer 1012; the destination address can point to the target location of the data storage, i.e., the specified physical address of the data buffer. For example, the destination address can be the starting address of the data buffer. The transfer length is the amount of data transferred in a single transfer operation and can be the same as the amount of sensor valid data. For example, both the transfer length and the amount of sensor valid data can be N bytes.

[0093] The descriptor memory area can be a dedicated memory area in DDR configured by the processor 102 for storing at least one descriptor.

[0094] The processor 102 can construct a first descriptor during the system initialization phase and write the first descriptor into the descriptor memory area to complete the initialization configuration of the first descriptor.

[0095] In some examples, the processor 102 may construct an SG linked list including a first descriptor during the initialization phase and store the SG linked list in a descriptor buffer to complete the initialization configuration of the SG linked list. The SG linked list may include one or more descriptors. This disclosure does not limit the number of descriptors included in the SG linked list; this disclosure provides an example of an SG linked list including two descriptors. For example, the SG linked list may include a first descriptor and a second descriptor.

[0096] Taking a first data buffer 1031 with a depth of 16 bytes and a sensor valid data volume of 30 bytes as an example, when the first data buffer 1031 receives sensor valid data, the communication controller 103 generates a first start signal and a second first start signal. In response to the first first start signal, the first DMA controller 104 reads a first descriptor from the descriptor memory area of ​​a preset memory, reads the first 16 bytes of sensor valid data from the first data buffer 1031 according to the source address of the first descriptor, and writes the first 16 bytes of sensor valid data into the data buffer of the preset memory according to the destination address of the first descriptor. Subsequently, in response to the second first start signal, it reads the remaining 14 bytes of sensor valid data from the first data buffer 1031 according to the source address of the first descriptor, and writes the remaining 14 bytes of sensor valid data into the data buffer of the preset memory according to the destination address of the first descriptor.

[0097] In some examples, processor 102 may disable interrupts for the first descriptor during the initialization phase, so that after the first DMA controller 104 writes valid sensor data to a specified location in the data buffer, it does not trigger a read interrupt, but instead automatically loads the descriptors following the first descriptor in the SG linked list.

[0098] In some embodiments of this disclosure, the first DMA controller 104 is further configured to read a second descriptor following the first descriptor after writing valid sensor data to a specified location in the data buffer.

[0099] The second descriptor is the second data transmission control parameter transmitted by the first DMA controller 104.

[0100] The second descriptor can be a descriptor following the first descriptor in the SG linked list. Similar to the first descriptor, it can be in the form of an SG node, serving as the core metadata structure for the first DMA controller 104 to perform the current time value transfer of the network card. It can include data transmission control parameters such as source address, destination address, and transmission length. The source address can point to the storage location of the data to be transferred, i.e., the physical address of the network card's time register; the destination address can point to the target location of the data storage, i.e., the address associated with the specified physical address and the data buffer. Taking a sensor's effective data volume of N bytes as an example: the destination address can be the starting address of the data buffer + N. The transmission length is the amount of data transferred in a single transmission operation and can be the same as the amount of data for the network card's current time value. For example, both the transmission length and the amount of data for the network card's current time value can be 4 bytes.

[0101] After writing valid sensor data to a specified location in the data buffer, the first DMA controller 104 automatically loads the second descriptor in the SG linked list.

[0102] Processor 102 can enable interrupts for the second descriptor during the initialization phase, so that after the first DMA controller 104 writes the current time value of the network card into the data buffer associated with the specified location, it triggers a read interrupt and transmits a read interrupt signal to processor 102.

[0103] The on-chip system supporting timestamp capture provided in this disclosure reads a first descriptor through a first DMA controller and achieves seamless automatic loading of the descriptor using a linked list of consecutive physical address pointers. This achieves both continuous and efficient data transmission and flexible transmission control through the descriptor. Furthermore, the data transmission-related operations are completed independently by the first DMA controller, consuming almost no CPU resources and reducing CPU resource overhead.

[0104] In some embodiments of this disclosure, the first DMA controller 104 is specifically configured to, in response to a second start signal, read the current time value of the network card from the time register of the network card based on a second descriptor; and, based on the second descriptor, write the current time value of the network card as a timestamp corresponding to the valid sensor data into the data buffer at a position associated with a specified location.

[0105] The preset clock includes the network card's precise hardware clock; the network card's current time value is the current time value of the time register, and the current time value of the time register is generated based on the precise hardware clock.

[0106] It is understood that the network card in this embodiment refers to a network card that integrates a PHC and a time register and supports reading the time register via DMA.

[0107] The location associated with a specified position in the data buffer can be a contiguous and adjacent region, together forming a physically contiguous storage space. For example, if the specified position in the data buffer is its starting address, then the associated positions can start from the address region beginning at the starting address + 1, forming a seamless contiguous storage range.

[0108] Taking the amount of valid sensor data as N, the depth of the first data buffer 1031 as 16 bytes, and the amount of placeholder data as 4 bytes, as an example, when the first data buffer 1031 receives placeholder data, the communication controller 103 generates a second start signal. The first DMA controller 104, in response to the second start signal, reads 4 bytes of the current time value from the network card's time register according to the source address of the second descriptor, and writes this 4-byte current time value as the timestamp corresponding to the valid sensor data to the address of the data buffer's starting address + N according to the destination address of the second descriptor.

[0109] The on-chip system supporting timestamp capture provided in this disclosure uses a first DMA controller to read and store hardware-level timestamps based on a second descriptor. This not only avoids time synchronization errors caused by software delays through hardware mechanisms, but also ensures the physical binding of valid sensor data and timestamps through continuous storage design of associated locations, providing reliable time reference support for scenarios such as high-precision multi-sensor data fusion.

[0110] In some embodiments of this disclosure, after the first DMA controller 104 writes the current time value of the preset clock as the timestamp corresponding to the valid sensor data into the data buffer, the first data buffer 1031 still has placeholder data cached. Therefore, in order to ensure the smooth acquisition of the next target sensor data and the capture of the timestamp, it is necessary to clear the placeholder data in the first data buffer 1031 after writing the current time value of the preset clock into the data buffer.

[0111] Continue to refer to Figure 1 As shown, the processor 102 is also configured to clear placeholder data in the first data buffer in response to a read interrupt signal.

[0112] The processor 102 can respond to a read interrupt signal, clear the placeholder data in the first data buffer, and then read the valid data of the sensor and the timestamp corresponding to the valid data. Alternatively, it can read the valid data of the sensor and the timestamp corresponding to the valid data first, and then clear the placeholder data in the first data buffer. This embodiment does not limit the order in which the processor 102 clears the placeholder data in the first data buffer and reads the valid data of the sensor and the timestamp corresponding to the valid data. This embodiment uses the example of the processor 102 responding to a read interrupt signal, clearing the placeholder data in the first data buffer, and then reading the valid data of the sensor and the timestamp corresponding to the valid data as an example for illustrative purposes.

[0113] The on-chip system supporting timestamp capture provided in this disclosure, by having the processor respond to a read interrupt signal and clear the placeholder data in the first data buffer, can avoid data confusion and triggering logic errors that may occur during the next acquisition of target sensor data and timestamp capture, thereby ensuring the smooth progress of subsequent operations.

[0114] like Figure 2 As shown above, in the above Figure 1 Based on the illustrated embodiment, the on-chip system 10 supporting timestamp capture also includes a second DMA controller 105. The communication controller 103 also includes a second data buffer 1032 corresponding to the second DMA controller 105.

[0115] The communication controller 103 is also configured to generate a third start signal in response to the occupied space of the second data buffer 1032 being less than a preset data amount threshold.

[0116] The second DMA controller 105 is also configured to, in response to the third start signal, read a data acquisition instruction from the instruction buffer and write the data acquisition instruction into the second data buffer 1032.

[0117] The communication controller 103 is also used to read data acquisition instructions from the second data buffer 1032 and send data acquisition instructions to the target sensor.

[0118] The second DMA controller 105 is preferably a Transmit Peripheral Direct Memory Access (TX PDMA) controller; the second data buffer 1032 is preferably a Transmit First In First Out (TX FIFO) queue in the SPI controller.

[0119] The depth of the second data buffer 1032 can be the same as the depth of the first data buffer 1031. For example, the depth of both the second data buffer 1032 and the first data buffer 1031 can be 16 bytes.

[0120] The preset data volume threshold refers to a preset data volume threshold in the second data buffer 1032, and can be determined comprehensively based on the SPI transmission rate, the depth of the second data buffer 1032, and the response latency of the second DMA controller 105. In some examples, the preset data volume threshold can be 1 / 4 to 1 / 2 of the depth of the second data buffer 1032. For example, if the depth of the second data buffer 1032 is 16 bytes, the preset data volume threshold can be 4 to 8 bytes. If the depth of the second data buffer 1032 is 32 bytes, the preset data volume threshold can be 8 to 16 bytes. This disclosure does not limit the size of the preset data volume threshold; this disclosure uses an example of a second data buffer 1032 depth of 16 bytes and a preset data volume threshold of 8 bytes for illustrative purposes.

[0121] The third start signal can be a prompt signal used to initiate the data acquisition command transfer by the second DMA controller 105. In some examples, the third start signal can be used to indicate that additional data acquisition commands are needed, and similar to the first start signal, it can also be called a handshake signal or a DMA request signal. For example, the third start signal can also be DREQ.

[0122] Similar to the data buffer, the instruction buffer can also be a dedicated memory region configured by the processor 102 in DDR, implemented using kernel-mode coherent memory, used to store data acquisition instructions. In some examples, the instruction buffer and the data buffer can reside in the same memory page and have the same capacity, for example, each occupying half of the memory page.

[0123] When the space occupied in the second data buffer 1032 (corresponding to the number of unsent data bytes, also known as the remaining data amount) is lower than a preset data amount threshold, the communication controller 103 can notify the second DMA controller 105 to replenish data to the second data buffer 1032 by pulling down the handshake signal of the second DMA controller 105.

[0124] The second DMA controller 105 can read the corresponding amount of data acquisition instruction from the instruction buffer and write it into the second data buffer 1032 each time it receives a notification to replenish data to the second data buffer 1032 (receives a third start signal), according to the cacheable space size of the second data buffer 1032, until it reads and writes the complete data acquisition instruction into the second data buffer 1032.

[0125] In some examples, the second DMA controller 105 is specifically configured to, in response to a third start signal, read a data acquisition instruction from the instruction buffer based on a third descriptor, and write the data acquisition instruction to the second data buffer 1032 based on the third descriptor.

[0126] Similar to the first or second descriptor, the third descriptor can also be in the form of an SG node, serving as the core metadata structure for the second DMA controller 105 to execute data acquisition instruction transfers. It can include data transfer control parameters such as source address, destination address, and transfer length. The source address can point to the physical address of the instruction buffer; the destination address can point to the address of the second data buffer 1032. The transfer length can be the amount of data in the data acquisition instruction and can be the same as the total amount of valid sensor data and occupied data. For example, if the amount of valid sensor data is 30 bytes and the amount of occupied data is 4 bytes, then the transfer length is 34 bytes.

[0127] The processor 102 can construct a third descriptor during the system initialization phase and write the third descriptor into the descriptor memory area to complete the initialization configuration of the third descriptor.

[0128] Meanwhile, the processor 102 can disable the interrupt for the third descriptor during the initialization phase, so that the second DMA controller 105 does not trigger a read interrupt after writing the data acquisition instruction to the second data buffer 1032.

[0129] Once the occupied space of the second data buffer 1032 falls below a preset data volume threshold, the communication controller 103 can generate a third start signal. Taking a data acquisition command of 34 bytes, a second data buffer 1032 depth of 16 bytes, and a data volume threshold of 8 bytes as an example, during the process of sending the data acquisition command to the target sensor through the second data buffer 1032, since a maximum of 16 bytes can be written to the buffer at a time, the 34-byte command needs to be transmitted in three parts (16 bytes + 16 bytes + 2 bytes). Therefore, the communication controller 103 generates three corresponding third start signals.

[0130] The second DMA controller 105 can respond to three third start signals, read data acquisition instructions from the instruction buffer in three separate reads based on the source address of the third descriptor, and write the data acquisition instructions into the second data buffer 1032 in three separate reads based on the destination address of the third descriptor.

[0131] The on-chip system supporting timestamp capture provided in this disclosure triggers the second DMA controller when the occupied space of the second data buffer is less than a preset data volume threshold. That is, the second DMA controller is driven by the status signal of the second data buffer itself, which can realize the on-demand transfer of data acquisition commands and resolve the contradiction between the small capacity of the second data buffer and the transmission of variable-length data acquisition commands.

[0132] Exemplary methods

[0133] Corresponding to the on-chip system supporting timestamp capture provided in the above embodiments, this disclosure also provides a timestamp capture method based on an on-chip system.

[0134] Figure 3 This is a flowchart illustrating an exemplary embodiment of a timestamp capture method based on a system-on-a-chip. Figure 3 As shown, this on-chip system-based timestamp capture method can be applied to, for example... Figure 1 The on-chip system 10 shown supports timestamp capture and may include steps 301 to 306 as follows.

[0135] Step 301: Send a data acquisition command to the target sensor via the communication controller.

[0136] Step 302: The communication controller receives valid sensor data transmitted by the target sensor in response to the first data buffer and generates a first start signal.

[0137] Step 303: In response to the first start signal, the first DMA controller reads valid sensor data from the first data buffer and writes the valid sensor data into the data buffer of the preset memory.

[0138] Step 304: The communication controller receives the placeholder data transmitted by the target sensor in response to the first data buffer and generates a second start signal.

[0139] Step 305: In response to the second start signal, the first DMA controller reads the current time value of the preset clock and writes the current time value of the preset clock as the timestamp corresponding to the valid data of the sensor into the data buffer; and after writing the current time value into the data buffer, transmits a read interrupt signal to the processor.

[0140] Step 306: The processor responds to the read interrupt signal and reads the valid sensor data and the timestamp corresponding to the valid sensor data from the data buffer.

[0141] like Figure 4 As shown above, in the above Figure 3Based on the embodiment shown, step 303, in response to the first start signal, reads valid sensor data from the first data buffer and writes the valid sensor data into the data buffer of the preset memory, which may include the following steps 3031 to 3033.

[0142] Step 3031: In response to the first start signal, the first DMA controller reads the first descriptor from the descriptor memory area of ​​the preset memory.

[0143] The first descriptor is the first data transmission control parameter transmitted by the first DMA controller.

[0144] Step 3032: The first DMA controller reads valid sensor data from the first data buffer according to the first descriptor.

[0145] Step 3033: The first DMA controller writes the valid sensor data to the specified location in the data buffer according to the first descriptor.

[0146] In some embodiments of this disclosure, after step 3033 in which the first DMA controller writes the valid sensor data to a specified location in the data buffer according to the first descriptor, the method further includes: reading a second descriptor after the first descriptor through the first DMA controller; wherein the second descriptor is a second data transmission control parameter transmitted by the first DMA controller.

[0147] like Figure 5 As shown above, in the above Figure 3 Based on the embodiment shown, step 305, in which the first DMA controller responds to the second start signal, reads the current time value of the preset clock, and writes the current time value of the preset clock as the timestamp corresponding to the valid data of the sensor into the data buffer, may include the following steps 3051 and 3052.

[0148] Step 3051: In response to the second start signal, the first DMA controller reads the current time value of the network card from the network card's time register based on the second descriptor.

[0149] The preset clock includes the network card's precise hardware clock; the network card's current time value is the current time value of the time register, and the current time value of the time register is generated based on the precise hardware clock.

[0150] Step 3052: The first DMA controller, based on the second descriptor, writes the current time value of the network card as the timestamp corresponding to the valid sensor data into the data buffer and associates it with the specified location.

[0151] like Figure 6 As shown, in Figure 3 Based on the embodiment shown, in step 305, the first DMA controller responds to the second start signal, reads the current time value of the preset clock, and writes the current time value of the preset clock as the timestamp corresponding to the valid data of the sensor into the data buffer; after writing the current time value into the data buffer, after transmitting a read interrupt signal to the processor, the method further includes step 307.

[0152] Step 307: In response to the read interrupt signal, the processor clears the placeholder data in the first data buffer.

[0153] like Figure 7 As shown above, in the above Figure 3 Based on the embodiment shown, the on-chip system further includes a second DMA controller, and the communication controller further includes a second data buffer corresponding to the second DMA controller; step 301 sends a data acquisition command to the target sensor through the communication controller, which may include the following steps 3011 to 3013.

[0154] Step 3011: The communication controller generates a third start signal in response to the fact that the occupied space of the second data buffer is less than a preset data volume threshold.

[0155] Step 3012: In response to the third start signal, the second DMA controller reads the data acquisition instruction from the instruction buffer and writes the data acquisition instruction into the second data buffer.

[0156] Step 3013: Read the data acquisition command from the second data buffer through the communication controller and send the data acquisition command to the target sensor.

[0157] Regarding the timestamp capture method based on a system-on-a-chip in the above embodiments, the specific execution methods of each step and the corresponding beneficial effects have been described in detail in the corresponding embodiments of the system-on-a-chip part that supports data communication. Please refer to the corresponding execution methods and beneficial technical effects of the above exemplary system part, which will not be repeated here.

[0158] Exemplary device

[0159] Figure 8 This is a schematic diagram of the structure of a system-on-a-chip-based timestamp capture device provided in an exemplary embodiment of this disclosure. Figure 8 As shown, the system-on-chip-based timestamp capture device 80 may include a sending module 801, a first generation module 802, a first transport module 803, a second generation module 804, a second transport module 805, and a reading module 806.

[0160] The transmitting module 801 is used to send data acquisition commands to the target sensor through the communication controller;

[0161] The first generation module 802 is used to generate a first start signal in response to receiving valid sensor data transmitted by the target sensor through the first data buffer via the communication controller.

[0162] The first transport module 803 is used to read valid sensor data from the first data buffer and write the valid sensor data into the data buffer of a preset memory in response to the first start signal via the first DMA controller.

[0163] The second generation module 804 is used to generate a second start signal in response to the first data buffer receiving placeholder data transmitted by the target sensor through the communication controller.

[0164] The second transport module 805 is used to read the current time value of a preset clock in response to the second start signal via the first DMA controller, and write the current time value of the preset clock as the timestamp corresponding to the valid data of the sensor into the data buffer; and after writing the current time value into the data buffer, transmit a read interrupt signal to the processor.

[0165] The read module 806 is used to read the valid sensor data and the timestamp corresponding to the valid sensor data from the data buffer in response to the read interrupt signal by the processor.

[0166] In some embodiments, continue to refer to Figure 8 As shown, the first transport module 803 is specifically used to read a first descriptor from the descriptor memory area of ​​a preset memory in response to a first start signal via a first DMA controller; to read valid sensor data from a first data buffer according to the first descriptor via the first DMA controller; and to write the valid sensor data into a specified location in the data buffer according to the first descriptor via the first DMA controller; wherein, the first descriptor is a first data transmission control parameter transmitted by the first DMA controller.

[0167] In some embodiments, continue to refer to Figure 8 As shown, the first transport module 803 is further configured to read a second descriptor following the first descriptor through the first DMA controller; wherein the second descriptor is a second data transmission control parameter transmitted by the first DMA controller.

[0168] In some embodiments, continue to refer to Figure 8As shown, the second transport module 805 is specifically used to respond to the second start signal via the first DMA controller, and based on the second descriptor, read the current time value of the network card from the network card's time register; and, based on the second descriptor, write the current time value of the network card as the timestamp corresponding to the valid sensor data into the data buffer at the location associated with the specified location via the first DMA controller. The preset clock includes the network card's precise hardware clock; the current time value of the network card is the current time value of the time register, and the current time value of the time register is generated based on the precise hardware clock.

[0169] like Figure 9 As shown above, in the above Figure 8 Based on the embodiment shown, the system-on-chip-based timestamp capture device 80 further includes a clearing module 807, which is used to clear placeholder data in the first data buffer in response to a read interrupt signal by the processor.

[0170] Continue to refer to Figure 8 As shown, the sending module 801 is specifically used to generate a third start signal in response to the second data buffer's occupied space being less than a preset data volume threshold via the communication controller; to read data acquisition instructions from the instruction buffer and write the data acquisition instructions into the second data buffer via the second DMA controller in response to the third start signal; and to read data acquisition instructions from the second data buffer and send the data acquisition instructions to the target sensor via the communication controller.

[0171] Regarding the timestamp capture device based on a system-on-a-chip in the above embodiments, the specific methods of operation of each module and the corresponding beneficial effects have been described in detail in the corresponding embodiment section of the data communication method based on a system-on-a-chip section. Please refer to the corresponding operation methods and beneficial technical effects in the above exemplary method section, which will not be repeated here.

[0172] Exemplary vehicle

[0173] Figure 10 This is a schematic diagram of the structure of a vehicle provided in an exemplary embodiment of this disclosure. Figure 10 As shown, the vehicle 100 has a target sensor 1001 and a system-on-a-chip 1002.

[0174] The target sensor 1001 is used to collect valid sensor data and placeholder data in response to a data acquisition command, and transmit the valid sensor data and placeholder data to the system on-chip 1002; wherein the data acquisition command is a command sent by the communication controller in the system on-chip 1002 to the target sensor.

[0175] The system-on-a-chip 1002 is configured to: generate a first start signal in response to receiving valid sensor data from a first data buffer in a communication controller; read the valid sensor data from the first data buffer in the system-on-a-chip and write the valid sensor data into a data buffer of a preset memory in response to the first data buffer; generate a second start signal in response to receiving placeholder data from the first data buffer; read the current time value of a preset clock in the system-on-a-chip and write the current time value of the preset clock as the timestamp corresponding to the valid sensor data into the data buffer in response to the second start signal; and transmit a read interrupt signal to the processor in the system-on-a-chip after writing the current time value into the data buffer; and, in response to the read interrupt signal, read the valid sensor data and the timestamp corresponding to the valid sensor data from the data buffer.

[0176] The target sensor 1001 may be an IMU located in a stable region near the center of gravity of the vehicle 100 chassis. This embodiment of the present disclosure does not limit the location of the target sensor 1001; however, this embodiment uses the example of the target sensor 1001 being located in a stable region near the center of gravity of the vehicle 100 chassis for illustrative purposes.

[0177] The System-on-Chip 1002 can be used with, for example Figure 1 The system-on-chip 10 shown corresponds to, and the system-on-chip 10 can be an implementation of the system-on-chip 1002.

[0178] Exemplary electronic devices

[0179] Figure 11 This is a schematic diagram of the structure of an electronic device provided in an exemplary embodiment of this disclosure, such as... Figure 11 As shown, the electronic device 110 may include a processor 1101 and a memory 1102 for storing executable instructions of the processor 1101; wherein, the processor 1101 is used to read executable instructions from the memory 1102 and execute the instructions to implement the above-mentioned... Figures 3 to 7 The illustrated embodiment provides a timestamp capture method based on a system-on-a-chip.

[0180] The processor 1101 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 110 to perform desired functions.

[0181] The memory 1002 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 1001 may execute the program instructions to implement the on-chip system-based timestamp capture method and / or other desired functions of the various embodiments of this disclosure described above.

[0182] In one example, the electronic device 110 may also include an input device 1103 and an output device 1104, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0183] Of course, for the sake of simplicity, Figure 11 Only some of the components of the electronic device 110 relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device 110 may include any other suitable components depending on the specific application.

[0184] Exemplary computer program products and computer-readable storage media

[0185] In addition to the methods and apparatus described above, embodiments of this disclosure may also provide a computer program product, including computer program instructions that, when executed by a processor, cause the processor to perform the steps of the system-on-chip-based timestamp capture method described in the various embodiments of this disclosure in the "Exemplary Methods" section above.

[0186] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of embodiments of this disclosure. These programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0187] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions thereon, which, when executed by a processor, cause the processor to perform the steps in the system-on-chip-based timestamp capture methods of the various embodiments of this disclosure described in the "Exemplary Methods" section above.

[0188] Computer-readable storage media may take the form of any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may include, but is not limited to, systems, apparatuses, or devices that are electrical, magnetic, optical, electromagnetic, infrared, or semiconductor, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0189] The basic principles of this disclosure have been described above with reference to specific embodiments. However, the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0190] Various modifications and variations can be made to this disclosure without departing from its spirit and scope. Therefore, this disclosure is also intended to include such modifications and variations if they fall within the scope of the claims of this disclosure and their equivalents.

Claims

1. An on-chip system supporting timestamp capturing, comprising a preset clock, a processor, a communication controller and a first direct memory access controller; the communication controller comprises a first data buffer corresponding to the first direct memory access controller; the communication controller is configured to send a data collection instruction to a target sensor; and generate a first start signal in response to the first data buffer receiving sensor valid data transmitted by the target sensor; the first direct memory access controller is configured to read the sensor valid data from the first data buffer and write the sensor valid data into a data buffer area of a preset memory in response to the first start signal; the communication controller is further configured to generate a second start signal in response to the first data buffer receiving placeholder data transmitted by the target sensor; the first direct memory access controller is further configured to read a current time value of the preset clock and write the current time value of the preset clock as a timestamp corresponding to the sensor valid data into the data buffer area in response to the second start signal; and transmit a read interrupt signal to the processor after writing the current time value into the data buffer area; the processor is configured to read the sensor valid data and the timestamp corresponding to the sensor valid data from the data buffer area in response to the read interrupt signal.

2. The system on chip of claim 1, wherein, The first direct memory access controller is specifically configured to: read a first descriptor from a descriptor memory area of the preset memory in response to the first start signal; wherein the first descriptor is a first data transmission control parameter transmitted by the first direct memory access controller; read the sensor valid data from the first data buffer according to the first descriptor; write the sensor valid data into a specified position of the data buffer area according to the first descriptor.

3. The system on chip of claim 2, the first DMA controller is further configured to read a second descriptor after the first descriptor after writing the sensor valid data to the specified location of the data buffer. The second descriptor is a second data transmission control parameter transmitted by the first direct memory access controller.

4. The system on chip of claim 3, wherein, The first direct memory access controller is specifically configured to: read the current time value of the network card from a time register of the network card based on the second descriptor in response to the second start signal; wherein the preset clock comprises an accurate hardware clock of the network card; the current time value of the network card is a current time value of the time register, and the current time value of the time register is generated based on the accurate hardware clock; write the current time value of the network card as the timestamp corresponding to the sensor valid data into a position associated with the specified position in the data buffer area based on the second descriptor.

5. The system on chip of claim 1, wherein, The processor is further configured to clear the placeholder data in the first data buffer in response to the read interrupt signal.

6. The on-chip system of claim 1, further comprising a second direct memory access controller, and the communication controller further comprises a second data buffer corresponding to the second direct memory access controller. The communication controller is further configured to generate a third start signal in response to an occupied space of the second data buffer being less than a preset data amount threshold; The second DMA controller is further configured to read the data acquisition instruction from the instruction buffer in response to the third start signal, and write the data acquisition instruction into the second data buffer; The communication controller is further configured to read the data acquisition instruction from the second data buffer, and send the data acquisition instruction to the target sensor.

7. The system on chip of any one of claims 1-6, wherein, The preset clock comprises a precise hardware clock of a network card; the communication controller comprises a serial peripheral interface controller; the first DMA controller comprises a receiving DMA controller, and the second DMA controller comprises a sending DMA controller; the target sensor comprises an inertial measurement unit; the first data buffer comprises a receiving first-in-first-out queue, and the second data buffer comprises a sending first-in-first-out queue.

8. A system on chip based time stamp capturing method, the system on chip comprising a preset clock, a processor, a communication controller and a first direct memory access controller; The communication controller comprises a first data buffer corresponding to the first DMA controller; and the method comprises: sending, by the communication controller, the data acquisition instruction to the target sensor; generating, by the communication controller, a first start signal in response to the first data buffer receiving valid sensor data transmitted by the target sensor; reading, by the first DMA controller, the valid sensor data from the first data buffer in response to the first start signal, and writing the valid sensor data into a data buffer of a preset memory; generating, by the communication controller, a second start signal in response to the first data buffer receiving placeholder data transmitted by the target sensor; reading, by the first DMA controller, a current time value of the preset clock in response to the second start signal, and writing the current time value of the preset clock as a time stamp corresponding to the valid sensor data into the data buffer; and transmitting, by the first DMA controller, a read interrupt signal to the processor after writing the current time value into the data buffer; reading, by the processor, the valid sensor data and the time stamp corresponding to the valid sensor data from the data buffer in response to the read interrupt signal.

9. The method of claim 8, further comprising: clearing, by the processor, the placeholder data in the first data buffer in response to the read interrupt signal.

10. The method of claim 8, wherein, The SoC further comprises a second DMA controller, and the communication controller further comprises a second data buffer corresponding to the second DMA controller; and the sending, by the communication controller, the data acquisition instruction to the target sensor comprises: generating, by the communication controller, a third start signal in response to an occupied space of the second data buffer being less than a preset data amount threshold; reading, by the second DMA controller, the data acquisition instruction from the instruction buffer in response to the third start signal, and writing the data acquisition instruction into the second data buffer; reading the data acquisition instruction from the second data buffer through the communication controller and sending the data acquisition instruction to the target sensor. 11.A vehicle comprising a target sensor and the system on chip according to any one of claims 1-7. The target sensor is configured to collect sensor valid data and placeholder data in response to a data collection instruction, and transmit the sensor valid data and the placeholder data to the system on chip. The data acquisition instruction is an instruction sent by a communication controller in the system on chip to a target sensor. The system on chip is configured to generate a first start signal in response to the first data buffer in the communication controller receiving the sensor valid data. In response to the first start signal, the sensor valid data is read from the first data buffer in the system on chip and written into a data buffer area of a preset memory. In response to the second start signal, a current time value of a preset clock in the system on chip is read and written into the data buffer area as a time stamp corresponding to the sensor valid data. 12.An electronic device comprising: a processor; a memory for storing executable instructions of the processor; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the system on chip based time stamp capturing method according to any one of claims 8-10. 13.A computer readable storage medium, the storage medium storing a computer program, the computer program being executed by a processor to implement the system on chip based time stamp capturing method according to any one of claims 8-10.

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