Semiconductor processing scheduling method, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a semiconductor processing scheduling method, electronic equipment and a storage medium. The method comprises the following steps: initializing an expansion search node set according to the current real-time state of the semiconductor processing equipment; the expanded search node set comprises wafer distribution corresponding to expanded search nodes, a corresponding current real-time state set and an optimal real-time state; the current real-time state in the current real-time state set comprises an action sequence and time information corresponding to the state; updating the real-time state of the expanded search node based on a pruning strategy, and updating the expanded search node set based on the updated real-time state; the pruning strategy filters the triggering action for updating the real-time state; and calculating an optimal scheduling path corresponding to the real-time state of the expanded search node based on the updated expanded search node set. According to the scheme of the embodiment, the scheduling failure phenomenon under the condition that the optimal action sequence does not meet the process time constraint or deadlock avoidance requirement is avoided, and the algorithm search efficiency is improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor processing scheduling method, electronic device, and storage medium. Background Technology

[0002] Semiconductor processing is one of the most advanced and complex manufacturing industries today. To meet the complexity and precision requirements of semiconductor processing, semiconductor processing equipment is often composed of multiple modules. For example, commonly used wafer fabrication cluster equipment typically includes a chamber, a vacuum transceiver (VTR), a loadlock, and an atmospheric side module (EFEM). The EFEM module can be further broken down into an atmospheric transceiver (ATR), a loading port (LP), an alignment point, and a cooling point, such as... Figure 1 As shown, the scheduling of semiconductor processing equipment involves rationally arranging the flow of all processed wafers through various modules within the equipment to improve production efficiency while meeting process requirements.

[0003] The core of semiconductor processing equipment scheduling is to fully consider the complex interactions between various objects such as processing modules (chambers, calibration positions, cooling positions), robotic arms, loading ports, and vacuum locks, and to rationally arrange the complex sequence and timetable of wafer pick-up, wafer placement, and processing operations in the system to minimize the time required to process a certain number of wafers. Therefore, the semiconductor processing equipment scheduling problem is a typical NP-hard problem. Summary of the Invention

[0004] This disclosure provides a semiconductor processing scheduling method, an electronic device, and a storage medium.

[0005] In a first aspect, embodiments of this disclosure provide a semiconductor processing scheduling method, the method comprising:

[0006] Based on the current real-time state St0 of the semiconductor processing equipment, initialize the extended search node set Φ; wherein, the extended search node set includes the wafer distribution M corresponding to each extended search node, the current real-time state set Sts0 corresponding to the wafer distribution M, and the optimal real-time state in the current real-time state set Sts0. Each current real-time state St0 in the current real-time state set Sts0 contains the action sequence and time information corresponding to the current real-time state St0;

[0007] The real-time state of the extended search nodes is updated based on a preset pruning strategy, and the set of extended search nodes Φ is updated based on the new real-time state of the updated extended search nodes; the pruning strategy is used to filter the triggering actions required to update the real-time state.

[0008] Based on the updated set of expanded search nodes Φ, calculate the optimal scheduling path corresponding to the real-time status of the expanded search nodes.

[0009] Secondly, embodiments of this disclosure provide an electronic device, the electronic device comprising:

[0010] One or more processors;

[0011] A memory having stored one or more programs that, when executed by one or more processors, cause the one or more processors to implement the semiconductor processing scheduling method.

[0012] Thirdly, embodiments of this disclosure provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the semiconductor processing scheduling method.

[0013] In this embodiment of the disclosure, an extended search node set Φ is initialized based on the current real-time state St0 of the semiconductor processing equipment; wherein, the extended search node set Φ includes the wafer distribution M corresponding to each extended search node, the current real-time state set Sts0 corresponding to the wafer distribution M, and the optimal real-time state in the current real-time state set Sts0. Each current real-time state St0 in the current real-time state set Sts0 contains the action sequence and time information corresponding to that current real-time state St0. Based on the aforementioned extended search node set Φ, different action sequences and their historical time records for the current real-time state St0 corresponding to the same wafer distribution are preserved. This supports the subsequent implementation of complex deadlock avoidance and process time constraints unique to semiconductor processing equipment scheduling in the algorithm, effectively preventing scheduling failures caused by the current shortest path search algorithm only recording wafer distribution M and its corresponding optimal action sequence when the corresponding optimal action sequence does not meet process time constraints or deadlock avoidance requirements. This ensures that the shortest path search algorithm can still cover suboptimal paths. In addition, by storing the optimal real-time state of each extended search node corresponding to each wafer distribution M in real time, This allows the algorithm to maintain high search efficiency, approaching that of current shortest path search algorithms, during the search process. Furthermore, in this embodiment, the real-time state of the expanded search nodes is updated based on a preset pruning strategy, and the set of expanded search nodes Φ is updated based on the new real-time state of the updated expanded search nodes. This pruning strategy filters the triggering actions required to update the real-time state, thereby retaining only a certain number of optimal actions to generate new real-time states, thus improving the algorithm's search efficiency. Attached Figure Description

[0014] In the accompanying drawings of the embodiments disclosed herein:

[0015] Figure 1 This is a schematic diagram of the structure of a clustering device for wafer fabrication in related technologies;

[0016] Figure 2 This is a flowchart of a semiconductor processing scheduling method provided in an embodiment of the present disclosure;

[0017] Figure 3 A flowchart of a method for initializing an expanded search node set based on the current real-time state St0 of the semiconductor processing equipment, provided in an embodiment of this disclosure;

[0018] Figure 4 A flowchart illustrating a method for initializing an expanded search node set based on first state data, provided in an embodiment of this disclosure;

[0019] Figure 5 A flowchart of a method for initializing the extended search node set into a set consisting solely of the root extended search node Nd0 corresponding to the current real-time state St0 = (M,R,T,PT,F) according to an embodiment of this disclosure;

[0020] Figure 6 A schematic diagram illustrating the differences between the expanded search nodes of the improved shortest path search algorithm provided in this embodiment and the search nodes of the traditional shortest path search algorithm.

[0021] Figure 7 A flowchart of a method for updating the real-time state of extended search nodes based on a preset pruning strategy, and updating the set of extended search nodes based on the new real-time state of the updated extended search nodes, provided in this embodiment of the disclosure.

[0022] Figure 8 The present disclosure provides an embodiment that uses first state data as the optimization target to select the optimal extended search node Nd from the extended search node set Φ. i And update the optimal extended search node Nd. i Flowchart of the method for achieving optimal real-time state;

[0023] Figure 9 The optimal extended search node Nd provided in this embodiment of the disclosure i The optimal real-time state is determined by filtering the optimal action set based on the action trigger time. Method flowchart;

[0024] Figure 10 The optimal set of triggering actions provided in the embodiments of this disclosure The flowchart shows the method for updating and expanding the search node set based on the new real-time state obtained after each action is triggered.

[0025] Figure 11 A flowchart illustrating a method for adding a new real-time state to an expanded search node set Φ, as provided in this embodiment of the disclosure;

[0026] Figure 12 This is a block diagram of an electronic device provided in an embodiment of the present disclosure. Detailed Implementation

[0027] To enable those skilled in the art to better understand the technical solutions of this disclosure, the communication-sensing data processing method and computer-readable storage medium provided in the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0028] The accompanying drawings of the embodiments disclosed herein are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the detailed embodiments to explain this disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the description of the detailed embodiments with reference to the accompanying drawings.

[0029] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0030] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. The term "and / or" as used in this disclosure includes any and all combinations of one or more of the associated enumerated entries. The singular forms "a" and "the" as used in this disclosure are also intended to include the plural forms, unless the context clearly indicates otherwise. The terms "comprising," "made of," etc., as used in this disclosure specify the presence of the stated feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0031] Unless otherwise specified, all terms used in this disclosure (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined in this disclosure.

[0032] Semiconductor processing is one of the most advanced and complex manufacturing industries today. To meet the complexity and precision requirements of semiconductor processing, semiconductor processing equipment is often composed of multiple modules. For example, commonly used wafer fabrication cluster equipment typically includes a chamber, a vacuum transceiver (VTR), a loadlock, and an atmospheric side module (EFEM). The EFEM module can be further broken down into an atmospheric transceiver (ATR), a loading port (LP), an alignment point, and a cooling point, such as... Figure 1 As shown, the scheduling of semiconductor processing equipment involves rationally arranging the flow of all processed wafers through various modules within the equipment to improve production efficiency while meeting process requirements.

[0033] The core of semiconductor processing equipment scheduling is to fully consider the complex interactions between various objects such as processing modules (chambers, calibration positions, cooling positions), robotic arms, loading ports, and vacuum locks, and to rationally arrange the complex sequence and timetable of wafer pick-up, wafer placement, and processing operations in the system to minimize the time required to process a certain number of wafers. Therefore, the semiconductor processing equipment scheduling problem is a typical NP-hard problem.

[0034] In terms of scheduling modes, semiconductor processing equipment scheduling can currently be divided into two types: periodic scheduling and aperiodic scheduling. Periodic scheduling primarily seeks a stable and repeatable sequence of periodic actions (the length of which is much smaller than the total number of processing actions for all wafers). Within this sequence, all schedulable wafers advance to the next processing action, minimizing the cycle time of the sequence to optimize the completion time of all wafers. Aperiodic scheduling, on the other hand, directly seeks the sequence of processing actions that minimizes the completion time of all wafers. Its computation time is longer than periodic scheduling, but it offers better flexibility and versatility. In practical applications, although periodic scheduling has the advantage of faster computation time, the scheduling problem may not have a stable scheduling cycle, and its applicability is narrower due to its lack of flexibility in many scheduling requirements, such as uncertain processing times, multiple types of cleaning trigger rules, and temporarily inserted scheduling tasks. With the improvement of computer processing power, aperiodic scheduling has gained widespread application.

[0035] Aperiodic scheduling can be further divided into two types: global scheduling and real-time scheduling. Global scheduling, which requires solving for the sequence of all processing actions on all wafers at once, produces a high-quality scheduling plan, but it is time-consuming and unsuitable for scenarios with significant changes in the scheduling environment or the objects being scheduled. Real-time scheduling, which does not require solving for the sequence of all processing actions on all wafers at once, but only needs to determine a certain length of processing action sequence, typically yields only one satisfactory solution. However, it offers better scheduling efficiency and applicability to fluctuating scenarios, and has been widely used in semiconductor processing equipment scheduling.

[0036] Currently, the scheduling methods applied to real-time scheduling of semiconductor processing equipment mainly fall into two categories: real-time scheduling based on historical scheduling data and rules, and real-time scheduling based on tree search. Real-time scheduling based on historical scheduling data and rules faces difficulties in constructing, maintaining, and iterating historical data and rule bases in practical applications. In contrast, real-time scheduling based on tree search can flexibly change the structure of the search tree according to different scheduling needs, offering high controllability, flexibility, and scalability, making it widely used in practice. However, due to the long tree search process, its scheduling search efficiency is typically low.

[0037] Currently, a tree-search-based material scheduling method has been proposed in related technologies. This method starts from an initial state and continuously determines the scheduling action for the next material based on the current material transport path information, updating the system state and generating a new child node, until all material scheduling actions are completed and the search tree generates its last child node. By traversing all paths from the root node to the last child node in the search tree, the action sequence corresponding to the shortest path is ultimately used as the action sequence of the scheduling plan. This technical solution involves searching and traversing the entire semiconductor processing equipment state tree. Because it does not effectively prune the entire search tree or employ intelligent algorithms for efficient node searching, its scheduling efficiency is relatively low, making it difficult to meet the real-time requirements of semiconductor processing equipment scheduling, and the quality of the solutions obtained in a short time is also unsatisfactory.

[0038] Currently, some related technologies abroad have proposed a periodic scheduling scheme calculation method considering dwell time constraints for single-arm, single-cascaded devices (cluster tools) through analytical analysis and deduction of relevant scheduling rules and strategies. However, this technical solution is only applicable to single-arm, single-cascaded devices (cluster tools) and cannot be applied to dual-arm or multi-cluster tools. Currently, dual-arm, multi-cascaded semiconductor processing equipment is the mainstream. The solution in this application needs to solve the real-time scheduling problem for different arm types and different cascade types. Furthermore, this technical solution is a periodic scheduling solution considering dwell time constraints, and is only applicable to periodic scheduling modes. Periodic scheduling, due to its lack of flexibility and narrow applicability, differs fundamentally from real-time scheduling under non-periodic scheduling modes (see background technology analysis). Therefore, this technical solution cannot solve the real-time scheduling problem under complex process time constraints and deadlock avoidance requirements that this disclosure aims to address.

[0039] The A-Star algorithm is an efficient method for finding the shortest path in static road networks. The formula for the A-Star algorithm is: f(n) = g(n) + h(n), where f(n) is the cost function of node n (n is a positive integer) from the initial point to the target point, g(n) is the actual cost from the initial node to node n in the state space, and h(n) is the estimated cost of the optimal path from n to the target node. In recent years, the A-Star algorithm, as an intelligent algorithm, has demonstrated high versatility and search efficiency in tree structure search, and has been widely applied in complex topology network pathfinding problems such as vehicle navigation, autonomous driving, and robot scheduling. Therefore, using the efficient A-Star algorithm to search the scheduling state tree of semiconductor processing equipment has become a solution to improve the versatility and efficiency of semiconductor processing equipment scheduling. However, since the original A-Star algorithm only supports the complete process search from the start point to the end point, further optimization is needed for its application in real-time scheduling plan search. Furthermore, it does not consider the deadlock avoidance and process time constraints unique to semiconductor processing equipment scheduling during the search, making it difficult to directly apply to the real-time scheduling of semiconductor processing equipment. Therefore, appropriate improvements are necessary.

[0040] Currently, a system scheduling method based on Petri nets (a mathematical representation of discrete parallel systems) and heuristic search has been proposed in related technologies. First, Petri nets are used to model the constituent elements of the manufacturing system, resulting in a Petri net model of the system. Second, the system resources in the Petri net model are initialized, and the A-Star search algorithm based on cost estimation is used to search the Petri net model, obtaining a partial reachability graph. Finally, with the minimum system operating cost as the objective function, an improved fruit fly optimization algorithm is used for path optimization, and the path that minimizes the objective function is output as the scheduling path. This technical solution uses the A-Star search algorithm combined with the fruit fly optimization algorithm to solve the global batch scheduling path. This method is a general solution using the original A-Star algorithm, but it does not consider the complex process time constraints and deadlock avoidance requirements of semiconductor processing equipment scheduling. Under the constraints of process time and deadlock avoidance in semiconductor processing equipment scheduling, a wafer distribution state may be achieved by multiple processing action sequences. However, each processing action sequence may not necessarily meet the deadlock avoidance and process time constraints. The existing A-Star algorithm only considers a single optimal action sequence for its search nodes and performs scheduling plan search based on this sequence. This may result in the inability to find a feasible solution that meets the requirements, leading to scheduling failure. Therefore, it is difficult to directly apply to the real-time scheduling problem of semiconductor processing equipment.

[0041] This disclosure addresses the real-time scheduling problem of semiconductor processing equipment under complex process time constraints and deadlock avoidance requirements. Building upon current shortest path search algorithms (e.g., A-star algorithm), it proposes a new extended search node to replace the search nodes in current shortest path search algorithms, addressing the scheduling failure problem caused by considering only a single optimal action sequence. Based on the characteristics of semiconductor processing equipment scheduling problems, it presents detailed methods and steps for selecting, filtering, and updating the algorithm's search nodes based on the new extended search node. During the search process, it avoids infeasible solutions that do not meet process time constraints and deadlock avoidance requirements, achieving efficient real-time scheduling of semiconductor processing equipment under complex process time constraints and deadlock avoidance requirements.

[0042] Specifically, in this embodiment of the present disclosure, an extended search node set is initialized based on the current real-time state St0 of the semiconductor processing equipment; wherein, the extended search node set includes the wafer distribution M corresponding to each extended search node, the current real-time state set Sts0 corresponding to the wafer distribution M, and the optimal real-time state in the current real-time state set Sts0. Each current real-time state St0 in the current real-time state set Sts0 contains the action sequence and time information corresponding to that current real-time state St0. Based on the aforementioned extended search node set, different action sequences and their historical time records for the current real-time state St0 corresponding to the same wafer distribution are preserved. This supports the subsequent implementation of complex deadlock avoidance and process time constraints unique to semiconductor processing equipment scheduling in the algorithm, effectively preventing scheduling failures caused by the current shortest path search algorithm only recording wafer distribution M and its corresponding optimal action sequence when the corresponding optimal action sequence does not meet process time constraints or deadlock avoidance requirements. This ensures that the shortest path search algorithm can still cover suboptimal paths. In addition, by storing the optimal real-time state of each extended search node corresponding to wafer distribution M in real time, This allows the algorithm to maintain high search efficiency, approaching that of current shortest path search algorithms, during the search process. Furthermore, this embodiment updates the real-time state of the expanded search nodes based on a preset pruning strategy, and updates the expanded search node set based on the new real-time state of the updated expanded search nodes. This pruning strategy filters the triggering actions required to update the real-time state, ensuring that only a certain number of optimal actions are retained to generate new real-time states, thus improving the algorithm's search efficiency.

[0043] The embodiments of this disclosure will be described in detail below.

[0044] This disclosure provides a semiconductor processing scheduling method, such as... Figure 2 As shown, the method may include steps S11-S13:

[0045] S11. Based on the current real-time state St0 of the semiconductor processing equipment, initialize the extended search node set; wherein, the extended search node set includes the wafer distribution M corresponding to each extended search node, the current real-time state set Sts0 corresponding to the wafer distribution M, and the optimal real-time state in the current real-time state set Sts0. Each current real-time state St0 in the current real-time state set Sts0 includes the action sequence and time information corresponding to that current real-time state St0.

[0046] In this embodiment of the disclosure, the scheme can be implemented based on a preset shortest path search algorithm, which may include, but is not limited to, the A-star algorithm. The extended search node set refers to the node set of the shortest path search algorithm.

[0047] In this embodiment of the disclosure, before initializing the extended search node set according to the current real-time state St0 of the semiconductor processing equipment, the method may further include:

[0048] Based on the hardware configuration of semiconductor processing equipment and the wafer processing path, construct action triggering rules for scheduling semiconductor processing equipment.

[0049] In this embodiment of the disclosure, the various modules in the semiconductor processing equipment include a robotic arm module and a processing module (including an LP (load port), a Loadlock (vacuum lock), a processing chamber, a cooling position, and a calibration position). The scheduling actions in the semiconductor processing equipment include two types: wafer picking and wafer placement. The wafer picking action involves using the robotic arm to remove the wafer from the processing module and place it onto the robotic arm, while the wafer placement action involves placing the wafer from the robotic arm into the processing module.

[0050] In this embodiment of the disclosure, before constructing the action triggering rules for semiconductor processing equipment scheduling based on the set of wafer processing paths, it is necessary to first clarify the wafer distribution involved in the semiconductor processing equipment scheduling problem proposed in this embodiment of the disclosure. This wafer distribution can be represented by M. Under a specific semiconductor processing equipment scheduling problem, the wafer distribution M of the semiconductor processing equipment represents the situation where each module in the semiconductor processing equipment is occupied by wafers at a certain moment. When any module is occupied by a wafer, the occupancy status of that module can be identified by a list indicating the wafer occupying that module; otherwise, the list indicating the occupancy status of that module is empty.

[0051] In this embodiment of the disclosure, the action triggering rules for scheduling the semiconductor processing equipment are constructed based on the hardware configuration of the semiconductor processing equipment and the wafer processing path, which may include:

[0052] Clarify the wafer distribution involved in the semiconductor processing equipment scheduling problem;

[0053] Under the wafer distribution, if any first action a satisfies the first preset triggering condition, it is confirmed that the first action a is triggerable.

[0054] In this embodiment of the disclosure, the first preset triggering condition may include, but is not limited to:

[0055] The first action, 'a', needs to be executed according to the wafer fabrication path requirements, but has not yet been executed in the wafer distribution action sequence R; and...

[0056] The preceding steps of the first action a have unused resources.

[0057] In this embodiment of the disclosure, the action triggering rule for semiconductor processing equipment scheduling can be constructed based on the hardware configuration of the semiconductor processing equipment and the wafer processing path. This can include: under a certain wafer distribution, if a certain first action a (such as wafer picking or placing) needs to be executed according to the requirements of the wafer processing path, and has not yet been executed in the action sequence R that arrives at the wafer distribution, and at the same time, there are wafers in the preceding steps of the first action a, and the resources required by the first action a are not completely occupied by other wafers (for example, there are still spare processing slots available for the first action a), then the first action a is triggerable.

[0058] In the embodiments disclosed herein, such as Figure 3 As shown, based on the current real-time state St0 of the semiconductor processing equipment, the shortest path search expansion node set is initialized, including steps S21-S22:

[0059] S21. Calculate the first state data under the current real-time state St0.

[0060] In this embodiment of the disclosure, the first state data refers to data that can indicate the current real-time state St0, and the first state data may include, but is not limited to, time data, location data, action data, etc.

[0061] In embodiments of this disclosure, for example, the first state data may include: a heuristic prediction of the completion time point F.

[0062] In this embodiment of the disclosure, calculating the first state data under the current real-time state includes:

[0063] Extract the current system time point T from the current real-time state St0 of the semiconductor processing equipment;

[0064] Under the current real-time state St0, the heuristic prediction of the completion time F under the current real-time state St0 is calculated based on the current system time point T and the preset first calculation formula.

[0065] In this embodiment of the disclosure, state information can be extracted from the current real-time state St0 of the semiconductor processing equipment. This state information may include, but is not limited to, any one or more of the following: wafer distribution M, the action sequence R from the initial state to the current wafer distribution M, the current system time point T, and the set of trigger times PT corresponding to all actions in the action sequence R, wherein the current system time point T is the trigger time of the last action in the action sequence R; and the set of all action trigger times PT is the set of all action trigger times in the action sequence R.

[0066] In this embodiment of the disclosure, the extracted state information includes the current system time point T, and the heuristically predicted completion time point F can be calculated based on the current system time point T.

[0067] In this embodiment of the disclosure, the first calculation formula may include:

[0068] F = T + H;

[0069]

[0070] Where F is the predicted completion time of the modified heuristic, H is the predicted remaining completion time, and γ is the proportion of remaining processing steps under the current real-time state St0.

[0071] In this embodiment of the disclosure, under the current real-time state, the heuristically predicted completion time F of the entire scheduling task is the current system time T plus the predicted remaining completion time H.

[0072] In this embodiment of the disclosure, the remaining completion time H can be predicted by evaluating the proportion γ of the remaining processing steps in the entire scheduling task at the current time point to the total time consumed by all steps in the entire scheduling task, and then using this proportion γ to calculate the remaining completion time H.

[0073] In this embodiment of the disclosure, the predicted remaining completion time H can also be calculated by other methods, such as, but not limited to, the module load method.

[0074] S22. Based on the first state data, initialize the expanded search node set.

[0075] In this embodiment, it is known that in traditional shortest path search algorithms (such as the A-star algorithm), a search node can only contain one optimal real-time state. Based on the characteristics of the semiconductor processing equipment scheduling problem, since a wafer distribution M may be reached by multiple processing action sequences, and each processing action sequence does not necessarily satisfy deadlock avoidance and process time constraints, the discrete distribution state of a wafer distribution M will correspond to multiple real-time states (each action can correspond to one real-time state), which can be represented as (M,R), that is, multiple action sequences corresponding to a wafer distribution M. This embodiment proposes a new extended search node, which includes the wafer distribution M and its corresponding set of real-time states, rather than a single optimal real-time state in the traditional shortest path search algorithm. In this way, the complex deadlock avoidance and process time constraints unique to semiconductor processing equipment scheduling can be fully considered, effectively preventing scheduling failures caused by the traditional shortest path search algorithm only recording the wafer distribution M and its corresponding optimal action sequence when the corresponding optimal action sequence does not meet process time constraints or deadlock avoidance requirements. The improved shortest path search algorithm of this application can still cover suboptimal paths. The detailed initialization scheme is described below.

[0076] In the embodiments disclosed herein, such as Figure 4As shown, the first state data includes: heuristically predicted completion time point F; based on the first state data, initializing the expanded search node set may include steps S31-S33:

[0077] S31. Obtain the state information of the current real-time state St0; the state information includes any one or more of the following: wafer distribution M, action sequence R from the initial state to the current wafer distribution M, the current system time point T, the set of trigger times PT corresponding to all actions in the action sequence R, and the above-mentioned heuristic prediction completion time point F.

[0078] S32. Based on the status information, the current real-time status St0 is represented as: St0 = (M, R, T, PT, F).

[0079] In this embodiment of the disclosure, based on the wafer distribution M, the action sequence R, the current system time T, the set of trigger times PT for all actions in the action sequence R, and the heuristically predicted completion time F calculated in the preceding steps, the current real-time state St0 can be represented as (M, R, T, PT, F). The current real-time state St0 not only represents the current wafer distribution and system time, but also the action sequence from the initial state to the wafer distribution, the trigger time of each action, and the prediction of the future completion time (i.e., the heuristically predicted completion time F).

[0080] S33. Based on the current real-time state St0 = (M, R, T, PT, F), initialize the extended search node set to a set consisting solely of the root extended search node Nd0 corresponding to the current real-time state St0.

[0081] In the embodiments disclosed herein, such as Figure 5 As shown, based on the current real-time state St0 = (M, R, T, PT, F), the set of extended search nodes is initialized to be a set consisting solely of the root extended search node Nd0 corresponding to the current real-time state St0, including steps S41-S45:

[0082] S41. Obtain the current real-time state set Sts0 of the root extended search node Nd0; the current real-time state set Sts0 is the set of all current real-time states St0 corresponding to the root extended search node Nd0, and the current real-time state set Sts0 is represented as: Sts0 = {St0}.

[0083] S42. Determine the wafer distribution M corresponding to the root expansion search node Nd0.

[0084] S43. Obtain the earliest current real-time state St0 from the current real-time state set Sts0, which is the optimal real-time state at the current time T.

[0085] S44. The root extended search node Nd0 is represented as:

[0086] S45. Initialize the extended search node set to a set Φ consisting solely of the root extended search node Nd0 corresponding to the current real-time state St0, where Φ = {Nd0}.

[0087] In this embodiment of the disclosure, the wafer distribution of the root expansion search node is denoted as M, and the current real-time state set Sts0 of the root expansion search node is denoted as {St0}. The earliest real-time state at the current time point T in the current real-time state set Sts0 is the optimal real-time state. This is the current real-time state St0 (because there is only one element in the current real-time state set Sts0 at the initial moment), so the root expansion search node Nd0 can be denoted as Therefore, in the improved shortest path search algorithm, the initial extended search node set Φ is initialized as a set Φ = {Nd0} consisting of the root extended search node corresponding to the current real-time state.

[0088] In this embodiment, based on the aforementioned extended search node set Φ, different action sequences reaching the same wafer distribution and their historical time records are all saved. This supports the subsequent implementation of complex deadlock avoidance and process time constraints unique to semiconductor processing equipment scheduling in the algorithm, effectively preventing scheduling failures caused by traditional shortest path search algorithms that only record wafer distribution M and its corresponding optimal action sequence when the corresponding optimal action sequence does not meet process time constraints or deadlock avoidance requirements. Furthermore, in this embodiment, the optimal real-time state of each extended search node corresponding to wafer distribution M is stored in real time. This allows the improved shortest path search algorithm to maintain its high efficiency, which is close to that of the traditional shortest path search algorithm, during the search process.

[0089] In this embodiment of the disclosure, a schematic diagram illustrating the differences between the expanded search nodes of the improved shortest path search algorithm and the search nodes of the traditional shortest path search algorithm is shown below. Figure 6 As shown.

[0090] S12. Update the real-time status of the extended search nodes in the extended search node set. Update the extended search node set based on a preset pruning strategy and the new real-time status of the updated extended search nodes. The pruning strategy is used to filter the triggering actions required to update the real-time status.

[0091] In the embodiments disclosed herein, such as Figure 7As shown, the real-time state of the expanded search nodes is updated based on a preset pruning strategy, and the set of expanded search nodes is updated based on the new real-time state of the expanded search nodes obtained from the update, including steps S51-S53:

[0092] S51. Using the first state data as the optimization objective, select the optimal extended search node Nd from the extended search node set Φ. i And update the optimal extended search node Nd i The optimal real-time state.

[0093] In the embodiments disclosed herein, such as Figure 8 As shown, the first state data includes: heuristically predicted completion time F; using the first state data as the optimization objective, the optimal extended search node Nd is selected from the extended search node set Φ. i And update the optimal extended search node Nd. i The optimal real-time state may include steps S61-S65:

[0094] S61. Determine the earliest heuristically predicted completion time F from the extended search node set Φ, and use it as the optimal extended search node Nd. i .

[0095] In this embodiment of the disclosure, the optimal extended search node Nd i The corresponding real-time state action path length is i.

[0096] S62, Expand the search node Nd from the optimal node Nd i The corresponding first real-time state set Sts i Obtain the earliest first optimal real-time state of the system at the current time T. As the optimal extended search node Nd i The corresponding optimal real-time state.

[0097] S63, From the first real-time state set Sts i Remove the first optimal real-time state. Obtain the second real-time state set Sts i _1.

[0098] S64, in the second real-time state set Sts i If no element exists in _1, remove the optimal expanded search node Nd from the expanded search node set Φ. i .

[0099] S65, in the second real-time state set Sts i If an element exists in _1, then from the second real-time state set Sts iSelect the earliest target real-time state from _1 at the current system time T. As the optimal extended search node Nd i The new optimal real-time state.

[0100] In this embodiment, the extended search node set Φ is the wafer distribution M and its corresponding real-time state set. A further proposed scheme for selecting the optimal extended search node in the improved shortest path search algorithm is: from the extended search node set Φ, the extended search node with the earliest heuristically predicted completion time F is selected as the optimal extended search node Nd. i , or optimal node Nd for short i .

[0101] In this embodiment of the disclosure, the optimal node Nd is further updated. i Optimal real-time state: Obtain the optimal node Nd i First optimal real-time state From the optimal node Nd i The first real-time state set Sts i Remove the first optimal real-time state. Obtain the second real-time state set Sts i _1. Remove the first optimal real-time state Afterwards, if the new Sts i (i.e., the second real-time state set Sts) i _1) If it contains no elements, then remove the optimal node Nd from the node set Φ. i Otherwise, from the new Sts i Select the earliest target real-time status at the current system time T. As the optimal node Nd i The new optimal real-time state.

[0102] In this embodiment of the disclosure, the above scheme enables the improved shortest path search algorithm to perform path search along the direction of the earliest heuristically predicted completion time F.

[0103] S52, Based on the optimal extended search node Nd i The optimal real-time state is determined by filtering the optimal action set based on the action trigger time.

[0104] In this embodiment of the disclosure, in order to meet the real-time requirements of semiconductor processing equipment scheduling, this embodiment of the disclosure introduces the idea of ​​pruning in the improved shortest path search algorithm to filter triggerable actions, retaining only a certain number of optimal actions to generate new real-time states, thereby improving the algorithm's search efficiency.

[0105] In this embodiment of the disclosure, the action triggering time includes, but is not limited to, the predicted triggering time of the action.

[0106] In the embodiments disclosed herein, such as Figure 9 As shown, based on the optimal extended search node Nd i The optimal real-time state is determined by filtering the optimal action set based on the action trigger time. This may include steps S71-S73:

[0107] S71. Determine the optimal extended search node Nd based on the preset action trigger rules. i The set of triggerable actions in the optimal real-time state is called the initial optimal action set.

[0108] S72. Calculate the initial optimal action set under the current real-time state. Predicted trigger time Pt ​​for all actions b .

[0109] In this embodiment of the disclosure, for the initial optimal action set The predicted trigger time Pt ​​of any second action b in the current real-time state b It can be calculated using the following formula:

[0110] Pt b =max(Ot) b ,Rt r )

[0111] Where r represents the module (robotic arm or processing module) required to execute the second action b, and according to the process sequence, the process execution time of the second action b is Ot. b The future availability time of the required module r is Rt. r .

[0112] S73. Based on the initial optimal action set Predicted trigger time Pt ​​for all actions b For the initial optimal action set Sort all actions in ascending order and obtain the first m predicted trigger times Pt. b The earliest actions constitute the filtered optimal action set. m is a positive integer.

[0113] S53. Trigger each action in the optimal action set, obtain the new real-time state after triggering each action, and update and expand the search node set based on the new real-time state.

[0114] In this embodiment, the extended search nodes are the wafer distribution M and its corresponding real-time state set. Considering the various process constraints of the semiconductor processing equipment scheduling state, an improved shortest path search algorithm with optimal node expansion rules and extended search node set update rules is further proposed.

[0115] In the embodiments disclosed herein, such as Figure 10 As shown, triggering the optimal action set For each action in the process, obtain the new real-time state obtained after triggering each action, and update and expand the search node set based on the new real-time state, including steps S81-S83:

[0116] S81. Based on the filtered optimal action set Trigger the optimal action set respectively Each action in the process yields a new real-time state.

[0117] In this embodiment of the disclosure, based on the filtered optimal action set Triggered separately Each action yields a new real-time state, including: for the optimal action set For any third action c, perform the following operation:

[0118] At the optimal extended search node Nd i optimal real-time state Under these conditions, the third action c is triggered; where, in the optimal real-time state The wafer distribution below is M i The action sequence is R i The current system time is T. i The set of all action trigger times is PT. i ;

[0119] M in wafer distribution i Based on this, the wafer distribution is modified according to the wafer position changed by triggering the third action c, resulting in a new wafer distribution M. i+1 ;

[0120] Add the third action c to the action sequence R. i At the tail, a new action sequence R is obtained. i+1 ;

[0121] Update the system's current time point T based on the trigger time of the third action c. i Let T be the current time point of the new system. i+1 ;

[0122] All action trigger time set PT iBased on this, update the list of current steps changed by the third action c, update the start time of each step, and obtain a new set of all action trigger times PT. i+1 ;

[0123] According to the new wafer distribution M i+1 New action sequence R i+1 The new system's current time point T i+1 And the new set of all action trigger times PT i+1 Calculate the new heuristic prediction of the completion time F. i+1 And construct a new real-time state St i+1 For (M) i+1 ,R i+1 ,T i+1 ,PT i+1 ,F i+1 ).

[0124] S82. Based on the new real-time status and the process requirements of semiconductor processing equipment scheduling, determine whether the new real-time status is a valid status.

[0125] In this embodiment of the disclosure, determining whether the new real-time state is a valid state based on the new real-time state and the process requirements of semiconductor processing equipment scheduling includes:

[0126] Based on the new real-time state St i+1 Based on preset action trigger rules, determine the optimal set of actions. Whether it is empty, in the optimal action set If the value is not empty, determine the new real-time state St. i+1 It is not deadlocked, and it is within the optimal set of actions. If the value is empty, determine the new real-time state St. i+1 It's deadlocked;

[0127] Determine the new real-time state St i+1 Does it meet all preset process time constraints in the new real-time state St? i+1 Determine the new real-time state St while satisfying all process time constraints. i+1 Time is feasible, in the new real-time state St i+1 Determine the new real-time state St if all process time constraints are not met. i+1 Time is not feasible;

[0128] In the new real-time state St i+1 Determine the new real-time state St if deadlock is not satisfied and time is feasible. i+1 It is in a valid state.

[0129] In this embodiment of the disclosure, the above-mentioned process time constraints may include, but are not limited to, three types: dwell time, clock time function Qtime, and initial state time constraints.

[0130] In this embodiment of the disclosure, based on the new real-time state St i+1 Action sequence R in i+1 Determine the new real-time state St i+1 Whether a time is feasible depends on whether all process time constraints are met. Process time constraints are typically manifested as the trigger time difference between two related actions falling within a certain range. Dwell time, Qtime, and initial state time constraints can all be expressed in this form. For example, the dwell time of a wafer in the processing chamber must meet both the minimum processing time requirement and the requirement that it cannot remain in the chamber for too long after processing. This means that the trigger time difference between the wafer placement and wafer removal actions in the same chamber must fall between the shortest processing time and the longest dwell time.

[0131] In this embodiment of the disclosure, for a certain process time constraint, its preceding action is c1, its subsequent action is c2, and the trigger time of the preceding action is... The subsequent action trigger time is The process time constraint interval is [t] lower ,t upper If the process time constraint is satisfied, it can be expressed as follows:

[0132]

[0133] S83. If the new real-time state is valid, add the new real-time state to the extended search node set Φ to update the extended search node set Φ.

[0134] In the embodiments disclosed herein, such as Figure 11 As shown, adding the new real-time state to the expanded search node set Φ can include steps S91-S93:

[0135] S91. Determine if the expanded search node set Φ contains a new real-time state St. i+1 The new wafer distribution M i+1 Same extended search node Nd i+1 .

[0136] S92, A new real-time state St exists in the expanded search node set Φ. i+1 The new wafer distribution M i+1 Same extended search node Nd i+1 In this case, the new real-time state St i+1 Add extended search node Nd i+1The real-time state set Sts i+1 In, and based on the expanded search node Nd i+1 The real-time state set Sts i+1 Update and expand search node Nd i+1 optimal real-time state

[0137] S93, The new real-time state St does not exist in the expanded search node set Φ. i+1 The new wafer distribution M ii1 Same extended search node Nd i+1 In this case, construct a new extended search node (M) i+1 ,{St i+1},St i+1 ), and will add a new extended search node (M) i+1 ,{St i+1},St i+1 Add to the expanded search node set Φ.

[0138] S13. Based on the updated set of expanded search nodes, calculate the optimal scheduling path corresponding to the real-time status of the expanded search nodes.

[0139] In this embodiment of the disclosure, the optimal scheduling path corresponding to the real-time status of the expanded search nodes is calculated based on the updated expanded search node set, including:

[0140] The steps of updating the real-time state of the expanded search nodes based on the preset pruning strategy and updating the expanded search node set based on the new real-time state obtained by the update are executed repeatedly until the path length corresponding to the real-time state of the newly generated expanded search node in the expanded search node set reaches the maximum search depth; the maximum search depth refers to the path length between the root expanded search node and the target expanded search node.

[0141] The scheduling path corresponding to the real-time state where the path length reaches the maximum search depth is output as the optimal scheduling path. In this embodiment of the disclosure, the steps of updating the real-time state of the extended search nodes based on the preset pruning strategy and updating the set of extended search nodes based on the new real-time state of the updated extended search nodes are executed cyclically until the action path length corresponding to the newly generated extended search nodes reaches |R|+N; where |R| is the action path length in the current real-time state and N is the maximum depth of forward search.

[0142] In this embodiment of the disclosure, an extended search node with an action path length of |R|+N can be output, and the entire action path R corresponding to the extended search node can be extracted. N As the optimal scheduling path, the entire action path R is... NRemove the parts of the action path R that overlap with the current real-time state to obtain an additional action path of length N. This is the optimal scheduling path for the next N steps under the current real-time state.

[0143] This disclosure embodiment includes at least the following advantages:

[0144] 1. To address the scheduling of semiconductor processing equipment under complex process time constraints and deadlock avoidance requirements, a new concept of extended search nodes is proposed. Based on the scheduling characteristics of semiconductor processing equipment and the improved shortest path search algorithm of the proposed extended search nodes, the scheduling failure problem caused by the traditional shortest path search algorithm, which only considers the search nodes represented by a single optimal action sequence, is solved.

[0145] 2. The intelligent search and pruning strategy, which integrates the shortest path search algorithm, enables efficient real-time scheduling of semiconductor processing equipment to meet the requirements of complex process time constraints and deadlock avoidance.

[0146] This disclosure also provides an electronic device 100, such as... Figure 12 As shown, the electronic device 100 may include:

[0147] One or more processors 101;

[0148] The memory 102 stores one or more programs that, when executed by the one or more processors 101, enable the one or more processors 101 to implement the semiconductor processing scheduling method.

[0149] One or more input / output I / O interfaces 103 are connected between the processor 101 and the memory 102 and configured to enable information exchange between the processor 101 and the memory 102.

[0150] The processor 101 is a device with data processing capabilities, including but not limited to a central processing unit (CPU); the memory 102 is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and flash memory (FLASH); the I / O interface (read / write interface) 103 is connected between the processor 101 and the memory 102, enabling information exchange between the processor 101 and the memory 102, including but not limited to a data bus (Bus).

[0151] In this embodiment of the disclosure, the processor 101, memory 102 and I / O interface 103 are interconnected via a bus, and thus connected to other components of the computing device.

[0152] This disclosure also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the semiconductor processing scheduling method.

[0153] Those skilled in the art will understand that all or some of the functional modules / units disclosed above can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0154] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be executed by several physical components working together.

[0155] Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technique for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk storage; read-only optical disc (CD-ROM), digital versatile disc (DVD) or other optical disc storage; magnetic cartridges, magnetic tapes, disk storage or other magnetic storage; and any other media that can be used to store desired information and can be accessed by a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0156] This disclosure has disclosed exemplary embodiments, and although specific terminology has been used, it is for general illustrative purposes only and should not be construed as limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A semiconductor processing scheduling method, characterized in that, The method includes: Based on the current real-time state St0 of the semiconductor processing equipment, initialize the extended search node set Φ; wherein, the extended search node set Φ includes the wafer distribution M corresponding to each extended search node, the current real-time state set Sts0 corresponding to the wafer distribution M, and the optimal real-time state in the current real-time state set Sts0. Each current real-time state St0 in the current real-time state set Sts0 contains the action sequence and time information corresponding to the current real-time state St0; The real-time state of the extended search nodes is updated based on a preset pruning strategy, and the set of extended search nodes Φ is updated based on the new real-time state of the updated extended search nodes; the pruning strategy is used to filter the triggering actions required to update the real-time state. Based on the updated set of expanded search nodes Φ, calculate the optimal scheduling path corresponding to the real-time status of the expanded search nodes.

2. The semiconductor processing scheduling method according to claim 1, characterized in that, The initialization of the extended search node set Φ based on the current real-time state St0 of the semiconductor processing equipment includes: Calculate the first state data under the current real-time state St0; based on the first state data, initialize the extended search node set Φ.

3. The semiconductor processing scheduling method according to claim 2, characterized in that, The first state data includes: heuristically predicted completion time F; The calculation of the first state data under the current real-time state includes: Extract the current system time point T from the current real-time state St0 of the semiconductor processing equipment; Under the current real-time state St0, the heuristic prediction of the completion time F under the current real-time state St0 is calculated based on the current system time point T and the preset first calculation formula.

4. The semiconductor processing scheduling method according to claim 3, characterized in that, The first calculation formula includes: F = T + H; Where H is the predicted remaining completion time, and γ is the proportion of remaining processing steps under the current real-time state St0.

5. The semiconductor processing scheduling method according to claim 2, characterized in that, The first state data includes: heuristically predicted completion time F; The initialization of the expanded search node set Φ based on the first state data includes: Obtain the state information of the current real-time state St0; the state information includes any one or more of the following: wafer distribution M, action sequence R of the wafer distribution M from the initial state to the current state, the current system time point T, the set of trigger times PT corresponding to all actions in the action sequence R, and the heuristic prediction completion time point F; Based on the state information, the current real-time state St0 is represented as: St0 = (M, R, T, PT, F); Based on the current real-time state St0 = (M, R, T, PT, F), the extended search node set Φ is initialized as a set consisting solely of the root extended search node Nd0 corresponding to the current real-time state St0.

6. The semiconductor processing scheduling method according to claim 5, characterized in that, The step of initializing the extended search node set Φ into a set consisting solely of the root extended search node Nd0 corresponding to the current real-time state St0 = (M, R, T, PT, F) according to the current real-time state St0 = (M, R, T, PT, F) includes: Obtain the current real-time state set Sts0 of the root extended search node Nd0; the current real-time state set Sts0 is the set of all current real-time states St0 corresponding to the root extended search node Nd0, and the current real-time state set Sts0 is represented as: Sts0 = {St0}. Determine the wafer distribution M corresponding to the root extended search node Nd0; The earliest current real-time state St0 in the current real-time state set Sts0 is the optimal real-time state. The root extended search node Nd0 is represented as: The extended search node set is initialized to be a set consisting solely of the root extended search node Nd0 corresponding to the current real-time state St0.

7. The semiconductor processing scheduling method according to claim 2, characterized in that, The process of updating the real-time state of the expanded search nodes based on a preset pruning strategy, and updating the expanded search node set Φ based on the new real-time state of the expanded search nodes obtained from the update, includes: Using the first state data as the optimization target, the optimal extended search node Nd is selected from the extended search node set Φ. i And update the optimal extended search node Nd i The optimal real-time state; Based on the optimal extended search node Nd i The optimal real-time state is determined by filtering the optimal action set based on the action trigger time. Trigger the optimal action set Each action in the process is used to obtain a new real-time state after triggering each action, and the expanded search node set Φ is updated based on the new real-time state.

8. The semiconductor processing scheduling method according to claim 7, characterized in that, The first state data includes: heuristically predicted completion time F; The optimal extended search node Nd is selected from the extended search node set Φ, with the first state data as the optimization target. i And update the optimal extended search node Nd i The optimal real-time state includes: The earliest heuristically predicted completion time F corresponding to the expanded search node is determined from the expanded search node set Φ, and this node is taken as the optimal expanded search node Nd. i ; From the optimal extended search node Nd i The corresponding first real-time state set Sts i Obtain the earliest first optimal real-time state of the system at the current time T. As the optimal extended search node Nd i The corresponding optimal real-time state; From the first real-time state set Sts i Remove the first optimal real-time state Obtain the second real-time state set Sts i _1; In the second real-time state set Sts i If no element exists in _1, the optimal extended search node Nd is deleted from the extended search node set Φ. i ; In the second real-time state set Sts i If an element exists in _1, then from the second real-time state set Sts i Select the earliest target real-time state from _1 at the current system time T. As the optimal extended search node Nd i The new optimal real-time state.

9. The semiconductor processing scheduling method according to claim 7, characterized in that, The action triggering time includes the predicted triggering time of the action; The optimal extended search node Nd i The optimal real-time state is determined by filtering the optimal action set based on the action trigger time. include: The optimal extended search node Nd is determined based on preset action trigger rules. i The set of triggerable actions in the optimal real-time state is called the initial optimal action set. Calculate the initial optimal action set in the current real-time state. Predicted trigger time Pt ​​for all actions b ; Based on the initial optimal action set Predicted trigger time Pt ​​for all actions b For the initial optimal action set Sort all actions in ascending order and obtain the first m predicted trigger times Pt. b The earliest actions constitute the filtered optimal action set. m is a positive integer.

10. The semiconductor processing scheduling method according to claim 9, characterized in that, The triggering of the optimal action set For each action in the process, obtain the new real-time state obtained after triggering each action, and update the extended search node set Φ based on the new real-time state, including: Based on the filtered optimal action set Trigger the optimal action set respectively The new real-time state is obtained by performing each action in the process. Based on the new real-time status and the process requirements of semiconductor processing equipment scheduling, determine whether the new real-time status is a valid status; If the new real-time state is valid, the new real-time state is added to the extended search node set Φ to update the extended search node set Φ.

11. The semiconductor processing scheduling method according to claim 10, characterized in that, The optimal action set filtered out Triggered separately Each action yields a new real-time state, including: for the optimal action set For any third action c, perform the following operation: In the optimal extended search node Nd i The optimal real-time state Under the following conditions, the third action c is triggered; wherein, in the optimal real-time state The wafer distribution below is M i The action sequence is R i The current system time is T. i The set of all action trigger times is PT. i ; The wafer is distributed with M i Based on this, the wafer distribution is modified according to the wafer position changed by triggering the third action c, resulting in a new wafer distribution M. i+1 ; Add the third action c to the action sequence R. i At the tail, a new action sequence R is obtained. i+1 ; Update the system's current time point T based on the trigger time of the third action c. i Let T be the current time point of the new system. i+1 ; All action trigger time set PT i Based on this, update the list of current steps changed by the third action c, update the start time of each step, and obtain a new set of all action trigger times PT. i+1 ; According to the new wafer distribution M i+1 The new action sequence R i+1 The new system current time point T i+1 And the new set of all action trigger times PT i+1 Calculate the new heuristic prediction of the completion time F. i+1 And construct a new real-time state St i+1 For (M) i+1 ,R i+1 ,T i+1 ,PT i+1 ,F i+1 ).

12. The semiconductor processing scheduling method according to claim 10, characterized in that, The step of determining whether the new real-time state is a valid state based on the new real-time state and the process requirements of the semiconductor processing equipment scheduling includes: Based on the new real-time state St i+1 Based on preset action trigger rules, determine the optimal action set. Is it empty in the optimal action set? If the value is not empty, determine the new real-time state St. i+1 It is not deadlocked, in the optimal set of actions. If the value is empty, determine the new real-time state St. i+1 It's deadlocked; Determine the new real-time state St i+1 Whether all preset process time constraints are met in the new real-time state St i+1 Determine the new real-time state St while satisfying all the process time constraints. i+1 Time is feasible in the new real-time state St i+1 If all the process time constraints are not met, determine the new real-time state St. i+1 Time is not feasible; In the new real-time state St i+1 Determine the new real-time state St if the conditions of no deadlock and time feasibility are met. i+1 It is in a valid state.

13. The semiconductor processing scheduling method according to claim 10, characterized in that, Adding the new real-time state to the expanded search node set Φ includes: Determine whether the extended search node set Φ contains a node that matches the new real-time state St. i+1 The new wafer distribution M i+1 Same extended search node Nd i+1 ; The new real-time state St exists in the extended search node set Φ. i+1 The new wafer distribution M i+1 Same extended search node Nd i+1 In the case of the new real-time state St i+1 Add the extended search node Nd i+1 The real-time state set Sts i+1 In, and according to the extended search node Nd i+1 The real-time state set Sts i+1 Update the extended search node Nd i+1 optimal real-time state The new real-time state St does not exist in the extended search node set Φ. i+1 The new wafer distribution M i+1 Same extended search node Nd i+1 In this case, construct a new extended search node (M) i+1 ,{St i+1 },St i+1 ), and the new extended search node (M) i+1 ,{St i+1 },St i+1 Add it to the extended search node set Φ.

14. The semiconductor processing scheduling method according to claim 1, characterized in that, The step of calculating the optimal scheduling path corresponding to the real-time state of the expanded search nodes based on the updated expanded search node set includes: The steps of updating the real-time state of the expanded search nodes based on the preset pruning strategy and updating the expanded search node set based on the new real-time state obtained by the update are executed repeatedly until the path length corresponding to the real-time state of the newly generated expanded search node in the expanded search node set reaches the maximum search depth; the maximum search depth refers to the path length between the root expanded search node and the target expanded search node. Output the scheduling path corresponding to the real-time status when the path length reaches the maximum search depth, as the optimal scheduling path.

15. The semiconductor processing scheduling method according to claim 1, characterized in that, Before initializing the expanded search node set based on the current real-time state St0 of the semiconductor processing equipment, the method further includes: Based on the hardware configuration of semiconductor processing equipment and the wafer processing path, construct action triggering rules for scheduling semiconductor processing equipment.

16. The semiconductor processing scheduling method according to claim 15, characterized in that, The step of constructing action triggering rules for semiconductor processing equipment scheduling based on the hardware configuration of the semiconductor processing equipment and the wafer processing path includes: Clarify the wafer distribution involved in the semiconductor processing equipment scheduling problem; Under the wafer distribution, if any first action a satisfies the first preset triggering condition, it is confirmed that the first action a is triggerable.

17. The semiconductor processing scheduling method according to claim 16, characterized in that, The first preset triggering condition includes: The first action a needs to be executed according to the wafer processing path requirements, but has not yet been executed in the action sequence R of the wafer distribution; and, The preceding steps of the first action a have unused resources.

18. An electronic device, characterized in that, The electronic device includes: One or more processors; A memory having stored one or more programs that, when executed by one or more processors, cause the one or more processors to implement the semiconductor processing scheduling method according to any one of claims 1-17.

19. A computer-readable storage medium storing a computer program that, when executed by a processor, implements the semiconductor processing scheduling method according to any one of claims 1-17.

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