Chip test circuit and test system

Abstract

The invention provides a chip test circuit and test system, which is applied to the technical field of test, and comprises an aging mother board, a plurality of aging daughter board modules and a plurality of level conversion chips, the plurality of aging daughter board modules are arranged on the aging mother board according to a preset column number; the level conversion chips are in one-to-one connection with the aging daughter board modules, and the number of the plurality of level conversion chips is consistent with the preset column number. According to the invention, the plurality of level conversion chips are connected with the aging daughter board modules one by one, so that the routing length of communication signals can be reduced, the reflection of the communication signals is reduced, and the level conversion chips have the relay driving capability, so that the communication speed of the communication signals can be greatly improved, and the firmware burning speed is improved.

Description

Technical Field

[0001] This application relates to the field of testing technology, and in particular to a chip testing circuit and testing system. Background Technology

[0002] In related technologies, the burn-in board consists of a motherboard and daughterboards. Firmware is burned onto chips on the daughterboards. During burning, the burning board transmits the firmware to each daughterboard via communication signals through the motherboard's burning interface. The communication signal lines on the motherboard use a daisy-chain layout, connecting the first daughterboard to the last. This results in extremely long communication signal lines on the motherboard, causing severe reflections and consequently slow firmware burning speed. Summary of the Invention

[0003] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a chip testing circuit and testing system, aiming to improve firmware burning speed.

[0004] In a first aspect, embodiments of this application provide a chip testing circuit, including: Aging motherboard, multiple aging daughterboard modules, and multiple level conversion chips; Multiple aging sub-board modules are arranged in a preset number of columns on the aging mother board; The level conversion chip is connected to the aging sub-board module one by one, and the number of the multiple level conversion chips is consistent with the preset number of columns.

[0005] According to some embodiments of this application, the aging sub-board module includes multiple aging sub-boards.

[0006] According to some embodiments of this application, the level conversion chip is connected to a plurality of the aging sub-boards.

[0007] According to some embodiments of this application, the chip testing circuit further includes: A programming interface is provided, which is connected to multiple level conversion chips.

[0008] According to some embodiments of this application, the chip testing circuit further includes: A plate-to-plate connector is provided, through which multiple aging sub-plates are connected to the aging mother plate.

[0009] According to some embodiments of this application, the chip testing circuit further includes: An expansion chip is connected to the programming interface, the level conversion chip, and the aging daughterboard, respectively.

[0010] According to some embodiments of this application, the number of aging sub-board modules is 10, and each aging sub-board module includes 18 aging sub-boards.

[0011] According to some embodiments of this application, the number of level conversion chips is 10.

[0012] According to some embodiments of this application, the level conversion chip is used to convert the input 3.3V level to a 1.8V level output.

[0013] Secondly, embodiments of this application provide a testing system, including the chip testing circuit described in the first aspect.

[0014] According to the technical solution of the embodiments of this application, at least the following beneficial effects are achieved: This application proposes a chip testing circuit and testing system, applied in the field of testing technology, including an aging motherboard, multiple aging daughterboard modules, and multiple level conversion chips; the multiple aging daughterboard modules are arranged on the aging motherboard according to a preset number of columns; the level conversion chips are connected to each of the aging daughterboard modules, and the number of the multiple level conversion chips is consistent with the preset number of columns. This application, by connecting multiple level conversion chips to the aging daughterboard modules one by one, can reduce the trace length of communication signals, reduce communication signal reflection, and the level conversion chips have relay driving capabilities, which can significantly improve the communication speed of communication signals and improve firmware burning speed.

[0015] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention are described below. It should be understood that the accompanying drawings described below are only for the convenience of clearly illustrating some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. The present invention will be further described below in conjunction with the accompanying drawings and embodiments: Figure 1 This is a schematic diagram of the structure of a chip test circuit provided in one embodiment of this application; Figure 2 This is a schematic diagram of the structure of a chip test circuit provided in another embodiment of this application. Detailed Implementation

[0017] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0018] In the description of this application, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0019] In the description of this invention, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0020] In this invention, unless otherwise explicitly specified and limited, terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0021] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0022] In some cases, aging tests on memory chips are a core part of semiconductor reliability engineering. They aim to expose early defects and potential failure mechanisms of the chip by applying accelerated conditions such as high temperature, high voltage, and high-frequency electrical stress, ensuring the long-term stability of the products leaving the factory. After memory chips are packaged, they generally undergo aging tests first, followed by other functional and performance tests. The purpose of aging tests is to eliminate chips that fail early, ensuring the quality of shipped products.

[0023] The burn-in board consists of a motherboard and daughterboards. Firmware is burned onto chips on the daughterboards. During burning, the burning board transmits the firmware to each daughterboard via communication signals through the motherboard's burning interface. The communication signal lines on the motherboard use a daisy-chain layout, connecting the first daughterboard to the last. This results in extremely long communication signal lines on the motherboard, causing severe reflections and consequently slow firmware burning speed.

[0024] Based on the above, this application proposes a chip testing circuit and testing system, aiming to improve the firmware burning speed.

[0025] The various embodiments of the chip test circuit of this application will be further described below with reference to the accompanying drawings.

[0026] like Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of a chip test circuit provided in one embodiment of this application.

[0027] In one embodiment, the chip test circuit includes an aging motherboard 100, multiple aging daughterboard modules 200, and multiple level conversion chips 300.

[0028] It is understood that multiple aging sub-board modules 200 are arranged in the aging motherboard 100 according to a preset number of columns, and the level conversion chip 300 is connected to each of the aging sub-board modules 200. The number of the multiple level conversion chips 300 is consistent with the preset number of columns.

[0029] It is understood that this application connects multiple level conversion chips 300 to the aging daughterboard module 200 one by one, thereby reducing the trace length of communication signals and reducing communication signal reflection. Furthermore, the level conversion chip 300 has the ability to relay drive, which can significantly improve the communication speed of communication signals and improve the firmware burning speed.

[0030] It is understood that the number of preset columns mentioned above can be 10 columns, and can be set according to actual needs. This application embodiment does not impose a specific limitation on it.

[0031] It is understood that the number of the aforementioned level conversion chips can be 10, and can be set according to actual needs. This application embodiment does not impose a specific limitation on it.

[0032] For example, by connecting 10 level conversion chips 300 to 10 aging daughterboard modules 200 one by one, the trace length of communication signals can be reduced, communication signal reflection can be reduced, and the level conversion chip 300 has the ability to relay drive, which can greatly improve the communication speed of communication signals and improve the firmware burning speed.

[0033] It is understood that the aging sub-board module 200 of this application includes multiple aging sub-boards.

[0034] For example, the chip test circuit includes 180 aging daughter boards, which are divided into 10 aging daughter board modules 200 and set on the aging mother board 100. Each aging daughter board module 200 includes 18 aging daughter boards, which are sequentially set on the aging mother board 100 to form a layout of 10 columns and 18 rows.

[0035] Understandably, each level conversion chip 300 is connected to multiple aging sub-boards in the corresponding aging sub-board module 200.

[0036] For example, the chip test circuit includes 10 aging daughterboard modules 200 and 10 level conversion chips 300. Each aging daughterboard module 200 includes 18 aging daughterboards, and each level conversion chip 300 is connected to the 18 aging daughterboards in the corresponding aging daughterboard module 200. Therefore, the trace length of the communication signal can be reduced, the reflection of the communication signal can be reduced, and the level conversion chip 300 has the ability to relay drive, which can greatly improve the communication speed of the communication signal and improve the firmware burning speed.

[0037] In another embodiment, the chip testing circuit also includes a programming interface 400, which is connected to a plurality of level conversion chips 300.

[0038] Understandably, the firmware is burned onto the chips on the aging motherboard. During firmware burning, the burning board transmits the firmware to each level conversion chip 300 through the burning interface 400 of the aging motherboard 100, and the transmission is carried out in the form of communication signals.

[0039] It is understood that the aforementioned communication signals can be set according to the actual situation, and this application embodiment does not impose specific limitations on them.

[0040] It is understandable that each level conversion chip 300 converts the 3.3V level of the communication signal at the programming interface 400 to a 1.8V level, and the communication signal converted by each level conversion chip 300 is only physically connected to the aging daughterboard chip in the corresponding aging daughterboard module 200.

[0041] In another embodiment, the chip test circuit also includes a board-to-board connector (not shown in the figure).

[0042] Understandably, multiple aging sub-boards are connected to the aging motherboard 100 via board-to-board connectors.

[0043] Understandably, connecting the aging sub-board and the aging motherboard 100 via the board-to-board connector facilitates the assembly and disassembly of the aging sub-board.

[0044] In addition, such as Figure 2 As shown, Figure 2 This is a schematic diagram of the structure of a chip test circuit provided in another embodiment of this application.

[0045] In one embodiment, the chip test circuit further includes an extension chip 500.

[0046] Understandably, the expansion chip 500 is connected to the programming interface 400, the level conversion chip 300, and the aging daughterboard, respectively.

[0047] For example, the chip testing circuit includes 10 aging daughterboard modules 200 and 10 level conversion chips 300. Each aging daughterboard module 200 includes 18 aging daughterboards, and 10 communication signals are sent to the chips in the 10 columns of aging daughterboard modules 200, mainly controlling the chip select pins of the 18 rows of aging daughterboard chips. This allows for the individual control of the chip select pins of 180 aging daughterboards (e.g., enabling level conversion chip 1). Figure 1 (By enabling the second row of chip select pins, the site2 aging daughterboard chip is selected). Therefore, only 28 GPIO ports are needed to meet the chip select requirements of 180 aging daughterboards, which means only 2 expansion chips 500 are needed. The 2 expansion chips 500 can output 36 GPIO ports. 10 GPIO ports control the enable pins of 10 level conversion chips 300 respectively, and 18 GPIO ports control the chip select pins of 18 rows of aging daughterboards (the chip select pins of each row are shorted together). Therefore, the chip of the aging daughterboard is changed from independent control to matrix control, which not only reduces production costs but also reduces maintenance difficulty.

[0048] It is understood that the chips on the aforementioned aging daughterboard can be configured according to actual needs, and this application embodiment does not impose specific limitations on them.

[0049] Based on the power supply number identification method of the above embodiments, the following presents various embodiments of the test system of this application.

[0050] One embodiment of this application also provides a testing system, which includes the chip testing circuit of any of the above embodiments.

[0051] It is worth noting that since the test system of this application embodiment includes the chip test circuit of any of the above embodiments, the specific implementation method and technical effect of the test system of this application embodiment can refer to the specific implementation method and technical effect of the chip test circuit of any of the above embodiments.

[0052] The above provides a detailed description of the preferred embodiments of this application. However, this application is not limited to the above-described embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A chip testing circuit, characterized in that, include: Aging motherboard, multiple aging daughterboard modules, and multiple level conversion chips; Multiple aging sub-board modules are arranged in a preset number of columns on the aging mother board; The level conversion chip is connected to the aging sub-board module one by one, and the number of the multiple level conversion chips is consistent with the preset number of columns.

2. The chip testing circuit according to claim 1, characterized in that, The aging sub-board module includes multiple aging sub-boards.

3. The chip testing circuit according to claim 2, characterized in that, The level conversion chip is connected to multiple aging sub-boards.

4. The chip testing circuit according to claim 1, characterized in that, The chip testing circuit also includes: A programming interface is provided, which is connected to multiple level conversion chips.

5. The chip testing circuit according to claim 2, characterized in that, The chip testing circuit also includes: A plate-to-plate connector is provided, through which multiple aging sub-plates are connected to the aging mother plate.

6. The chip testing circuit according to claim 4, characterized in that, The chip testing circuit also includes: An expansion chip is connected to the programming interface, the level conversion chip, and the aging daughterboard, respectively.

7. The chip testing circuit according to claim 1, characterized in that, The number of aging sub-board modules is 10, and each aging sub-board module includes 18 aging sub-boards.

8. The chip testing circuit according to claim 1, characterized in that, The number of level conversion chips is 10.

9. The chip testing circuit according to claim 1, characterized in that, The level conversion chip is used to convert the input 3.3V level to a 1.8V level output.

10. A testing system, characterized in that, Includes the chip test circuit as described in any one of claims 1 to 9.

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