Low-power-consumption wake-up circuit and electronic equipment
By adding control signal latching and level conversion functions to the GPIO circuit design, the problem that existing wake-up circuits cannot effectively control the low-power state of the chip is solved, achieving arbitrary GPIO wake-up and low-power effects, and reducing the chip area and cost.
Patent Information
- Application Number
- CN202511579611.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-31
- Publication Date
- 2026-02-03
AI Technical Summary
Existing wake-up circuits cannot be woken up by any GPIO, require a large logic area and consume a lot of power, and cannot effectively control the low-power state of the chip.
By adding control signal latching and level conversion functions to ordinary GPIO circuit design, and supporting the wake-up of any GPIO through wake-up detection circuit and power management state machine, the control information of GPIO is latched in sleep mode, reducing circuit area and power consumption.
It implements arbitrary GPIO wake-up function, reduces circuit area and power consumption, lowers chip manufacturing cost, and improves chip design quality.
Smart Images
Figure CN121461965A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of chip design, in particular to a low-power wake-up circuit and electronic equipment. BACKGROUND
[0002] In electronic products powered by batteries, chip power consumption is a very important indicator. The power consumption in the low-power state will determine the service life of the electronic product or the period of replacing the battery. Therefore, when designing a chip, various methods need to be used to control power consumption, including multi-power domain design, clock shutdown, and power shutdown. Using the power shutdown method, the chip will not consume any power, and the power consumption is the lowest. However, in the low-power state, some GPIO (General Purpose Input / Output) is still needed to wake up to the working mode. The existing wake-up circuit cannot wake up through any GPIO, and needs a large logic area and high power consumption. SUMMARY
[0003] The present application aims to at least solve one of the technical problems existing in the prior art. To this end, the present application provides a low-power wake-up circuit and electronic equipment, which adds control signal latching and level conversion functions to the ordinary GPIO circuit design, latches the control information of the GPIO interface unit when the chip enters the low-power state, and can support any GPIO wake-up, reducing the circuit area and power consumption.
[0004] In one aspect, the present application provides a low-power wake-up circuit, comprising: A GPIO module, the GPIO module comprising a plurality of GPIO interface units and a level conversion unit corresponding to the GPIO interface units, the GPIO interface unit having an input signal path enable for transmitting an input signal to the level conversion unit; A wake-up detection circuit, the wake-up detection circuit comprising a plurality of wake-up circuits, the wake-up circuit comprising a multi-channel signal selector, a glitch elimination module, and an edge detection module, the input end of the multi-channel signal selector being connected to the output end of the level conversion unit, the output end of the signal selector being connected to the input end of the glitch elimination module, and the output end of the glitch elimination module being connected to the input end of the edge detection module; A power management state machine, the power management state machine being controlled by a wake-up signal generated by the edge detection module; A stabilized power supply, the switch of the stabilized power supply being controlled by the power management state machine, and the stabilized power supply being turned on in the case of wake-up; A working circuit is arranged in the same power domain as the GPIO interface unit, and the working circuit and the GPIO interface unit are arranged in a power domain that can be turned off.
[0005] According to some embodiments of the application, the GPIO interface unit has a YD low-voltage input signal and a YH high-voltage input signal, the YD low-voltage input signal cannot be used in a sleep state due to the shutdown of the voltage regulator, and in the sleep state, an external level is transmitted to the level conversion unit through the YH high-voltage input signal, and then the level conversion unit converts the level into a logic level for subsequent processing.
[0006] According to some embodiments of the application, the level conversion unit includes a latch level converter, which includes a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, and an eighth MOS tube, the source of the first MOS tube is connected to the sources of the second MOS tube and the eighth MOS tube, the drain of the first MOS tube is connected to the source of the third MOS tube, the drain of the third MOS tube is connected to the drains of the fifth MOS tube and the seventh MOS tube, the source of the fifth MOS tube is connected to the drain of the sixth MOS tube, and the source of the sixth MOS tube is connected to the drains of the fourth MOS tube and the eighth MOS tube.
[0007] According to some embodiments of the application, the gate of the first MOS tube is controlled by an IE control signal, and the gates of the third MOS tube and the fourth MOS tube are controlled by an ISO isolation signal.
[0008] According to some embodiments of the application, when the ISO isolation signal is high, the IEH output signal is controlled by the IE control signal when entering the working state.
[0009] According to some embodiments of the application, when the IE control signal is high, the first MOS tube and the fifth MOS tube are turned off, the second MOS tube, the third MOS tube, the fourth MOS tube, and the sixth MOS tube are turned on, and the IEH output signal outputs a high level.
[0010] According to some embodiments of the application, when the IE control signal is low, the first MOS tube, the third MOS tube, the fourth MOS tube, and the fifth MOS tube are turned on, the second MOS tube and the sixth MOS tube are turned off, and the IEH output signal outputs a low level.
[0011] According to some embodiments of the present application, the power management state machine outputs a GPIO latch signal, and before closing the voltage stabilizer power supply, the GPIO latch signal is pulled low, so that the control signal of the GPIO interface unit can be latched.
[0012] According to some embodiments of the present application, in the sleep state, the ISO isolation signal is low, the third MOS tube and the fourth MOS tube are turned off, and the IEH output signal is latched by the seventh MOS tube and the eighth MOS tube to save the previous state.
[0013] In another aspect, the embodiments of the present application provide an electronic device comprising the low-power wake-up circuit.
[0014] The embodiments of the present application have at least the following beneficial effects: The low-power wake-up circuit provided by the present application comprises a GPIO module, a wake-up detection circuit, a power management state machine, a voltage stabilizer power supply and a working circuit. The GPIO module comprises a plurality of GPIO interface units and level conversion units corresponding to the GPIO interface units, and the GPIO interface units have input signal path enablement. The wake-up detection circuit comprises a plurality of groups of wake-up circuits, and the wake-up circuits comprise a plurality of signal selectors, a glitch elimination module and an edge detection module. The circuit structure for arbitrary GPIO wake-up is provided, the control information of the GPIO is latched when the chip enters the low-power state by adding the control signal latching function on the ordinary GPIO circuit design, the ability of the GPIO signal input is preserved. Then, through the dedicated wake-up level conversion logic, the wake-up signal is transmitted to the level and edge detection logic circuit, and finally the chip is woken up to the working state. The circuit area and power consumption are reduced, the chip is woken up to the working state by any GPIO, the area is small and the power consumption is low, so that the chip manufacturing cost is reduced and the chip design quality is improved.
[0015] Additional aspects and advantages of the present application will be made apparent from the following description, which, taken together with the accompanying drawings, describes an embodiment of the present application. BRIEF DESCRIPTION OF DRAWINGS
[0016] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the following description, taken together with the accompanying drawings, in which: Figure 1 The circuit structure schematic diagram of the low-power wake-up circuit of the embodiments of the present application is shown in the figure; Figure 2 The circuit structure schematic diagram of the GPIO interface unit of the GPIO module of the low-power wake-up circuit is shown in the figure; Figure 1 The circuit structure schematic diagram of the GPIO interface unit of the GPIO module of the low-power wake-up circuit is shown in the figure; Figure 3 The circuit structure schematic diagram of the GPIO interface unit of the GPIO module of the low-power wake-up circuit is shown in the figure; Figure 1Circuit structure diagram of latch level shifter of level conversion unit of GPIO module of low-power wake-up circuit; Figure 4 Timing diagram of power management state machine of low-power wake-up circuit of the embodiment of the present application controlling GPIO interface unit; Figure 5 Jump control flow chart of power management state machine of low-power wake-up circuit of the embodiment of the present application. DETAILED DESCRIPTION
[0017] The embodiments of the present application will be described in detail below, examples of which are shown in the drawings, wherein the same or similar notations represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only, for the purpose of explaining the present application, and should not be understood as a limitation of the present application.
[0018] In the description of the present application, it should be understood that the orientation description, such as the orientation or position relationship indicated by up, down, front, back, left, right, etc. is based on the orientation or position relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as a limitation of the present application, which does not indicate or imply that the device or element indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application.
[0019] In the description of the present application, the meaning of "several" is one or more, the meaning of "multiple" is two or more, greater than, less than, more than, etc. are understood as not including the number, "above", "below", "within", etc. are understood as including the number. If there is a description of "first", "second", etc. is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features or implicitly indicating the order of indicated technical features.
[0020] In the description of the present application, unless otherwise explicitly limited, the words "set", "install", "connect" and "connected" should be broadly understood, and the skilled person in the art can reasonably determine the specific meaning of the above words in the present application in combination with the specific content of the technical solution.
[0021] The technical solutions of the present application will be described in detail below by referring to the drawings and specific embodiments.
[0022] Please refer to Figure 1 The embodiment discloses a low-power wake-up circuit, which comprises a GPIO module 100, a wake-up detection circuit 200, a power management state machine 300, a voltage stabilizing power supply 400 and a working circuit 500. The GPIO module 100 comprises a plurality of GPIO interface units and a level conversion unit corresponding to the GPIO interface units, and the GPIO interface unit is, for exampleFigure 1 The GPIO1, GPIO2, GPIO3 and GPIO4 shown have input signal channel enable for transmitting input signals to the level conversion unit; the wake-up detection circuit 200 includes multiple groups of wake-up circuits, each group of wake-up circuits including a multipath signal selector, a glitch elimination module and an edge detection module, the input end of the multipath signal selector being connected to the output end of the level conversion unit, the output end of the signal selector being connected to the input end of the glitch elimination module, and the output end of the glitch elimination module being connected to the input end of the edge detection module; the power management state machine 300 is controlled by the wake-up signal generated by the edge detection module; the switch of the voltage stabilizing power supply 400 is controlled by the power management state machine 300, and in the case of wake-up, the voltage stabilizing power supply 400 is turned on; the working circuit 500 and the GPIO interface unit are arranged in the same power domain, and the working circuit 500 and the GPIO interface unit are both arranged in the power domain that can be turned off. In the multiple groups of wake-up circuits, for example Figure 1 the first wake-up circuit and the second wake-up circuit in the first wake-up circuit and the second wake-up circuit can be configured as rising edge trigger and low level trigger. It should be noted that in the process of designing the low-power chip, how to divide the power domain, how to place fewer modules in the always-on domain, and how to maintain the wake-up of any GPIO of the chip are challenging.
[0023] Please refer to Figure 2 The GPIO interface unit has YD low-voltage input signal and YH high-voltage input signal, and the YD low-voltage input signal cannot be used due to the closing of the voltage stabilizing power supply 400 in the sleep state. When a low level or a high level is detected, an interrupt is triggered, for example, in the sleep state, the external level is transmitted to the level conversion unit through the YH high-voltage input signal, and then the subsequent processing is performed after the level conversion unit converts it into a logic level. Wherein VDDL is a low-voltage power supply, which will be turned off in the sleep state. In order to realize the wake-up function supported by the power-off domain GPIO, the GPIO latch signal is output by the power management state machine 300 for control, and the GPIO latch signal is pulled low before the voltage stabilizing power supply is enabled, so that the control signal of the GPIO can be latched. Figure 2 In the figure, IE represents low-voltage input enable, OE represents low-voltage output enable, PU represents low-voltage pull-up enable, PD represents low-voltage pull-down enable, XD represents low-voltage output signal, YD represents low-voltage input signal, YH represents high-voltage input signal, ISO represents isolation signal, VDDH represents high-voltage power supply (always on), VSSH represents high-voltage ground, VDDL represents low-voltage power supply (turn off), and VSSL represents low-voltage ground.
[0024] Please refer to Figure 3The level conversion unit comprises a latch level converter, the latch level converter comprises a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7 and an eighth MOS transistor M8, the source of the first MOS transistor M1 is connected with the source of the second MOS transistor M2 and the eighth MOS transistor M8, the drain of the first MOS transistor M1 is connected with the source of the third MOS transistor M3, the drain of the third MOS transistor M3 is connected with the drain of the fifth MOS transistor M5 and the seventh MOS transistor M7, the source of the fifth MOS transistor M5 is connected with the drain of the sixth MOS transistor M6, and the source of the sixth MOS transistor M6 is connected with the drain of the fourth MOS transistor M4 and the eighth MOS transistor M8. Compared with the common GPIO circuit, the latch level converter is adopted, and the GPIO interface unit has two input signals, one is a YD low-voltage input signal, and the other is a YH high-voltage input signal. The YD low-voltage input signal cannot be used in the sleep state due to the shutdown of the voltage stabilizing power supply; in the sleep state, the external level is transmitted to the level conversion unit through the YH high-voltage input signal, and subsequent processing is performed after the level conversion unit is converted into a logic level, so as to enter the working state.
[0025] Please refer to Figure 3 The gate of the first MOS transistor M1 is controlled by an IE control signal, and the gates of the third MOS transistor M3 and the fourth MOS transistor M4 are controlled by an ISO isolation signal. In the working state, when the ISO isolation signal is high, the IEH output signal is controlled by the IE control signal. When the IE control signal is high, the first MOS transistor M1 and the fifth MOS transistor M5 are cut off, the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4 and the sixth MOS transistor M6 are turned on, and the IEH output signal outputs a high level. When the IE control signal is low, the first MOS transistor M1, the third MOS transistor M3, the fourth MOS transistor M4 and the fifth MOS transistor M5 are turned on, the second MOS transistor M2 and the sixth MOS transistor M6 are cut off, and the IEH output signal outputs a low level.
[0026] Please refer to Figure 3 and Figure 4 The power management state machine 300 outputs a GPIO latch signal, and the GPIO latch signal is pulled low before the voltage stabilizing power supply 400 is enabled, so that the control signal of the GPIO interface unit can be latched.
[0027] Please refer to Figure 3 and Figure 4 In the sleep state, the ISO isolation signal is low, the third MOS transistor M3 and the fourth MOS transistor M4 are cut off, and the IEH output signal is latched by the seventh MOS transistor M7 and the eighth MOS transistor M8 to save the previous state.
[0028] Please refer toFigure 4 and Figure 5 In the sleep state, the wake-up is triggered by the GPIO interface unit, the voltage regulator 400 is turned on, and power is provided to the working circuit 500. The overall working logic is that, in the sleep state, the GPIO interface unit keeps the input signal path enabled, and transmits the input signal to the level conversion unit. The output of the level conversion unit is connected to the multi-channel signal selector, which is used to select which channel of the GPIO as the wake-up source. The output of the signal selector is connected to the glitch filter module, so that the small interference glitches on the GPIO will not mistakenly wake up the system. After the input signal passes through the glitch filter, it enters the edge detection module to generate a wake-up signal to control the power management state machine 300. The power management state machine 300 controls the switch of the voltage regulator 400, which is turned on in the wake-up state. The GPIO interface unit is the interaction interface between the chip and the outside, which is used for communication transmission, and is usually in the same power domain as the working circuit 500. The working circuit 500 and the GPIO work in a power domain that can be turned off. The level conversion unit, the wake-up detection circuit 200 and the power management state machine 300 work in a normally-on power domain. The power management state machine 300 outputs the GPIO latch signal, which is pulled low before the voltage regulator 400 is enabled, so that the control signal of the GPIO interface unit can be latched. In the sleep state, the ISO isolation signal is low, and the IEH output signal is latched to save the previous state.
[0029] The embodiment also provides an electronic device comprising the low-power wake-up circuit.
[0030] Please refer to Figure 5 In the working state, if the chip receives a write sleep instruction, the ISO isolation signal is turned off, and the voltage regulator 400 is disabled, so that the chip enters the sleep state. In the sleep state, if a GPIO wake-up signal is generated, the power management state machine 300 outputs the GPIO latch signal, which is pulled low before the voltage regulator 400 is enabled, so that the control signal of the GPIO interface unit can be latched. Then, the voltage regulator 400 is enabled, and the ISO isolation signal is turned on, and the chip enters the working state again. By latching the control information of the GPIO interface unit when the chip enters the low-power state, the signal input capability of the GPIO interface unit is preserved. Then, through the dedicated wake-up level conversion logic, the signal is transmitted to the wake-up detection circuit, so that a wake-up signal is generated to wake up the chip to the working state. With smaller circuit area and lower power consumption, any GPIO can be used to wake up the chip to the working state, which is small in size and low in power consumption, thereby reducing the manufacturing cost of the chip and improving the design quality of the chip.
[0031] The embodiments of the present application are described in detail above with reference to the drawings, but the present application is not limited to the above-described embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the spirit of the present application.
Claims
1. A low-power wake-up circuit, characterized in that, include: The GPIO module includes multiple GPIO interface units and level conversion units corresponding to the GPIO interface units. The GPIO interface units have input signal path enable for transmitting input signals to the level conversion units. A wake-up detection circuit includes multiple wake-up circuits, each including a multiplexer, a glitch removal module, and an edge detection module. The input of the multiplexer is connected to the output of the level conversion unit, the output of the multiplexer is connected to the input of the glitch removal module, and the output of the glitch removal module is connected to the input of the edge detection module. A power management state machine, which is controlled by a wake-up signal generated by the edge detection module; A regulated power supply, the switching of which is controlled by the power management state machine, which turns on the regulated power supply when the system is woken up; The working circuit and the GPIO interface unit are located in the same power domain, and both the working circuit and the GPIO interface unit are located in a power domain that can be turned off.
2. The low-power wake-up circuit according to claim 1, characterized in that, The GPIO interface unit has a YD low-voltage input signal and a YH high-voltage input signal. The YD low-voltage input signal cannot be used in the sleep state because the regulated power supply is turned off. In the sleep state, the external level is transmitted to the level conversion unit through the YH high-voltage input signal, and then converted into a logic level by the level conversion unit for subsequent processing.
3. The low-power wake-up circuit according to claim 2, characterized in that, The level conversion unit includes a latch level converter, which includes a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, and an eighth MOSFET. The source of the first MOSFET is connected to the sources of the second MOSFET and the eighth MOSFET. The drain of the first MOSFET is connected to the source of the third MOSFET. The drain of the third MOSFET is connected to the drains of the fifth MOSFET and the seventh MOSFET. The source of the fifth MOSFET is connected to the drain of the sixth MOSFET. The source of the sixth MOSFET is connected to the drains of the fourth MOSFET and the eighth MOSFET.
4. The low-power wake-up circuit according to claim 3, characterized in that, The gate of the first MOS transistor is controlled by the IE control signal, and the gates of the third and fourth MOS transistors are controlled by the ISO isolation signal.
5. The low-power wake-up circuit according to claim 4, characterized in that, When the ISO isolation signal is high, the IEH output signal is controlled by the IE control signal.
6. The low-power wake-up circuit according to claim 5, characterized in that, When the IE control signal is high, the first MOSFET and the fifth MOSFET are cut off, while the second MOSFET, the third MOSFET, the fourth MOSFET, and the sixth MOSFET are turned on, and the IEH output signal is high.
7. The low-power wake-up circuit according to claim 5, characterized in that, When the IE control signal is low, the first MOSFET, the third MOSFET, the fourth MOSFET, and the fifth MOSFET are turned on, while the second MOSFET and the sixth MOSFET are turned off, and the IEH output signal is low.
8. The low-power wake-up circuit according to claim 5, characterized in that, The power management state machine outputs a GPIO latch signal. Before turning off the regulated power supply, the GPIO latch signal is pulled low so that the control signal of the GPIO interface unit can be latched.
9. The low-power wake-up circuit according to claim 8, characterized in that, In sleep mode, the ISO isolation signal is low, the third and fourth MOSFETs are turned off, and the IEH output signal is latched by the seventh and eighth MOSFETs to save the previous state.
10. An electronic device, characterized in that, Includes the low-power wake-up circuit as described in any one of claims 1 to 9.