Digital clock recovery system and method
A digital clock recovery system combining polynomial interpolation and pre-computation modules with bit operations resolves the contradiction between accuracy and complexity in clock recovery in high-speed optical communication systems, reduces hardware resource consumption, and improves response speed and robustness.
Patent Information
- Application Number
- CN202511569339.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-30
- Publication Date
- 2026-02-03
AI Technical Summary
In existing high-speed optical communication systems, digital clock recovery technology faces problems such as the contradiction between interpolation accuracy and complexity, high complexity of division operations, and high consumption of hardware resources, which affect the recovery quality and response speed.
A polynomial interpolator combined with a pre-computation module is used to calculate the target sample value through polynomial fitting, and bit operations are used to replace division operations to construct an efficient feedback loop, including an interpolator, a timing error detector, a loop filter, and a numerically controlled oscillator.
It achieves high-precision clock recovery, reduces computational complexity and hardware resource consumption, improves response speed and system robustness, and is suitable for high-speed optical communication systems.
Smart Images
Figure CN121461973A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of digital signal processing technology, and more specifically, to a digital clock recovery system and method for high-speed optical communication. Background Technology
[0002] In high-speed optical communication systems, such as optical digital signal processing chips with speeds of 10G and above, one of the core tasks of the receiver is to accurately recover the transmitter's clock information from the received asynchronously sampled data stream. This process is called clock data recovery. Accurate clock recovery is the foundation for subsequent data decision-making; it ensures that the signal is decided at the optimal sampling time, thereby maximizing the accuracy of data transmission.
[0003] Currently, digital clock recovery technology typically employs a feedback control loop. This loop generally includes four basic modules: an interpolator, a timing error detector, a loop filter, and a numerically controlled oscillator (CNC). Its working principle is as follows: the interpolator resamples the asynchronously sampled data based on the timing information provided by the CNC oscillator to obtain data points synchronized with the recovered clock; the timing error detector analyzes the resampled data to determine whether the current sampling time is earlier or later than the optimal sampling time and outputs a corresponding error signal; the loop filter smooths and filters this error signal to generate a stable control signal, driving the CNC oscillator to adjust its output timing information. Through continuous adjustments in this feedback loop, the loop is eventually locked, achieving precise clock recovery.
[0004] However, existing technologies face some inherent challenges in pursuing high performance. First, there is a trade-off between accuracy and complexity in the selection of interpolators. To reduce computational complexity, simple methods such as linear interpolation are often used, but this leads to insufficient interpolation accuracy, introducing large errors in high-speed signal processing and affecting recovery quality. Second, although higher-order interpolation methods such as cubic interpolation can significantly improve accuracy, their algorithms themselves are computationally intensive. Direct implementation in hardware would consume significant logic resources and introduce long processing delays, which is unacceptable for high-speed systems. Finally, when the numerically controlled oscillator in the loop calculates new timing information (especially fractional intervals), traditional normalization methods typically require division operations. Dividers are complex in hardware implementation, consume high power, and are time-consuming, becoming a bottleneck limiting the overall loop performance and response speed. Summary of the Invention
[0005] In view of the deficiencies in the prior art, the purpose of this invention is to provide a digital clock recovery system and method.
[0006] A digital clock recovery system according to the present invention includes an interpolator, a timing error detector, a loop filter, and a numerically controlled oscillator, wherein the interpolator, timing error detector, loop filter, and numerically controlled oscillator constitute a feedback loop; The interpolator is a polynomial interpolator that calculates the target sample value based on at least three known sample points around the target point through polynomial fitting. The system also includes a pre-calculation module, and the interpolator obtains the target sample value or an intermediate value used to calculate the target sample value by querying the pre-calculation module; The numerically controlled oscillator is configured to determine the base point and fractional interval for the interpolator by bit manipulation of the value of an internal phase accumulator, thereby avoiding division operations.
[0007] Preferably, the polynomial interpolator is a cubic interpolator, which is calculated based on four known sampling points around the target point.
[0008] Preferably, the pre-calculation module is a lookup table that pre-stores the interpolation results or interpolation coefficients corresponding to different fraction intervals.
[0009] Preferably, the numerically controlled oscillator determines the base point by performing a right shift operation on the phase accumulator value, and determines the fractional interval by performing a bitwise AND operation or a truncation operation on the phase accumulator value.
[0010] Preferably, the timing error detector adopts the Gardner timing error detection scheme.
[0011] Preferably, the loop filter is a proportional-integral filter, which includes a proportional path for responding to the current error and an integral path for accumulating historical errors.
[0012] Preferably, the polynomial interpolator is a cubic interpolator; The pre-calculation module is a lookup table; and The numerically controlled oscillator determines the base point by performing a right shift operation on the phase accumulator value, and determines the fractional interval by performing a bitwise AND operation or a truncation operation on the phase accumulator value.
[0013] A digital clock recovery method performed by a digital clock recovery system according to the present invention includes: Based on the timing information output, polynomial interpolation is performed on the input asynchronous sampled data to generate interpolated data; The timing error in the interpolated data is detected to generate an error signal; The error signal is filtered to generate a control signal; The timing information is updated according to the control signal, and the updated timing information is fed back for interpolation. The steps for performing polynomial interpolation include: obtaining the target sample value or an intermediate value used to calculate the target sample value by querying a pre-calculation module; The step of updating the timing information includes: determining the base point and fractional interval for interpolation by performing bit operations on a phase accumulator value to avoid division operations.
[0014] Preferably, the step of performing polynomial interpolation specifically involves performing cubic interpolation calculations based on four known sampling points around the target point.
[0015] Preferably, the step of determining the base point and fractional interval by performing bit operations specifically includes: The base point is determined by performing a right shift operation on the phase accumulator value; and The fractional interval is determined by performing a bitwise AND operation or a truncation operation on the phase accumulator value.
[0016] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention ensures the accuracy of clock recovery by employing a high-precision polynomial interpolator; at the same time, by combining a pre-calculation module, it simplifies complex real-time interpolation operations into a lookup operation, significantly reducing computational latency and hardware complexity, and effectively resolving the contradiction between accuracy and efficiency.
[0017] 2. This invention simplifies the hardware logic and shortens the calculation time by using efficient bit operations in the numerically controlled oscillator instead of traditional division operations to generate timing information, enabling the clock recovery loop to respond and lock more quickly.
[0018] 3. The significant reduction in computational complexity of this invention directly translates into savings in chip area and power consumption, making this solution more practical and competitive in resource-sensitive applications such as high-speed optical digital signal processing chips.
[0019] 4. The smooth and fast-response loop control of this invention helps to improve the locking speed and stability of the clock recovery loop, and enhances the system's robustness to line noise and signal distortion. Attached Figure Description
[0020] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a schematic diagram of the structure of a digital clock recovery system provided in an embodiment of the present invention; Figure 2A flowchart of a digital clock recovery method provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of a proportional-integral loop filter in an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating the principle of cubic interpolation in an embodiment of the present invention. Detailed Implementation
[0021] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.
[0022] Example 1 This invention discloses a digital clock recovery system. Please refer to [link / reference]. Figures 1 to 4 In this embodiment, the system includes: The interpolator (interp) calculates the target sample value at the desired time (specified by nco) based on a set of sampled values at a fixed rate. The cubic interpolation scheme used in this invention is a high-precision interpolation method based on polynomial fitting. Its core idea is to fit a smooth cubic polynomial curve using four known sampled points around the target point, and then use this curve to estimate the value of the target point.
[0023] The timing error detector (TED) uses the Gardner TED scheme to analyze the interpolated signal and determine whether the current sampling time is too early, too late, or just right. Based on three sampling points s0, s1, and s2, (s0-s2)*s1 is calculated, and an error value related to the magnitude and direction of the timing error is output to the loop filter (lpf).
[0024] The loop filter (LPF) receives a coarse and noisy error signal from the TED circuit. If this signal is directly fed to the NCO (Network Control Operator), the NCO's rhythm will fluctuate wildly, causing the loop to become unstable and unable to lock. Therefore, the output of the TED circuit must be smoothed and controlled; this is the purpose of the loop filter. The loop filter used in this invention is a proportional-integral (PI) filter, consisting of two paths: an integral path and a proportional path. The proportional path immediately responds to the current error, while the integral path stores and accumulates historical errors.
[0025] The numerically controlled oscillator (nco) uses the error value after loop filtering and employs an optimized normalization scheme, rather than the classic normalization scheme, to calculate a base point s and a fractional interval u. s determines the starting index of the input data block used for calculation, while u (typically in the range [0,1)) specifies the precise position between the two sampling points s and s+1. The nco module outputs the values of s and u to the interp module.
[0026] Example 2 This embodiment, as a more specific example, provides a high-performance, low-complexity digital clock recovery system and corresponding method. This system is applicable to high-speed optical communication, for example, it can be integrated into optical digital signal processing chips with speeds of 10G and above, for accurately recovering the clock from asynchronously sampled data and synchronizing the data. See also... Figure 1 The system is a closed-loop feedback structure, comprising an interpolator, a timing error detector, a loop filter, and a numerically controlled oscillator connected in sequence. These four modules are connected in series and end to end, forming a complete feedback loop.
[0027] Please see Figure 1 The diagram illustrates the overall structure of a digital clock recovery system according to an embodiment of this application. The system is constructed as a closed-loop feedback control system, its core purpose being to dynamically adjust the sampling time to ultimately lock it at the optimal decision position. Specifically, the system mainly includes an interpolator, a timing error detector, a loop filter, and a numerically controlled oscillator. These four modules are connected in series, forming a complete feedback loop.
[0028] The system's workflow is as follows: The asynchronous sampled data stream from the analog-to-digital converter (not shown at the front end) is first fed into the interpolator. The core function of the interpolator is to resample the discrete asynchronous sampling points based on the precise timing information provided by the numerically controlled oscillator to calculate the signal amplitude at a specified moment in the recovery clock, thereby generating interpolated data synchronized with the recovery clock.
[0029] To reduce computational complexity while maintaining high accuracy, this system also includes a pre-computation module that works in conjunction with the interpolator. During interpolation, the interpolator does not perform all the complex real-time calculations; instead, it directly retrieves the final interpolation result or key intermediate values used to calculate the result by querying the pre-computation module. This design, which transforms time-consuming complex calculations into efficient lookup operations, significantly reduces processing latency and hardware resource consumption.
[0030] The synchronous data stream output by the interpolator is sent to the timing error detector. The timing error detector analyzes the data stream to determine whether the current interpolation time is ahead or behind the ideal sampling time, quantifies the deviation, and generates a timing error signal ted_err.
[0031] The timing error signal ted_err is then input into the loop filter. Understandably, the error signal output by the timing error detector may contain noise or high-frequency jitter. Therefore, the loop filter's function is to smooth and filter this signal, extracting the stable, slowly changing components from the error signal to generate a smooth control signal that reflects the long-term, stable adjustment trend required by the loop.
[0032] The smoothing control signal output from the loop filter is sent to the numerically controlled oscillator (CNC). As the core of the entire loop, the CNC adjusts its internal oscillation frequency according to the input control signal and generates timing information for the next moment. This timing information typically includes two parts: a base point 's' and a fractional interval 'u'. The base point 's' is used to locate a reference sampling point in the input asynchronous sampled data buffer, while the fractional interval 'u' represents the precise offset of the actual interpolation point relative to this base point. The CNC feeds the newly generated timing information back to the interpolator to guide it in adjusting the interpolation position in the next operation.
[0033] Through the above cyclic process of interpolation, error measurement, filtering, and frequency modulation, the loop continuously corrects the timing deviation until the timing error signal ted_err approaches zero, at which point the loop reaches a locked state. This indicates that the system has successfully recovered the transmitter's clock from the asynchronous data, and the interpolator can continuously output data at the optimal sampling time.
[0034] In one specific implementation: the interpolator is a cubic polynomial interpolator, which performs fitting calculations based on four known asynchronous sampling points around the target interpolation point to obtain high interpolation accuracy.
[0035] The pre-calculation module is a lookup table that pre-stores the interpolation results or interpolation coefficients (such as Farrow structural coefficients) corresponding to different fraction intervals u.
[0036] The timing error detector employs the Gardner algorithm, which uses the decision point (s1) in the middle of the symbol and the transition point (s0, s2) at the symbol boundary to generate a timing error signal by calculating ted_err = s1 × (s0 - s2). This algorithm requires no decision data and is simple to implement.
[0037] The loop filter is a proportional-integral filter (see...). Figure 3Its proportional path provides fast response, and the integral path eliminates steady-state error. The two outputs are added together to generate a smooth control signal.
[0038] The numerically controlled oscillator incorporates a phase accumulator and is configured to efficiently generate timing information through bit operations to avoid division. Specifically, the base point s is obtained by performing a right shift operation on the current value of the phase accumulator, and the fractional interval u is obtained by performing a bitwise AND or OR operation to extract the low-order bits. This design significantly reduces logical complexity and computational latency.
[0039] The digital clock recovery method corresponding to this embodiment (see [link]). Figure 2 The following steps are executed cyclically: S201: Based on the timing information, perform polynomial interpolation on the asynchronous sampled data by querying the pre-calculation module; S202: Detect timing errors using the Gardner algorithm; S203: Perform proportional-integral filtering on the error signal; S204: Update the timing information through bit operations. This process is repeated until the loop is locked.
[0040] In summary, this embodiment combines high-precision interpolation, pre-calculation acceleration, and a high-efficiency bit-operated numerically controlled oscillator, which significantly reduces computational complexity and latency while ensuring recovery accuracy.
[0041] Example 3 This embodiment is a variation of Embodiment 2, the main difference being the specific implementation of the interpolator. In this embodiment, the interpolator is a quadratic (parabolic) interpolator, which performs fitting calculations based on at least three known sampling points around the target point. Accordingly, the pre-calculation module stores the data used for quadratic interpolation.
[0042] Compared to the cubic interpolation in Example 2, this example further reduces computational complexity and storage overhead by sacrificing some interpolation accuracy, providing another option for the trade-off between performance and resources. This indicates that the polynomial interpolator of the present invention can cover quadratic, cubic, or higher-order implementations.
[0043] Example 4 This embodiment illustrates another implementation of the pre-computation module, where the interpolator still uses cubic interpolation. In this embodiment, the pre-computation module is a coefficient read-only memory, which pre-stores interpolation coefficients (such as Farrow structure coefficients) for real-time calculation, rather than the final interpolation result.
[0044] During operation, the interpolator reads coefficients from the pre-calculation module and uses its internal calculation unit to perform multiplication and addition operations with the sampled data in real time to obtain the interpolation result.
[0045] This solution offers a different trade-off between hardware logic resources and storage resources than Embodiment 1, demonstrating that the "pre-computation module" of this invention can encompass the technical means of storing final or intermediate values (such as coefficients) to accelerate real-time computation.
[0046] Those skilled in the art will understand that, besides implementing the system and its various devices, modules, and units provided by this invention in the form of purely computer-readable program code, the same functions can be achieved entirely through logical programming of the method steps, making the system and its various devices, modules, and units of this invention function in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, the system and its various devices, modules, and units provided by this invention can be considered as a hardware component, and the devices, modules, and units included therein for implementing various functions can also be considered as structures within the hardware component; alternatively, the devices, modules, and units for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.
[0047] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.
[0048] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features of the present invention can be arbitrarily combined with each other.
Claims
1. A digital clock recovery system, characterized in that, It includes an interpolator, a timing error detector, a loop filter, and a numerically controlled oscillator, wherein the interpolator, timing error detector, loop filter, and numerically controlled oscillator constitute a feedback loop; The interpolator is a polynomial interpolator that calculates the target sample value based on at least three known sample points around the target point through polynomial fitting. The system also includes a pre-calculation module, and the interpolator obtains the target sample value or an intermediate value used to calculate the target sample value by querying the pre-calculation module; The numerically controlled oscillator is configured to determine the base point and fractional interval for the interpolator by bit manipulation of the value of an internal phase accumulator, thereby avoiding division operations.
2. The digital clock recovery system according to claim 1, characterized in that, The polynomial interpolator is a cubic interpolator that performs calculations based on four known sampling points around the target point.
3. The digital clock recovery system according to claim 2, characterized in that, The pre-calculation module is a lookup table that pre-stores the interpolation results or interpolation coefficients corresponding to different fraction intervals.
4. The digital clock recovery system according to claim 3, characterized in that, The numerically controlled oscillator determines the base point by performing a right shift operation on the phase accumulator value, and determines the fractional interval by performing a bitwise AND operation or a truncation operation on the phase accumulator value.
5. The digital clock recovery system according to claim 4, characterized in that, The timing error detector adopts the Gardner timing error detection scheme.
6. The digital clock recovery system according to claim 5, characterized in that, The loop filter is a proportional-integral filter, which includes a proportional path for responding to the current error and an integral path for accumulating historical errors.
7. The digital clock recovery system according to claim 1, characterized in that, The polynomial interpolator is a cubic interpolator; The pre-calculation module is a lookup table; and The numerically controlled oscillator determines the base point by performing a right shift operation on the phase accumulator value, and determines the fractional interval by performing a bitwise AND operation or a truncation operation on the phase accumulator value.
8. A digital clock recovery method executed by a digital clock recovery system, comprising: Based on the timing information output, polynomial interpolation is performed on the input asynchronous sampled data to generate interpolated data; The timing error in the interpolated data is detected to generate an error signal; The error signal is filtered to generate a control signal; The timing information is updated according to the control signal, and the updated timing information is fed back for interpolation. Its features are, The steps for performing polynomial interpolation include: obtaining the target sample value or an intermediate value used to calculate the target sample value by querying a pre-calculation module; The step of updating the timing information includes: determining the base point and fractional interval for interpolation by performing bit operations on a phase accumulator value to avoid division operations.
9. The digital clock recovery method executed by the digital clock recovery system according to claim 8, characterized in that, The specific steps for performing polynomial interpolation are as follows: perform cubic interpolation calculations based on four known sampling points around the target point.
10. The digital clock recovery method performed by the digital clock recovery system according to claim 8 or 9, characterized in that, The steps of determining the base point and fractional interval by performing bit operations specifically include: The base point is determined by performing a right shift operation on the phase accumulator value; and The fractional interval is determined by performing a bitwise AND operation or a truncation operation on the phase accumulator value.