High-parallelism data acquisition and playback method, device and system based on FPGA (Field Programmable Gate Array)

Abstract

The invention discloses a high-parallelism data acquisition and playback method, device and system based on an FPGA (Field Programmable Gate Array), and belongs to the field of signal processing, and the method comprises the following steps: S1, data acquisition: accessing an external signal, sequentially completing signal filtering, band-pass sampling and ADC (Analog to Digital Converter) conversion, and then storing; and S2, data playback: sequentially performing first caching, orthogonal down-conversion, low-pass filtering, second caching, interpolation, orthogonal up-conversion and DAC conversion on the acquired data, and outputting the data to related receiving equipment. The system supports high-speed data acquisition, high-throughput signal storage and large-bandwidth signal playback, and has a very high engineering application value.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of signal processing, more particularly, to a high-parallelism data acquisition and playback method, device and system based on FPGA. BACKGROUND

[0002] Today, the digital wave sweeps the world, and the communication technology develops rapidly, and more and more communication equipment works in a wide frequency band, which gives birth to a large amount of data and brings a serious challenge to the data processing speed. Under this application background, how to realize the high-speed conversion between digital signals and analog signals becomes an important topic in the field of integrated circuits. In the field of satellite communication, high-precision data sampling of related signals is required, and the signal bandwidth is large, the sampling rate is high, and the data transmission amount is large.

[0003] The current common data acquisition and playback technology has deficiencies in resource utilization and processing speed, especially in the aspect of large-capacity data storage, and there is a lack of existing equipment in the market. SUMMARY

[0004] The purpose of the present application is to overcome the deficiencies of the prior art, provide a high-parallelism data acquisition and playback method, device and system based on FPGA, provide a new solution, support high-speed data acquisition, high-throughput signal storage, large-bandwidth signal playback, etc., and have high engineering application value.

[0005] The purpose of the present application is achieved by the following scheme: A high-parallelism data acquisition and playback method based on FPGA, comprising the following steps: S1, data acquisition: accessing external signals, sequentially completing signal filtering, bandpass sampling and ADC conversion, and then storing; S2, data playback: sequentially performing first buffering, quadrature down-conversion, low-pass filtering, second buffering, interpolation, quadrature up-conversion and DAC conversion on the collected data, and then outputting to related receiving equipment.

[0006] Further, in step S1, the signal filtering specifically includes the following sub-steps: completing signal filtering inside the channel, and filtering out the out-of-band interference components when the signal enters the digital processing stage.

[0007] Further, in step S1, the bandpass sampling and ADC conversion specifically include the following sub-steps: The signal completing channel filtering enters the ADC conversion module through a hardware interface to perform bandpass sampling and analog-to-digital conversion, and down-converts the bandpass-sampled signal to baseband for processing after the bandpass sampling; According to the bandpass sampling theorem, the sampling rate The highest frequency of the bandpass signal , and the lowest frequency of the bandpass signal satisfies the following relationship: wherein n is a positive integer, and the value range is: .

[0008] Further, an anti-aliasing band-pass filter is added before A / D sampling to eliminate spectral aliasing caused by out-of-band noise.

[0009] Further, in step S1, the storing specifically includes a sub-step of splicing the data after ADC conversion according to a data interface applicable to the storage medium: matching the data bit width, transmission rate, etc. of the interface between the signal processing board and the storage medium, and ensuring that the signal can be stored on the storage medium without errors.

[0010] Further, in step S2, the first buffering specifically includes a sub-step of using a RAM buffer to transmit the data transmitted from the storage medium, completing the matching of the data transmission rate between the storage medium and the signal processing board, and facilitating subsequent module continuous processing; at the same time, another function of this module is to complete the isolation of the GTX processing clock and the subsequent data processing clock, so as to avoid timing problems.

[0011] Further, in step S2, the quadrature down-conversion specifically includes a sub-step of further moving the signal after band-pass sampling from an intermediate frequency to a baseband, and reading out quadrature carrier data from a ROM table and multiplying the quadrature carrier data with the signal, respectively.

[0012] Further, in step S2, the low-pass filtering specifically includes a sub-step of low-pass filtering the data after down-conversion to prevent the quality of the playback signal from being deteriorated. Let the original signal be , and the data after quadrature down-conversion be: ; ; The quadrature component of the original signal is obtained by using a low-pass filter with a cutoff frequency fc to filter out the double-frequency component. and ; The filter uses a FIR2 filter, and the filter order is 11; the filter cutoff frequency is set to: ; wherein the signal bandwidth is B, the AD sampling rate is , and according to engineering experience, the actual cutoff frequency is adjusted as needed on the basis of this value.

[0013] Further, in step S2, the second buffering specifically includes a sub-step of: The data is first buffered by the RAM for the interpolation module to read slowly, and meanwhile, once the amount of data read by the interpolation module equals the set length L, the data buffer interface module is requested for data with a length of L, so as to match the processing rate before and after interpolation; wherein L can be modified according to requirements.

[0014] Further, in step S2, the interpolation specifically comprises the sub-steps of: interpolating the baseband-processed symbol data to the sampling rate corresponding to the DAC; when interpolating, the interpolation multiple is set as: , wherein represents the DAC sampling rate, represents the baseband-processed symbol rate; the interpolator controls the rate of the entire data flow, one data symbol is used for interpolation, and then one or two data symbols are requested from the front module, and the interpolator can be performed according to IQ respectively.

[0015] Further, in step S2, the orthogonal up-conversion specifically comprises the sub-steps of: up-converting the data after baseband processing and interpolation to a specified center frequency, and the orthogonal up-conversion is as follows: ; , wherein and respectively represent the baseband data after completing symbol interpolation, and represents the intermediate frequency required for signal output during playback.

[0016] Further, in step S2, after the orthogonal up-conversion, the step of performing interface conversion and clock matching processing on the data after the orthogonal up-conversion is further included, so as to adapt to the output form of the DAC.

[0017] Further, in step S2, the DAC conversion specifically comprises the sub-step that the signal output by the DAC is sent to a channel, and after completing filtering in the channel, the signal is output to a related receiving device through a cable.

[0018] A high-parallelism data acquisition and playback device based on FPGA, comprising a processor and a memory, and the memory stores a computer program, when the computer program is loaded by the processor, the method as claimed in any one of the above is executed.

[0019] A high-parallelism data acquisition and playback system based on FPGA, comprising the high-parallelism data acquisition and playback device based on FPGA as claimed in the above.

[0020] The beneficial effects of the present application include: The application can reduce performance loss in signal processing, simplify circuit design difficulty, greatly reduce data storage rate during data acquisition, save hardware resources, and improve system cost performance.

[0021] The application can realize high-speed conversion between digital signals and analog signals, solve the difficulties and pain points of current market acquisition and playback equipment, support high-speed data acquisition, high-throughput signal storage, and large-bandwidth signal playback. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor under the premise of not paying creative labor.

[0023] Figure 1 The spectrum diagram before and after 600MHz intermediate frequency sampling in the embodiment of the application; Figure 2 The recovery process diagram of the original signal during data playback in the embodiment of the application; Figure 3 The processing flowchart during data acquisition in the embodiment of the application; Figure 4 The processing flowchart during data playback in the embodiment of the application; Figure 5 The QPSK signal with a bandwidth of 450Msps in the embodiment of the application; Figure 6 The 8PSK signal with a bandwidth of 300Msps in the embodiment of the application. DETAILED DESCRIPTION

[0024] All features disclosed in all embodiments of the present specification, or all steps in the methods or processes impliedly disclosed, can be combined and / or extended, replaced, unless mutually exclusive features and / or steps.

[0025] After experiencing creative thinking, the inventors of the present application believe that: With the rapid development of satellite communication and related technologies, the strategic value of data acquisition and playback services is becoming increasingly prominent. The importance of data acquisition and playback services is gradually reflected in all aspects of modern information society. On the one hand, in areas where ground stations cannot cover, such as the polar region, ocean, and desert, satellite networks can break through geographical limitations. For example, the short message function of the Beidou system can provide centimeter-level positioning and status feedback for ocean-going ships. In low-orbit satellite constellations (such as StarLink), high-resolution remote sensing satellites (such as WorldView) are used to form a three-dimensional collection matrix of spectrum, radar, and visible light. In 2023, the EMIT test by NASA proved that the hyperspectral instrument carried by the International Space Station can accurately monitor global methane emission sources. In terms of weather warning, the Fengyun-4 satellite can generate a global atmospheric three-dimensional temperature and humidity field every minute, increasing the accuracy of typhoon path prediction by 30%. In terms of emergency response, such as earthquake observation, data acquisition, mapping, and analysis are also important.

[0026] On the other hand, data playback functions can provide more convenient and rapid processing solutions for many applications. Data playback is known as the value engine of space-time compression. High-throughput satellites (such as Viasat-3) and inter-satellite laser links are used to build a space CDN network. Amazon AWS ground station services have achieved the function of direct cloud storage of satellite data, reducing the data transmission delay from weeks to minutes. At the same time, data playback can be used as the basis for digital twinning. The global electromagnetic environment data continuously observed and transmitted by SpaceX Starlink satellites provides a real training set for 6G network modeling. China's Jilin constellation has cumulatively played back 300 million square kilometers of images, supporting the training of AI recognition models for major global ports. In addition, data playback also brings great convenience to business development. The daily new map data of Planet Labs helps farmers accurately assess disaster losses, and the efficiency of claim processing is improved by 5 times. Energy pipeline monitoring: Maxar satellite playback data combined with InSar technology can detect millimeter-level displacement of oil and gas pipelines.

[0027] In other aspects, radar testing and electronic reconnaissance: ultra-wideband systems can continuously collect and playback complex electromagnetic environment signals to verify the anti-interference capability of equipment. Intelligent manufacturing: through real-time acquisition and fault playback of equipment status data, predictive maintenance and process optimization are achieved. High-frequency transaction monitoring: dynamic playback technology combined with NLP event tagging quickly locates abnormal transaction periods.

[0028] Smart city: intelligent segmentation playback of traffic monitoring video supports accident analysis and traffic optimization. Biomedical signal analysis: high-precision acquisition of electrocardiogram and electroencephalogram signals, and superimposition of noise simulation in real environment during playback to improve the robustness of diagnosis algorithms.

[0029] In the field of modern technology, data acquisition and post-playback algorithm has important application background. With the rapid development of various technologies such as radar technology and vehicle-mounted sensor technology, the requirements for data acquisition are becoming higher and higher, and need to meet the conditions of high precision, large dynamic, high speed, etc. At the same time, in order to adapt to the increasing work index and the optimization design requirements of various information processing algorithms and system working parameters, and facilitate the debugging, fault positioning and performance evaluation of the system, it is very important to play back the data and analyze it. However, the traditional data acquisition and playback method has many shortcomings. For example, low sampling rate, short recording time, slow processing speed, low playback efficiency and poor compatibility, etc., which gradually cannot meet the needs of various fields, so it is necessary to continuously research and improve the data acquisition and post-playback algorithm to meet the needs of modern technology development.

[0030] In another aspect, data acquisition and playback services are evolving from auxiliary tools to new infrastructure. According to the prediction of NSR, the global satellite data service market will reach 20 billion US dollars by 2027, and the real-time playback service will have a compound annual growth rate of 28%.

[0031] In a preferred embodiment, the difficulties and pain points faced by current market acquisition and playback equipment are addressed, especially involving a processing technical solution that supports high-speed data acquisition, high-throughput signal storage, and large-bandwidth signal playback. Specifically, a data acquisition and playback system architecture suitable for high sampling accuracy, multiple sampling rates, large bandwidth, and high data throughput is proposed. This architecture supports the acquisition and playback of multiple intermediate frequency signals, has ultra-large storage capacity, simple and easy-to-implement algorithms, moderate resource consumption, supports variable intermediate frequency playback, supports visual analysis of the signal acquisition and playback process, and has high engineering application value. Specifically, it includes data acquisition and playback processes.

[0032] As shown in Figure 3 , the main steps of data acquisition are as follows: Step A1: After the external signal enters the system, signal filtering is completed inside the channel. To save storage resources, bandpass sampling is used for signal acquisition, and a lower sampling rate is used to achieve the acquisition of a larger bandwidth signal. Bandpass sampling has the problem of signal aliasing, so the present solution needs to filter out the out-of-band interference components when the signal enters the digital processing stage, reducing the performance loss in the signal processing process.

[0033] Step A2: Bandpass sampling and ADC conversion, the signal filtered by the channel and AGC is input into the ADC through the hardware interface for bandpass sampling and analog-to-digital conversion, and the down-conversion of the signal is completed; In actual engineering applications, in order to save hardware resources, bandpass sampling is often used. According to the bandpass sampling theorem, the sampling rate , the highest frequency of the bandpass signal and the lowest frequency of the band-pass signal The following relationship needs to be met:

[0034] Wherein: n is a positive integer, the value range is:

[0035] The band-pass sampling has the following advantages: 1) Reducing the sampling rate; 2) Reducing the workload of the back-end data processing, and improving the processing efficiency.

[0036] With the center frequency of 600MHz, the maximum bandwidth of the intermediate frequency signal is 200MHz, and the sampling rate is at least 400Msps. Here, the sampling rate of the ADC is selected as 480Msps in the band-pass sampling scheme, and the sampled signal is located in the third Nyquist interval. The center frequency changes from 600MHz to 120MHz after sampling, and the information carried by the 600MHz intermediate frequency signal is completely retained. The related spectrum change is shown in Figure 1 .

[0037] During data playback, the 600MHz intermediate frequency signal is still taken as an example for illustration. As shown in Figure 1 , the original 600MHz intermediate frequency signal is shifted to 120MHz after band-pass sampling, and needs to be interpolated, band-pass filtered and up-converted to restore to 600MHz intermediate frequency. The present scheme considers that the band-pass filtering will have a great impact on the signal quality when implemented digitally, and the series of processing during playback has less impact on the signal quality if the band-pass sampled signal is down-converted to baseband for processing. Therefore, during playback processing, the 120MHz intermediate frequency signal is first down-converted to baseband, and then interpolated, up-converted to 600MHz intermediate frequency, and then sent out through the DAC, so as to complete the reconstruction of the original signal. Figure 2 The 600MHz intermediate frequency signal spectrum transformation relationship diagram is given.

[0038] In fact, the band-pass sampling is equivalent to a frequency converter, and the back-end can directly process the lower harmonic components after signal sampling, which simplifies the circuit design difficulty. In practical application, an anti-aliasing band-pass filter needs to be added before A / D sampling to eliminate the spectral aliasing caused by out-of-band noise. With band-pass sampling, the data storage rate can be greatly reduced during data acquisition, saving hardware resources and improving the system performance-price ratio.

[0039] Step A3: In order to successfully store the down-converted data, the data after ADC conversion is spliced according to the data interface suitable for the storage medium: the matching of the data bit width and transmission rate between the interface of the signal processing board and the storage medium is realized, and it is ensured that the signal can be completely and accurately stored on the storage medium.

[0040] As shown in Figure 4 , the main steps of data playback are as follows: Step B1: Data buffer interface, that is, using RAM buffer to transmit the data transmitted from the storage medium, completing the matching of the data transmission rate between the storage medium and the signal processing board, facilitating the continuous processing of the subsequent modules; another function of this module is to complete the "isolation" function of the GTX processing clock and the subsequent data processing clock, so as to avoid timing problems.

[0041] Step B2: Quadrature down-conversion, further moving the signal after bandpass sampling from intermediate frequency to baseband; at this time, the quadrature carrier data is read out from the ROM table and multiplied with the signal respectively; Step B3: Low-pass filtering: low-pass filtering the down-converted data to filter out unnecessary interference components and prevent them from deteriorating the quality of the playback signal; Let the original signal be , and the data after quadrature down-conversion be: ; ; The quadrature components of the original signal and are obtained by using a low-pass filter with a cutoff frequency of fc to filter out the double-frequency components.

[0042] The filter uses a conventional FIR2 filter. When designing the filter, the number of orders used will directly affect the filtering effect and further affect the quality of the playback signal. Therefore, the number of orders cannot be too small when designing the filter. On the other hand, in order to playback a large bandwidth signal, the parallelism of the FPGA processing is high. If the number of orders of the filter is too large, the number of multipliers used in the FPGA implementation will increase sharply. Therefore, a compromise needs to be made between the playback quality and hardware resources. According to actual tests, when the number of orders of the filter is 11, the low-pass filtering effect is significant, and the playback quality meets the requirements.

[0043] Another important parameter in filter design is the cutoff frequency. Assuming that the signal bandwidth is B and the AD sampling rate is , the cutoff frequency should be set to: . According to engineering experience, the actual cutoff frequency should be adjusted as needed based on this value.

[0044] Step B4: Further cache data from discontinuous to continuous. In order to facilitate processing, data processing of step B1 to step B3 is in segments, while the data required by the subsequent interpolation module is discontinuous, i.e. one, two or even three at a time. Data cache 2 module uses RAM to cache the previous data for the interpolation module to read out slowly. At the same time, as long as the amount of data read out by the interpolation module is equal to the set length L, the data cache interface module is requested for data of length L at a time. In this way, the matching of the processing rate before and after interpolation is completed. L can be modified as needed, and the default setting is 1024.

[0045] Step B5: Interpolate the baseband processed symbol data to the sampling rate corresponding to the DAC. When interpolating, the interpolation multiple is related to the baseband processed symbol rate and the sampling rate of the DAC. Assuming the interpolation multiple is: , wherein represents the sampling rate of the DAC, represents the baseband processed symbol rate. In actual application, on the one hand, the interpolation multiple is not always an integer, and on the other hand, the symbol rate of different applications is not always the same, therefore, the design of the interpolator often needs to support arbitrary multiple interpolation.

[0046] The interpolator controls the rate of the entire data stream, which is mainly realized by the "request 2" sent by the interpolator to cache 2. That is, one data symbol is used for interpolation, and then a data symbol is requested from the previous module. In actual execution, in order to meet the high throughput requirement, multiple data can be requested from cache 2 at a time. Since the data is IQ two-way, the implementation is performed separately according to IQ.

[0047] Step B6: Quadrature up-conversion, which converts the data after baseband processing and interpolation to a specified center frequency. The quadrature up-conversion is as follows: ; wherein, and respectively represent the baseband data after completing symbol interpolation, and represents the intermediate frequency required for signal output during playback. In order to support arbitrary variable output intermediate frequency, the sine and cosine carrier waves during quadrature up-conversion use matlab to generate and store ROM tables, and the address of the read-out data is calculated according to different center frequency control words during use, and the read-out data is multiplied and added with the interpolated baseband data, i.e. the quadrature up-conversion is completed; Step B7: DAC data interface, the data after quadrature up-conversion is no longer independent two-way, but complete real signal. In order to adapt to the output form of the DAC, interface conversion, clock matching and other work are required.

[0048] Step B8: The signal output by the DAC is sent to a channel, and after filtering in the channel, it is output to a relevant receiving device through a cable.

[0049] The replay data is grabbed from the FPGA, demodulated by Matlab simulation software, and then the corresponding constellation diagram of the signal is drawn: (1) QPSK signal with a bandwidth of 450Msps, as shown in Figure 5 ; (2) 8PSK signal with a bandwidth of 300Msps, as shown in Figure 6 .

[0050] It should be noted that the following embodiments can be combined and / or extended, replaced, etc. in any logical manner within the scope of protection defined in the claims of the present application, such as disclosed technical principles, disclosed technical features or implicitly disclosed technical features.

[0051] Embodiment 1 A high-parallelism data acquisition and replay method based on FPGA, comprising the following steps: S1, data acquisition: access external signals, and sequentially complete signal filtering, bandpass sampling and ADC conversion, and then store; S2, data replay: sequentially perform first buffering, quadrature down-conversion, low-pass filtering, second buffering, interpolation, quadrature up-conversion and DAC conversion on the collected data, and then output to a relevant receiving device.

[0052] Embodiment 2 On the basis of embodiment 1, in step S1, the signal filtering specifically includes the following sub-steps: completing signal filtering inside the channel, and filtering out the out-of-band interference components when the signal enters the digital processing stage.

[0053] Embodiment 3 On the basis of embodiment 2, in step S1, the bandpass sampling and ADC conversion specifically include the following sub-steps: The signal filtered by the channel is input into the ADC conversion module through a hardware interface to perform bandpass sampling and analog-to-digital conversion, and after the bandpass-sampled signal is down-converted to baseband, it is processed; According to the bandpass sampling theorem, the sampling rate , the highest frequency of the bandpass signal , and the lowest frequency of the bandpass signal satisfy the following relationship: Wherein, n is a positive integer, and the value range is: .

[0054] Embodiment 4 On the basis of embodiment 3, an anti-aliasing bandpass filter is added before A / D sampling to eliminate the spectral aliasing caused by out-of-band noise.

[0055] Embodiment 5 On the basis of Embodiment 1, in step S1, the storing specifically comprises a substep of splicing the data after ADC conversion according to a data interface applicable to the storage medium; the matching of data bit width and transmission rate between the signal processing board and the storage medium is realized, and it is ensured that the signal can be stored on the storage medium without error.

[0056] Embodiment 6 On the basis of Embodiment 1, in step S2, the first buffering specifically comprises a substep of buffering the data transmitted from the storage medium by using a RAM, so as to complete the matching of data transmission rate between the storage medium and the signal processing board, and facilitate the continuous processing of the subsequent module; meanwhile, another role of this module is to complete the isolation of the GTX processing clock and the subsequent data processing clock, so as to avoid the timing problem.

[0057] Embodiment 7 On the basis of Embodiment 1, in step S2, the quadrature down-conversion specifically comprises a substep of further moving the signal after bandpass sampling from intermediate frequency to baseband, and reading out quadrature carrier data from a ROM table and multiplying the quadrature carrier data with the signal respectively.

[0058] Embodiment 8 On the basis of Embodiment 3, in step S2, the low-pass filtering specifically comprises a substep of performing low-pass filtering on the data after down-conversion, so as to prevent the quality of the playback signal from being deteriorated. Let the original signal be , the data after quadrature down-conversion be: ; ; The quadrature component of the original signal is obtained by using a low-pass filter with a cutoff frequency of fc to filter out the double-frequency component. and ; The filter uses a FIR2 filter, and the filter order is 11; the filter cutoff frequency is set to: ; wherein, the signal bandwidth is B, the AD sampling rate is , and according to engineering experience, the actual cutoff frequency is adjusted on demand on the basis of the value.

[0059] Embodiment 9 On the basis of Embodiment 8, in step S2, the second buffering specifically comprises a substep of: The data is first buffered by the RAM for the interpolation module to read slowly; meanwhile, as long as the amount of data read by the interpolation module equals the set length L, the data buffer interface module is requested for data of length L at a time, so as to match the processing rate before and after interpolation; wherein L can be modified according to requirements.

[0060] Embodiment 10 On the basis of Embodiment 1, in step S2, the interpolation specifically comprises the sub-steps of: interpolating the baseband-processed symbol data to the sampling rate corresponding to the DAC; during interpolation, the interpolation multiple is set as: wherein represents the sampling rate of the DAC, represents the symbol rate of the baseband processing; the interpolator controls the rate of the entire data stream, one data symbol is used for interpolation, and then one or two data symbols are requested from the front module, and the interpolator can be performed according to IQ respectively.

[0061] Embodiment 11 On the basis of Embodiment 1, in step S2, the quadrature up-conversion specifically comprises the sub-steps of: up-converting the data after baseband processing and interpolation to a specified center frequency, and the quadrature up-conversion is as follows: ; wherein, and respectively represent the baseband data after completion of symbol interpolation, and represents the intermediate frequency required for signal output during playback. Specifically, the sine and cosine carriers during optional quadrature up-conversion are generated and stored using matlab and ROM table, and the address of each read data is calculated according to different center frequency control words during use, and after reading, the baseband data after interpolation is multiplied and added, so as to complete the quadrature up-conversion.

[0062] Embodiment 12 On the basis of Embodiment 11, in step S2, after the quadrature up-conversion, the step of: performing interface conversion and clock matching processing on the data after the quadrature up-conversion, so as to adapt to the output form of the DAC.

[0063] Embodiment 13 On the basis of Embodiment 1, in step S2, the DAC conversion specifically comprises the sub-step that the signal output by the DAC is sent to a channel, and after completing filtering in the channel, is output to a related receiving device through a cable.

[0064] Embodiment 14 A high-parallelism data acquisition and playback device based on FPGA, comprising a processor and a memory, the memory storing a computer program, when the computer program is loaded by the processor and executed, the method of any one of embodiments 1-13 is executed.

[0065] Embodiment 15 A high-parallelism data acquisition and playback system based on FPGA, comprising the high-parallelism data acquisition and playback device based on FPGA of embodiment 14.

[0066] The units described in the embodiments of the present application can be implemented by software, or by hardware, or by a combination of software and hardware. The units described can also be located in a single processor. In some cases, the names of the units do not constitute a limitation on the units themselves.

[0067] According to an aspect of the embodiments of the present application, a computer program product or computer program is provided, which includes computer instructions stored in a computer readable storage medium. A processor of a computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions, so that the computer device executes the method provided in the various optional implementation manners described above.

[0068] As another aspect, the embodiments of the present application also provide a computer readable medium, which can be included in the electronic device described in the above embodiments, or can exist separately without being assembled into the electronic device. The computer readable medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to implement the method described in the above embodiments.

Claims

1. A high-parallelism data acquisition and playback method based on FPGA, characterized in that, Includes the following steps: S1, Data Acquisition: Receive external signals, and sequentially perform signal filtering, bandpass sampling, and ADC conversion before storing the data; S2, Data Playback: The acquired data is sequentially buffered, quadrature downconverted, low-pass filtered, buffered, interpolated, quadrature upconverted, and converted by a DAC before being output to the relevant receiving device.

2. The FPGA-based high-parallelism data acquisition and playback method according to claim 1, characterized in that, In step S1, the signal filtering specifically includes the following sub-steps: completing signal filtering within the channel and filtering out out-of-band interference components when the signal enters the digital processing stage.

3. The FPGA-based high-parallelism data acquisition and playback method according to claim 2, characterized in that, In step S1, the bandpass sampling and ADC conversion specifically include the following sub-steps: The signal after channel filtering enters the ADC conversion module through the hardware interface for bandpass sampling and analog-to-digital conversion, and then the bandpass sampled signal is down-converted to baseband for post-processing. According to the bandpass sampling theorem, the sampling rate... The highest frequency of the bandpass signal and the lowest frequency of the bandpass signal. The following relationship must be satisfied: Where n is a positive integer, and its value range is: .

4. The FPGA-based high-parallelism data acquisition and playback method according to claim 3, characterized in that, An anti-aliasing bandpass filter is added before A / D sampling to eliminate spectral aliasing caused by out-of-band noise.

5. The FPGA-based high-parallelism data acquisition and playback method according to claim 1, characterized in that, In step S1, the storage specifically includes the following sub-steps: splicing the data after ADC conversion according to the data interface applicable to the storage medium: achieving matching of data bit width, transmission rate, etc. between the interface between the signal processing board and the storage medium, ensuring that the signal can be stored completely and without error on the storage medium.

6. The FPGA-based high-parallelism data acquisition and playback method according to claim 1, characterized in that, In step S2, the first caching specifically includes the following sub-steps: using RAM to cache the data transmitted from the storage medium to match the data transmission rate between the storage medium and the signal processing board, facilitating continuous processing by subsequent modules; at the same time, another function of this module is to isolate the GTX processing clock from the subsequent data processing clock, avoiding timing issues.

7. The FPGA-based high-parallelism data acquisition and playback method according to claim 1, characterized in that, In step S2, the quadrature downconversion specifically includes the following sub-steps: the signal after bandpass sampling is further shifted from the intermediate frequency to the baseband, which is achieved by reading the quadrature carrier data from the ROM table and multiplying it with the signal respectively.

8. The FPGA-based high-parallelism data acquisition and playback method according to claim 3, characterized in that, In step S2, the low-pass filtering specifically includes the following sub-steps: performing low-pass filtering on the down-converted data to prevent it from degrading the quality of the playback signal; Let the original signal be The data after orthogonal downconversion is as follows: ； ； The second harmonic component is filtered out using a low-pass filter with a cutoff frequency of fc, from which the quadrature components of the original signal are obtained. and ; The filter used is an FIR2 filter with an order of 11; the filter cutoff frequency is set as follows: Wherein, the signal bandwidth is B, and the AD sampling rate is Based on engineering experience, the actual cutoff frequency is adjusted as needed based on this value.

9. The FPGA-based high-parallelism data acquisition and playback method according to claim 8, characterized in that, In step S2, the second cache specifically includes the following sub-steps: The data is first cached in RAM for the interpolation module to read slowly. At the same time, as soon as the amount of data read by the interpolation module is equal to the set length L, it immediately requests a data of length L from the data cache interface module to complete the matching of processing rates before and after interpolation. The value of L can be modified as needed.

10. The FPGA-based high-parallelism data acquisition and playback method according to claim 1, characterized in that, In step S2, the interpolation specifically includes the following sub-steps: The symbol data processed by the baseband is interpolated to the sampling rate corresponding to the DAC; during interpolation, the interpolation factor is set to: ,in Indicates the DAC sampling rate. This indicates the symbol rate of the baseband processing; the rate of the entire data stream is controlled by an interpolator. Interpolation uses one data symbol, and then requests one or two data symbols from the preceding module. The interpolator can be used separately for I and Q.

11. The FPGA-based high-parallelism data acquisition and playback method according to claim 1, characterized in that, In step S2, the orthogonal up-conversion specifically includes the following sub-steps: The data, after baseband processing and interpolation, is frequency-converted to the specified center frequency. The orthogonal upconversion is as follows: ； in, and These represent the baseband data after symbolic interpolation, and... This indicates the intermediate frequency (IF) that the signal needs to be output during playback.

12. The FPGA-based high-parallelism data acquisition and playback method according to claim 11, characterized in that, In step S2, after the quadrature up-conversion, the following step is also included: The data after quadrature upconversion undergoes interface conversion and clock matching to adapt to the output format of the DAC.

13. The FPGA-based high-parallelism data acquisition and playback method according to claim 1, characterized in that, In step S2, the DAC conversion specifically includes the following sub-steps: the signal output by the DAC is sent to the channel, filtered in the channel, and then output to the relevant receiving device via a cable.

14. A high-parallelism data acquisition and playback device based on FPGA, characterized in that, It includes a processor and a memory, wherein the memory stores a computer program that, when loaded by the processor, executes the method as described in any one of claims 1 to 13.

15. A high-parallelism data acquisition and playback system based on FPGA, characterized in that, Includes the FPGA-based high-parallelism data acquisition and playback device as described in claim 14.

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