High-speed comparator and analog-to-digital converter suitable for assembly line ADC (analog-to-digital converter)

Abstract

The high-speed comparator comprises a bias control circuit and a pre-amplifier which are connected with each other, the bias control circuit is used for periodically receiving a first group of control signals, when the first group of control signals is at a low level, the pre-amplifier works normally, and when the first group of control signals is at a low level, the pre-amplifier works normally; when the first group of control signals are in high level, the preamplifier stops working; and the pre-amplifier is used for periodically receiving the second group of control signals, when the second group of control signals is at a low level, the pre-amplifier enters a reproducible moment of a latching stage, and when the second group of control signals is at a high level, the reproducible moment is cut off, so that the pre-amplifier is latched. The power consumption of the comparator is greatly reduced. In a high-speed assembly line ADC, the power consumption of the comparator can be remarkably reduced, the overall power consumption is further reduced, and the benefits brought by the comparator are more obvious along with the increase of the sampling rate.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically to a high-speed comparator and analog-to-digital converter suitable for pipelined ADCs. Background Technology

[0002] High-speed comparators are key modules in analog-to-digital converters (ADCs). For example, Flash ADCs use 2n-1 comparators to process the input signal directly in parallel, requiring 255 comparators for 8-bit resolution. In pipelined ADCs, each pipeline decision stage uses the Flash ADC form, requiring at least 42 comparators in a 14-bit ADC. The power consumption of comparators accounts for a very high proportion of the entire ADC. Therefore, low-power control technology for comparators is crucial.

[0003] High-speed comparators are primarily used in high-speed pipelined ADC architectures. High-speed comparators in high-speed pipelined ADCs typically employ a pre-amplifier + latch structure. Compared to a simple dynamic latch, this structure offers several advantages: the pre-amplifier stage amplifies weak signals, significantly reducing the latch's offset voltage and providing isolation, greatly suppressing feedback noise. It also supports rail-to-rail input, is compatible with low-supply-voltage applications, has strong anti-interference capabilities, and is insensitive to reference voltage fluctuations. The latch improves fast response and speed. However, this structure has disadvantages: the pre-amplifier stage introduces static power consumption, and the longer the regeneration time, the greater the power consumption, reflecting the latch's response bandwidth requirements.

[0004] Therefore, in high-speed pipelined ADCs, how to reduce the power consumption caused by a large number of high-speed comparators has become an urgent problem to be solved. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a high-speed comparator and analog-to-digital converter suitable for pipelined ADCs. The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a high-speed comparator suitable for pipelined ADCs, comprising an interconnected bias control circuit and a preamplifier, wherein: The bias control circuit is used to periodically receive a first set of control signals. When the first set of control signals is low, the preamplifier is enabled to work normally, and when the first set of control signals is high, the preamplifier is disabled. The preamplifier is used to periodically receive a second set of control signals. When the second set of control signals is low, the preamplifier enters the regenerable time of the latching phase. When the second set of control signals is high, the regenerable time ends, and the preamplifier latches.

[0006] In one embodiment of the present invention, the first set of control signals includes control signal RST1 and control signal RST1A; The bias control circuit includes a MOS switch M8 and a MOS capacitor M9, wherein: The gate of the MOS switch M8 is connected to the control signal RST1 terminal, the drain is connected to the bias voltage VB terminal, the source is connected to the drain and source of the MOS capacitor M9, and is connected to the preamplifier. The gate of the MOS capacitor M9 is connected to the control signal RST1A terminal.

[0007] In one embodiment of the present invention, the second set of control signals includes control signal RST2 and control signal RST3; The preamplifier includes MOS switches M0, M1, M2, M3, M4, M5, M6, and M7, wherein: The gate of the MOS switch M0 is connected to the source of the MOS switch M8, the drain of the MOS capacitor M9, and the source of the MOS capacitor M9. The source is connected to the power supply VDD terminal, and the drain is connected to the source of the MOS switch M1 and the source of the MOS switch M2. The gate of the MOS switch M1 is connected to the differential input signal INP terminal, and the drain is connected to the drain of the MOS switch M6, the source of the MOS switch M5, the drain of the MOS switch M3, the gate of the MOS switch M4, and the latch. The gate of the MOS switch M2 is connected to the differential input signal INN terminal, and the drain is connected to the drain of the MOS switch M5, the drain of the MOS switch M7, the gate of the MOS switch M3, the drain of the MOS switch M4, and the latch. The source of the MOS switch M3 and the source of the MOS switch M4 are both grounded, and the gate of the MOS switch M5 is connected to the control signal RST2 terminal. The gates of both MOS switch M6 and MOS switch M7 are connected to the control signal RST3 terminal, and the sources of both MOS switch M6 and MOS switch M7 are connected to the power supply VDD terminal.

[0008] In one embodiment of the present invention, the MOS switch M8, the MOS capacitor M9 and the MOS switch M0 are all PMOS transistors or all NMOS transistors.

[0009] In one embodiment of the present invention, the high-speed comparator further includes a pulse generation circuit, which is connected to the bias control circuit and the preamplifier respectively, for periodically providing a first set of control signals and a second set of control signals.

[0010] In one embodiment of the present invention, the pulse generation circuit includes MOS switch M19, MOS switch M20, MOS switch M21, inverter I5, inverter I6, NAND gate I7, NOR gate I8, NAND gate I9, inverter I10, and inverter I11, wherein: The source of the MOS switch M19 is connected to the power supply VDD terminal, the drain is connected to the drain of the MOS switch M20, the drain of the MOS switch M21, the input terminal of the inverter I5, and the first input terminal of the NAND gate I9, and the gate and the second input terminal of the NAND gate I9 are connected to a latch. The source of the MOS switch M20 and the source of the MOS switch M21 are both grounded, and the gate of the MOS switch M20 and the gate of the MOS switch M21 are both connected to latches. The output terminal of inverter I5 and the input terminal of inverter I6 are both connected to the gate of MOS switch M5. The output terminal of inverter I6 is connected to the third input terminal of NAND gate I9, the first input terminal of NAND gate I7, and the first input terminal of NOR gate I8. The output terminal of NAND gate I9 is ​​connected to the gate of MOS switch M6 and the gate of MOS switch M7. The second input terminal of NAND gate I7 ​​is connected to the output terminal of inverter I10. The input terminal of inverter I10 and the output terminal of NOR gate I8 are both connected to the gate of MOS switch M9. The second input terminal of NOR gate I8 is connected to the output terminal of inverter I11. The input terminal of inverter I11 and the output terminal of NAND gate I7 ​​are both connected to the gate of MOS switch M8.

[0011] In one embodiment of the invention, the high-speed comparator further includes a latch connected to the preamplifier and the pulse generation circuit.

[0012] In one embodiment of the present invention, the latch includes MOS switches M10, M11, M12, M13, M14, M15, M16, M17, and M18, inverters I0, I1, I2, and I3, wherein: The source of the MOS switch M10 is connected to the ground terminal, the drain is connected to the source of the MOS switch M11, the source of the MOS switch M12, the source of the MOS switch M13 and the source of the MOS switch M14, and the gate is connected to the gate of the MOS switch M10 and the second input terminal of the NAND gate I9. The drain of the MOS switch M11 is connected to the drain of the MOS switch M15, the input terminal of the inverter I0, the drain of the MOS switch M16, and the drain of the MOS switch M12, and the gate is connected to the drain of the MOS switch M1 and the drain of the MOS switch M3. The gate of the MOS switch M12 is connected to the output terminal of the inverter I0, the input terminal of the inverter I1, the gate of the MOS switch M21, and the gate of the MOS switch M16. The output terminal of the inverter I1 is connected to the differential output OUTP terminal. The drain of MOS switch M13 is connected to the drain of MOS switch M17, the input terminal of inverter I2, the drain of MOS switch M14, and the drain of MOS switch M18. The gate is connected to the output terminal of inverter I2, the input terminal of inverter I3, the gate of MOS switch M20, and the gate of MOS switch M17. The output terminal of inverter I3 is connected to the differential output OUTN terminal. The gate of the MOS switch M14 is connected to the drain of the MOS switch M2 and the drain of the MOS switch M4; The sources of MOS switch M15, MOS switch M16, MOS switch M17, and MOS switch M18 are all connected to the power supply VDD terminal. The gates of MOS switch M15 and MOS switch M18 are both connected to the gate of MOS switch M10 and the second input terminal of NAND gate I9.

[0013] Secondly, embodiments of the present invention also provide an analog-to-digital converter, including the high-speed comparator described in any of the above embodiments.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: In high-speed pipelined ADCs, numerous high-speed comparators are a crucial component. To reduce overall power consumption, a bias control circuit periodically controls the preamplifier's operating state. Specifically, when the first set of control signals is low, the preamplifier operates normally; when it is high, it stops operating; and when the second set of control signals is low, it enters the regenerable latching phase. When the second set of control signals is high, the regenerable phase ends, and the preamplifier latches. This reduces the preamplifier's power consumption. Furthermore, precise control and shortened regenerable time during the latching phase further reduce power consumption (as the comparator is in the latching phase). Simultaneously, overall performance is maintained. Therefore, this invention significantly reduces comparator power consumption. In high-speed pipelined ADCs, this invention significantly reduces comparator power consumption, thereby lowering overall power consumption. The benefits of this invention become more pronounced as the sampling rate increases.

[0015] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a conventional high-speed comparator provided by the present invention; Figure 2 This is a schematic diagram of a high-speed comparator based on a clock-controlled preamplifier and a latch, provided by the present invention. Figure 3 This is a schematic diagram of a high-speed comparator suitable for use in a pipelined ADC, provided by an embodiment of the present invention. Figure 4 This is a schematic diagram of another high-speed comparator structure suitable for pipelined ADCs provided by an embodiment of the present invention; Figure 5 This is a schematic diagram of a pulse generation circuit provided in an embodiment of the present invention; Figure 6 This is a timing diagram provided in an embodiment of the present invention. Detailed Implementation

[0017] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0018] like Figure 1 As shown, Figure 1 As a traditional preamplifier, it operates continuously during both the preamplification and latching phases; VB1 is on throughout the entire cycle, resulting in high power consumption. At higher sampling rates, the need for greater bandwidth demands leads to even higher power consumption. Figure 2 As shown, Figure 2While controlling the preamplifier's bias current via clock (CLK) can reduce power consumption by half, in practical applications, direct clock control makes the preamplifier's gain susceptible to process variations and PVT changes, resulting in uncontrollable bias current, low reliability, and limitations at higher sampling rates, thus restricting its application scope. Furthermore, Figure 1 and Figure 2 The latch section operates for half a cycle after the comparator enters the latching phase, resulting in high power consumption.

[0019] Based on this, the present invention provides a high-speed comparator suitable for pipelined ADCs. Please refer to [link to relevant documentation]. Figure 3 , Figure 3 This is a schematic diagram of a high-speed comparator suitable for use in a pipelined ADC, provided by an embodiment of the present invention. The high-speed comparator includes a bias control circuit and a preamplifier connected to each other, wherein: The bias control circuit is used to periodically receive the first set of control signals. When the first set of control signals is low, the preamplifier is enabled to work normally, and when the first set of control signals is high, the preamplifier is disabled. The preamplifier is used to periodically receive the second set of control signals. When the second set of control signals is low, the preamplifier enters the regenerable time of the latching phase. When the second set of control signals is high, the regenerable time ends, and the preamplifier latches.

[0020] In one specific embodiment, the first set of control signals includes control signal RST1 and control signal RST1A. See also... Figure 4 The bias control circuit includes a MOS switch M8 and a MOS capacitor M9, wherein: The gate of MOS switch M8 is connected to the control signal RST1 terminal, the drain is connected to the bias voltage VB terminal, the source is connected to the drain and source of MOS capacitor M9, and connected to the preamplifier. The gate of MOS capacitor M9 is connected to the control signal RST1A terminal.

[0021] In one specific embodiment, the second set of control signals includes control signal RST2 and control signal RST3. Please continue reading. Figure 4 The preamplifier includes MOS switches M0, M1, M2, M3, M4, M5, M6, and M7, where: The gate of MOS switch M0 is connected to the source of MOS switch M8, the drain of MOS capacitor M9, and the source of MOS capacitor M9. The source is connected to the power supply VDD terminal, and the drain is connected to the source of MOS switch M1 and the source of MOS switch M2. The gate of MOS switch M1 is connected to the differential input signal INP terminal, and the drain is connected to the drain of MOS switch M6, the source of MOS switch M5, the drain of MOS switch M3, the gate of MOS switch M4, and the latch. The gate of MOS switch M2 is connected to the differential input signal INN terminal, and the drain is connected to the drain of MOS switch M5, the drain of MOS switch M7, the gate of MOS switch M3, the drain of MOS switch M4, and the latch. The source of MOS switch M3 and the source of MOS switch M4 are both grounded, and the gate of MOS switch M5 is connected to the control signal RST2 terminal. The gates of MOS switch M6 and MOS switch M7 are both connected to the control signal RST3 terminal, and the sources of MOS switch M6 and MOS switch M7 are both connected to the power supply VDD terminal.

[0022] Optionally, MOS switch M8, MOS capacitor M9 and MOS switch M0 are all PMOS transistors or all NMOS transistors. The remaining MOS switches can be adjusted by those skilled in the art according to actual use.

[0023] In one specific embodiment, the high-speed comparator of this embodiment further includes a pulse generation circuit, which is connected to the bias control circuit and the preamplifier respectively, for periodically providing a first set of control signals and a second set of control signals.

[0024] Further, please see Figure 5 The pulse generation circuit includes MOS switch M19, MOS switch M20, MOS switch M21, inverter I5, inverter I6, NAND gate I7, NOR gate I8, NAND gate I9, inverter I10, and inverter I11, wherein: The source of MOS switch M19 is connected to the power supply VDD terminal, and the drain is connected to the drain of MOS switch M20, the drain of MOS switch M21, the input terminal of inverter I5, and the first input terminal of NAND gate I9. The gate and the second input terminal of NAND gate I9 are connected to the latch. The source of MOS switch M20 and the source of MOS switch M21 are both grounded, and the gate of MOS switch M20 and the gate of MOS switch M21 are both connected to latches. The output of inverter I5 and the input of inverter I6 are connected to the gate of MOS switch M5. The output of inverter I6 is connected to the third input of NAND gate I9, the first input of NAND gate I7, and the first input of NOR gate I8. The output of NAND gate I9 is ​​connected to the gates of MOS switch M6 and MOS switch M7. The second input of NAND gate I7 ​​is connected to the output of inverter I10. The input of inverter I10 and the output of NOR gate I8 are connected to the gate of MOS switch M9. The second input of NOR gate I8 is connected to the output of inverter I11. The input of inverter I11 and the output of NAND gate I7 ​​are connected to the gate of MOS switch M8.

[0025] In one specific embodiment, the high-speed comparator of this embodiment further includes a latch connected to the preamplifier and the pulse generation circuit.

[0026] Further reading is available upon request. Figure 5 The latch includes MOS switches M10, M11, M12, M13, M14, M15, M16, M17, and M18, inverters I0, I1, I2, and I3, wherein: The source of MOS switch M10 is connected to the ground terminal, the drain is connected to the source of MOS switch M11, the source of MOS switch M12, the source of MOS switch M13 and the source of MOS switch M14, and the gate is connected to the gate of MOS switch M10 and the second input terminal of NAND gate I9. The drain of MOS switch M11 is connected to the drain of MOS switch M15, the input terminal of inverter I0, the drain of MOS switch M16, and the drain of MOS switch M12, and the gate is connected to the drain of MOS switch M1 and the drain of MOS switch M3. The gate of MOS switch M12 is connected to the output terminal of inverter I0, the input terminal of inverter I1, the gate of MOS switch M21, and the gate of MOS switch M16. The output terminal of inverter I1 is connected to the differential output OUTP terminal. The drain of MOS switch M13 is connected to the drain of MOS switch M17, the input terminal of inverter I2, the drain of MOS switch M14, and the drain of MOS switch M18. The gate is connected to the output terminal of inverter I2, the input terminal of inverter I3, the gate of MOS switch M20, and the gate of MOS switch M17. The output terminal of inverter I3 is connected to the differential output OUTN terminal. The gate of MOS switch M14 is connected to the drain of MOS switch M2 and the drain of MOS switch M4; The sources of MOS switch M15, MOS switch M16, MOS switch M17, and MOS switch M18 are all connected to the power supply VDD terminal. The gates of MOS switch M15 and MOS switch M18 are both connected to the gate of MOS switch M10 and the second input terminal of NAND gate I9.

[0027] In this embodiment, when control signals RST1 and RST1A are low, MOS switch M8 is turned on, and the gate voltage of MOS switch M0 is the bias voltage V. B When the upper plate (gate) of MOS capacitor M9 is connected to a low level, MOS capacitor M9 charges, and the Vgs of MOS switch M0 is greater than Vth, allowing the preamplifier to operate normally. When control signals RST1 and RST1A are high, MOS switch M8 is turned off, the upper plate of MOS capacitor M9 is connected to a high level, and the voltage of MOS capacitor M9 changes. According to the law of charge conservation, this causes the Vgs of MOS switch M0 to be less than Vth, and the voltage of the gate of MOS switch M0 to increase. By adjusting the size of MOS capacitor M9, it is ensured that the increased voltage cannot turn on MOS switch M0, at which point the preamplifier stops working, thus achieving a power saving of nearly 50%. See the detailed timing diagram below. Figure 6 .

[0028] In this embodiment, a low-level pulse (e.g.,) of the control signal RST2 is generated by a pulse generation circuit. Figure 6 When control signal RST2 is low, MOS switch M5 is turned on, officially entering the regenerable latching phase. Control signal RST3 is also low, turning on MOS switches M6 and M7, and the comparator performs the final comparison. When control signals RST2 and RST3 are high, the regenerable latching phase ends, and the comparator latches the final comparison result through MOS switches M10 to M18. In this embodiment, the pulse generation circuit allows for precise control of the low-level pulse width of control signal RST2, thereby accurately controlling the regenerable latching phase and saving 50% of power consumption (when the comparator is in the latching phase). See the specific timing diagram below. Figure 6 .

[0029] The pulse generation circuit is implemented as follows: MOS switches M19, M20, and M21 perform logical operations on the clock input CLK, comparator internal nodes NODE_2P and NODE_2N to generate signal NODE_3. Inverting NODE_3 via inverter I5 yields control signal RST2. Precise control of the pulse width of control signal RST2 is achieved by controlling MOS switches M19, M20, M21, and inverter I5. Delaying inverters I5 and I6 yields NODE_4. Logic operations are then performed on NODE_3, NODE_4, and CLK to generate control signals RST1, RST1A, and RST3. The specific timing sequence is as follows: Figure 6 As shown.

[0030] about Figure 6 Explanation of the working sequence: Figure 6 The control signal CLKP is the operating clock of the comparator, and its frequency is consistent with the sampling and holding frequency of the pipelined ADC. Figure 6 In the input signal, 0 represents a low level and 1 represents a high level. When CLKP=0, the comparator is in the pre-amplification stage; when CLKP=1, the comparator is in the latching stage, and CLKN is the complementary signal to CLKP. RST1 and RST1A are the control signal timing sequences for the bias control circuit, used to dynamically bias the pre-amplifier. When the bias is off, power consumption is reduced by nearly 50%. RST2 and RST3 are the control signal timing sequences for the pre-amplifier, used in the latching stage, providing precise control and shortening the latch's regeneration time, saving 50% of power consumption (when the comparator is in the latching stage).

[0031] The circuit structure of this invention is simple and has a small footprint. The bias control circuit consists of only one MOS switch and one MOS capacitor, and the reset control only requires three MOS switches (MOS switch M5, MOS switch M6, and MOS switch M7), making implementation simple and reducing the layout area. Furthermore, control can be achieved using simple NAND, NOR, and inverter logic combinations, making the control method simple and easy to implement.

[0032] This invention is unaffected by process variations and PVT changes. The bias voltage of the preamplifier is generated by the bias control circuit and is temperature-independent. When the MOS switch M0 is turned on, the current can be accurately replicated, ensuring the gain and bandwidth of the preamplifier. The latch reset control circuit can be implemented using small-sized devices, has low parasitics, and through precise control and shortening the latch regeneration time, not only is the speed improved and power consumption reduced, but it is also less susceptible to PVT changes.

[0033] In pipelined ADCs, high-speed comparators are a crucial component, requiring a large number of them throughout the entire ADC. In ADCs with even higher sampling rates, the increased bandwidth demands on high-speed comparators lead to higher power consumption in the preamplifiers and latches. In this case, the power savings achieved by the high-speed comparators provided by this invention become even more significant. Therefore, for high-speed ADC chip design, reducing the power consumption of the preamplifiers and latches can effectively reduce the overall power consumption of the high-speed ADC.

[0034] The high-speed comparator provided by this invention significantly reduces power consumption while maintaining the advantages of a pre-amplifier + latch structure. Firstly, by periodically controlling the on / off state of the pre-amplifier bias current in the high-speed comparator, the bias current is turned off during sampling, saving power consumption; during hold, the bias current is turned on, allowing the pre-amplifier to operate normally, thus saving 50% of the total pre-amplifier power consumption. Secondly, by adding a reset switch, precise pulse control and shortened latch regeneration time during the latching phase save 50% of power consumption (comparator latching phase). It has excellent compatibility with pipelined ADCs and is suitable for ADCs with higher sampling rates; the effect becomes more pronounced as the sampling rate increases.

[0035] This invention also provides an analog-to-digital converter, including the high-speed comparator described in the above embodiments.

[0036] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0037] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0038] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, disclosure, and appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0039] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, any modifications made without departing from the inventive concept should be considered within the scope of protection of the present invention.

Claims

1. A high-speed comparator suitable for pipelined ADCs, characterized in that, Includes interconnected bias control circuitry and a preamplifier, wherein: The bias control circuit is used to periodically receive a first set of control signals. When the first set of control signals is low, the preamplifier is enabled to work normally, and when the first set of control signals is high, the preamplifier is disabled. The preamplifier is used to periodically receive a second set of control signals. When the second set of control signals is low, the preamplifier enters the regenerable time of the latching phase. When the second set of control signals is high, the regenerable time ends, and the preamplifier latches.

2. The high-speed comparator according to claim 1, characterized in that, The first set of control signals includes control signal RST1 and control signal RST1A; The bias control circuit includes a MOS switch M8 and a MOS capacitor M9, wherein: The gate of the MOS switch M8 is connected to the control signal RST1 terminal, the drain is connected to the bias voltage VB terminal, the source is connected to the drain and source of the MOS capacitor M9, and is connected to the preamplifier. The gate of the MOS capacitor M9 is connected to the control signal RST1A terminal.

3. The high-speed comparator according to claim 2, characterized in that, The second set of control signals includes control signal RST2 and control signal RST3; The preamplifier includes MOS switches M0, M1, M2, M3, M4, M5, M6, and M7, wherein: The gate of the MOS switch M0 is connected to the source of the MOS switch M8, the drain of the MOS capacitor M9, and the source of the MOS capacitor M9. The source is connected to the power supply VDD terminal, and the drain is connected to the source of the MOS switch M1 and the source of the MOS switch M2. The gate of the MOS switch M1 is connected to the differential input signal INP terminal, and the drain is connected to the drain of the MOS switch M6, the source of the MOS switch M5, the drain of the MOS switch M3, the gate of the MOS switch M4, and the latch. The gate of the MOS switch M2 is connected to the differential input signal INN terminal, and the drain is connected to the drain of the MOS switch M5, the drain of the MOS switch M7, the gate of the MOS switch M3, the drain of the MOS switch M4, and the latch. The source of the MOS switch M3 and the source of the MOS switch M4 are both grounded, and the gate of the MOS switch M5 is connected to the control signal RST2 terminal. The gates of both MOS switch M6 and MOS switch M7 are connected to the control signal RST3 terminal, and the sources of both MOS switch M6 and MOS switch M7 are connected to the power supply VDD terminal.

4. The high-speed comparator according to claim 3, characterized in that, The MOS switch M8, the MOS capacitor M9, and the MOS switch M0 are all either PMOS transistors or NMOS transistors.

5. The high-speed comparator according to claim 3, characterized in that, It also includes a pulse generation circuit, which is connected to the bias control circuit and the preamplifier respectively, for periodically providing a first set of control signals and a second set of control signals.

6. The high-speed comparator according to claim 5, characterized in that, The pulse generation circuit includes MOS switch M19, MOS switch M20, MOS switch M21, inverter I5, inverter I6, NAND gate I7, NOR gate I8, NAND gate I9, inverter I10, and inverter I11, wherein: The source of the MOS switch M19 is connected to the power supply VDD terminal, the drain is connected to the drain of the MOS switch M20, the drain of the MOS switch M21, the input terminal of the inverter I5, and the first input terminal of the NAND gate I9, and the gate and the second input terminal of the NAND gate I9 are connected to a latch. The source of the MOS switch M20 and the source of the MOS switch M21 are both grounded, and the gate of the MOS switch M20 and the gate of the MOS switch M21 are both connected to latches. The output terminal of inverter I5 and the input terminal of inverter I6 are both connected to the gate of MOS switch M5. The output terminal of inverter I6 is connected to the third input terminal of NAND gate I9, the first input terminal of NAND gate I7, and the first input terminal of NOR gate I8. The output terminal of NAND gate I9 is ​​connected to the gate of MOS switch M6 and the gate of MOS switch M7. The second input terminal of NAND gate I7 ​​is connected to the output terminal of inverter I10. The input terminal of inverter I10 and the output terminal of NOR gate I8 are both connected to the gate of MOS switch M9. The second input terminal of NOR gate I8 is connected to the output terminal of inverter I11. The input terminal of inverter I11 and the output terminal of NAND gate I7 ​​are both connected to the gate of MOS switch M8.

7. The high-speed comparator according to claim 6, characterized in that, It also includes a latch connected to the preamplifier and the pulse generation circuit.

8. The high-speed comparator according to claim 7, characterized in that, The latch includes MOS switches M10, M11, M12, M13, M14, M15, M16, M17, and M18, inverters I0, I1, I2, and I3, wherein: The source of the MOS switch M10 is connected to the ground terminal, the drain is connected to the source of the MOS switch M11, the source of the MOS switch M12, the source of the MOS switch M13 and the source of the MOS switch M14, and the gate is connected to the gate of the MOS switch M10 and the second input terminal of the NAND gate I9. The drain of the MOS switch M11 is connected to the drain of the MOS switch M15, the input terminal of the inverter I0, the drain of the MOS switch M16, and the drain of the MOS switch M12, and the gate is connected to the drain of the MOS switch M1 and the drain of the MOS switch M3. The gate of the MOS switch M12 is connected to the output terminal of the inverter I0, the input terminal of the inverter I1, the gate of the MOS switch M21, and the gate of the MOS switch M16. The output terminal of the inverter I1 is connected to the differential output OUTP terminal. The drain of MOS switch M13 is connected to the drain of MOS switch M17, the input terminal of inverter I2, the drain of MOS switch M14, and the drain of MOS switch M18. The gate is connected to the output terminal of inverter I2, the input terminal of inverter I3, the gate of MOS switch M20, and the gate of MOS switch M17. The output terminal of inverter I3 is connected to the differential output OUTN terminal. The gate of the MOS switch M14 is connected to the drain of the MOS switch M2 and the drain of the MOS switch M4; The sources of MOS switch M15, MOS switch M16, MOS switch M17, and MOS switch M18 are all connected to the power supply VDD terminal. The gates of MOS switch M15 and MOS switch M18 are both connected to the gate of MOS switch M10 and the second input terminal of NAND gate I9.

9. An analog-to-digital converter, characterized in that, Includes the high-speed comparator as described in any one of claims 1 to 8.

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