Communication method, electronic equipment, communication device and storage medium

Abstract

The embodiment of the invention provides a communication method, electronic equipment, a communication device and a storage medium, which are applied to the technical field of signal processing and are used for improving the precision of signal rate measurement. The communication method comprises the steps of obtaining the pulse width of a first clock signal based on a pulse width sequence of an input signal; determining a reference signal pulse width corresponding to each input signal pulse width based on each input signal pulse width and the pulse width of the first clock signal; based on each input signal pulse width and the corresponding reference signal pulse width, determining a clock skew corresponding to each input signal pulse width to obtain a clock skew sequence; performing a sliding window operation on the clock skew sequence based on a window width to obtain an updated clock skew sequence; and under the condition that all clock skew in the updated clock skew sequence is smaller than a skew threshold value, obtaining the signal rate of the input signal based on the corrected input signal pulse width sequence.

Description

Technical Field

[0001] This application relates to the field of signal processing technology, and in particular to a communication method, electronic device, communication apparatus, and storage medium. Background Technology

[0002] In the fields of digital communication and high-speed signal testing, accurate clock recovery is crucial, serving as the foundation for precise jitter analysis, eye diagram plotting, and other operations. In instruments such as oscilloscopes, clock recovery first requires accurately measuring the signal rate to extract accurate clock information. Therefore, high-precision signal rate measurement is a key technical indicator of concern in the industry. Summary of the Invention

[0003] This application discloses a communication method, electronic device, communication apparatus, and storage medium for improving the accuracy of signal rate measurement.

[0004] In a first aspect, this application provides a communication method, comprising: obtaining the pulse width of a first clock signal based on a pulse width sequence of an input signal, wherein the pulse width sequence of the input signal includes multiple input signal pulse widths arranged in chronological order, and the pulse width of the first clock signal is the smallest input signal pulse width in the pulse width sequence of the input signal; determining a reference signal pulse width corresponding to each input signal pulse width based on each input signal pulse width and the pulse width of the first clock signal, wherein the reference signal pulse width is the pulse width corresponding to the smallest integer multiple of the input signal pulse width among multiple integer multiples of the pulse width of the first clock signal; and determining a clock deviation corresponding to each input signal pulse width based on each input signal pulse width and the corresponding reference signal pulse width, thereby obtaining a clock deviation sequence, wherein the clock deviation is the difference between each input signal pulse width and the corresponding reference signal pulse width. A sliding window operation is performed on the clock skew sequence based on the window width to obtain an updated clock skew sequence. The sliding window operation includes multiple sliding window processes, with the step size between windows corresponding to each sliding window process being the sliding window step size. Each sliding window process includes: if the change in clock skew within the window is greater than a change threshold, correcting the input signal pulse width corresponding to the clock skew within the window and updating the clock skew sequence within the window. Here, the window width is a preset time interval, and the change value is the difference between the maximum and minimum clock skew values ​​within the window. If all clock skews in the updated clock skew sequence are less than the skew threshold, the signal rate of the input signal is obtained based on the corrected input signal pulse width sequence.

[0005] In this embodiment, by introducing a sliding window-based correction mechanism, the problem of inaccurate signal rate measurement caused by signal jitter is effectively improved on the one hand, and the efficiency of signal rate measurement is improved while ensuring the accuracy of signal rate measurement on the other hand, thereby achieving high-precision and high-efficiency signal rate recovery. Specifically, an initial reference clock signal (i.e., the first clock signal) is established using the smallest input signal pulse width among multiple input signal pulse widths, and the deviation between each input signal pulse width and an integer multiple of the pulse width of the nearest first clock signal (i.e., the reference signal pulse width) is calculated to form a clock deviation sequence. Theoretically, under ideal jitter-free conditions, the values ​​of each input signal pulse width are accurate, and the signal rate is the reciprocal of the pulse width of the first clock signal, and each input signal pulse width should be an integer multiple of the pulse width of the first clock signal, that is, all deviations should be 0. However, this application notes that due to signal jitter, the values ​​of the input signal pulse widths are not completely accurate, so using the reciprocal of the pulse width of the first clock signal as the signal rate may also be inaccurate. This application utilizes the property that, theoretically, the pulse width of the input signal should be an integer multiple of the pulse width of the first clock signal. The resulting clock deviation sequence can reflect the clock deviation distribution of the input signal pulse width. Then, in the correction phase, a sliding window mechanism is used to traverse the clock deviation sequence. When the deviation change value within the window (the difference between the maximum and minimum clock deviation values ​​within the window) exceeds a preset threshold, the pulse width corresponding to the steepest change point within the window (i.e., the point where signal jitter is most likely) is specifically corrected. This avoids the defect of inaccurate rate calculation caused by inaccurate values ​​of individual input signal pulse widths (misjudgments caused by severe jitter).

[0006] Furthermore, compared to global optimization algorithms that require complex fitting or adjustment for each data point, the sliding window strategy of this embodiment significantly reduces computational complexity. It avoids handling all subtle jitter, focusing instead on significant aberrations exceeding a threshold caused by cumulative effects, achieving a good balance between accurate correction and computational efficiency. The pulse width sequence after sliding window correction more realistically reflects the ideal periodic characteristics of the signal, thereby improving the accuracy of signal rate calculation.

[0007] In one possible implementation, correcting the input signal pulse width corresponding to the clock deviation includes: when the change in clock deviation within the window is greater than a change threshold and the clock deviation jumps downward, the corrected input signal pulse width is greater than the uncorrected input signal pulse width by the pulse width corresponding to a first clock signal; and when the change in clock deviation within the window is greater than a change threshold and the clock deviation jumps upward, the corrected input signal pulse width is less than the uncorrected input signal pulse width by the pulse width corresponding to a first clock signal.

[0008] In this embodiment, when the deviation change exceeds a threshold using a sliding window, the direction of the deviation jump is further analyzed to perform targeted correction: When the clock deviation jumps downward, it indicates that the current pulse width is "shorter" than its closest ideal integer multiple reference pulse width. This usually means that the pulse width may have been "undercounted" by a complete clock cycle (the pulse width corresponding to the first clock signal) in practice. In this case, increasing the corrected pulse width by the pulse width corresponding to the first clock signal helps to compensate for the missing cycle count and bring the pulse width estimate back to near the correct integer multiple reference. When the clock deviation jumps upward, it indicates that the current pulse width is "longer," and it is very likely that the pulse width corresponding to the first clock signal has been "overcounted." In this case, decreasing the corrected pulse width by the pulse width corresponding to the first clock signal helps to eliminate redundant cycle counts and correct overestimation errors.

[0009] In one possible implementation, the method further includes: increasing the window width if, in the updated clock skew sequence, there is at least one clock skew greater than or equal to a skew threshold; and performing a sliding window operation on the clock skew sequence based on the increased window width to obtain the updated clock skew sequence.

[0010] In this embodiment, the initial fixed window width may not be able to effectively capture all integer-cycle misjudgments caused by severe jitter or complex noise patterns. By setting a closed-loop feedback rule that "if a clock deviation exceeding the deviation threshold still exists after scanning, the window width is increased and the sliding window operation is re-executed," the algorithm can intelligently judge the current correction effect. If it has not fully converged (i.e., there is still a large deviation), the detection field of view is automatically widened (the window is increased), which may discover and correct global, cumulative errors that are masked or not accurately located under a smaller window. This self-adjusting mechanism ensures that the correction process can move towards completely eliminating significant deviations.

[0011] In one possible implementation, increasing the window width includes: increasing the width of the sliding window from X times the pulse width of the first clock signal to (X+1) times the pulse width of the first clock signal, and continuing to slide and scan subsequent clock offsets, where X is a positive integer.

[0012] In this embodiment, the "pulse width of the first clock signal" (i.e., the minimum pulse width) is used as the adjustment reference unit, ensuring that the expansion of the window is strictly aligned with the clock cycle characteristics of the signal itself. This avoids the uncertainties that may arise from using arbitrary or unitless step sizes for adjustment, ensuring that each window increase corresponds to precisely covering one more potential clock cycle position on the time axis. This is more conducive to systematically and structurally capturing and correcting deviation patterns caused by misjudgments of integer numbers of cycles, enhancing the reliability of the entire adjustment process and the consistency of the results.

[0013] In one possible implementation, X is greater than or equal to 3 and less than or equal to 10.

[0014] In this embodiment, the lower limit of the window width is set to be no less than the pulse width of three first clock signals (X≥3), ensuring that the window has basic signal observation capabilities. A window with a width covering at least three pulse widths of the first clock signals can effectively accommodate at least one complete signal transition cycle and the necessary context information, enabling it to reliably distinguish between random small-amplitude jitter and systematic, abrupt deviations caused by misjudgments of integer cycles. This avoids misjudgments (e.g., misidentifying normal jitter as abrupt changes) or missed detections of consecutive errors that may occur due to insufficient field of view when the window is too narrow, ensuring the stability and accuracy of the initial detection. Furthermore, setting the upper limit to no more than 10 pulse widths of the first clock signals (X≤10) effectively controls computational complexity and prevents excessive smoothing.

[0015] In one possible implementation, the variation threshold is the pulse width of the first clock signal.

[0016] In this embodiment, by directly linking the change threshold to the signal's own characteristic—the "pulse width of the first clock signal"—it means that the standard for judging whether a "sudden change" exists within a window is based on the ideal period length of the signal itself. When the difference between the maximum and minimum values ​​of the clock deviation within the window exceeds the pulse width of a first clock signal, it physically indicates that at least one cumulative misjudgment of an integer number of clock cycles has occurred within the window (e.g., a pulse width is under- or over-counted by a complete first clock signal pulse width). This threshold based on the intrinsic scale of the signal is more reasonable and universal than arbitrarily setting a fixed numerical threshold (such as a voltage or time value). It can adapt to signals of different rates, effectively avoiding missed detections (threshold too high) or false detections (threshold too low) caused by improper threshold settings, and ensuring that only significant deviations truly caused by integer period errors will trigger the correction mechanism.

[0017] In one possible implementation, obtaining the signal rate of the input signal based on the modified input signal pulse width sequence includes: obtaining the signal rate of the input signal using the least squares method based on the modified input signal pulse width sequence.

[0018] In this embodiment, the least squares method is used to calculate the signal rate based on the corrected pulse width sequence. This combines the advantage of front-end sliding window correction in eliminating integer errors with back-end mathematical optimization theory, thereby improving the accuracy of signal rate measurement.

[0019] In one possible implementation, the signal rate of the input signal is obtained using the least squares method based on the modified input signal pulse width sequence. This includes: obtaining a second clock signal based on the modified input signal pulse width sequence, where the pulse width corresponding to the second clock signal is the smallest signal pulse width in the modified input signal pulse width sequence; obtaining the number of clock pulse widths contained in each modified input signal pulse width based on the second clock signal, where the number of clock pulse widths is the ratio of the corresponding modified input signal pulse width to the pulse width of the second clock signal; and obtaining the signal rate of the input signal using the least squares method based on the number of clock pulse widths corresponding to each modified input signal pulse width. The least squares method is used to adjust the signal rate and phase to minimize the sum of squares of the deviations between the clock edge and the edge of the corresponding output signal, obtained by summing the product of the reciprocal of the signal rate and the number of clock pulse widths corresponding to each modified input signal pulse width, and the target phase corresponding to each modified input signal pulse width.

[0020] In this embodiment, the corrected data is not directly used for the final calculation. Instead, an updated clock reference—a second clock signal (whose pulse width is the minimum value in the corrected sequence)—is extracted first. The pulse width corresponding to the second clock signal is a more accurate reference than the initial "first clock signal pulse width," generated based on higher-quality, more ideal corrected data. Based on this, the precise number of clock cycles (which can be a non-integer multiple) contained in each corrected pulse width is calculated using this superior reference. This is equivalent to performing data preprocessing and parameter pre-calibration before entering the final least-squares optimization, providing a significantly improved initial starting point for subsequent mathematical optimization, thereby achieving higher overall final accuracy. Furthermore, the least-squares method used in this embodiment minimizes the overall deviation (sum of squared errors) between the ideal clock edge generated based on the estimated clock parameters (the reciprocal of the signal rate, corresponding to the minimum signal pulse width, i.e., the clock signal pulse width and phase) and the actual data edge of the original input signal through mathematical optimization. Since the ideal clock edge position is directly determined by both the signal rate and phase parameters, joint adjustment and optimization of these two parameters using the least squares method can systematically eliminate residual random errors and small systematic deviations. This makes the final calculated signal rate and phase values ​​statistically optimal estimates, closer to the true values, thus ensuring the theoretically high accuracy of the clock recovery results.

[0021] In one possible implementation, the communication method is applied to a communication system, which includes a signal generation device and a clock recovery device. The signal generation device is used to execute any of the communication methods described above. The clock recovery device includes a phase detection unit and a voltage-controlled oscillator (VCO) unit. After obtaining the signal rate of the input signal, the communication method further includes: the signal generation device inputting the signal rate to the VCO unit to obtain a recovered clock signal output by the VCO unit, which is used for clock recovery. The phase detection unit outputs a control signal based on the recovered clock signal and a mapping table. The mapping table characterizes the mapping relationship between the control signal and the input signal levels corresponding to the transition edges of the recovered clock signal. The control signal is used to control the VCO unit to adjust its oscillation frequency and phase so that the edges of the recovered clock signal and the input signal are synchronized.

[0022] In this embodiment, the calculated precise signal rate is input to the voltage-controlled oscillator (VCO) unit, which can directly generate a highly matched recovery clock signal. More importantly, by introducing a feedback control loop based on a mapping table (which uses the input signal level corresponding to the transition edge of the recovery clock to look up the table and output a control signal to fine-tune the frequency and phase of the VCO unit), the phase detection unit's control strategy based on the mapping table provides an efficient and robust phase synchronization mechanism. Compared to calculating the control signal by setting up hardware circuits such as adders and comparators, this application does not require complex hardware circuits but can quickly obtain the result by looking up the table, greatly reducing computational complexity and significantly improving phase detection speed.

[0023] In one possible implementation, in the mapping table, when the input signal level corresponding to a transition edge of the recovery clock signal is high, and the input signal level corresponding to the preceding transition edge of the recovery clock signal is high, the control signal is low. When the input signal level corresponding to a transition edge of the recovery clock signal is high, and the input signal level corresponding to the preceding transition edge of the recovery clock signal is low, the control signal is high. When the input signal level corresponding to a transition edge of the recovery clock signal is low, and the input signal level corresponding to the preceding transition edge of the recovery clock signal is high, the control signal is high. When the input signal level corresponding to a transition edge of the recovery clock signal is low, and the input signal level corresponding to the preceding transition edge of the recovery clock signal is low, the control signal is low.

[0024] In this embodiment, by examining only the timing of the recovery clock transition and the input signal level (high or low) of the previous moment, it is possible to clearly determine whether the current phase relationship is "leading" or "lagging," and output a corresponding binary control signal (high or low level) to instruct the voltage-controlled oscillator (VCO) unit to "accelerate" or "decelerate." For example, when the recovery clock edge captures the input signal changing from "high" to "low" (corresponding to the third case in the embodiment), it indicates that the recovery clock may be ahead of the effective data window of the input signal. At this time, a "high" level control signal is output to cause the VCO unit to decelerate appropriately to align the phase. This avoids complex analog voltage comparisons or digital calculations, resulting in fast decision-making speed, small hardware implementation area, and low power consumption, making it suitable for application in clock data recovery circuits of high-speed serial interfaces.

[0025] Secondly, this application provides an electronic device, including a communication interface and a processor. The processor is coupled to the communication interface and is used to execute any of the communication methods described in the first aspect.

[0026] Thirdly, this application provides a communication device, comprising: a minimum pulse width calculation module, configured to obtain the pulse width of a first clock signal based on a pulse width sequence of input signals, wherein the pulse width sequence of input signals includes multiple input signal pulse widths arranged in chronological order, and the pulse width of the first clock signal is the smallest input signal pulse width in the pulse width sequence of input signals; a reference pulse width calculation module, configured to determine a reference signal pulse width corresponding to each input signal pulse width based on each input signal pulse width and the pulse width of the first clock signal, wherein the reference signal pulse width is the pulse width corresponding to the smallest integer multiple of the pulse width of the first clock signal that has the smallest difference from the input signal pulse width; and a clock deviation calculation module, configured to determine the clock deviation corresponding to each input signal pulse width based on each input signal pulse width and the corresponding reference signal pulse width, thereby obtaining a clock deviation sequence, wherein the clock deviation is the difference between each input signal pulse width and the corresponding reference signal pulse width. The pulse width correction module performs a sliding window operation on the clock offset sequence based on the window width to obtain an updated clock offset sequence. The sliding window operation includes multiple sliding window processes, with the step size between windows for each process being the sliding window step size. Each sliding window process includes: if the change in clock offset within the window is greater than a threshold, correcting the input signal pulse width corresponding to the clock offset within the window and updating the clock offset sequence within the window. The window width is a preset time interval, and the change value is the difference between the maximum and minimum clock offset values ​​within the window. The judgment module, when all clock offsets in the updated clock offset sequence are less than the offset threshold, determines the signal rate of the input signal based on the corrected input signal pulse width sequence.

[0027] Fourthly, this application provides a computer-readable storage medium including instructions. When executed on a processor, the instructions cause the processor to perform any of the communication methods described in the first aspect.

[0028] The technical principles and beneficial effects of the second, third, and fourth aspects can be referred to the relevant explanations in the first aspect above, and will not be repeated here. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This application provides a flowchart illustrating a communication method according to an embodiment. Figure 1 ; Figure 2 This illustration shows a schematic diagram of the pulse width sequence of an input signal provided in an embodiment of this application; Figure 3 A schematic diagram of a sliding window operation provided in an embodiment of this application is shown; Figure 4 This application provides a flowchart illustrating a communication method according to an embodiment. Figure 2 ; Figure 5 This application provides a flowchart illustrating a communication method according to an embodiment. Figure 3 ; Figure 6 This application provides a flowchart illustrating a communication method according to an embodiment. Figure 4 ; Figure 7 A schematic diagram of a clock recovery circuit provided in an embodiment of this application is shown; Figure 8 This paper shows a schematic diagram of the structure of a half-speed phase detector provided in an embodiment of this application; Figure 9 The diagram shows the output waveform of a half-speed phase detector provided in an embodiment of this application. Figure 10 This paper shows a schematic diagram of the structure of a clock recovery device provided in an embodiment of this application; Figure 11 The diagram shows the output waveform of a half-speed phase detector model provided in an embodiment of this application. Figure 12 A schematic diagram of the structure of a communication system provided in an embodiment of this application is shown; Figure 13 This application provides a flowchart illustrating a communication method according to an embodiment. Figure 5 ; Figure 14 This paper shows a schematic diagram of the structure of a communication device provided in an embodiment of this application; Figure 15 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown.

[0031] Explanation of reference numerals in the attached figures: 1- Clock recovery circuit; 10-Phase-locked loop structure; 101-Phase detector; 102-Loop filter; 103-Voltage controlled oscillator; 100-half-speed phase detector; 1001 - First D flip-flop; 1002 - Second D flip-flop; 1003 - XOR circuit; 3-Communication system; 31 - Signal generating device; 4- Clock recovery device; 41-Phase detection unit; 42-Judgment unit; 43-Loop filter unit; 44-Voltage controlled oscillator unit; 6-communication device; 61 - Minimum pulse width calculation module; 62 - Reference pulse width calculation module; 63 - Clock deviation calculation module; 64 - Pulse width correction module; 65 - Judgment module; 8-Electronic devices; 81-Processor; 82-Memory; 83-Communication interface. Detailed Implementation

[0032] It should be noted that the terms "first" and "second" used in the embodiments of this application are only used to distinguish features of the same type and should not be construed as indicating relative importance, quantity, order, etc.

[0033] The terms "exemplary" or "for example" used in the embodiments of this application are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0034] The terms “coupling,” “coupled,” and “connection” used in the embodiments of this application should be interpreted broadly. For example, they can refer to a physical direct connection or an indirect connection achieved through electronic devices.

[0035] As current high-speed digital design evolves towards faster speeds and greater data throughput, increasingly higher demands are being placed on the transmission speed of communication systems. As a crucial component, communication interface technology is also continuously improving its transmission bandwidth to keep pace with the times.

[0036] Serial communication technology, due to its advantages of high transmission rate, strong anti-interference capability, and small number of channels and pins required, has gradually replaced traditional parallel solutions and become the mainstream technology for implementing high-speed communication interfaces. Specifically, serial communication technology can include, but is not limited to, peripheral component interconnect express (PICE) protocol, universal serial bus (USB), and serializer / deserializer (SerDes) interface technologies.

[0037] In high-speed serial transmission, to avoid clock skew issues in parallel transmission, the clock signal (CLK) is embedded into the data stream during transmission. The receiving end then needs to extract the clock information using clock data recovery (CDR) technology and sample the data based on the recovered clock to ensure the accuracy and reliability of signal transmission and reception.

[0038] Example 1: Clock recovery methods for high-speed serial interfaces such as SerDes, PCIe, and USB often employ simple algorithms, such as estimating the signal rate based on the minimum pulse width. However, these methods are susceptible to interference when the signal exhibits severe jitter, noise, or complex coding patterns, potentially leading to misjudgments of integer multiples of the basic clock unit and thus introducing fundamental errors. These errors propagate throughout the recovery chain, causing the recovered clock information (which may include clock frequency or phase) to deviate from the true value, significantly impacting the reliability of measurement results from downstream analysis modules such as jitter and eye diagram measurements. Achieving high-precision and robust clock recovery in high-jitter environments has become a key technical challenge for improving the performance of test instruments.

[0039] Clock recovery first requires accurate measurement of the signal rate in order to extract accurate clock information. Therefore, high-precision signal rate measurement is a key technical indicator of interest in the industry. To improve the accuracy of signal rate measurement, this disclosure provides a communication method that effectively mitigates the problem of misjudgment of integer clock cycles caused by signal jitter by introducing a sliding window-based correction mechanism, thereby achieving high-precision and high-efficiency signal rate measurement. Figure 1 As shown, Figure 1The following is a flowchart illustrating a communication method provided in an embodiment of this application, specifically including steps S110-S150: S110. Based on the pulse width sequence of the input signal, obtain the pulse width of the first clock signal.

[0040] In some possible implementations, the input signal can be a non-return-to-zero (NRZ) and n-level pulse amplitude modulation (PAMn) signal. For example... Figure 2 As shown, Figure 2 This illustration shows a schematic diagram of an input signal pulse width sequence according to an embodiment of this application. The input signal pulse width sequence includes multiple input signal pulse widths arranged in time order (e.g., t1, t2, t3, t4, ..., tn-1, tn). By performing edge detection on the input signal waveform (e.g., the time point when the voltage crosses a preset threshold), a series of time intervals between adjacent edges are calculated, i.e., the "pulse width sequence". The pulse width of the first clock signal is the smallest input signal pulse width in the input signal pulse width sequence.

[0041] like Figure 2 As shown, the pulse width sequence can include: first pulse width = t2-t1, second pulse width = t3-t2, third pulse width = t4-t3, ..., n-1th pulse width = tn-tn-1.

[0042] In some implementations, an edge detection module can be configured in the detection device, such as a digital signal processor (DSP). When the sampled input signal voltage changes from below a threshold to above a threshold (or vice versa), the precise sampling timestamp (e.g., t1, t2, t3, t4, ..., tn-1, tn) is recorded. The difference between consecutive timestamps is calculated to obtain a pulse width array or pulse width sequence. A comparator is used to find the minimum value in the array or sequence, and the smallest input signal pulse width is output as the pulse width of the first clock signal.

[0043] S120. Based on the pulse width of each input signal and the pulse width of the first clock signal, determine the reference signal pulse width corresponding to each input signal pulse width.

[0044] In some possible implementations, the reference signal pulse width is the pulse width corresponding to the smallest integer multiple of the difference between the pulse width of the first clock signal and the pulse width of the input signal.

[0045] Theoretically, each actual pulse width in the pulse width sequence of the input signal should include an integer number of pulse widths of the first clock signal. Calculate the ratio or quotient of each actual pulse width (e.g., first pulse width = t2 - t1, second pulse width = t3 - t2, third pulse width = t4 - t3, ..., n-1th pulse width = tn - tn-1) to the pulse width of the first clock signal. Round this ratio or quotient to the nearest integer, and select the integer multiple that is closest to the measured value. The pulse width corresponding to this value is the "reference signal pulse width".

[0046] In some implementations, the input signal edge timestamps are t1=0.98ns, t2=2.93ns, t3=3.91ns, t4=6.86ns, and t5=8.81ns, for example.

[0047] The pulse width sequence is as follows: first pulse width = 1.95ns, second pulse width = 0.98ns, third pulse width = 2.95ns, and fourth pulse width = 1.95ns. The minimum pulse width is the second pulse width = 0.98ns, so the second pulse width = 0.98ns is taken as the pulse width of the first clock signal.

[0048] The reference signal pulse width with a first pulse width of 1.95ns is denoted as the first reference signal pulse width. Then, the first pulse width / second pulse width = 1.95ns / 0.98ns ≈ 1.99. 1.99 is rounded to 2. The first reference signal pulse width = 2 × 0.98 = 1.96ns.

[0049] The reference signal pulse width with a second pulse width of 0.98ns is denoted as the second reference signal pulse width. Then, we have: second pulse width / second pulse width = 0.98ns / 0.98ns = 1, and the second reference signal pulse width = 0.98ns.

[0050] The reference signal pulse width with a third pulse width of 2.95ns is denoted as the third reference signal pulse width. Then, the third pulse width / the second pulse width = 2.95ns / 0.98ns ≈ 3.01. 3.01 is rounded to 3. Therefore, the third reference signal pulse width = 3 × 0.98 = 2.94ns.

[0051] The fourth pulse width is 1.95ns. The reference signal pulse width is denoted as the fourth reference signal pulse width. Then, the fourth pulse width / the second pulse width = 1.95ns / 0.98ns ≈ 1.99. 1.99 is rounded to 2. The fourth reference signal pulse width = 2 × 0.98 = 1.96ns.

[0052] S130. Based on the pulse width of each input signal and the corresponding pulse width of the reference signal, determine the clock deviation corresponding to each input signal pulse width to obtain the clock deviation sequence.

[0053] In some possible implementations, clock skew is the difference between each input signal pulse width and its corresponding reference signal pulse width, i.e., clock skew = input signal pulse width - reference signal pulse width. This sequence of differences is called the "clock skew sequence," and it quantifies how much each pulse width deviates from its ideal integer multiple of its period; ideally, without jitter, all deviations should be zero. Figure 3 As shown, Figure 3 The diagram illustrates a sliding window operation according to an embodiment of this application, where the horizontal axis represents time and the vertical axis represents clock deviation.

[0054] In some implementations, the example corresponding to step S120 will continue to be used. The clock deviation with a first pulse width of 1.95ns is denoted as the first clock deviation. Then, the first clock deviation = first pulse width - first reference signal pulse width = 1.95ns - 1.96ns = -0.01ns.

[0055] The clock deviation of the second pulse width = 0.98ns is denoted as the second clock deviation. Then: Second clock deviation = Second pulse width - Second reference signal pulse width = 0.98ns - 0.98ns = 0.00ns.

[0056] The clock deviation with a third pulse width of 2.95ns is denoted as the third clock deviation. Then, the third clock deviation = third pulse width - third reference signal pulse width = 2.95 - 2.94 = 0.01ns.

[0057] The clock deviation of the fourth pulse width = 1.95ns is denoted as the fourth clock deviation. Then: Fourth clock deviation = fourth pulse width - fourth reference signal pulse width = 1.95ns - 1.96ns = -0.01ns.

[0058] S140. Perform a sliding window operation on the clock skew sequence based on the window width to obtain an updated clock skew sequence.

[0059] In some possible implementations, the window width is a preset time interval. A window width can be X times the pulse width of the first clock signal, where X can be a positive integer greater than or equal to 3 and less than or equal to 10. For example, ... Figure 3 As shown, a window width can be three times the pulse width of the first clock signal, meaning a window width can cover three consecutive clock offset values.

[0060] Setting the lower limit of the window width to no less than the pulse width of three first clock signals (X≥3) ensures that the window has basic signal observation capabilities. A window with a width covering at least three pulse widths of the first clock signals can effectively accommodate at least one complete signal transition cycle and the necessary contextual information, enabling it to reliably distinguish between random small-amplitude jitter and systematic, abrupt deviations caused by misjudgments of integer cycles. This avoids misjudgments (e.g., misidentifying normal jitter as abrupt changes) or missed detections of consecutive errors that may occur due to insufficient field of view when the window is too narrow, ensuring the stability and accuracy of the initial detection. Furthermore, setting the upper limit to no more than the pulse width of ten first clock signals (X≤10) effectively controls computational complexity and prevents excessive smoothing. This upper limit ensures that the sliding window operation always operates within a limited and manageable range, avoiding the problems of a sharp increase in computational resources and a decrease in real-time performance caused by unlimited window enlargement. More importantly, an excessively wide window (such as one much wider than the pulse width of 10 first clock signals) can over-smooth the details of the clock skew sequence, potentially masking discrete, localized integer-cycle misjudgments, thus weakening the targetedness and accuracy of the correction algorithm. Setting the upper limit within the pulse width of 10 first clock signals allows the algorithm to moderately expand its scope to handle more complex error patterns while maintaining sufficient attention to local mutations, achieving the optimal balance between correction capability and computational efficiency.

[0061] The sliding window operation involves multiple sliding window processes. The step size between the windows corresponding to each sliding window process is called the sliding window step size. The sliding window step size can be smaller than the window width to avoid missed detections. The sliding window operation slides along the deviation sequence according to the sliding window step size.

[0062] In some scenarios, when the signal fluctuates drastically, the rounding in step S120 may lead to errors in determining integer multiples. For example, a pulse width that should be two first clock signals might be misjudged as the pulse width of three first clock signals. This can create abrupt changes in the deviation sequence that are close to the pulse width of one first clock signal.

[0063] In view of this, in some embodiments, each sliding window process includes: if the change in clock offset within the window is greater than a threshold, correcting the pulse width of the input signal corresponding to the clock offset within the window and updating the clock offset sequence within the window. If the change in clock offset within the window is less than the threshold, no correction is made, and the sliding window operation continues.

[0064] The change in clock skew within the window can be the difference between the maximum and minimum clock skew values ​​within the window, i.e., the change in clock skew = maximum clock skew - minimum clock skew. The change threshold can be the pulse width of the first clock signal. This step detects and corrects such errors by scanning the skew sequence through a sliding window.

[0065] By directly linking the change threshold to a characteristic of the signal itself—the pulse width of the first clock signal—it means that the standard for judging whether a "sudden change" exists within a window is based on the ideal period length of the signal itself. When the difference between the maximum and minimum values ​​of the clock deviation within the window exceeds the pulse width of a first clock signal, it physically indicates that at least one cumulative misjudgment of an integer number of clock cycles has occurred within that window (e.g., a pulse width is under- or over-counted by a complete first clock signal pulse width). This threshold based on the intrinsic scale of the signal is more reasonable and universal than arbitrarily setting a fixed threshold value (such as a voltage or time value). It can adapt to signals of different rates, effectively avoiding missed detections (threshold too high) or false detections (threshold too low) caused by improper threshold settings, and ensuring that only significant deviations truly caused by integer period errors will trigger the correction mechanism.

[0066] In other scenarios, when correcting the pulse width of the input signal corresponding to the clock deviation within the correction window, the position with the steepest change in adjacent deviations within the abrupt change window is found. The pulse width corresponding to this position is most likely to be misjudged as an integer, and can be corrected according to the direction of the deviation jump.

[0067] Specifically, in some implementations, such as Figure 4 As shown, Figure 4 This paper illustrates a flowchart of a communication method provided in an embodiment of this application. The correction of the input signal pulse width corresponding to the clock deviation specifically includes steps a1-a2: Step a1: When the change value of the clock deviation within the window is greater than the change threshold and the clock deviation jumps downward, the pulse width of the corrected input signal is greater than the pulse width of the input signal before correction by the pulse width corresponding to the first clock signal.

[0068] Step a2: When the change in clock deviation within the window is greater than the change threshold and the clock deviation jumps upward, the corrected input signal pulse width is less than the original input signal pulse width by the pulse width corresponding to the first clock signal.

[0069] In some examples, when performing sliding window processing, the deviation sequence is traversed, and the change in clock deviation within the window is calculated in each iteration as the maximum value of clock deviation (max) minus the minimum value of clock deviation (min). If the change in clock deviation is greater than the change threshold, the index i of the largest absolute value |clock deviation[i+1] - clock deviation[i]| within the window is found, and then the integer multiples of the i-th pulse width are corrected by ±1, and all subsequent related calculations are updated.

[0070] In a specific embodiment, taking the pulse width of the first clock signal as 1.0 ns, the change threshold as the pulse width of the first clock signal as 1.0 ns, and the window width as 3 times the pulse width of the first clock signal as an example.

[0071] The measured pulse width of a certain input signal is 3.07 ns. The calculated ratio of the measured pulse width to the pulse width of the first clock signal is approximately 3.27 / 1.0 ≈ 3.27. The reference signal pulse width is 3.0 ns, and the clock offset is 3.27 - 3.0 = +0.27 ns. If the subsequent clock offset sequence shows a sudden change: […, +0.27, -0.82, -0.72…], for the window [+0.27, -0.82, -0.72], the change within the window is 0.27 - (-0.82) = 1.09 ns. 1.09 ns is greater than the change threshold, which is the pulse width of the first clock signal, 1.0 ns.

[0072] Furthermore, since the change from +0.27 to -0.82 is determined to be a downward transition, the integer multiple of the pulse width of a certain input signal is corrected from 3 to 4. After correction, the reference pulse width is 4.0 ns, and the new deviation is 3.27 - 4.0 = -0.73 ns. At this point, the deviation sequence becomes […, -0.73, -0.82, -0.72…], which has better continuity with the surrounding deviations.

[0073] In this embodiment, when the deviation change exceeds a threshold using a sliding window, the direction of the deviation jump is further analyzed to perform targeted correction: When the clock deviation jumps downward, it indicates that the current pulse width is "shorter" than its closest ideal integer multiple reference pulse width. This usually means that the pulse width may have been "undercounted" by a complete clock cycle (the pulse width corresponding to the first clock signal) in practice. In this case, increasing the corrected pulse width by the pulse width corresponding to the first clock signal helps to compensate for the missing cycle count and bring the pulse width estimate back to near the correct integer multiple reference. When the clock deviation jumps upward, it indicates that the current pulse width is "longer," and it is very likely that the pulse width corresponding to the first clock signal has been "overcounted." In this case, decreasing the corrected pulse width by the pulse width corresponding to the first clock signal helps to eliminate redundant cycle counts and correct overestimation errors.

[0074] S150. If all clock deviations in the updated clock deviation sequence are less than the deviation threshold, the signal rate of the input signal is obtained based on the corrected input signal pulse width sequence.

[0075] In some possible implementations, the pulse width sequence is considered sufficiently corrected when the sliding window correction is complete and all values ​​in the entire deviation sequence are less than the deviation threshold. At this point, the final signal rate is calculated based on the corrected, more accurate pulse width sequence.

[0076] The deviation threshold can be determined based on the pulse width of the first clock signal. For example, the deviation threshold can be equal to the product of a preset coefficient and the pulse width of the first clock signal, such as deviation threshold = 0.1 × pulse width of the first clock signal.

[0077] In some implementations, the signal rate corresponding to the smallest input signal pulse width in the modified input signal pulse width sequence can be used as the signal rate of the input signal.

[0078] In other implementations, the signal rate of the input signal can be obtained using the least squares method based on the corrected input signal pulse width sequence. Using the least squares method to calculate the signal rate based on the corrected pulse width sequence combines the advantage of front-end sliding window correction in eliminating integer errors with back-end mathematical optimization theory, thereby improving the accuracy of signal rate measurement. For example... Figure 5 As shown, Figure 5 The diagram shows a flowchart of a communication method provided in an embodiment of this application. Based on the modified input signal pulse width sequence, the signal rate of the input signal is obtained using the least squares method, specifically including steps S151-S153: S151. Based on the corrected input signal pulse width sequence, the second clock signal is obtained.

[0079] In some examples, the pulse width corresponding to the second clock signal is the smallest signal pulse width in the corrected input signal pulse width sequence.

[0080] After the sliding window processing in step S140, the pulse width sequence of the input signal has been optimized to eliminate misjudgments over integer clock cycles as much as possible. At this point, the minimum value is sought again from this higher-quality "corrected input signal pulse width sequence." This new minimum value (the pulse width of the second clock signal) is closer to the actual clock signal pulse width than the pulse width of the first clock signal because it is based on more reliable data. The pulse width of this "second clock signal" is used as a more accurate benchmark for subsequent finer calculations.

[0081] S152. Based on the second clock signal, obtain the number of clock pulse widths contained in each corrected input signal pulse width.

[0082] In some examples, the clock pulse width is the ratio of the corresponding corrected input signal pulse width to the pulse width of the second clock signal.

[0083] Using the more accurate pulse width of the second reference clock signal obtained in the previous step, re-evaluate how many such reference cycles are contained in each corrected pulse width. Since the pulse width has been corrected, the division result here (number of clock pulse widths) will be very close to an integer, but it allows for decimals (such as 3.01, 1.98), which preserves finer fractional cycle information than the rounding in step S120, providing high-precision input for subsequent least-squares fitting.

[0084] S153. Based on the number of clock pulse widths corresponding to each corrected input signal pulse width, the signal rate of the input signal is obtained using the least squares method.

[0085] In some examples, the least squares method is used to adjust the signal rate and phase to minimize the sum of squares of the deviations between the clock edge and the edge of the corresponding output signal, obtained by multiplying the reciprocal of the signal rate and the number of clock pulses corresponding to each corrected input signal pulse width and the sum of the target phase corresponding to each corrected input signal pulse width.

[0086] In one example, the goal of using the least squares method is to find an optimal clock period T (the reciprocal of the signal rate) and target phase φ such that the overall error between all ideal clock edges generated by them and the corrected edges of the actual signal is minimized.

[0087] The objective function of the least squares method is to minimize Σ(((N_i×T+φ)-t_i)^2).

[0088] Where T represents the clock period, or the reciprocal of the signal rate. t_i represents the timestamp of the i-th actual signal edge in the input signal. N_i represents the number of clock pulses corresponding to the i-th corrected input signal pulse width. φ represents the target phase, which can be 0.

[0089] The goal of the least squares method is to adjust T and φ to minimize the sum of the fitting errors ((N_i*T+φ)-t_i)^2 for all edges. The T and φ obtained in this way are statistically optimal estimates of the true clock parameters.

[0090] In the embodiments shown in steps S151-S153, the corrected data is not directly used for the final calculation. Instead, an updated clock reference—a second clock signal (whose pulse width is the minimum value in the corrected sequence)—is extracted first. The pulse width corresponding to the second clock signal is a more accurate reference than the initial "first clock signal pulse width," generated based on higher-quality, more ideal corrected data. Based on this, the precise number of clock cycles (which can be a non-integer multiple) contained in each corrected pulse width is calculated using this superior reference. This is equivalent to performing data preprocessing and parameter pre-calibration before entering the final least-squares optimization, providing a significantly improved initial starting point for subsequent mathematical optimization, thereby achieving higher final accuracy overall. Furthermore, the least-squares method used in this embodiment minimizes the overall deviation (sum of squared errors) between the ideal clock edge generated based on the estimated clock parameters (the reciprocal of the signal rate, corresponding to the minimum signal pulse width, i.e., the clock signal pulse width and phase) and the actual data edge of the original input signal through mathematical optimization. Since the ideal clock edge position is directly determined by both the signal rate and phase parameters, joint adjustment and optimization of these two parameters using the least squares method can systematically eliminate residual random errors and small systematic deviations. This makes the final calculated signal rate and phase values ​​statistically optimal estimates, closer to the true values, thus ensuring the theoretically high accuracy of the clock recovery results.

[0091] In the embodiments shown in steps S110-S150, by introducing a sliding window-based correction mechanism, the problem of inaccurate signal rate measurement caused by signal jitter is effectively improved on the one hand, and the efficiency of signal rate measurement is improved while ensuring the accuracy of signal rate measurement on the other hand, thereby achieving high-precision and high-efficiency signal rate recovery. Specifically, an initial reference clock signal (i.e., the first clock signal) is established using the smallest input signal pulse width among multiple input signal pulse widths, and the deviation between each input signal pulse width and an integer multiple of the pulse width of the nearest first clock signal (i.e., the reference signal pulse width) is calculated to form a clock deviation sequence. Theoretically, under ideal jitter-free conditions, the values ​​of each input signal pulse width are accurate, and the signal rate is the reciprocal of the pulse width of the first clock signal, and each input signal pulse width should be an integer multiple of the pulse width of the first clock signal, that is, all deviations should be 0. However, this application notes that due to signal jitter, the values ​​of the input signal pulse widths are not completely accurate, so using the reciprocal of the pulse width of the first clock signal as the signal rate may also be inaccurate. This application utilizes the property that, theoretically, the pulse width of the input signal should be an integer multiple of the pulse width of the first clock signal. The resulting clock deviation sequence can reflect the clock deviation distribution of the input signal pulse width. Then, in the correction phase, a sliding window mechanism is used to traverse the clock deviation sequence. When the deviation change value within the window (the difference between the maximum and minimum clock deviation values ​​within the window) exceeds a preset threshold, the pulse width corresponding to the steepest change point within the window (i.e., the point where signal jitter is most likely) is specifically corrected. This avoids the defect of inaccurate rate calculation caused by inaccurate values ​​of individual input signal pulse widths (misjudgments caused by severe jitter).

[0092] Furthermore, compared to global optimization algorithms that require complex fitting or adjustment for each data point, the sliding window strategy of this embodiment significantly reduces computational complexity. It avoids handling all subtle jitter, focusing instead on significant aberrations exceeding a threshold caused by cumulative effects, achieving a good balance between accurate correction and computational efficiency. The pulse width sequence after sliding window correction more realistically reflects the ideal periodic characteristics of the signal, thereby improving the accuracy of signal rate calculation.

[0093] In other possible implementations, such as Figure 6 As shown, Figure 6 The diagram shows a flowchart of a communication method provided in an embodiment of this application. The correction of the input signal pulse width corresponding to the clock deviation specifically includes steps S160-S170: S160. If, in the updated clock skew sequence, there is a clock skew greater than or equal to the skew threshold, increase the window width.

[0094] In some implementations, the width of the sliding window can be increased from X times the pulse width of the first clock signal to (X+1) times the pulse width of the first clock signal, and the sliding window can continue to scan subsequent clock offsets, where X is a positive integer.

[0095] Using the "pulse width of the first clock signal" (i.e., the minimum pulse width) as the adjustment reference unit ensures that the expansion of the window is strictly aligned with the clock cycle characteristics of the signal itself. This avoids the uncertainties that may arise from using arbitrary or unitless step sizes for adjustment, ensuring that each window increase corresponds to precisely covering one more potential clock cycle position on the time axis. This is more conducive to systematically and structurally capturing and correcting deviation patterns caused by misjudgments of integer numbers of cycles, enhancing the reliability of the entire adjustment process and the consistency of the results. Furthermore, this embodiment uses small-amplitude, discrete increments with a unit pulse width as the step size (e.g., from the pulse width of 3 first clock signals to the pulse width of 4 first clock signals). The algorithm can maintain high sensitivity to local drastic changes in the initial small window while gradually and gently expanding the detection field of view. If the small window fails to completely resolve all deviations, a slightly larger window (e.g., the pulse width of 4 first clock signals) can better observe the cumulative trend of deviations across cycles or identify complex error patterns that are "segmented" under the smaller window. This gradual adjustment method, compared to jumping to an excessively large window all at once, avoids smoothing out or obscuring local details that should be corrected due to an overly wide window. It also avoids oscillations or over-adjustment caused by improper step size, making the entire adaptive process smoother and more controllable, and optimizing the correction effect.

[0096] S170. Perform a sliding window operation on the clock skew sequence based on the increased window width to obtain an updated clock skew sequence.

[0097] The specific implementation of step S170 is similar to that of step S140. For details, please refer to the specific implementation of step S140. It will not be repeated here.

[0098] In this embodiment, by introducing a dynamic adjustment mechanism for the window width, the adaptive capability and reliability of the final correction result of the sliding window correction algorithm are further enhanced. Specifically, this embodiment enables the communication method to have the ability of adaptive iterative optimization. An initial fixed window width may not be able to effectively capture all integer period misjudgments caused by severe jitter or complex noise patterns. By setting a closed-loop feedback rule of "if there is still a clock deviation exceeding the deviation threshold after the scan is completed, increase the window width and re-execute the sliding window operation", the algorithm can intelligently judge the current correction effect. If it has not fully converged (i.e., there is still a large deviation), it automatically widens the detection field of view (increases the window), thereby potentially discovering and correcting global and cumulative errors that are masked or not accurately located under a smaller window. This self-adjustment mechanism ensures that the correction process can move towards completely eliminating significant deviations. In addition, this embodiment can also achieve an optimized balance between correction accuracy and computational efficiency. The algorithm does not use a large window for global calculation from the beginning (that would bring unnecessary computation and may reduce the sensitivity to local mutations), but adopts a gradual strategy of "from fine to broad". Local mutation points are processed efficiently with a smaller window first. If discrepancies still exist after processing, the window width is increased for a more comprehensive analysis. This strategy can correct these discrepancies with minimal computational cost in most cases, increasing complexity only when necessary, thus achieving higher overall processing efficiency.

[0099] Example 2: Clock recovery methods for high-speed serial interfaces such as SERDES, PCIe, and USB can also be implemented based on a phase-locked loop (PLL) structure. A PLL is a phase error control system that adjusts the output signal (clock signal) by comparing the phase between the input and output signals to achieve synchronization between the output and input signals.

[0100] like Figure 7 As shown, Figure 7 A schematic diagram of a clock recovery circuit provided in an embodiment of this application is shown.

[0101] Figure 7 A clock recovery circuit based on a phase-locked loop (PLL) is shown. The clock recovery circuit 1 includes a PLL structure 10, which comprises a phase detector (PD) 101, a loop filter (LF) 102, and a voltage-controlled oscillator (VCO) 103. This device tracks the embedded clock in the input data by adjusting the phase of the oscillating clock through the loop, thereby recovering the clock signal from the data signal.

[0102] The phase detector 101 may include, but is not limited to, a Hogge phase detector, an Alexander phase detector, and a half-speed phase detector. The phase detector 101 compares the phase of the input signal with the phase of the output signal (clock signal) of the voltage-controlled oscillator 103 to detect the phase difference between them. This phase difference is converted into a voltage signal, the magnitude and polarity of which reflect the magnitude and direction of the phase difference. For example, if the phase of the input signal leads the phase of the output signal of the voltage-controlled oscillator 103, the phase detector 101 will output a positive voltage. Conversely, it will output a negative voltage.

[0103] In one specific embodiment, taking a simple half-speed phase detector as an example, such as... Figure 8 As shown, Figure 8 The diagram shows a half-speed phase detector according to an embodiment of this application. The half-speed phase detector 100 includes a first D flip-flop 1001, a second D flip-flop 1002, and an XOR unit 1003. Figure 8 The output signal Q1 represents the output signal of the first D flip-flop 1001, and the output signal Q2 represents the output signal of the second D flip-flop 1002.

[0104] The relationship between the input signal, clock signal, and output signal of a D flip-flop (including the first D flip-flop 1001 and the second D flip-flop 1002, taking rising edge triggering as an example) is shown in Table 1: Table 1

[0105] The half-speed phase detector 100 outputs at different positions based on the input signal and the clock signal, such as... Figure 9 As shown, Figure 9 The diagram shows the output waveform of a half-speed phase detector according to an embodiment of this application, wherein the input signal in the waveform is modulated using both high and low levels. Figure 9 The output signal Q1 represents the output signal of the first D flip-flop 1001, the output signal Q2 represents the output signal of the second D flip-flop 1002, and the phase detection result represents the control signal of the XOR 1003, which can be represented as a voltage signal.

[0106] The loop filter 102 filters the signal output from the phase detector to remove high-frequency noise and interference, making the signal smoother. The filtered signal is then used to control the voltage-controlled oscillator 103. The loop filter 102 is typically a low-pass filter, which allows low-frequency signals to pass through while suppressing high-frequency noise, thereby improving the stability and accuracy of clock recovery.

[0107] The voltage-controlled oscillator 103 adjusts its oscillation frequency according to the control voltage output by the loop filter 102. When the control voltage changes, the output frequency of the voltage-controlled oscillator 103 also changes accordingly. During clock recovery, the output signal of the voltage-controlled oscillator 103 serves as the recovered clock signal (recovered clock signal) for sampling the input high-speed serial data. By continuously adjusting the frequency of the voltage-controlled oscillator 103, the phase of its output recovered clock signal gradually synchronizes with the phase of the input signal, thereby achieving clock recovery and outputting the clock signal.

[0108] exist Figure 7 In the phase-locked loop-based clock recovery scheme shown, the phase detector 101, as the main module, is responsible for comparing the phase of the input signal with the feedback clock. Its performance directly affects the accuracy and efficiency of clock recovery. However, the phase detector consists of multiple adders and comparators, which consumes a lot of hardware resources and has high computational complexity, leading to increased signal processing delay.

[0109] by Figure 8 Taking the half-speed phase detector shown as an example, its internal logic units, such as D flip-flops and XOR circuits, need to be constructed sequentially. A point-by-point traversal method is used to sample and compare the phase of the input signal and the feedback clock, and then output the phase detection result. For scenarios with more complex flip-flop combinations and more varied signal characteristics (such as signals containing complex modulation patterns, mixed clocks, or large clock jitter), the computational burden of the phase detector will increase dramatically, and its processing efficiency will decrease significantly.

[0110] Furthermore, the 10-loop throughput of the phase-locked loop (PLL) structure is limited by the computational efficiency of the phase detector, becoming a key bottleneck restricting the overall data bandwidth. In high-speed communication or real-time processing systems, low-bandwidth loop throughput will lead to the accumulation of signal phase errors, increased clock recovery delay, and even the inability to track changes in signal frequency and phase in a timely manner. This severely affects the overall efficiency and reliability of clock signal recovery, reducing the transmission performance and stability of the communication system.

[0111] In order to solve such Figure 7 Due to the high computational complexity of the phase detector 101 in the clock recovery scheme shown, this application provides a clock recovery device, such as... Figure 10 As shown, Figure 10 A schematic diagram of a clock recovery device provided in an embodiment of this application is shown.

[0112] like Figure 10 As shown, the clock recovery device 4 includes a phase detection unit 41, a judgment unit 42, a loop filtering unit 43, and a voltage-controlled oscillator unit 44. It achieves dynamic recovery and phase synchronization of the clock signal through a closed-loop feedback mechanism. The specific working process is as follows: The phase detector unit 41 simultaneously receives the input signal and the recovered clock signal fed back from the voltage-controlled oscillator unit 44 (the fed-back recovered clock signal serves as a reference clock signal), and directly determines the phase detection result through a pre-constructed mapping table (or state transition table). The mapping table characterizes the mapping relationship between the phase detection result and the level of the input signal corresponding to the transition edge of the recovered clock signal fed back from the voltage-controlled oscillator unit 44. Compared to phase detectors based on adders and comparators (such as...), this approach... Figure 7 The phase detector 101 shown or Figure 8 Unlike the half-speed phase detector 100 shown, this embodiment directly obtains the phase difference information by looking up the mapping relationship table, avoiding the complex point-by-point calculation process, significantly reducing the computational complexity and improving the phase detection speed.

[0113] The phase detection result is input as a control signal to the judgment unit 42. The judgment unit 42 determines whether the phase detection result converges. If the phase detection result does not converge, it is input to the loop filter unit 43. The loop filter unit 43 performs low-pass filtering on the phase detection result and outputs a smooth voltage signal. This voltage signal is then input to the voltage-controlled oscillator unit 44 to dynamically adjust the oscillation frequency and phase. If the phase detection result converges, a control command is output to the voltage-controlled oscillator unit 44. The control command instructs the voltage-controlled oscillator unit 44 to output the clock signal currently fed back to the phase detection unit 41 as the clock signal recovered from the input signal.

[0114] The clock signal output by the voltage-controlled oscillator unit 44 is fed back to the phase detector unit 41, forming a closed-loop feedback system. Through multiple iterations, the phase difference between the clock signal and the input signal is continuously reduced until the preset convergence condition is met (such as the phase difference being less than a threshold or the results of multiple consecutive iterations being stable), and finally a stable and accurate clock signal is output.

[0115] In one specific embodiment, with Figure 8 Taking the half-speed phase detector 100 shown as an example, the expression for the phase detection result Vout can be derived by modeling the D flip-flops and XORers. For example, the state transition table of the D flip-flops (including the first D flip-flop 1001 and the second D flip-flop 1002) can be equivalent to formula (1): Formula (1).

[0116] in, This indicates the state of the D flip-flop output after being triggered by the rising edge of the clock signal CLK. This represents the data value at the input of the D flip-flop at the sampling point preceding the rising edge of the clock signal CLK.

[0117] The XOR converter 1003 conversion table can be equivalent to: .

[0118] Where m represents the XOR output, and p and q represent the output signals of the first D flip-flop 1001 and the second D flip-flop 1002, respectively. This represents the negation of q. express Inverse of.

[0119] In summary, the half-speed phase detector 100 can be equivalent to formula (2): Formula (2).

[0120] in, This indicates the state of the D flip-flop output after being triggered by the falling edge of the clock signal CLK. This represents the data value at the input of the D flip-flop at the sampling point preceding the falling edge of the clock signal CLK. express Inverse of, express Inverse of, express Inverse of, express Inverse of.

[0121] Based on the data model of the half-speed phase detector 100, the output at different positions is as follows, according to the input signal and the clock signal. Figure 11 As shown, Figure 11 The diagram shows the output waveform of a half-speed phase detector model provided in an embodiment of this application.

[0122] like Figure 11 As shown, all initial states are 0 by default. The input signal corresponding to the first rising edge of the clock (R1) is low, and the input signal corresponding to the first falling edge F1 is high. Therefore, the phase detection result Vout during the R1~F1 period can be calculated using the above formulas (1) and (2): .

[0123] .

[0124] .

[0125] Similarly, the phase detection result Vout during the time interval F1~R2 can be calculated using the above formulas (1) and (2): .

[0126] .

[0127] .

[0128] Similarly, all the above states can be output as corresponding values, such as F1~R2, R2~F2, F2~R3, R3~F3, F3~R4, R4~F4, F4~R5, and R5~F5, etc., and a mapping table can be obtained, as shown in Table 2: Table 2

[0129] In Table 2, This indicates the level of the input signal when the clock signal is at its rising edge. This indicates the level of the input signal when the clock signal is at its falling edge.

[0130] Specifically, as shown in Table 2, when the level of the input signal corresponding to one edge of the recovery clock signal is high, and the level of the input signal corresponding to the previous edge of the recovery clock signal is high, the control signal (the phase detection result can be used as the control signal) is low.

[0131] The control signal is high when the level of the input signal corresponding to one of the rising edges of the recovery clock signal is high and the level of the input signal corresponding to the previous rising edge of the recovery clock signal is low.

[0132] The control signal is high when the level of the input signal corresponding to one edge of the recovery clock signal is low and the level of the input signal corresponding to the previous edge of the recovery clock signal is high.

[0133] When the level of the input signal corresponding to one of the transition edges of the recovery clock signal is low, and the level of the input signal corresponding to the previous transition edge of the recovery clock signal is low, the control signal is low.

[0134] After the above processing, it is no longer necessary to perform phase detection operations (flip-flop calculation, XOR operator calculation) point by point; only the edge detection is performed. , The record is processed and the corresponding phase detection result Vout is output. Subsequent non-edge positions retain the previous output value Voutpre.

[0135] In this embodiment, by examining only the timing of the recovery clock transition and the input signal level (high or low) of the previous moment, it is possible to clearly determine whether the current phase relationship is "leading" or "lagging," and output a corresponding binary control signal (high or low level) to instruct the voltage-controlled oscillator to "accelerate" or "decelerate." For example, when the recovery clock edge captures the input signal changing from "high" to "low" (corresponding to the third case in the embodiment), it indicates that the recovery clock may be ahead of the effective data window of the input signal. At this time, a "high" level control signal is output to cause the voltage-controlled oscillator to decelerate appropriately to align the phase. This avoids complex analog voltage comparisons or digital calculations, resulting in fast decision-making speed, small hardware implementation area, and low power consumption, making it suitable for application in clock data recovery circuits of high-speed serial interfaces.

[0136] Furthermore, this embodiment establishes a mapping relationship between the input signal, the restored clock signal, and the control signal. It directly obtains the control signal representing the phase difference based on the level state of the signal transition edge, and then recovers the clock signal of the input signal based on the control signal. Compared to hardware phase detection circuit schemes, this implementation eliminates complex adders and comparators, simplifying the phase detection process to a signal state query operation. This significantly reduces computational complexity, significantly improves phase detection processing speed, and achieves efficient and low-complexity clock recovery.

[0137] Example 3: like Figure 12 As shown, Figure 12 A schematic diagram of a communication system provided in an embodiment of this application is shown. The communication system 3 includes a signal generation device 31 and a... Figure 10 The clock recovery device 4 is shown. To achieve faster and more accurate locking of the clock information of the input signal and realize effective clock recovery, the signal generation device 31 can input a generated signal rate as the initial oscillation frequency of the voltage-controlled oscillator unit 44. Because different signal rates correspond to different data transmission rhythms, the initial frequency of the voltage-controlled oscillator unit 44 needs to be matched with the signal rate to lock the clock information of the input signal faster and more accurately, thus achieving effective clock recovery. For example, for high-speed signals, the initial frequency of the voltage-controlled oscillator unit 44 needs to be set relatively high to accommodate fast data transmission.

[0138] In some implementations, such as Figure 12 As shown, the signal rate obtained in Embodiment 1 can be used as the initial oscillation frequency. The clock recovery device 4 operates by restoring the clock based on the signal rate, as follows: Figure 13 As shown, Figure 13 The following is a flowchart illustrating a communication method provided in an embodiment of this application, specifically including steps S210-S220: S210: Input the signal rate to the voltage-controlled oscillator unit to obtain the recovery clock signal output by the voltage-controlled oscillator unit.

[0139] In some examples, the voltage-controlled oscillator unit 44 generates a recovery clock signal based on the signal rate and transmits the clock signal back to the phase detector unit 41. The recovery clock signal is used for clock recovery.

[0140] S220, the phase detector unit outputs control signals based on the recovered clock signal and the mapping table.

[0141] In some examples, a mapping table is used to characterize the mapping relationship between the levels of the input signals corresponding to the transition edges of the control signal and the recovery clock signal, as shown in Table 2.

[0142] The control signal is used to control the voltage-controlled oscillator unit 44 to adjust the oscillation frequency and phase so that the edges of the recovery clock signal and the input signal are consistent.

[0143] In this embodiment, the calculated precise signal rate is input to the voltage-controlled oscillator (VCO) unit, which can directly generate a highly matched recovery clock signal. More importantly, by introducing a feedback control loop based on a mapping table (which uses the input signal level corresponding to the transition edge of the recovery clock to look up the table and output a control signal to fine-tune the frequency and phase of the VCO unit), the phase detection unit's control strategy based on the mapping table provides an efficient and robust phase synchronization mechanism. Compared to calculating the control signal by setting up hardware circuits such as adders and comparators, this application does not require complex hardware circuits but can quickly obtain the result by looking up the table, greatly reducing computational complexity and significantly improving phase detection speed.

[0144] The "mapping table" explicitly defines the correspondence between the input signal level (e.g., high, low, rising edge, falling edge) observed at the edge of the recovered clock and the control commands (e.g., acceleration, deceleration, hold) to be applied to the voltage-controlled oscillator (VCO). Compared to complex real-time calculations, this lookup method offers faster response, more deterministic logic, and simpler implementation, making it particularly suitable for high-speed hardware circuits. It enables the system to quickly respond to phase errors between the input signal and the recovered clock, driving the VCO to perform precise compensation, ultimately achieving and maintaining phase locking, and ensuring the long-term stability of the recovered clock.

[0145] Example 4: Based on the above embodiments, this embodiment provides a communication device, such as... Figure 14 As shown, a communication device 6 is provided according to an embodiment of this application. The communication device 6 can be a signal generation device 31, including a minimum pulse width calculation module 61, a reference pulse width calculation module 62, a clock deviation calculation module 63, a pulse width correction module 64, and a judgment module 65.

[0146] The minimum pulse width calculation module 61 is used to obtain the pulse width of the first clock signal based on the pulse width sequence of the input signal. The pulse width sequence of the input signal includes multiple input signal pulse widths arranged in time order, and the pulse width of the first clock signal is the smallest input signal pulse width in the pulse width sequence of the input signal.

[0147] The reference pulse width calculation module 62 is used to determine the reference signal pulse width corresponding to each input signal pulse width based on the pulse width of each input signal and the pulse width of the first clock signal. The reference signal pulse width is the pulse width corresponding to the smallest integer multiple of the input signal pulse width among multiple integer multiples of the pulse width of the first clock signal.

[0148] The clock deviation calculation module 63 is used to determine the clock deviation corresponding to each input signal pulse width based on each input signal pulse width and the corresponding reference signal pulse width, and to obtain a clock deviation sequence. The clock deviation is the difference between each input signal pulse width and the corresponding reference signal pulse width.

[0149] The pulse width correction module 64 is used to perform a sliding window operation on the clock offset sequence based on the window width to obtain an updated clock offset sequence. The sliding window operation includes multiple sliding window processes, with the step size between the windows corresponding to each sliding window process being the sliding window step size. Each sliding window process includes: if the change value of the clock offset within the window is greater than the change threshold, correcting the pulse width of the input signal corresponding to the clock offset within the window and updating the clock offset sequence within the window. The window width is a preset time interval, and the change value is the difference between the maximum value and the minimum value of the clock offset within the window.

[0150] The judgment module 65 is used to obtain the signal rate of the input signal based on the corrected input signal pulse width sequence, provided that all clock deviations in the updated clock deviation sequence are less than the deviation threshold.

[0151] In some embodiments, the pulse width correction module 64 is further configured to, when the change in clock deviation within the window is greater than the change threshold and the clock deviation jumps downward, make the corrected input signal pulse width greater than the uncorrected input signal pulse width by the pulse width corresponding to the first clock signal. And when the change in clock deviation within the window is greater than the change threshold and the clock deviation jumps upward, make the corrected input signal pulse width less than the uncorrected input signal pulse width by the pulse width corresponding to the first clock signal.

[0152] In some embodiments, the communication device 6 further includes a window adjustment module and an acquisition module.

[0153] The window adjustment module is used to increase the window width if there is a clock skew greater than or equal to a skew threshold among all clock skews in the updated clock skew sequence.

[0154] The acquisition module is used to perform a sliding window operation on the clock skew sequence based on an increased window width to obtain an updated clock skew sequence.

[0155] In some implementations, the window adjustment module is also used to increase the width of the sliding window from X times the pulse width of the first clock signal to (X+1) times the pulse width of the first clock signal, and continue to slide and scan subsequent clock offsets, where X is a positive integer.

[0156] In some implementations, X in the window adjustment module is greater than or equal to 3 and less than or equal to 10.

[0157] In some implementations, the determination module 65 is also used to obtain the signal rate of the input signal based on the modified input signal pulse width sequence using the least squares method.

[0158] In some implementations, the determination module 65 is further configured to obtain a second clock signal based on the corrected input signal pulse width sequence, wherein the pulse width corresponding to the second clock signal is the smallest signal pulse width in the corrected input signal pulse width sequence. Based on the second clock signal, the number of clock pulse widths contained in each corrected input signal pulse width is obtained, wherein the number of clock pulse widths is the ratio of the corresponding corrected input signal pulse width to the pulse width of the second clock signal. Based on the number of clock pulse widths corresponding to each corrected input signal pulse width, the signal rate of the input signal is obtained using the least squares method. The least squares method is used to adjust the signal rate and phase to minimize the sum of squares of the deviations between the clock edge and the edge of the corresponding output signal, obtained by multiplying the reciprocal of the signal rate and the number of clock pulse widths corresponding to each corrected input signal pulse width, and the sum of the target phase corresponding to each corrected input signal pulse width.

[0159] Based on the above embodiments, this embodiment also provides a communication system, such as... Figure 12 As shown.

[0160] The signal generation device 31 or the communication device 6 is used to input the signal rate to the voltage-controlled oscillator unit to obtain the recovery clock signal output by the voltage-controlled oscillator. The recovery clock signal is used for clock recovery.

[0161] A phase detector unit outputs a control signal based on the recovered clock signal and a mapping table. The mapping table represents the mapping relationship between the control signal and the input signal levels corresponding to the transition edges of the recovered clock signal. The control signal controls the voltage-controlled oscillator to adjust its oscillation frequency and phase so that the edges of the recovered clock signal and the input signal are synchronized. In some embodiments, in the mapping table of the phase detector unit, if the input signal level corresponding to one transition edge of the recovered clock signal is high, and the input signal level corresponding to the previous transition edge of the recovered clock signal is also high, the control signal is low. If the input signal level corresponding to one transition edge of the recovered clock signal is high, and the input signal level corresponding to the previous transition edge of the recovered clock signal is low, the control signal is high. If the input signal level corresponding to one transition edge of the recovered clock signal is low, and the input signal level corresponding to the previous transition edge of the recovered clock signal is high, the control signal is high. When the level of the input signal corresponding to one of the transition edges of the recovery clock signal is low, and the level of the input signal corresponding to the previous transition edge of the recovery clock signal is low, the control signal is low.

[0162] Example 5: This embodiment also provides a computer-readable storage medium. Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0163] Example 6: This embodiment also provides, such as Figure 15 The diagram illustrates an electronic device according to an embodiment of this application. The electronic device 8 includes one or more processors 81, a memory 82, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components communicate with each other using different buses and can be mounted on a common motherboard or otherwise installed as needed. The processor can process instructions executed within the electronic device 8, including instructions stored in or on memory to display graphical information of a GUI on an external input / output device (such as a display device coupled to the interface).

[0164] In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple storage devices, if desired. Similarly, multiple electronic devices 8 can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system).

[0165] Processor 81 may be a central processing unit, a network processor, or a combination thereof. Processor 81 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0166] The memory 82 stores instructions executable by at least one processor 81 to cause the at least one processor 81 to perform the method shown in the above embodiments.

[0167] The memory 82 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function. The data storage area may store data created by the use of the electronic device 8 based on the display of an app landing page. Furthermore, the memory 82 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device.

[0168] Memory 82 may include volatile memory, such as random access memory. Memory may also include non-volatile memory, such as flash memory, hard disk, or solid-state drive. Memory 82 may also include combinations of the above types of memory.

[0169] The electronic device 8 also includes a communication interface 83 for communicating with other devices or communication networks.

[0170] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0171] All of the above modules or units can be implemented using software. For example, the clock recovery device 4, phase detection unit 41, judgment unit 42, loop filter unit 43, and voltage-controlled oscillator unit 44 can be implemented using software.

[0172] In this application, "implemented through software" means that the processor reads and executes program instructions stored in memory to implement the functions corresponding to the aforementioned modules or units. Here, the processor refers to a processing circuit capable of executing program instructions, including but not limited to at least one of the following: a central processing unit (CPU), a microprocessor, a digital signal processor (DSP), a microcontroller unit (MCU), or an artificial intelligence processor, etc., and other processing circuits capable of running program instructions. In other embodiments, the processor may also include circuits with other processing functions (such as hardware circuits for hardware acceleration, bus and interface circuits, etc.). The processor can be presented as an integrated chip, for example, as an integrated chip whose processing function only includes executing software instructions, or it can also be presented as a SoC (system on a chip), that is, on a single chip, in addition to the processing circuit capable of running program instructions (usually referred to as the "core"), it also includes other hardware circuits for implementing specific functions (of course, these hardware circuits can also be implemented separately based on ASIC or FPGA). Correspondingly, the processing functions, in addition to executing software instructions, may also include various hardware acceleration functions (such as AI calculation, encoding / decoding, compression / decompression, etc.).

[0173] It should be noted that when this application is implemented in software, different software can be used, and it is not limited to using only one type of software. For example, one module or unit can be implemented using a CPU, while another module or unit can be implemented using a DSP. Of course, it is not limited to using the same software (such as all using a CPU) for some or all modules or units.

[0174] The foregoing preferred embodiments have further illustrated the objectives, technical solutions, and advantages of the present invention. It should be understood that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A communication method, characterized in that, include: Based on the pulse width sequence of the input signal, the pulse width of the first clock signal is obtained. The pulse width sequence of the input signal includes multiple input signal pulse widths arranged in chronological order. The pulse width of the first clock signal is the smallest input signal pulse width in the pulse width sequence of the input signal. Based on the pulse width of each input signal and the pulse width of the first clock signal, a reference signal pulse width corresponding to each input signal pulse width is determined. The reference signal pulse width is the pulse width corresponding to the smallest integer multiple of the pulse width of the first clock signal and the pulse width of the input signal. Based on each input signal pulse width and the corresponding reference signal pulse width, the clock deviation corresponding to each input signal pulse width is determined to obtain a clock deviation sequence, wherein the clock deviation is the difference between each input signal pulse width and the corresponding reference signal pulse width. A sliding window operation is performed on the clock skew sequence based on the window width to obtain an updated clock skew sequence. The sliding window operation includes multiple sliding window processes, with the step size between the windows corresponding to each sliding window process being the sliding window step size. Each sliding window process includes: if the change value of the clock skew within the window is greater than a change threshold, correcting the input signal pulse width corresponding to the clock skew within the window and updating the clock skew sequence within the window; wherein, the window width is a preset time distance, and the change value is the difference between the maximum value and the minimum value of the clock skew within the window; If all clock deviations in the updated clock deviation sequence are less than the deviation threshold, the signal rate of the input signal is obtained based on the corrected input signal pulse width sequence.

2. The communication method according to claim 1, characterized in that, The correction of the input signal pulse width corresponding to the clock deviation includes: When the change in clock offset within the window is greater than the change threshold, and the clock offset jumps downwards, the corrected input signal pulse width is greater than the uncorrected input signal pulse width by the pulse width corresponding to the first clock signal; and If the change value of the clock deviation within the window is greater than the change threshold, and the clock deviation jumps upward, the corrected input signal pulse width is less than the uncorrected input signal pulse width by the pulse width corresponding to the first clock signal.

3. The communication method according to claim 1, characterized in that, The method further includes: If, in the updated clock skew sequence, there is at least one clock skew greater than or equal to a skew threshold, the window width is increased; and The sliding window operation is performed on the clock skew sequence based on the increased window width to obtain an updated clock skew sequence.

4. The communication method according to claim 3, characterized in that, Increasing the window width includes: The width of the sliding window is increased from X times the pulse width of the first clock signal to (X+1) times the pulse width of the first clock signal, and the sliding window continues to scan the subsequent clock offset, where X is a positive integer.

5. The communication method according to claim 4, characterized in that, X is greater than or equal to 3 and less than or equal to 10.

6. The communication method according to claim 1, characterized in that, The change threshold is the pulse width of the first clock signal.

7. The communication method according to any one of claims 1-6, characterized in that, The step of obtaining the signal rate of the input signal based on the corrected input signal pulse width sequence includes: Based on the corrected input signal pulse width sequence, the signal rate of the input signal is obtained using the least squares method.

8. The communication method according to claim 7, characterized in that, The process of obtaining the signal rate of the input signal based on the modified input signal pulse width sequence using the least squares method includes: Based on the corrected input signal pulse width sequence, a second clock signal is obtained, and the pulse width corresponding to the second clock signal is the smallest signal pulse width in the corrected input signal pulse width sequence. Based on the second clock signal, the number of clock pulses contained in each corrected input signal pulse width is obtained, wherein the number of clock pulses is the ratio of the corresponding corrected input signal pulse width to the pulse width of the second clock signal; Based on the number of clock pulse widths corresponding to each of the corrected input signal pulse widths, the signal rate of the input signal is obtained using the least squares method; The least squares method is used to adjust the signal rate and phase to minimize the sum of squares of the deviations between the clock edge and the edge of the corresponding output signal, which are obtained by multiplying the reciprocal of the signal rate and the number of clock pulses corresponding to each of the corrected input signal pulse widths and the sum of the target phases corresponding to each of the corrected input signal pulse widths.

9. The communication method according to claim 1, characterized in that, It is used in communication systems, which include: A signal generating apparatus for performing the communication method as described in any one of claims 1-8; The clock recovery device includes a phase detector unit and a voltage-controlled oscillator unit; After obtaining the signal rate of the input signal, the communication method further includes: The signal generation device inputs the signal rate to the voltage-controlled oscillator unit to obtain the recovered clock signal output by the voltage-controlled oscillator unit, and the recovered clock signal is used for clock recovery; The phase detection unit outputs a control signal based on the recovered clock signal and the mapping table; the mapping table is used to characterize the mapping relationship between the control signal and the level of the input signal corresponding to the transition edge of the recovered clock signal. The control signal is used to control the voltage-controlled oscillator unit to adjust the oscillation frequency and phase so that the edges of the recovery clock signal and the input signal are consistent.

10. The communication method according to claim 9, characterized in that, In the mapping table, When the level of the input signal corresponding to a transition edge of the recovery clock signal is high, and the level of the input signal corresponding to the previous transition edge of the recovery clock signal is high, the control signal is low. The control signal is high when the level of the input signal corresponding to one of the rising edges of the recovery clock signal is high and the level of the input signal corresponding to the previous rising edge of the recovery clock signal is low. The control signal is high when the level of the input signal corresponding to one transition edge of the recovery clock signal is low and the level of the input signal corresponding to the previous transition edge of the recovery clock signal is high. The control signal is low when the level of the input signal corresponding to one of the transition edges of the recovery clock signal is low, and the level of the input signal corresponding to the previous transition edge of the recovery clock signal is low.

11. An electronic device, characterized in that, include: Communication interface; A processor, coupled to the communication interface, is used to execute the communication method as described in any one of claims 1-10.

12. A communication device, characterized in that, include: The minimum pulse width calculation module is used to obtain the pulse width of the first clock signal based on the pulse width sequence of the input signal. The pulse width sequence of the input signal includes multiple input signal pulse widths arranged in chronological order, and the pulse width of the first clock signal is the smallest input signal pulse width in the pulse width sequence of the input signal. The reference pulse width calculation module is used to determine the reference signal pulse width corresponding to each input signal pulse width based on each input signal pulse width and the pulse width of the first clock signal. The reference signal pulse width is the pulse width corresponding to the smallest integer multiple of the input signal pulse width among multiple integer multiples of the pulse width of the first clock signal. The clock skew calculation module is used to determine the clock skew corresponding to each input signal pulse width based on each input signal pulse width and the corresponding reference signal pulse width, and to obtain a clock skew sequence, wherein the clock skew is the difference between each input signal pulse width and the corresponding reference signal pulse width; A pulse width correction module is used to perform a sliding window operation on the clock deviation sequence based on a window width to obtain an updated clock deviation sequence. The sliding window operation includes multiple sliding window processes, with the step size between the windows corresponding to each sliding window process being the sliding window step size. Each sliding window process includes: if the change value of the clock deviation within the window is greater than a change threshold, correcting the pulse width of the input signal corresponding to the clock deviation within the window and updating the clock deviation sequence within the window; wherein, the window width is a preset time distance, and the change value is the difference between the maximum value and the minimum value of the clock deviation within the window; The judgment module is used to determine the signal rate of the input signal based on the corrected input signal pulse width sequence, provided that all clock deviations in the updated clock deviation sequence are less than the deviation threshold.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes instructions that, when executed on a processor, cause the processor to perform the communication method as described in any one of claims 1-10.

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