Dynamic random access memory and manufacturing method thereof
By forming a notch facing the bit line at the bottom of the insulating structure and using a dielectric layer to protect the capacitor contacts, the problems of capacitor contact bridging and interference are solved, thereby improving the performance and reliability of DRAM.
Patent Information
- Application Number
- CN202411380726.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-08-02
- Filing Date
- 2024-09-30
- Publication Date
- 2026-02-03
AI Technical Summary
As DRAM becomes increasingly integrated, the aspect ratio of capacitor contacts increases, leading to increased resistance in the capacitor contacts. Furthermore, bridging or interference can easily occur during the etching process, affecting DRAM performance and manufacturing yield.
Two notches are formed at the bottom of the insulating structure, facing each other along the extension direction of the bit line, and first and second dielectric layers are formed on the notches to protect the capacitor contacts, prevent short circuits or interference, and reduce resistance.
It reduces bridging or interference between capacitor contacts, improves DRAM reliability and operating speed, reduces resistance and parasitic capacitance, and increases manufacturing yield.
Smart Images
Figure CN121463433A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present invention relates to a dynamic random access memory (DRAM) and a method of manufacturing the same, and more particularly to a capacitor contact of the DRAM and a method of manufacturing the same. BACKGROUND
[0002] As DRAMs are highly integrated, the size and pitch of the capacitor contacts used to connect the substrate and the capacitor are also reduced, resulting in a larger aspect ratio of the capacitor contacts, which reduces the alignment margin of the capacitor contacts during the photolithography process and increases the resistance of the capacitor contacts. In addition, during the etching process for forming the capacitor contact trench, the insulating material on the sidewall of the trench bottom can be thinned or damaged, resulting in unexpected bridging or interference between the subsequently filled capacitor contacts, which reduces the performance and manufacturing yield of the DRAM.
[0003] To improve such problems, a conventional DRAM increases the thickness of the insulating material on the sidewall of the trench, but this solution results in an increase in the resistance of the capacitor contacts under the same size design. If the same resistance is to be maintained, the miniaturization of the DRAM is adversely affected.
[0004] Another conventional DRAM forms a capacitor contact hole that expands toward the bit line from the bottom of the insulating layer between the bit lines, so that the capacitor contact overlaps the bit line in the vertical projection. However, the capacitor contact hole that expands toward the bit line limits the area of the bit line contact, not only increasing the resistance of the bit line contact, but also increasing the risk of collapse of the bit line contact. In addition, the capacitor contact hole that expands toward the bit line also brings the bit line contact closer to the capacitor contact, thereby increasing the parasitic capacitance of the bit line contact and the capacitor contact, and increasing the risk of leakage current. Therefore, there are still some problems to be overcome regarding DRAMs and their manufacturing techniques. SUMMARY
[0005] The present invention proposes a DRAM and a method of manufacturing the same, which can improve the problem of unexpected bridging or interference between capacitor contacts, and does not affect the design of the bit line contact to improve the problem of interference of the capacitor contact with the bit line contact.
[0006] A dynamic random access memory includes a substrate, bit lines disposed on the substrate, insulating structures disposed on the substrate and located between adjacent bit lines, wherein a lower portion of each insulating structure has two notches, and the notches face each other along an extension direction of each bit line, a capacitor contact disposed on the substrate and located in a via between adjacent insulating structures, a first dielectric layer disposed on sidewalls of the via above the notches and located between each insulating structure and the capacitor contact, and a second dielectric layer including a first portion and a second portion. The first portion is disposed on the first dielectric layer and located between the first dielectric layer and the capacitor contact, and the second portion is disposed in the notches and located between the lower portion of the insulating structure and the capacitor contact.
[0007] A method of manufacturing a dynamic random access memory includes forming bit lines on a substrate, forming insulating structures on the substrate and located between adjacent bit lines, wherein a lower portion of each insulating structure has two notches, and the notches face each other along an extension direction of each bit line, forming a capacitor contact on the substrate and located in a via between adjacent insulating structures, conformally forming a first dielectric layer on sidewalls of the via above the notches and located between each insulating structure and the capacitor contact, and forming a second dielectric layer including a first portion and a second portion, wherein the first portion is formed on the first dielectric layer and located between the first dielectric layer and the capacitor contact, and wherein the second portion is formed in the notches and located between the lower portion of the insulating structure and the capacitor contact. BRIEF DESCRIPTION OF DRAWINGS
[0008] Various aspects of embodiments of the application will be described in connection with the following figures. It should be noted that the figures are not drawn to scale and that elements of various figures can be added, expanded, or removed from the figures, and that the proportions of the various features can be arbitrarily scaled for the sake of clarity. Figures are intended as illustrative examples only and are not limiting of the scope of the application.
[0009] Figures 1-11 A method of manufacturing a DRAM of an embodiment of the application is shown in cross-sectional views corresponding to various steps.
[0010] Figure 12 A perspective view of a DRAM of an embodiment of the application is shown.
[0011] Figure 13 A top view of a DRAM of an embodiment of the application is shown.
[0012] Figures 14-17 A method of manufacturing a DRAM of another embodiment of the application is shown in cross-sectional views corresponding to various steps.
[0013] Figures 18-20 A method of manufacturing a DRAM of yet another embodiment of the application is shown in cross-sectional views corresponding to various steps.
[0014] Reference Signs
[0015] 10, 20, 30: dynamic random access memory
[0016] 100: substrate
[0017] 120: shallow trench isolation structure
[0018] 200: word line
[0019] 220: dielectric layer
[0020] 240: barrier layer
[0021] 260: conductive fill
[0022] 280: cap layer
[0023] 300: bit line
[0024] 301: bit line contact structure
[0025] 320: dielectric layer
[0026] 340: conductive layer
[0027] 360: hard mask
[0028] 380: spacer
[0029] 400: insulating material layer
[0030] 400': insulating structure
[0031] 400C: notch
[0032] 400R1: recess
[0033] 400R2: recess
[0034] 400T2: via
[0035] 420: liner
[0036] 440, 460: insulating layer
[0037] 520: first dielectric material
[0038] 521: first dielectric layer
[0039] 540: second dielectric material
[0040] 541: second dielectric layer
[0041] 541-1: first portion
[0042] 541-2: second portion
[0043] 600:capacitor contact
[0044] 620:conductive material
[0045] 620P:protrusion
[0046] 640:barrier layer
[0047] 660:conductive fill
[0048] 700:isolation structure
[0049] A-A':section line
[0050] D1:width
[0051] D2:horizontal depth
[0052] H1:thickness
[0053] H2:depth DETAILED DESCRIPTION
[0054] Some embodiments or examples are disclosed herein for implementing various components of the embodiments of the present application, but are not intended to limit the present application. For example, the description of a first component being formed on a second component can include embodiments in which the first and second components are in direct contact, and can also include embodiments in which the first and second components are not in direct contact. Similarly, additional steps can be performed before, during, and / or after various stages described in these embodiments. Some components can be replaced or omitted from different embodiments. Although some embodiments are discussed with reference to steps performed in a particular order, these steps can be performed in another logical order. In addition, the present application can repeat element symbols and / or letters in various examples. Such repetition is for the purpose of simplification and clarity, and does not in itself dictate a relationship between various embodiments and / or configurations discussed.
[0055] According to the present application, two notches can be formed in the lower portion of the insulating structure before the capacitor contact is formed, and the notches face each other along the extension direction of the bit line, so that the second dielectric layer formed on the notches later will not be damaged by the subsequent etching process, to avoid short circuit or interference between the capacitor contacts. In some embodiments, the capacitor contact can be filled in the notches, so that the capacitor contact has a single-sided protrusion, thereby reducing the resistance. Therefore, the reliability and operating speed of the DRAM can be improved according to the present application.
[0056] It is important to note that during DRAM operation, the bit voltage difference between the temporarily stored "0" and "1" states must be maintained at a sufficiently large value in order for the sensing amplifier to function properly. According to the formula for bit voltage difference, the smaller the parasitic capacitance between the bit line contact and the capacitor contact, the larger the bit voltage difference. Since the notch of this invention extends parallel to the bit line extension direction, the parasitic capacitance between the bit line contact and the capacitor contact can be reduced. In other words, according to this invention, the determination of "0" and "1" states becomes more efficient, thereby increasing DRAM performance.
[0057] Figures 1-11 This is a cross-sectional schematic diagram illustrating the various stages of forming a dynamic random access memory 10 according to some embodiments of the present invention. In this embodiment, only a portion of the DRAM is shown; the remaining portion of the DRAM can be formed by known structures or methods, and will not be described in detail here.
[0058] Reference Figure 1 The dynamic random access memory 10 may include a substrate 100, a shallow trench isolation structure 120 formed in the substrate 100, word lines 200, and an insulating material layer 400 formed on the substrate 100. In one embodiment, the word lines 200 may include a dielectric layer 220, a barrier layer 240, a conductive filler 260, and a capping layer 280. Furthermore, the insulating material layer 400 may include a liner 420, an insulating layer 440, and an insulating layer 460. The insulating layer 440 is located between the liner 420 and the insulating layer 460. The shallow trench isolation structure 120 electrically isolates the active area (AA) in the substrate 100. The substrate 100, the shallow trench isolation structure 120, and the word lines 200 can be formed using any known methods and structures, and therefore will not be described in detail here.
[0059] In some embodiments, substrate 100 may be a semiconductor substrate, such as a silicon substrate. Furthermore, in some embodiments, the semiconductor substrate may also be: an elemental semiconductor, including germanium; a compound semiconductor, including gallium nitride, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, including silicon-germanium alloy, gallium arsenide-phosphide-gallium alloy, aluminum arsenide-indium alloy, aluminum arsenide-gallium arsenide-gallium arsenide-indium arsenide-gallium arsenide-indium arsenide-gallium arsenide-indium arsenide-gallium arsenide-indium arsenide-gallium arsenide-indium arsenide-gallium arsenide-indium arsenide-gallium arsenide-indium arsenide-phosphide-gallium arsenide-indium arsenide-indium arsenide-phosphide-indium arsenide-gallium arsenide-indium arsenide-phosphide-indium arsenide-indium arsenide-phosphide-gallium arsenide-indium arsenide-indium arsenide-phosphide-indium ...
[0060] In addition, the substrate 100 may include various P-type doped regions and / or N-type doped regions (not shown) formed by processes such as ion implantation and / or diffusion.
[0061] In some embodiments, the dielectric layer 220 may be made of a high-k oxide, such as hafnium oxide, hafnium silicate, hafnium oxynitride, hafnium aluminum oxide, hafnium lanthanum oxide, hafnium zirconium oxide, hafnium tantalum oxide, hafnium titanium oxide, lanthanum oxide, aluminum oxide, alumina silicon, zirconium oxide, titanium oxide, tantalum oxide, yttrium oxide, silicon oxynitride, or other suitable materials. The barrier layer 240 may be made of tantalum nitride, nickel silicide, cobalt silicide, titanium nitride, tungsten nitride, tungsten carbonitride, titanium aluminum, titanium tantalum nitride, titanium aluminum nitride, tantalum nitride, tantalum carbonitride, tantalum carbide, silicon tantalum nitride, or other known materials. The conductive filler 260 may be made of amorphous silicon, polycrystalline silicon, polycrystalline germanium, polycrystalline silicon germanium, metal nitride, metal silicide, metal carbide, metal oxide, or metal. The metal may include cobalt, ruthenium, aluminum, palladium, platinum, tungsten, copper, titanium, tantalum, silver, gold, or nickel. The conductive filler 260 may be made of tungsten. The capping layer 280 may be made of a low-k nitride, such as silicon nitride, silicon oxynitride, silicon carbonitride, or silicon oxynitride carbide.
[0062] In some embodiments, the material of the liner 420 may be, for example, silicon nitride. The insulating layer 440 may include a spin-on dielectric (SOD), such as spin-on glass (SOG) or other flowable oxides. In some embodiments, the material of the insulating layer 460 may include tetraethoxysilane or other similar materials. Since vias 400T2 for filling capacitor contacts 600 will subsequently be formed in the insulating layer 400, improving the flatness of the insulating layer 400 helps improve the stability of the overall structure; SOD can be used to form the insulating layer 440 to improve surface flatness. In an embodiment not shown, the insulating layer 440 does not use SOD or SOG, and the liner 420 may be omitted.
[0063] In one embodiment, the top surface of the insulating material layer 400 may be subjected to a planarization process (such as chemical mechanical polishing) to improve the flatness of the top surface of the insulating material layer 400, thereby improving the manufacturing yield of the subsequently formed capacitor contact 600.
[0064] In addition to the materials mentioned above, the insulating material layer 400 may also be made of silicon oxide, silicon oxynitride, silicon carbonitride, undoped silicate glass, doped silicon oxide such as boron-doped phospho-silicate glass (BPSG), fused silica glass (FSG), phospho-silicate glass (PSG), boron-doped silicate glass (BSG), low dielectric constant dielectric materials, other suitable dielectric materials, or combinations thereof.
[0065] Reference Figure 2 A groove 400R1 can be formed in the insulating material layer 400. It should be noted that the bottom surface of the groove 400R1 is higher than the bottom surface of the insulating material layer 400. In other words, the groove 400R1 does not etch through the insulating material layer 400, so that the substrate 100 is not exposed by the groove 400R1. By forming a groove 400R1 that does not etch through the insulating material layer 400, the present invention can more effectively control the critical dimensions of the capacitor contact 600 (described in detail below) and can protect the lower part of the insulating material layer 400. From the top view, the groove 400R1 can be located between adjacent bit lines 300 (described in detail below) without overlapping with them. The depth of the groove 400R1 can be greater than or equal to half the thickness of the insulating material layer 400. The groove 400R1 can be formed by any suitable etching process. For example, anisotropic etching (e.g., dry etching) can be used to form the groove 400R1. Next, isotropic (e.g., wet etching) methods can be used to adjust the critical dimensions of the groove 400R1. In some embodiments, one or more etching cycles can be performed until the groove 400R1 reaches the desired size and depth.
[0066] Reference Figure 3 A first dielectric material 520 may be compliantly formed on the bottom surface and sidewalls of the groove 400R1. In some embodiments, the first dielectric material 520 extends not only within the surface of the groove 400R1 but also onto the top surface of the insulating material layer 400. The first dielectric material 520 may be similar in material to the capping layer 280.
[0067] Reference Figure 4The horizontal portion of the first dielectric material 520 (e.g., the portion located on the bottom surface of the groove 400R1 and the portion located on the top surface of the insulating material layer 400) is removed to form a first dielectric layer 521 that only covers the sidewalls of the groove 400R1. The horizontal portion of the first dielectric material 520 can be etched by an anisotropic etching process (e.g., reactive ion etching or electro-particle etching). The first dielectric layer 521 can be used to protect the upper part of the subsequently formed insulating structure 400' and to prevent the subsequently formed capacitor contact 600 from diffusing into the insulating structure 400'.
[0068] If a via is formed through the insulating material layer and exposes the substrate before the formation of the first dielectric material, the first dielectric material will be formed on the exposed substrate surface. In this case, during the subsequent removal of the horizontal portion of the first dielectric material, the first dielectric material at the bottom of the via sidewall is easily thinned, resulting in a lower thickness at the bottom of the formed first dielectric layer. In particular, the larger the aspect ratio of the via, the greater the angle of the via sidewall. This exacerbates the thinning of the bottom of the first dielectric layer, or even causes it to break, leading to short circuits or interference between the subsequently formed capacitor contacts. Therefore, in this invention, by forming the first dielectric material 520 on the sidewall of the groove 400R1 of the un-etched insulating material layer 400, the problem of short circuits or interference between the subsequently formed capacitor contacts 600 can be effectively avoided.
[0069] Reference Figure 5 The first dielectric layer 521 can be used as a mask to etch the insulating material layer 400 (or the lower part of the insulating material layer 400) below the groove 400R1, so that the groove 400R1 extends downward to become a via 400T2 exposing the substrate 100. Furthermore, the etched insulating material layer 400 can become multiple insulating structures 400'. In other words, the bottom surface of the via 400T2 is lower than the bottom surface of the first dielectric layer 521. One or more etching cycles can be performed until the substrate 100 is exposed. According to some embodiments, since the critical dimensions of the groove 400R1 are easy to control and the presence of the first dielectric layer 521 provides protection, the critical dimensions of the via 400T2 are also easy to control. It is worth noting that in this step, the substrate 100 is not etched. Anisotropic dry etching can be used to form the via 400T2.
[0070] As previously described, if the first dielectric material is formed on the surface of a via exposed to the substrate, the bottom of the formed first dielectric layer may have a lower thickness. In this case, the subsequent etching step used to expose the substrate and remove surface impurities may damage the bottom of the first dielectric layer on the sidewall of the via, thereby eroding the lower part of the insulating structure and creating a gap. If this gap causes adjacent vias to accidentally bridge, the capacitor contacts subsequently filled into the vias may also fill the gap and bridge with each other, causing an electrical short circuit.
[0071] Reference Figure 6 According to one embodiment of the present invention, before removing impurities from the surface of the substrate 100, a notch 400C may be formed at the bottom of the sidewall of the via 400T2 exposed through the first dielectric layer 521. Thus, the lower part of each insulating structure 400' has two notches 400C, and the two notches 400C face each other along the extension direction of the bit line 300.
[0072] In some embodiments, the extension direction of the notch 400C may be parallel to the extension direction of the bit line 300, for example, along the X-axis (refer to Figure 12). The notch 400C may extend into the lower portion of the insulating structure 400', and the first dielectric layer 521 may be located above the notch 400C. In some preferred embodiments, to further reduce interference between subsequently formed capacitor contacts 600 and more effectively protect the lower portion of the insulating structure 400', the maximum horizontal depth D2 from the extended dashed line of the main surface of the first dielectric layer 521 to the surface of the notch 400C may be less than half of the maximum width D1 of the insulating structure 400', and may be greater than 5% of the maximum width D1 of the insulating structure 400'. Furthermore, the depth H2 of the first dielectric layer 521 may be greater than or equal to half of the thickness H1 of the insulating structure 400'. In some embodiments, the notch 400C may be formed using isotropic wet etching, while simultaneously etching the shallow trench isolation structure 120 to form a groove above the shallow trench isolation structure 120. Substrate 100 is essentially unaffected by the isotropic wet etching process.
[0073] Reference Figure 7 The second dielectric material 540 can be compliantly deposited on the surface of the via 400T2 having a notch 400C. In some embodiments, the second dielectric material 540 can be compliantly formed on the top surface of the insulating structure 400', in addition to lining the surfaces of the via 400T2 and the notch 400C. Furthermore, the second dielectric material 540 can fill a groove above the shallow trench isolation structure 120. To improve fabrication efficiency, the thickness of the second dielectric material 540 may not exceed half the maximum width D1 of the insulating structure 400'. The material of the second dielectric material 540 may be similar to the material of the capping layer 280. Atomic layer deposition with better step coverage can be used to form the second dielectric material 540.
[0074] Reference Figure 8The second dielectric layer 541 can be formed by removing, for example, the horizontal portion of the second dielectric material 540 (e.g., the portion located on the bottom surface of the via 400T2, the portion above the shallow trench isolation structure 120, and the portion on the top surface of the insulating structure 400') using an anisotropic etching process. The first portion 541-1 of the second dielectric layer 541 can be formed on the first dielectric layer 521, while the second portion 541-2 of the second dielectric layer 541 can be formed on the notch 400C.
[0075] According to one embodiment, the contour of the notch 400C can protect the second portion 541-2 of the second dielectric layer 541 from subsequent etching processes (e.g., etching of the substrate 100). In this way, the second portion 541-2 of the second dielectric layer 541 can provide good protection for the lower part of the insulating structure 400', thereby preventing short circuits or interference between subsequently formed capacitor contacts 600. Furthermore, the present invention increases the flexibility of structural design and manufacturing processes through the combination of the first dielectric layer 521 and the second dielectric layer 541.
[0076] Next, the substrate 100 can be etched. An anisotropic etching process with high selectivity for the substrate 100 can be used to etch the substrate 100 to remove impurities from its surface, thereby reducing the contact resistance of the subsequently formed capacitor contacts 600. During the etching of the substrate 100, the second portion 541-2 of the second dielectric layer 541 is protected by the contour of the notch 400C, preventing damage to the second portion 541-2. In some embodiments, the etched substrate 100 is substantially flush with the remaining shallow trench isolation structure 120, facilitating the subsequent filling of the capacitor contacts 600.
[0077] Reference Figure 9 Conductive material 620 can be filled into the through-hole 400T2. In some embodiments, the conductive material 620 is further filled into the recess 400C to form a protrusion 620P. This configuration can reduce the resistance of the capacitor contact 600, thereby improving the operating speed of the DRAM. In other words, the protrusion 620P is embedded in the insulating structure 400', and the first dielectric layer 521 is located above the protrusion 620P. In this way, the first portion 541-1 of the second dielectric layer 541 can be located between the first dielectric layer 521 and the conductive material 620, and the second portion 541-2 can be located between the insulating structure 400' and the protrusion 620P. Furthermore, in embodiments where the liner 420 is omitted, the protrusion 620P can directly contact the substrate 100. This further increases the contact area between the capacitor contact 600 and the substrate 100, thereby reducing contact resistance and enhancing the reliability of the dynamic random access memory 10. The conductive material 620 may be made of polycrystalline silicon, polycrystalline germanium, polycrystalline silicon-germanium, or other polycrystalline materials.
[0078] Reference Figure 10 According to one embodiment, the capacitor contact material may include a conductive material 620, a barrier layer 640, and a conductive filler 660 formed sequentially. A groove may be formed by etching the top of the conductive material 620, followed by the compliant formation of the barrier layer 640 within the groove, and the conductive filler 660 filling the groove is formed on the barrier layer 640. The material of the barrier layer 640 may be similar to that of the barrier layer 240. The material of the conductive filler 660 may be similar to that of the conductive filler 260.
[0079] Reference Figures 11-13 According to one embodiment, the dynamic random access memory 10 may include an isolation structure 700 through the capacitive contact material to separate the capacitive contact material located in each via 400T2 into two independent capacitive contacts 600. Figure 11 is a schematic cross-sectional view obtained according to section line A-A' of Figure 13. The position of the isolation structure 700 may overlap with the position of the shallow trench isolation structure 120 in the vertical projection. In a cross-section parallel to the extension direction of bit line 300 (e.g., section line A-A' shown in Figure 13), after the isolation structure 700 is formed, each capacitive contact 600 has a protrusion 620P embedded in the insulating structure 400' on only one side, while the other side is a planar sidewall adjacent to the isolation structure 700. From another viewpoint, the insulating structure 400' located between adjacent isolation structures 700 has a notch 400C on both opposite sides. In other words, the two sides of each capacitive contact 600 are asymmetrical, while the two sides of the insulating structure 400' are symmetrical. The material of the isolation structure 700 may be similar to that of the shallow trench isolation structure 120. Each capacitor contact 600 is configured to electrically connect the upper capacitor (not shown) to the lower substrate 100. According to a preferred embodiment, the top surface of the capacitor contact 600 may be flush with the top surface of the insulating structure 400' and the top surface of the isolation structure 700 to improve the manufacturing yield of the upper capacitor.
[0080] exist Figure 12 and Figure 13In addition to the aforementioned substrate 100, shallow trench isolation structure 120, word lines 200, insulating structure 400', capacitor contacts 600, first dielectric layer 521, second dielectric layer 541, and isolation structure 700, the dynamic random access memory 10 of this embodiment also includes bit lines 300 and bit line contact structures 301. The extension direction of the bit lines 300 (e.g., along the X-axis) is different from the extension direction of the word lines 200 (e.g., along the Y-axis). Notably, the extension direction of the protrusion 620P is parallel to the extension direction of the bit lines 300 (e.g., along the X-axis) and is embedded in the insulating structure 400'. The bit line contact structures 301 are disposed, for example, on the substrate 100 between adjacent word lines 200, for electrically connecting the substrate 100 and the bit lines 300. Any known process, structure, and material can be used to form the bit line contact structures 301. In a preferred embodiment, the bit line contact structure 301 may not overlap with the character line 200 in the vertical projection, thereby further reducing the interference between the bit line contact structure 301 and the character line 200 and facilitating miniaturization.
[0081] In some embodiments, bit lines 300 and bit line contact structures 301 are formed before the insulating structure 400' is formed. Interleaved insulating structures 400' and capacitive contacts 600 may be arranged along the extension direction of the bit lines 300 (e.g., along the X-axis) on opposite sides of each bit line 300, and these contacts may be self-aligned and fill the spaces between adjacent bit lines 300. Therefore, the capacitive contacts 600 may also be referred to as self-aligned contacts (SAC). Bit lines 300 may include a dielectric layer 320, a conductive layer 340, and a hard mask 360 sequentially formed on the substrate 100 and the bit line contact structures 301, and spacers 380 formed on the sidewalls of the dielectric layer 320, the conductive layer 340, and the hard mask 360. The material of the dielectric layer 320 may be similar to the material of the dielectric layer 220. The material of the conductive layer 340 may be similar to the material of the conductive filler 260. The material of the hard mask 360 may be similar to the material of the capping layer 280. The material of the spacer 380 can be selected from low dielectric constant materials, such as oxides, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxynitrocarbide, air gaps and combinations thereof.
[0082] Reference Figure 12After forming the via 400T2, the bit line 300 can be exposed. Therefore, the first dielectric layer 521 and the second dielectric layer 541 can be disposed between the bit line 300 and the capacitor contact 600, for example, formed between the spacer 380 and the capacitor contact 600. In this way, the parasitic capacitance between the bit line 300 and the capacitor contact 600 can be reduced. Furthermore, since the present invention provides an additional second dielectric layer 541 between the spacer 380 and the capacitor contact 600, even if the thickness of the spacer 380 is reduced for miniaturization, the interference between the bit line 300 and the capacitor contact 600 can still be reduced.
[0083] In some preferred embodiments, to further reduce the parasitic capacitance between the bit line 300 and the capacitor contact 600, the bottom surface of the first dielectric layer 521 is lower than the bottom surface of the conductive layer 340 of the bit line 300. Furthermore, the capacitor contact 600, the bit line contact structure 301, and the bit line 300 do not overlap in their vertical projections. In other words, the capacitor contact 600 is separated from the bit line contact structure 301 and the bit line 300. This configuration further reduces interference and improves the structural stability of the bit line contact structure 301 and the bit line 300, thereby increasing manufacturing yield.
[0084] Reference Figure 13 Since the character line 200 is embedded in the substrate 100 and the protrusion 620P is embedded in the insulating structure 400', the character line 200 and the protrusion 620P are indicated by dashed lines. In one embodiment, the protrusion 620P may partially overlap with the character line 200 in vertical projection, which is beneficial for miniaturization.
[0085] The above embodiment illustrates that a first dielectric layer 521 is first formed, then a via 400T2 and a notch 400C are formed, and a second dielectric layer 541 is formed on the surface of the via 400T2 and the notch 400C. Figures 14-17 This is a cross-sectional schematic diagram illustrating the stages of forming the dynamic random access memory 20 according to another embodiment of the present invention. (Refer to...) Figure 14 In the process of doing such Figures 1-4 Following the steps shown (e.g., after forming the first dielectric layer 521), the first dielectric layer 521 can be used as an insulating material layer 400 beneath the etched groove 400R1 to extend the groove 400R1 downwards to form a groove 400R2 that does not expose the substrate 100. A notch 400C can be formed at the bottom of the sidewall of the groove 400R2 exposed through the first dielectric layer 521.
[0086] Reference Figure 15 A second dielectric material 540 can be formed. In addition to being lined on the surfaces of the groove 400R2 and the notch 400C, the second dielectric material can also be compliantly formed on the top surface of the insulating material layer 400.
[0087] Reference Figure 16 The horizontal portion of the second dielectric material 540 can be removed to form a second dielectric layer 541. Next, using the second dielectric layer 541 as a mask, the insulating material layer 400 below the recess 400R2 is removed to extend the recess 400R2 downwards to form a via 400T2 exposing the substrate 100. Furthermore, the etched insulating material layer 400 can form multiple insulating structures 400'. Thus, the bottom of the sidewall of the via 400T2 does not contain the first dielectric layer 521 and / or the second dielectric layer 541. In some preferred embodiments, to further reduce the parasitic capacitance between the bit line 300 and the capacitor contact 600, the bottom surface of the second dielectric layer 541 can be lower than the bottom surface of the conductive layer 340 of the bit line 300. In some preferred embodiments, to further reduce the parasitic capacitance between the bit line 300 and the capacitor contact 600, the thickness of the second dielectric layer 541 can be greater than the thickness of the first dielectric layer 521. Then, the substrate 100 can be etched.
[0088] Reference Figure 17 Capacitor contacts 600 and isolation structures 700, including protrusions 620P, can be formed within the through-hole 400T2. The fabrication of the dynamic random access memory 20 is completed when the isolation structure 700 is formed. It should be noted that other details not specifically described in this embodiment are similar to those shown in the embodiment of the dynamic random access memory 10, and therefore will not be repeated.
[0089] The above embodiment illustrates that the second dielectric material 540 does not fill the notch 400C. Figures 18-20 This is a cross-sectional schematic diagram illustrating the various stages of forming the dynamic random access memory 30 according to another embodiment of the present invention. (Refer to...) Figure 18 In the process of doing such Figures 1-6 Following the steps shown, a second dielectric material 540 can be deposited in the through-hole 400T2 having a notch 400C. The second dielectric material 540 can fill the notch 400C.
[0090] Reference Figure 19 The horizontal portion of the second dielectric material 540 can be removed to form the second dielectric layer 541. In a particular embodiment of the invention, the second portion 541-2 of the second dielectric layer 541 may substantially fill the notch 400C.
[0091] Reference Figure 20Capacitor contacts 600 and isolation structures 700 can be formed within the through-hole 400T2. The fabrication of the dynamic random access memory 30 is completed when the isolation structure 700 is formed. Since the second portion 541-2 of the second dielectric layer 541 substantially fills the recess 400C, the capacitor contacts 600 of the dynamic random access memory 30 do not have protrusions 620P that fill the recess 400C. This design reduces voids generated during the filling of the recess 400C by the conductive material 620. It should be noted that other details not specifically described in this embodiment are similar to those shown in the embodiment of the dynamic random access memory 10, and therefore will not be repeated.
[0092] According to the DRAM and its manufacturing method of the present invention, during the manufacturing of the capacitor contact, a first dielectric material is formed in a groove that has not been etched through the insulating structure. The first dielectric layer is used as a mask to etch the insulating material layer below the groove, extending the groove downwards to become a deeper groove or a via exposing the substrate. Next, a notch is formed at the bottom of the sidewall of the deeper groove or the via exposing the substrate, and a second dielectric layer is formed in the notch. The second dielectric layer may or may not fill the notch. In this way, the second dielectric layer in the notch is not damaged by subsequent etching processes, and the subsequently formed capacitor contact can have a protrusion filling the notch (if the notch is not filled by the second dielectric layer). If the protrusion directly contacts the substrate, the contact area between the capacitor contact and the substrate can be further increased, thereby reducing contact resistance and enhancing the reliability of the DRAM. Other advantages of the embodiments of the present invention have been explained in the above embodiments and will not be repeated here.
[0093] This invention is applicable to the fabrication of miniaturized DRAM to increase the total number of dies on a chip. Therefore, this invention reduces the production cost and energy consumption of individual ICs, as well as the energy consumption of subsequent packaging, thereby reducing carbon emissions during DRAM production. Furthermore, in the DRAM of this invention, the manufacturing yield is improved due to the reduction of accidental bridging or interference between capacitor contacts. In some preferred embodiments, even the contact resistance of capacitor contacts and interference with bit line contact structures or between bit lines can be reduced. Therefore, this invention improves sensing margin, thereby reducing power consumption and increasing operating speed, making it suitable for low-power products. Thus, this invention provides a green semiconductor technology.
[0094] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same objectives and / or advantages as the embodiments described herein. Moreover, such equivalent structures do not depart from the spirit and scope of the present invention, and various changes and substitutions can be made without departing from the spirit and scope of the present invention.
Claims
1. A dynamic random access memory, characterized in that, include: A substrate; Multiple bit lines are disposed on the substrate; Multiple insulating structures are disposed on the substrate and located between adjacent bit lines, wherein each insulating structure has two notches at its lower part and the two notches face each other along the extension direction of each bit line; A capacitor contact is disposed on the substrate and located in a through hole between adjacent plurality of insulating structures; A first dielectric layer is disposed on the sidewall of the through hole located above the two recesses, and is located between each of the insulating structures and the capacitor contact; as well as A second dielectric layer, comprising: A first part is disposed on the first dielectric layer and located between the first dielectric layer and the capacitor contact; as well as A second part is disposed in the two recesses and located between the lower part of each of the insulating structures and the capacitor contact.
2. The dynamic random access memory as described in claim 1, characterized in that, Including: An isolation structure is disposed in the through hole to separate the two capacitor contacts located in the through hole; and A shallow trench isolation structure is disposed in the substrate.
3. The dynamic random access memory as described in claim 2, characterized in that, Each of the capacitor contacts includes a conductive material, and the conductive material is filled into each of the recesses to form a one-sided protrusion embedded in each of the insulating structures.
4. The dynamic random access memory as described in claim 3, characterized in that, The single-sided protrusion directly contacts the substrate.
5. The dynamic random access memory as described in claim 3, characterized in that, The extension direction of the single-sided protrusion is parallel to the extension direction of each bit line.
6. The dynamic random access memory as described in claim 2, characterized in that, The location of the isolation structure overlaps with the location of the shallow trench isolation structure in the vertical projection.
7. The dynamic random access memory as described in claim 1, characterized in that, The maximum horizontal depth of the extension line from the main surface of the first dielectric layer to the surface of the two notches is less than half the maximum width of each of the insulating structures and greater than 5% of the maximum width of each of the insulating structures.
8. The dynamic random access memory as described in claim 2, characterized in that, Including: Multiple character lines are disposed in the substrate; as well as A single-line contact structure is located on the substrate between adjacent character lines.
9. The dynamic random access memory as described in claim 8, characterized in that, Each bit line includes a dielectric layer, a conductive layer, and a hard mask sequentially disposed on the substrate, and a spacer formed on the sidewalls of the dielectric layer, the conductive layer, and the hard mask, wherein the first dielectric layer and the second dielectric layer are located between the spacer and the capacitor contact.
10. The dynamic random access memory as described in claim 9, characterized in that, The bottom surface of the first dielectric layer is lower than the bottom surface of the conductive layer.
11. The dynamic random access memory as described in claim 8, characterized in that, The capacitor contact is separated from the bit line contact structure and each bit line.
12. The dynamic random access memory as described in claim 3, characterized in that, Including: Multiple character lines are disposed in the substrate. The single-sided protrusion overlaps with the plurality of character lines in the vertical projection.
13. The dynamic random access memory as described in claim 9, characterized in that, The bottom surface of the second dielectric layer is lower than the bottom surface of the conductive layer of each bit line, and the bottom surface of the second dielectric layer is higher than the top surface of the substrate.
14. The dynamic random access memory as described in claim 1, characterized in that, The thickness of the second dielectric layer is greater than the thickness of the first dielectric layer.
15. The dynamic random access memory as described in claim 14, characterized in that, The second part of the second dielectric layer fills the two notches.
16. A method for manufacturing a dynamic random access memory, characterized in that, include: Multiple bit lines are formed on a substrate; Multiple insulating structures are formed on the substrate and located between adjacent bit lines, wherein each insulating structure has two notches at its lower part and the two notches face each other along the extension direction of each bit line; A capacitor contact is formed on the substrate and located in a through-hole between adjacent plurality of insulating structures; A first dielectric layer is compliantly formed on the sidewall of the via located above the two notches, and is located between each of the insulating structures and the capacitor contact; as well as A second dielectric layer is formed, comprising a first portion and a second portion, wherein the first portion is formed on the first dielectric layer and located between the first dielectric layer and the capacitor contact, and wherein the second portion is formed in the two notches and located between the lower part of the insulating structure and the capacitor contact.
17. The method for manufacturing a dynamic random access memory as described in claim 16, characterized in that, Forming the plurality of insulating structures includes: An insulating material layer is formed on the substrate; A groove is formed in the insulating material layer, the bottom surface of the groove is higher than the bottom surface of the insulating material layer, and the groove is located between adjacent bit lines, wherein the first dielectric layer is compliantly formed on the sidewall of the groove; After compliantly forming the first dielectric layer, the insulating material layer beneath the grooves is etched to form the two notches at the bottom of the insulating material layer; and The groove extends downward to form the through hole exposing the substrate, and the insulating material layer forms the plurality of insulating structures.
18. The method for manufacturing a dynamic random access memory as described in claim 17, characterized in that, The depth of the groove is greater than or equal to half the thickness of the insulating material layer.
19. The method for manufacturing a dynamic random access memory as described in claim 17, characterized in that, Including: After forming the second dielectric layer, the substrate is etched; and Using the first dielectric layer as a mask, the insulating material layer below the groove is etched, and the two notches are formed at the bottom of the through-hole sidewall exposed by the first dielectric layer.
20. The method for manufacturing a dynamic random access memory as described in claim 17, characterized in that, Including: After the second dielectric layer is formed, the substrate is etched. Using the first dielectric layer as a mask, the insulating material layer below the groove is etched to extend the groove downwards into a deeper groove that does not expose the substrate, and the two notches are formed at the bottom of the sidewall of the deeper groove exposed by the first dielectric layer; and Using the second dielectric layer as a mask, the insulating material layer below the deeper groove is etched to extend the deeper groove downwards to form the via exposed to the substrate, and the insulating material layer forms the plurality of insulating structures.