Manufacturing method of semiconductor device

Abstract

The invention provides a manufacturing method of a semiconductor device, and the method comprises the steps: depositing a second stress layer after forming a groove which can expose the top surface of an active region and enables the boundary vertex angle of a device isolation structure to be removed, and carrying out the annealing, so as to introduce stress to enhance the compactness of the device isolation structure, the second stress layer is further etched to expose the vertex angle and the top surface of the active region and form a side wall on the top side wall of the device isolation structure, so that the blocking capability of the device isolation structure on oxygen transverse diffusion when a thicker gate oxide layer is formed is improved; and the problem that a beak is generated due to the fact that oxygen transversely diffuses to penetrate through the device isolation structure into an adjacent active region is avoided. Furthermore, impurity elements for improving the oxidation rate of the active region are doped in the top of the active region in the groove and / or impurity elements for consuming oxygen transversely diffused from the active region are doped in the side wall of the top of the device isolation structure, so that the beak problem in the forming process of the gate oxide layer is reduced or even eliminated.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and in particular to a method for manufacturing a semiconductor device. Background Technology

[0002] With the continuous miniaturization of semiconductor components and the demands of specific applications, current product designs often require the manufacture of high-voltage transistors. A high-voltage transistor is a transistor capable of withstanding higher voltages while ensuring that the gate does not break down under high voltage operation. Generally, the gate oxide layer (HVGOX) of a high-voltage transistor is relatively thick (e.g., in...). (and above), and is generally completed through furnace tube oxidation process. In the existing furnace tube growth process of the gate oxide layer of high voltage transistors, oxygen (O2) diffuses laterally during the vertical growth of the gate oxide layer of the high voltage transistor. The lateral diffusion of O2 causes oxidation of the active region that is blocked by masking layers such as SiN around the gate oxide layer formation area of ​​the high voltage transistor, resulting in the bird's beak problem, which affects the reliability of the device and the yield of the product. Summary of the Invention

[0003] The purpose of this invention is to provide a method for manufacturing a semiconductor device that can improve the bird beak problem that occurs during the formation of the gate oxide layer.

[0004] To achieve the above objectives, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps:

[0005] A substrate is provided having a device isolation structure and a trench, the device isolation structure defining an active region in the substrate, and the trench exposing a top surface of the active region, including a corner sidewall, and a top sidewall of the device isolation structure adjacent to the active region.

[0006] A second stress layer is deposited on the inner surface of the trench and on the device surface around the trench and annealed to densify the device isolation structure on the sidewall of the trench.

[0007] The second stress layer is etched to form a sidewall covering the top sidewall of the device isolation structure exposed by the trench;

[0008] The top of the active region exposed by the trench and / or the top sidewall of the device isolation structure are doped with corresponding impurity elements. The impurity elements doped in the active region are used to increase the oxidation rate of the active region, and the impurity elements doped in the device isolation structure are used to consume oxygen diffused into the device isolation structure.

[0009] The top of the active region in the trench is thermally oxidized to form the desired gate oxide layer.

[0010] Optionally, the step of providing a substrate having device isolation structures and trenches includes:

[0011] An isolation structure for the device is formed in the substrate to define an active region;

[0012] A stress isolation layer is deposited on the substrate and the device isolation structure, and the top surface of the stress isolation layer is planarized, with the remaining stress isolation layer at least burying the top of the active region.

[0013] Deposit the first stress layer;

[0014] The first stress layer and the stress isolation layer on the boundary apex corner of the active region and the adjacent device isolation structure are etched to form a trench;

[0015] The active region with a portion of its thickness in the opening and the boundary corner of the device isolation structure are etched away to reduce the top height of the active region and thus form the trench. Alternatively, the active region in the opening is first thermally oxidized to form a sacrificial oxide layer, the sacrificial oxide layer is then removed by wet processing, and the device isolation structure is side-cut to reduce the top height of the active region and remove the boundary corner of the device isolation structure, thus forming the trench.

[0016] Optionally, the thickness of the second stress layer is less than or equal to 1 / 2 of the thickness of the first stress layer.

[0017] Optionally, the bottom of the trench at the boundary of the device isolation structure is lower than the top surface of the active region in the trench to form a side trench; the bottom end of the side wall abuts against the bottom surface of the side trench or is spaced apart from the bottom surface of the side trench.

[0018] Optionally, the steps for forming the sidewall are as follows: first, the second stress layer is etched using a dry etching process to remove the second stress layer on the top surface of the first stress layer and on the top surface of the active region in the trench; then, the remaining second stress layer is wet-etched to expose the top corner surface of the active region, and the remaining second stress layer on the top sidewall of the device isolation structure forms the sidewall.

[0019] Optionally, the manufacturing method further includes at least one of the following parameters:

[0020] (1) The materials of the device isolation structure and the stress isolation layer include an oxide layer;

[0021] (2) The first stress layer includes a nitrided layer and / or a nitrogen oxide layer;

[0022] (3) The second stress layer includes a nitrided layer and / or a nitrogen oxide layer;

[0023] (4) The longitudinal depth of the trench above the active region is

[0024] (5) The impurity elements include silicon and / or germanium;

[0025] (6) The device isolation structure is a shallow trench isolation structure, and the top of the shallow trench isolation structure is generally higher than the top of the active region before the trench is formed;

[0026] (7) The deposition thickness of the first stress layer is

[0027] (8) The annealing includes spike annealing and / or laser annealing.

[0028] Optionally, appropriate impurity elements may be incorporated into the top of the active region exposed by the trench and / or the top sidewall of the device isolation structure by means of ion implantation or diffusion doping processes.

[0029] Optionally, the top of the active region exposed by the trench and the top sidewall of the device isolation structure are implanted with ions containing the impurity elements by tilted ion implantation process, and the corresponding impurity elements are doped into the top of the active region exposed by the trench and the top sidewall of the device isolation structure.

[0030] Optionally, after incorporating the impurity element and before thermally oxidizing the top of the active region in the trench, the method further includes: performing surface oxidation on the top of the active region in the trench to round the corners of the active region and form an oxide film; wherein, during the formation of the gate oxide layer, the corners of the active region remain rounded under the constraint of the oxide film.

[0031] Optionally, the surface of the active region in the trench is purged with oxygen at 60°C to 80°C to form an oxide film.

[0032] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0033] 1. After forming trenches that expose the top surface of the active region and remove the boundary corners of the device isolation structure, a second stress layer is deposited and annealed to introduce stress to enhance the compactness of the device isolation structure. The second stress layer is further etched to expose the corners and top surface of the active region and form sidewalls on the top sidewalls of the device isolation structure. This improves the ability of the device isolation structure to block lateral oxygen diffusion when a thicker gate oxide layer is formed, and avoids the bird beak problem caused by lateral oxygen diffusion through the device isolation structure into the adjacent active region.

[0034] 2. Doping the top of the active region with appropriate impurity elements to increase the oxidation rate of the active region, accelerate the oxidation process, reduce the oxidation time, and reduce the bird beak; and / or, doping the top sidewall of the device isolation structure with appropriate impurity elements to serve as a consumable for oxygen laterally diffused into the device isolation structure during the formation of the gate oxide layer, thereby reducing oxygen passing through the device isolation structure and reducing or even eliminating the bird beak.

[0035] 3. Furthermore, after incorporating appropriate impurity elements into the active region and / or the device isolation structure, an oxide film is formed on the surface of the active region by oxidation, which rounds the corners of the active region. This can improve the uniformity of the growth rate of the gate oxide layer during subsequent thermal oxidation growth and avoid the problem of increased leakage current at the corners of the active region. Attached Figure Description

[0036] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0037] Figure 1 This is a schematic diagram of a bird's beak generated during the formation of the high-voltage gate oxide layer in high-voltage devices using existing technology.

[0038] Figure 2 This is a schematic diagram of a semiconductor device manufacturing method according to an embodiment of the present invention.

[0039] Figures 3 to 9 yes Figure 2 A schematic diagram of the cross-sectional structure of a semiconductor device in a manufacturing method shown. Detailed Implementation

[0040] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0041] The inventors of this application have discovered through research, please refer to... Figure 1 During the process of forming the gate oxide (HVGOX) layer of a high-voltage transistor through furnace tube thermal oxidation, in addition to the vertical growth of the HVGOX layer, there is also lateral diffusion of O2 (oxygen). O2 diffuses laterally through the surrounding device isolation structure (e.g., a shallow trench isolation structure, STI) and into the active region AA, which is blocked by the SiN hard mask layer, resulting in a bird's beak effect (e.g.,...). Figure 1 The generation of the region shown by the dashed circle, and the presence of the bird's beak, can easily lead to the following problems:

[0042] (1) This results in an abnormally thick silicon oxide layer on the surface of the active region AA (i.e., the active region AA that is shielded by the SiN hard mask layer) used as the source and drain regions of the high voltage transistor, which affects the implementation of subsequent processes.

[0043] (2) When the lateral length of these bird beaks is long, they can easily pass through the top surface of the adjacent active region (i.e., the active region AA that is covered by the SiN hard mask layer) from one side of a device isolation structure (e.g., STI) and connect with another device isolation structure (e.g., STI), which results in the inability to form metal silicide (not shown) on the active region (i.e., the active region AA that is covered by the SiN hard mask layer).

[0044] (3) Even if the bird's beak formed on the top surface of the active region AA, which is covered by the SiN hard mask layer, is not connected to another device isolation structure (such as STI), if the bird's beak is too large, it may encroach on the area of ​​the active region where metal silicide should be formed, resulting in the inability to form metal silicide with normal morphology on the active region (such as insufficient metal silicide formation), causing problems such as high resistance state of the formed contact hole CT and high RC delay, high power consumption of high voltage transistor or even failure to work properly.

[0045] (4) Subsequently, the amount of etching solution such as HF acid needs to be increased to wet remove the beak. If the window for wet removal of the beak is insufficient, the beak will remain, which may still cause the contact hole CT (not shown) formed on the active area to be unable to connect to the metal silicide, thus forming a high-resistivity state of the CT.

[0046] Therefore, improving or reducing the bird's beak problem during the gate oxide layer formation process is now imperative.

[0047] The current solutions to the above problems mainly focus on: first, improving the furnace tube process (e.g., adjusting the furnace tube thermal oxidation process parameters, including increasing the process temperature) to reduce the thickness of the bird's beak formed by O2 lateral diffusion and oxidation; second, improving other processes to enhance the blocking ability of O2 diffusion and reduce the bird's beak effect; and third, increasing the amount of HF acid or etching time in subsequent processes to lose more oxide layers, thereby reducing or even removing the bird's beak formed by oxidation.

[0048] These methods have the following drawbacks: First, they challenge the limits of furnace control processes and alter the morphology of the gate oxide layer (HVGOX) of high-voltage transistors. Second, they can damage the gate oxide layer of high-voltage transistors due to increased HF acid content or etching time, thus affecting device reliability.

[0049] Based on this, the present invention provides a method for manufacturing a semiconductor device. After forming a trench that exposes the top surface of the active region and removes the apex corners of the device isolation structure, a second stress layer is deposited and annealed to introduce stress to enhance the compactness of the device isolation structure. The second stress layer is further etched to expose the apex corners and top surface of the active region and to form sidewalls on the top sidewalls of the device isolation structure. This improves the ability of the device isolation structure to block lateral oxygen diffusion when forming a thicker gate oxide layer, avoiding the bird's beak problem caused by lateral oxygen diffusion through the device isolation structure into the adjacent active region. Furthermore, appropriate impurity elements are doped into the top of the active region and / or the top sidewalls of the device isolation structure to accelerate the oxidation process of the active region, reduce oxidation time, and reduce the bird's beak; and / or, during the formation of the gate oxide layer, impurity elements in the device isolation structure are used to consume laterally diffused oxygen, reducing oxygen penetration through the device isolation structure, thereby reducing or even eliminating the bird's beak problem.

[0050] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0051] Please refer to Figure 2 An embodiment of the present invention provides a method for manufacturing a semiconductor device, which includes the following steps:

[0052] S1, a substrate having a device isolation structure and a trench is provided, the device isolation structure defining an active region in the substrate, the trench exposing a top surface of the active region including a corner sidewall and a top sidewall of the device isolation structure adjacent to the active region;

[0053] S2, deposit a second stress layer on the inner surface of the trench and the device surface around the trench and anneal it to densify the device isolation structure on the sidewall of the trench;

[0054] S3, etch the second stress layer to form a sidewall covering the top sidewall of the device isolation structure exposed by the trench;

[0055] S4, doping the top of the active region exposed by the trench and / or the top sidewall of the device isolation structure with a corresponding impurity element, the impurity element being used to increase the oxidation rate of the active region and / or to consume oxygen diffused into the device isolation structure;

[0056] S5, thermally oxidize the top of the active region in the trench to form the desired gate oxide layer.

[0057] In step S1, please refer to Figure 3 The provided substrate can be any suitable semiconductor substrate material, such as pure silicon, silicon germanium (SiGe), silicon carbide (SiC), or silicon-on-insulator (SOI), etc. The further steps of forming the device isolation structure 100b and trench 104 in the substrate include:

[0058] (1) Please refer to Figure 3 A pad oxide layer (PAD OX) 101 is formed on the substrate by any suitable process such as thermal oxidation, atomic layer deposition or plasma-enhanced chemical vapor deposition.

[0059] (2) Please refer to Figure 3 A series of processes, including hard mask deposition, photolithography, and etching, are used to etch the substrate to form shallow trenches (not shown). Linear oxide layers (not shown) are then formed on the inner surface of the shallow trenches using thermal oxidation, atomic layer deposition, or plasma-enhanced chemical vapor deposition. Next, insulating dielectric material is deposited using chemical vapor deposition to fill the shallow trenches. Excess insulating dielectric material is further removed using chemical mechanical polishing or wet etching, thereby forming a shallow trench isolation structure (STI) filled in the shallow trenches, which serves as the device isolation structure 100b. The device isolation structure 100b defines active regions (AA) 100a within the substrate. As an example, multiple active regions 100a can be defined in the substrate, such as high-voltage NMOS active regions and high-voltage PMOS active regions. Figure 3 Only one active region 100a is shown. As an example, the top of the device isolation structure 100b may be higher than the top of the active region 100a.

[0060] It should be understood that after forming the device isolation structure 100b, the pad oxide layer 101 can be retained or removed as needed. Furthermore, before or after forming the device isolation structure, P-type ion implantation such as boron can be performed in the corresponding region of the substrate to form a P-well region (not shown), and N-type ion implantation such as arsenic or phosphorus can be performed to form an N-well region (not shown).

[0061] (3) Please refer to Figure 3The stress isolation layer 102 can be formed by any suitable process such as atomic layer deposition, plasma-enhanced chemical vapor deposition, or thermal oxidation (e.g., in-situ vapor oxidation). The stress isolation layer 102 can include any suitable oxide layer such as silicon oxide or a high-k dielectric with a dielectric constant k greater than that of silicon oxide, and its thickness is thicker than that of the pad oxide layer 101 or the natural oxide layer on the substrate. Then, any suitable process such as chemical mechanical polishing (CMP) can be used to planarize the top surface of the stress isolation layer 102 to obtain a flat process surface. The remaining stress isolation layer 102 still buries the top of the active region 100a and can bury the device isolation structure 100b (at this time, the remaining stress isolation layer 102 on the top surface of the device isolation structure 100b is relatively thin) or expose the top surface of the device isolation structure 100b (at this time, the top surface of the remaining stress isolation layer 102 is flush with the top surface of the remaining device isolation structure 100b).

[0062] (4) Please refer to Figure 3 The first stress layer 103 can be deposited on the surface of the stress isolation layer 102 or similar structure using any suitable process, such as atomic layer deposition, plasma-enhanced chemical vapor deposition, or chemical vapor deposition. This process involves depositing a nitride layer (e.g., silicon nitride), an oxide nitride layer (e.g., silicon oxynitride), or a composite layer of oxide and oxide layers. This first stress layer 103 can serve as a hard mask layer during subsequent trench formation or introduce stress into the device isolation structure during subsequent annealing. In this process, the stress isolation layer 102 can buffer the stress on the active region 100a caused by the deposition of the first stress layer 103. Optionally, the deposition thickness of the first stress layer 103 is... For example, the deposition thickness of the first stress layer 103 is about.

[0063] (5) Please refer to Figure 4The first stress layer 103 is photolithographically and dry-etched to open the first stress layer 103 at the boundary corner of the active region 100a and the adjacent device isolation structure 100b, forming a corresponding opening (unmarked) to define the area where the trench 104 is to be formed. In this process, the stress isolation layer 102 can serve as a protective layer to prevent damage to the active region 100a, etc., during the etching process of opening the first stress layer 103. Subsequently, under the masking of the first stress layer 103, any suitable etching process, such as dry etching or wet etching, can be used to continue etching along the opening of the first stress layer 103, sequentially opening the stress isolation layer 102 and the pad oxide layer 101, exposing the top of the active region 100a and the boundary corner of the device isolation structure 100b at the bottom of the opening. Then, any suitable etching process, such as dry etching or wet etching, can be used to continue etching along the opening to the exposed top of the active region 100a and the boundary corner of the device isolation structure 100b, causing the top of the active region 100a to drop to the required height, forming the required trench 104. This trench 104 can expose the top surface of the active region 100a, including the corner sidewall, and the top sidewall of the device isolation structure 100b adjacent to the active region 100a.

[0064] The longitudinal depth of trench 104 needs to meet the thickness requirements of the subsequently formed gate oxide layer. As an example, the longitudinal depth of trench 104 above active region 100a is...

[0065] Since the trench 104 extends laterally to the apex region where the device isolation structure 100b is removed, the process window for forming the gate oxide layer can be expanded in the subsequent process. It can also meet the requirements of minimum spacing such as gate-to-source contact plugs of high voltage transistors. This is beneficial for the subsequent self-aligned formation of the gate oxide layer in the trench 104 and avoids affecting the device reliability.

[0066] Optionally, after etching the active region 100a, any suitable etching solution such as HF acid solution, SPM (a mixture of H2SO4, H2O2, and H2O), or SCI (a mixture of NH4OH, H2O2, and H2O) can be used for wet cleaning to remove etching residues. During this process, the device isolation structure 100b in the trench 104 is further wet-etched, causing the height of the device isolation structure 100b in the trench 104 to continue decreasing below the top of the active region 100a. This forms a side trench 104a between the top sidewall of the device isolation structure 100b in the trench 104 and the top sidewall of the active region 100a. This side trench 104a ensures that the sidewall and top surface of the apex corner of the active region AA are exposed. That is, the bottom of the trench 104 at the boundary of the device isolation structure 100b is lower than the top surface of the active region 100b in the trench 104. The side ditch 104a is also part of the trench 104.

[0067] It should be understood that, in the above example, after etching open the first stress layer 103, stress isolation layer 102 and pad oxide layer 101 to expose the top surface of the active region 100a, the active region 100a is further etched under the mask of the first stress layer 103 to form the trench 104, but the technical solution of the present invention is not limited to this. In other examples of the present invention, after etching open the first stress layer 103, stress isolation layer 102 and pad oxide layer 101 to form an opening exposing the top surface of the active region 100a, the top of the active region 100a at the bottom of the opening is first thermally oxidized to form a sacrificial oxide layer (not shown) of the required thickness. Then, the sacrificial oxide layer is removed by any suitable process such as wet etching, so that the top surface of the active region 100a is lowered to the required depth to form a trench 104. During this process, the device isolation structure 100b is also side-grooved to form a side trench 104a, thereby exposing the sidewall of the top corner of the active region 100a (i.e., the boundary sidewall of the device isolation structure 100b) through the side trench 104a.

[0068] In step S2, please refer to Figure 5 Any suitable process, such as chemical vapor deposition, can be used to deposit a nitride layer (e.g., silicon nitride), an oxide nitride layer (e.g., silicon nitride), or a composite layer material formed by stacking nitride and oxide nitride layers as the second stress layer 105. Any suitable annealing process, such as spike annealing or laser annealing, can be used for post-deposition annealing (e.g., spike annealing followed by laser annealing). This generates downward stress on the active region 100a, which is conducted to the device isolation structure 100b to increase the internal pressure of the device isolation structure 100b and make it denser.

[0069] The second stress layer 105 is thinner than the first stress layer 103. On the one hand, together with the first stress layer 103, it increases the stress on the device isolation structure 100b, making the device isolation structure 100b more compact, blocking the diffusion rate of O2 during the subsequent formation of the gate oxide layer, and improving the bird beak effect. On the other hand, it forms a sidewall on the top sidewall of the device isolation structure 100b during the subsequent formation of the gate oxide layer, so as to further block the penetration of oxygen during the subsequent formation of the gate oxide layer.

[0070] For example, the deposition thickness of the second stress layer 105 is half or less of the deposition thickness of the first stress layer 103, so as to avoid it being too thick and introducing too much stress into the active region 100a in the trench 104, thus affecting the device performance.

[0071] In step S3, please refer to Figure 6A and Figure 6B First, any suitable etching process, such as dry etching, can be used to etch the second stress layer 105 to remove the second stress layer 105 on the top surface of the first stress layer 103 and on the top surface of the active region 100b in the trench 104. Then, wet etching is performed on the remaining second stress layer 105 to remove etching residues and the remaining second stress layer 105 on the top of the active region 100b, thereby re-exposing the top surface of the active region 100b and the side surface of the top corner. The remaining second stress layer 105 on the top sidewall of the device isolation structure 100b (or the sidewall of the trench 104) is formed as a sidewall 105a.

[0072] It should be understood that in step S3, process parameters such as the concentration of the wet etching solution and the wet etching time will affect the bottom height of the sidewall 105a formed in the trench 104. Figure 6A In the example shown, after wet etching, the sidewall 105a extends downward from the sidewall of the first stress layer 103 on the sidewall of the trench 104 to the bottom end of the sidewall exposed by the side trench 104a on the device isolation structure 100b. That is, the bottom end of the sidewall 105a abuts against the bottom surface of the side trench 104a, thereby maximizing the oxygen barrier effect of the sidewall 105a during the subsequent gate oxide layer formation process. And... Figure 6B In the example shown, after wet etching, the sidewall 105a extends downward from the sidewall of the first stress layer 103 on the sidewall of the trench 104 to the upper part of the sidewall of the device isolation structure 100b exposed by the side trench 104a. There is a gap between the bottom end of the sidewall 105a and the bottom surface of the side trench 104a (i.e., the bottom end of the sidewall 105a is a certain height away from the bottom surface of the side trench 104a). Thus, while ensuring the oxygen blocking effect of the sidewall 105a in the subsequent gate oxide layer formation process, it also makes it easier for the corresponding impurity elements to enter the top sidewall of the device isolation structure 100b when they are subsequently doped.

[0073] Please refer to Figure 7 In step S4, any suitable doping process, such as diffusion doping or ion implantation, can be used to dope the top of the active region 100a exposed in the trench 104 and / or the top sidewall of the device isolation structure 100b with the corresponding impurity element 106.

[0074] Specifically, the impurity element 106 incorporated into the top of the active region 100a exposed by trench 104 can increase the oxidation rate of the active region 100a during the subsequent oxidation of the top of the active region 100a to form a gate oxide layer. The impurity element 106 incorporated into the top sidewall of the device isolation structure 100b exposed by trench 104 can react with laterally diffused oxygen molecules during the thermal oxidation process of the subsequent gate oxide layer formation, thereby consuming the oxygen diffused into the device isolation structure 100b and preventing oxygen from passing through the top of the device isolation structure 100b and reacting with the active region on the other side of the top of the device isolation structure 100b to form a "bird's beak" effect. Therefore, the impurity elements incorporated into the top of the active region 100a and the sidewall of the device isolation structure 100b at trench 104 can be the same or different.

[0075] Optionally, the impurity elements incorporated into the top of the active region 100a at the trench 104 and the sidewall of the device isolation structure 100b are the same, and may include silicon, germanium, or a mixture of silicon and germanium ions.

[0076] As an example, please refer to Figure 7 In step S4, ion implantation containing the corresponding impurity element 106 is performed on the top of the active region 100a exposed in the trench 104 (including the side trench 104a) and the top sidewall of the device isolation structure 100b using a tilted ion implantation process. The corresponding impurity element 106 (i.e., impurity ions) is incorporated into the top of the active region 100a exposed in the trench 104 and the top sidewall of the device isolation structure 100b. The impurity element 106 (i.e., impurity ions) implanted in the device isolation structure 100b serves as a consumable for oxygen penetrating into the device isolation structure 100b during the subsequent gate oxide layer formation process, reducing the beak-like formation caused by oxygen penetrating the device isolation structure 100b. Meanwhile, the impurity element 106 (i.e., impurity ions) injected into the active region 100a is used to break up the lattice of the surface layer of the active region 100a, making the surface of the active region 100a loose, so that an oxide film can be formed quickly in the subsequent process, making the active region rounded, and accelerating the oxidation process of the surface layer of the active region 100a in the subsequent gate oxide layer formation process, which can reduce the oxidation time and thus reduce the beak.

[0077] It should be understood that when there are multiple ions of impurity element 106, impurity elements can be doped into the top of the active region 100a at trench 104 and the top sidewall of the device isolation structure 100b by means of co-implantation or multi-step implantation with different ions implanted in each step.

[0078] Alternatively, please refer to Figure 8 After step S4 and before proceeding to step S5, the top of the active region 100a in the trench 104 is first surface-oxidized to round the corners of the active region 100a and form an oxide film 107. The oxide film 107 can improve the uniformity of the thermal oxidation growth rate of the gate oxide layer on the active region 100a in subsequent processes, avoiding the problem that the growth rate of the gate oxide layer near the corners of the active region 100a is relatively slower than other positions when the gate oxide layer is thermally oxidized on the active region. This maintains the rounded corners of the active region 100a and avoids the problem of concentrated current at the corners of the active region 100a causing the gate oxide layer to break down or the leakage current to increase.

[0079] As an example, oxygen at 60°C–80°C is used to purge the surface of the active region 100a in the trench 104, forming an oxide film 107. This replaces the sacrificial oxide layer formed by the high-temperature furnace tube for rounding the corners of the active region 100a, reducing the heat budget and thus reducing the degree of beak formation during the subsequent gate oxide layer formation process. The thickness of this oxide film 107 can be arbitrarily suitable, as long as it achieves the purpose of rounding the corners of the active region; for example, its thickness is...

[0080] In step S5, please refer to Figure 9 Based on the required gate oxide thickness, a corresponding thermal oxidation process recipe is set. Following this recipe, the top of the active region 100a exposed by the thermal oxidation trench 104 is thermally oxidized, thereby self-aligning the growth of a gate oxide layer (HVGOX) 108 of the required thickness. During this process, the impurity elements incorporated into the active region 100a can increase the oxidation rate of the active region 100a, and under the constraint of the oxide film 107, the corners of the active region 100a can be rounded during the formation of the gate oxide layer 108. Simultaneously, the impurity elements 106 incorporated into the device isolation structure 100b can react with laterally diffused oxygen to consume oxygen, forming a denser material 106a (e.g., a denser oxide layer), preventing oxygen from penetrating the device isolation structure 100b and causing a bird's beak effect.

[0081] Furthermore, the thickness of the gate oxide layer (HVGOX) 108 is sufficient to restore the surface flatness between the active region 100a and the top surface of the device isolation structure 100b relative to its surrounding region.

[0082] Optionally, when the materials of the first stress layer 103 and the sidewall 105a on the top sidewall of the device isolation structure 100b are the same or similar, after the required gate oxide layer 108 is formed, the first stress layer 103 and the sidewall 105a can be further removed together by a wet etching process.

[0083] It should be understood that the above embodiments are all illustrated using shallow trench isolation (STI) as an example. However, the technical solution of the present invention is not limited to this. In other embodiments of the present invention, local field oxygen isolation (RFO) structures can be used to replace shallow trench isolation (STI) structures as device isolation structures.

[0084] In summary, the semiconductor device manufacturing method of the present invention, after forming a trench that exposes the top surface of the active region and removes the boundary corners of the device isolation structure, deposits a second stress layer and anneals it to introduce stress to enhance the compactness of the device isolation structure. Furthermore, the second stress layer is etched to expose the corners and top surface of the active region and to form sidewalls on the top sidewalls of the device isolation structure. This improves the ability of the device isolation structure to block lateral oxygen diffusion when forming a thicker gate oxide layer, avoiding the bird's beak problem caused by lateral oxygen diffusion through the device isolation structure into the adjacent active region. Furthermore, impurity elements that increase the oxidation rate of the active region are doped in the top of the active region in the trench, and / or impurity elements that consume oxygen laterally diffused from the active region are doped in the top sidewalls of the device isolation structure, thereby reducing or even eliminating the bird's beak problem during the gate oxide formation process.

[0085] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Includes the following steps: A substrate is provided having a device isolation structure and a trench, the device isolation structure defining an active region in the substrate, and the trench exposing a top surface of the active region, including a corner sidewall, and a top sidewall of the device isolation structure adjacent to the active region. A second stress layer is deposited on the inner surface of the trench and on the device surface around the trench and annealed to densify the device isolation structure on the sidewall of the trench. The second stress layer is etched to form a sidewall covering the top sidewall of the device isolation structure exposed by the trench; The top of the active region exposed by the trench and / or the top sidewall of the device isolation structure are doped with corresponding impurity elements. The impurity elements doped in the active region are used to increase the oxidation rate of the active region, and the impurity elements doped in the device isolation structure are used to consume oxygen diffused into the device isolation structure. The top of the active region in the trench is thermally oxidized to form the desired gate oxide layer.

2. The manufacturing method as described in claim 1, characterized in that, The steps of providing a substrate having device isolation structures and trenches include: An isolation structure for the device is formed in the substrate to define an active region; A stress isolation layer is deposited on the substrate and the device isolation structure, and the top surface of the stress isolation layer is planarized, with the remaining stress isolation layer at least burying the top of the active region. Deposit the first stress layer; The first stress layer and the stress isolation layer on the boundary apex corner of the active region and the adjacent device isolation structure are etched to form an opening; The active region with a portion of its thickness in the opening and the boundary corner of the device isolation structure are etched away to reduce the top height of the active region and thus form the trench. Alternatively, the active region in the opening is first thermally oxidized to form a sacrificial oxide layer, the sacrificial oxide layer is then removed by wet processing, and the device isolation structure is side-cut to reduce the top height of the active region and remove the boundary corner of the device isolation structure, thus forming the trench.

3. The manufacturing method as described in claim 2, characterized in that, The thickness of the second stress layer is less than or equal to 1 / 2 of the thickness of the first stress layer.

4. The manufacturing method as described in claim 2, characterized in that, The bottom of the trench at the boundary of the device isolation structure is lower than the top surface of the active region in the trench to form a side trench; the bottom end of the side wall abuts against the bottom surface of the side trench or is spaced apart from the bottom surface of the side trench.

5. The manufacturing method as described in claim 2, characterized in that, It also includes at least one of the following parameters: (1) The materials of the device isolation structure and the stress isolation layer include an oxide layer; (2) The first stress layer includes a nitrided layer and / or an oxide layer; (3) The second stress layer includes a nitrided layer and / or a nitrogen oxide layer; (4) The longitudinal depth of the trench above the active region is (5) The impurity elements include silicon and / or germanium; (6) The device isolation structure is a shallow trench isolation structure, and the top of the shallow trench isolation structure is generally higher than the top of the active region before the trench is formed; (7) The deposition thickness of the first stress layer is (8) The annealing includes spike annealing and / or laser annealing.

6. The manufacturing method as described in claim 1, characterized in that, The steps for forming the sidewall are as follows: First, the second stress layer is etched using a dry etching process to remove the second stress layer on the top surface of the first stress layer and on the top surface of the active area in the trench; The remaining second stress layer is then wet-etched to expose the apex surface of the active region, and the remaining second stress layer on the top sidewall of the device isolation structure forms the sidewall.

7. The manufacturing method as described in claim 1, characterized in that, By means of ion implantation or diffusion doping, appropriate impurity elements are incorporated into the top of the active region exposed by the trench and / or the top sidewall of the device isolation structure.

8. The manufacturing method as described in claim 7, characterized in that, The top of the active region exposed by the trench and the top sidewall of the device isolation structure are implanted with ions containing the impurity elements by tilted ion implantation process, and the corresponding impurity elements are incorporated into the top of the active region exposed by the trench and the top sidewall of the device isolation structure.

9. The manufacturing method according to any one of claims 1-8, characterized in that, After incorporating the impurity element and before thermally oxidizing the top of the active region in the trench, the method further includes: performing surface oxidation on the top of the active region in the trench to round the corners of the active region and form an oxide film; wherein, during the formation of the gate oxide layer, the corners of the active region remain rounded under the constraint of the oxide film.

10. The manufacturing method as described in claim 9, characterized in that, The surface of the active region in the trench is purged with oxygen at 60°C to 80°C to form an oxide film.

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