Semiconductor device and forming method thereof

Abstract

The invention relates to a semiconductor device and a forming method thereof. Source / drain contacts of the nanostructured transistor are formed such that the source / drain contacts are recessed within an underlying source / drain region of the nanostructured transistor using a multi-step etch process. Recessing the source / drain contact within the source / drain region provides a greater amount of surface area for the source / drain contact to contact the source / drain region. This provides an increased contact surface area between the source / drain contact and the source / drain region, and due to a less limited current flow path between the source / drain region and the source / drain contact, the increased contact surface area provides a reduced contact resistance between the source / drain region and the source / drain contact. In this manner, a reduced contact resistance between the source / drain region and the source / drain contact enables greater power efficiency for nanostructured transistors.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor devices and methods of forming the same. BACKGROUND

[0002] As semiconductor device fabrication advances and technology process node sizes decrease, transistors can be affected by short channel effects (SCEs) such as hot carrier degradation, barrier lowering, and quantum confinement. Additionally, for smaller technology nodes, as the gate length of a transistor decreases, source / drain (S / D) electron tunneling increases, which increases the off-state current of the transistor (current that flows through the channel of the transistor when the transistor is in an off configuration). Silicon (Si) / silicon germanium (SiGe) nanoscale transistors (e.g., nanowires, nanosheets, and gate-all-around (GAA) devices) are potential candidates to overcome short channel effects at smaller technology nodes. Relative to other types of transistors, nanoscale transistors are effective structures that can experience reduced SCEs and enhanced carrier mobility. SUMMARY

[0003] According to one embodiment of the present disclosure, a method of forming a semiconductor device is provided, comprising: forming a plurality of nanoscale channels arranged in a direction substantially perpendicular to a substrate of the semiconductor device; forming source / drain regions adjacent to the plurality of nanoscale channels; forming a dielectric layer over the source / drain regions; forming a gate structure that wraps at least three sides of the plurality of nanoscale channels; forming a recess through the dielectric layer and into the source / drain regions such that a bottom of the recess is at a depth in the semiconductor device that is lower than a topmost nanoscale channel of the plurality of nanoscale channels and substantially equal to or lower than a top surface of a second nanoscale channel of the plurality of nanoscale channels, wherein the second nanoscale channel is below the topmost nanoscale channel; and forming a source / drain contact in the recess such that the source / drain contact extends into the source / drain regions.

[0004] According to one embodiment of the present disclosure, a method of forming a semiconductor device is provided, comprising: forming a plurality of nanostructure channels, the plurality of nanostructure channels arranged in a direction substantially perpendicular to a substrate of the semiconductor device; forming a source / drain region adjacent to the plurality of nanostructure channels; forming a dielectric layer over the source / drain region; forming a gate structure wrapping at least three sides of the plurality of nanostructure channels; performing a first etch operation to form a recess through the dielectric layer and into the source / drain region, such that a bottom of the recess is at a first depth in the recess; performing a second etch operation to increase the recess from the first depth to a second depth, the second depth being below a topmost nanostructure channel of the plurality of nanostructure channels; and forming a source / drain contact in the recess, such that the source / drain contact extends into the source / drain region.

[0005] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a plurality of nanostructure channels arranged in a first direction in the semiconductor device; a gate structure over and wrapping the plurality of nanostructure channels; a source / drain region adjacent to sides of the gate structure and adjacent to ends of the plurality of nanostructure channels in a second direction substantially perpendicular to the first direction; a contact etch stop layer (CESL) extending along sidewalls of the gate structure and a top surface of the source / drain region; an interlayer dielectric (ILD) layer over the CESL; a plurality of internal spacers between the source / drain region and the gate structure; and a source / drain contact extending through the ILD layer, through the CESL, and into the source / drain region to a depth below a topmost internal spacer of the plurality of internal spacers. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the disclosure, can be best understood from the following detailed description when read with the accompanying drawings, in which: It should be noted that the various features are not necessarily drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of discussion. Skilled artisans appreciate that other process steps can be used and that the order of the steps can be changed.

[0007] Figures 1A-1C is an illustration of an example implementation of the fin definition process described herein.

[0008] Figure 2 is an illustration of an example dummy gate structure formation process described herein.

[0009] Figure 3 is an illustration of an example implementation of the source / drain recess formation process described herein.

[0010] Figure 4A andFigure 4B is a pictorial illustration of an example implementation of the interlevel spacer formation process described herein.

[0011] Figure 5A and Figure 5B is a pictorial illustration of an example implementation of the source / drain region formation process described herein.

[0012] Figure 6 is a pictorial illustration of an example implementation of the interlevel dielectric formation process described herein.

[0013] Figure 7A and Figure 7B is a pictorial illustration of an example implementation of the replacement gate process described herein.

[0014] Figures 8A-8G is a pictorial illustration of an example implementation of the source / drain contact formation process described herein.

[0015] Figure 9 is a pictorial illustration of an example implementation of the semiconductor device described herein.

[0016] Figure 10 is a pictorial illustration of an example implementation of the semiconductor device described herein.

[0017] Figure 11 is a pictorial illustration of an example implementation of the semiconductor device described herein.

[0018] Figure 12 is a flow diagram of an example process associated with forming the semiconductor device described herein.

[0019] Figure 13 is a flow diagram of an example process associated with forming the semiconductor device described herein. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. For simplicity, in the following description, a particular example is described in terms that would probably be practiced by an artisan. Nevertheless, it is contemplated that the word "example" would serve as a transition word in this patent document enabling this patent to scope up to its full breadth, including its alternative embodiments and / or configurations. For example, in the following description, forming a first feature over or on a second feature can include embodiments in which the first feature and the second feature are formed in direct contact, and can also include embodiments in which additional features can be formed between the first feature and the second feature such that the first feature and the second feature can not be in direct contact. Moreover, the present disclosure can repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0021] Furthermore, spatially relative terms (e.g., "beneath," "below," "lower," "above," "upper," and the like) can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0022] Nanowire transistors, nanosheet transistors, GAA transistors, multi-bridge channel transistors, nanoribbon transistors, and / or other types of nanowire transistors can overcome one or more of the above-mentioned drawbacks of some types of transistors. However, nanowire transistors face manufacturing challenges that can lead to performance issues, manufacturing yield issues, and / or device failures.

[0023] For example, as feature sizes are reduced, various portions of nanowire transistors can be susceptible to increased resistance. One such portion of a nanowire transistor that can be susceptible to increased resistance is the connection between a source / drain region of the nanowire transistor and a source / drain contact formed on the source / drain region. As the size (e.g., lateral width) of the source / drain region and the source / drain contact are reduced, the contact surface area between the source / drain region and the source / drain contact is reduced. The reduced contact surface area between the source / drain region and the source / drain contact limits the flow of electrons between the source / drain region and the source / drain contact, which increases current crowding around the source / drain region and the source / drain contact. The increased current crowding leads to increased contact resistance between the source / drain region and the source / drain contact. This can lead to reduced power efficiency of the nanowire transistor and / or reduced switching speed of the nanowire transistor, among other things.

[0024] In some implementations described herein, a source / drain contact of a nanowire transistor is formed such that the source / drain contact is recessed within an underlying source / drain region of the nanowire transistor. A multi-step etching process can be performed to form a recess in the source / drain region such that the recess extends at least below a topmost nanowire channel of the nanowire transistor. In some implementations, the recess can be formed in the source / drain region such that the recess extends below intermediate nanowire channels and / or to the depth of a bottommost nanowire channel of the nanowire transistor.

[0025] The increased depth of the recesses (e.g., relative to performing a single etching operation to form the recesses to the depth of the first nanowire channel) provides a greater amount of surface area for the source / drain contacts (e.g., formed in the recesses) to contact the source / drain regions. This provides an increased contact surface area between the source / drain contacts and the source / drain regions, and the increased contact surface area provides a reduced contact resistance between the source / drain regions and the source / drain contacts due to a less restricted current flow path between the source / drain regions and the source / drain contacts. In this way, the reduced contact resistance between the source / drain regions and the source / drain contacts enables greater power efficiency to be achieved for the nanowire transistors, and / or enables increased switching speed to be achieved for the nanowire transistors, among other things.

[0026] Figures 1A-1C is an illustration of an example implementation 100 of the fin defining process described herein. The example implementation 100 includes an example of forming a fin structure and associated shallow trench isolation (STI) regions of a semiconductor device 105 described herein. The semiconductor device 105 can be fabricated to include one or more transistors. The one or more transistors can include nanowire transistor(s), such as nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge-channel transistors, nanoribbon transistors, and / or other types of nanowire transistors. The example implementation 100 includes an example of forming a fin structure and associated STI regions of a transistor of the semiconductor device 105.

[0027] Figures 1A-1C perspective view and a cross-sectional view along line A-A in the perspective view of the semiconductor device 105 are shown. As shown, processing of the semiconductor device 105 is performed in conjunction with a semiconductor substrate 110. The semiconductor substrate 110 includes a silicon (Si) substrate, a substrate formed of a material including silicon, a Group III-V compound semiconductor material (e.g., gallium arsenide (GaAs)) substrate, a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or another type of semiconductor substrate. Figure 1A

[0028] A layer stack 115 is formed on the semiconductor substrate 110. The layer stack 115 can be referred to as a superlattice. The layer stack 115 includes a plurality of alternating layers arranged in a direction substantially perpendicular to the semiconductor substrate 110 (e.g., a z-direction). For example, the layer stack 115 includes vertically alternating layers of a sacrificial nanowire layer 120 and a nanowire channel layer 125 above the semiconductor substrate 110. Figure 1A ​The number of sacrificial nanostructure layers 120 and the number of nanostructure channel layers 125 shown is an example, and other numbers of sacrificial nanostructure layers 120 and nanostructure channel layers 125 are within the scope of the present disclosure.

[0029] The sacrificial nanostructure layers 120 enable a vertical distance to be defined between adjacent nanostructure channels formed from the nanostructure channel layers 125, and serve as a placeholder layer for subsequently formed gate structures of transistors of the semiconductor device 105 formed around the nanostructure channels. The sacrificial nanostructure layers 120 include a first material composition, and the nanostructure channel layers 125 include a second material composition. In some implementations, the first material composition and the second material composition are the same material composition. In some implementations, the first material composition and the second material composition are different material compositions. As an example, the sacrificial nanostructure layers 120 can include silicon germanium (SiGe), and the nanostructure channel layers 125 can include silicon (Si). This enables the sacrificial nanostructure layers 120 and / or the nanostructure channel layers 125 to be selectively etched depending on the type of etchant used (e.g., such that the sacrificial nanostructure layers 120 can be etched while the nanostructure channel layers 125 are not etched, such that the nanostructure channel layers 125 can be etched while the sacrificial nanostructure layers 120 are not etched).

[0030] One or more types of deposition tools can be used to deposit and / or grow the alternating layers of the layer stack 115 on the semiconductor substrate 110 to include nanostructures (e.g., nanosheets). For example, the sacrificial nanostructure layers 120 and / or the nanostructure channel layers 125 can be grown using a deposition tool by epitaxial growth, which can include an epitaxial technique such as molecular beam epitaxy (MBE), a metal-organic chemical vapor deposition (MOCVD) process, and / or another suitable epitaxial technique. Additionally and / or alternatively, the sacrificial nanostructure layers 120 and / or the nanostructure channel layers 125 can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or another suitable deposition technique.

[0031] One or more mask layers can be formed (e.g., using one or more deposition tools) on the layer stack 115. The mask layer(s) can include a hard mask (HM) layer 130, a cap layer 135, an oxide layer 140, and / or a nitride layer 145. The mask layer(s) can be used to perform a fin patterning operation to form fin structures in the semiconductor substrate 110.

[0032] As Figure 1BAs shown, the layer stack 115 and the semiconductor substrate 110 are etched to remove portions of the layer stack 115 and the semiconductor substrate 110. This results in the formation of a fin structure 150 extending over the semiconductor substrate 110. The fin structure 150 may extend in the y-direction within the semiconductor device 105 and may be arranged in the x-direction within the semiconductor device 105. The fin structure 150 includes portions 155 of the layer stack 115 above and / or on the fin portions 160 above the semiconductor substrate 110. The fin structure 150 can be formed by patterning one or more mask layers and etching the semiconductor substrate 110 based on the pattern formed in one or more mask layers. One or more mask layers can be patterned using photolithography techniques, including dual-patterning or multi-patterning techniques. The semiconductor substrate 110 can be etched based on the pattern using an etching tool employing dry etching techniques (e.g., reactive ion etching), wet etching techniques, and / or combinations thereof.

[0033] like Figure 1B As further shown, some fin structures 150 can be formed with different widths for different types of nanostructure transistors. As an example, a first subgroup fin structure 150a can be formed for a p-type nanostructure transistor (e.g., a p-type metal-oxide-semiconductor (PMOS) nanostructure transistor), and a second subgroup fin structure 150b can be formed for an n-type nanostructure transistor (e.g., an n-type metal-oxide-semiconductor (NMOS) nanostructure transistor). As another example, the first subgroup fin structure 150a can be formed for a nanostructure transistor configured to operate at a lower voltage, and the second subgroup fin structure 150b can be formed for a nanostructure transistor configured to operate at a higher voltage.

[0034] like Figure 1C As shown, a liner 165 and an STI region 170 are formed between adjacent fin portions 160 of the fin structure 150. The liner 165 and the STI region 170 may each comprise a dielectric material, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), fluorine-doped silicate glass (FSG), low-k dielectric materials and / or another suitable insulating material.

[0035] The liner can be deposited conformally using a deposition tool (e.g., using ALD or other conformal deposition techniques), and a dielectric layer can be deposited on the liner 165 (e.g., using CVD, PVD, ALD, and / or other suitable deposition techniques) such that the dielectric layer completely fills the spaces between the fin structures 150 and extends over the top of the fin structures 150. A planarization or polishing operation (e.g., a chemical mechanical planarization (CMP) operation) can then be performed using a planarization tool to planarize the dielectric layer such that the top surface of the dielectric layer is approximately coplanar with the top of the nitride layer 145. The nitride layer 145 serves as a CMP stop layer in the planarization operation. The dielectric layer can then be etched using an etching tool to form the STI region 170 such that the top surface of the STI region 170 is approximately coplanar with or below the bottommost sacrificial nanostmcture layer 120.

[0036] As indicated above, Figures 1A-1C are provided by way of example. Other examples can differ Figures 1A-1C from the examples described.

[0037] Figure 2 is an illustration of an example implementation 200 of the dummy gate formation process described herein. The example implementation 200 includes an example of forming a dummy gate structure 205 of a nanostmcture transistor of a semiconductor device 105. In some implementations, the operations described in connection with the example implementation 700 are performed after the processes described in connection with the example implementation 600. Figures 1A-1C

[0038] Figure 2 A perspective view of the semiconductor device 105 on which the dummy gate structure 205 is formed is shown. The dummy gate structure 205 (also referred to as a dummy gate stack or a temporary gate structure) is formed over portions of the fin structures 150 and portions of the STI region 170. The dummy gate structure 205 extends in the x-direction and is arranged in the y-direction such that the dummy gate structure 205 is approximately perpendicular to the fin structures 150. The dummy gate structure 205 is a sacrificial structure that will be replaced by a replacement gate structure or a replacement gate stack at a later process stage of the semiconductor device 105. The dummy gate structure 205 can also be used to define a source / drain (S / D) recess in which source / drain regions of the nanostmcture transistor are formed in the fin structures 150.

[0039] ​Dummy gate structure 205 can include gate electrode layer 210, hard mask layer 215 over and / or on gate electrode layer 210, spacer layer 220 on opposite sides of gate electrode layer 210, and gate dielectric layer 225 under gate electrode layer 210. Gate electrode layer 210 includes polysilicon (PO) or other material. Hard mask layer 215 includes one or more layers, such as an oxide layer (e.g., a liner oxide layer, which can include silicon dioxide (Si02) or another material) and a nitride layer (e.g., a liner nitride layer, which can include silicon nitride (e.g., Si3N4) or another material) formed over the oxide layer. Spacer layer 220 includes silicon oxycarbide (SiOC), nitrogen-free SiOC, or other suitable material. Gate dielectric layer 225 can include silicon oxide (e.g., SiO2such as SiO2), silicon nitride (e.g., Si3N4such as Si3N4), high dielectric constant (high-k) dielectric material (e.g., a dielectric material having a dielectric constant greater than about 3.9), and / or another suitable material. x x y

[0040] Various semiconductor processing techniques (e.g., depositing layers of dummy gate structure 205, patterning layers of dummy gate structure 205 to define dummy gate structure 205, and / or other semiconductor processing techniques) can be used to form the layers of dummy gate structure 205.

[0041] Figure 2 Reference cross-sections used in subsequent figures described herein are also shown. Cross-section A-A is in the x-z plane (referred to as a y-cut), across fin structure 150, in a source / drain region of semiconductor device 105. Cross-section B-B is in the y-z plane (referred to as an x-cut), perpendicular to cross-section A-A, and across dummy gate structure 205 and along the underlying fin structure 150. Cross-section C-C is in the x-z plane, parallel to cross-section A-A and perpendicular to cross-section B-B, and along dummy gate structure 205. For clarity, subsequent figures refer to these reference cross-sections. In some figures, some reference numbers for components or features shown therein can be omitted to avoid obscuring other components or features, for ease of depicting the figures.

[0042] As indicated above, Figure 2 are provided by way of example. Other examples can differ from those described. Figure 2 without departing from the scope of the disclosure.

[0043] Figure 3 ​​​This is an illustration of an example implementation 300 of the source / drain recess formation process described herein. Example implementation 300 includes an example of forming a source / drain recess 305 for a nanostructured transistor for a semiconductor device 105. Figure 2 The multiple perspectives shown include Figure 2 The perspective of the cross-sectional plane AA in the middle Figure 2 The viewpoint of the cross-sectional plane BB in the middle, and Figure 2 (From the perspective of the cross-sectional plane CC) shown Figure 3 In some implementations, in combination Figures 1A-2 The described process is followed by the operation described in conjunction with example implementation 300.

[0044] like Figure 3 As shown in cross-sectional planes AA and BB, a source / drain recess 305 is formed through a portion 155 of the fin structure 150 during the etching operation. The source / drain recess 305 is formed on opposite sides of the dummy gate structure 205. The etching operation can be performed using an etching tool and can be referred to as a strained source / drain (SSD) etching operation. In some implementations, the etching operation includes the use of plasma etching techniques, wet chemical etching techniques, and / or another type of etching technique.

[0045] The source / drain recesses 305 also extend into a portion of the fin portion 160 of the fin structure 150. This results in the formation of a mesa region 310 in the fin structure 150. The sidewall of each source / drain recess 305 below the portion of the layer stack 155 corresponds to the sidewall of the mesa region 310. The mesa region 310 (also referred to as the base) refers to the region of the fin portion 160 of the fin structure 150 in which a nanostructured channel is defined from the nanostructured channel layer 125. The nanostructured channel 315 extends between adjacent source / drain recesses 305 and is located below the dummy gate structure 205 and between adjacent source / drain recesses 305.

[0046] The nanostructured channel 315 includes a silicon-based nanostructure (e.g., nanosheets or nanowires) that serves as the semiconductor channel for the nanostructured transistor of the semiconductor device 105. In some implementations, the nanostructured channel 315 may include silicon-germanium (SiGe) or another silicon-based material. The nanostructured channel 315 is arranged in a direction generally perpendicular to the semiconductor substrate 110 (e.g., the z-direction). In other words, the nanostructured channel 315 is arranged vertically or stacked above the semiconductor substrate 110.

[0047] As pointed out above, Figure 3 Provided as an example. Other examples may be provided in relation to... Figure 3 The descriptions are different.

[0048] Figure 4A and Figure 4B is an illustration of an example implementation 400 of the internal spacer formation process described herein. The example implementation 400 includes an example of forming an internal spacer between the ends of the nanostructure channels 315 exposed in the source / drain recesses 305. From Figure 2 the multiple perspectives shown (including Figure 2 the perspective of cross-sectional plane A-A in Figure 2 the perspective of cross-sectional plane B-B in Figure 2 the perspective of cross-sectional plane C-C in Figure 4A and Figure 4B In some implementations, the operations described in connection with the example implementation 400 are performed after the process described in connection with Figures 1A-3 In some implementations, the operations described in connection with the example implementation 400 are performed after the process described in connection with

[0049] As shown in cross-section A-A and cross-section B-B in Figure 4A the ends of the sacrificial nanostructure layer 120 can be etched laterally (e.g., in an x-direction generally parallel to the length of the sacrificial nanostructure layer 120) in an etching operation, thereby forming cavities 405 between the ends of the nanostructure channels 315 exposed in the source / drain recesses 305. The wet etching operation can be performed using an etching tool to selectively etch the ends of the sacrificial nanostructure layer 120 relative to the nanostructure channels 315, thereby forming the cavities 405. Additionally and / or alternatively, another etching technique, such as dry etching (e.g., gas-based etching), can be used.

[0050] As shown in cross-section plane A-A and cross-section plane B-B in Figure 4B internal spacers (InSPs) 410 are formed in the cavities 405 in the ends of the sacrificial nanostructure layer 120 exposed in the source / drain recesses 305. The internal spacers 405 can be included to reduce parasitic capacitance in the nanostructure transistors and to prevent the source / drain regions (subsequently formed in the source / drain recesses 305) from being etched in a nanosheet release operation to remove the sacrificial nanostructure layer 120 between the nanostructure channels 315. The internal spacers 410 include silicon nitride (Si x N y ), silicon oxide (SiO x ), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and / or another dielectric material.

[0051] To form the interior spacers 410, a deposition tool can be used to deposit a layer of dielectric material in the cavities 405 and along the sidewalls and bottom surfaces of the source / drain recesses 305. The layer of dielectric material can be deposited using a CVD technique, a PVD technique, and an ALD technique, and / or another deposition technique. Subsequently, an etching tool is used to remove excess material of the layer of dielectric material from the source / drain recesses such that the remaining portions correspond to the interior spacers 410. Alternatively, a precursor that selectively bonds to the material of the sacrificial nanomesh layer 120 without bonding to the material of the fin portions 160 and the nanomesh channels 315 can be used to selectively form the interior spacers 410 on the ends of the sacrificial nanomesh layer 120.

[0052] As indicated above, Figure 4A and Figure 4B are provided by way of example. Other examples can differ Figure 4A and Figure 4B described with respect to

[0053] Figure 5A and Figure 5B is an illustration of an example implementation 500 of the source / drain region formation process described herein. The example implementation 500 includes an example of forming source / drain regions of a nanomesh transistor of a semiconductor device 105. From Figure 2 multiple perspectives, including a perspective of a cross-sectional plane A-A in Figure 2 a perspective of a cross-sectional plane B-B in Figure 2 a perspective of a cross-sectional plane C-C in Figure 2 are shown in Figure 5A and Figure 5B In some implementations, the operations described in connection with the example implementation 500 are performed after the processes described in connection with Figures 1A-4B

[0054] As indicated above, Figure 5A cross-section A-A and cross-section B-B in

[0055] As indicated above, Figure 5B ​The source / drain recesses 305 can be filled with one or more layers to form source / drain regions 510 in the source / drain recesses 305, as shown in cross-sectional plane A-A and cross-sectional plane B-B. For example, a deposition tool can be used to deposit a first epitaxial layer 515 (sometimes referred to as “LI”) at the bottom of the source / drain recesses 305 and on the recessed end of the nanostructure channel 315 in the cavity 505. As another example, the deposition tool can deposit a second epitaxial layer 520 (sometimes referred to as “L2”) in the source / drain recesses 305. The second epitaxial layer 520 can fill the remaining area in the source / drain recesses 305 under the dummy gate structure 205 and can be in contact with the first epitaxial layer 515 and the inner spacers 410 that are still exposed in the source / drain recesses 305.

[0056] A “source / drain region” can refer to either a source or a drain, individually or collectively, depending on the context. The source / drain regions 510 can be included on opposite sides of the dummy gate structure 205, such that the nanostructure channel 315 under the dummy gate structure 205 extends between and is electrically coupled to the source / drain regions 510.

[0057] The first epitaxial layer 515 and the second epitaxial layer 520 of the source / drain regions 510 can each include a semiconductor material, such as silicon (Si), silicon germanium (SiGe), silicon arsenide (SiAs), silicon phosphorus (SiP), and / or another semiconductor material. The first epitaxial layer 515 and the second epitaxial layer 520 can each be doped with one or more types of dopants, such as arsenic (As), phosphorus (P), and / or boron (B), among others.

[0058] For a p-type metal-oxide-semiconductor (PMOS) nanostructure transistor, the first epitaxial layer 515 and the second epitaxial layer 520 of the source / drain regions 510 can each include silicon germanium (SiGe) doped with boron (B). The germanium (Ge) concentration of the second epitaxial layer 520 can be greater than the germanium (Ge) concentration of the first epitaxial layer 515. For example, the germanium (Ge) concentration of the second epitaxial layer 520 can be included in a range of about 40% to about 60%, while the germanium (Ge) concentration of the first epitaxial layer 515 can be included in a range of about 10% to about 20%. However, other values and ranges are within the scope of the present disclosure. The boron (B) dopant concentration of the second epitaxial layer 520 and the boron (B) dopant concentration of the first epitaxial layer 515 can each be included in a range of about 5 x 1019cm-3to about 5 x 1020cm-3. However, other values and ranges are within the scope of the present disclosure. 20 21 However, other values and ranges are within the scope of the present disclosure.

[0059] ​For n-type metal-oxide-semiconductor (NMOS) nanostructure transistors, the first epitaxial layer 515 and the second epitaxial layer 520 of the source / drain region 510 can each include silicon (Si) doped with arsenic (As) and / or phosphorus (P), or the like. The dopant concentration of the second epitaxial layer 520 can be greater than the dopant concentration of the first epitaxial layer 515. For example, the dopant concentration of the second epitaxial layer 520 can be included in a range from about 2 x 1019atoms / cm3to about 9 x 1019atoms / cm3, while the dopant concentration of the first epitaxial layer 515 can be included in a range from about 1 x 1019atoms / cm3to about 1 x 1020atoms / cm3. However, other values and ranges are within the scope of the present disclosure. 21 21 20 21 However, other values and ranges are within the scope of the present disclosure.

[0060] The first epitaxial layer 515 and the second epitaxial layer 520 of the source / drain region 510 can each be epitaxially grown, deposited (e.g., using CVD, PVD, ALD), and / or formed using one or more other deposition techniques. For example, a deposition tool can epitaxially grow a merged region 525 of the first epitaxial layer 515 at the bottom of the source / drain recess 305. The merged region 525 can include a continuous layer of epitaxially grown material that spans upward from the mesa region 310 to the end of the bottommost nanostructure channel 315.

[0061] As another example, a deposition tool can epitaxially grow a plurality of non- contiguous second epitaxial regions 530 of the first epitaxial layer 515 on the recessed end of the nanostructure channel 315 in the cavity 505 such that the non-contiguous second epitaxial regions 530 are located above the merged region 525. The non-contiguous second epitaxial regions 530 are regions of epitaxially grown material that do not contact each other (e.g., due to being separated by the internal spacers 410) and do not contact the merged region 525. The second epitaxial layer 520 can grow on portions of the internal spacers 410 that are exposed between the non-contiguous second epitaxial regions 530 and between the merged region 525 and the non-contiguous second epitaxial regions 530.

[0062] As indicated above, Figure 5A and Figure 5B are provided by way of example. Other examples can differ from those described with respect to Figure 5A and Figure 5B without departing from the scope of the present disclosure.

[0063] Figure 6 is a depiction of an example implementation 600 of an interlayer dielectric (ILD) formation process described herein. The depiction is from a plurality of perspectives, including a perspective of a cross-sectional plane A-A in Figure 2 , Figure 2 a perspective of a cross-sectional plane B-B in Figure 2 , and Figure 2 ​​​shown in FIG. 6B (e.g., from the perspective of cross-sectional plane C-C in FIG. 6B). Figure 6 In some implementations, the operations described in conjunction with Figures 1A-5B The operations described in conjunction with example implementation 600 are performed after the processes described.

[0064] As shown in FIG. 6B (e.g., from the perspective of cross-sectional plane C-C in FIG. 6B). Figure 6 A dielectric layer 605 is formed over the source / drain regions 510, as shown in FIG. 6B (e.g., from the perspective of cross-sectional plane A-A and cross-sectional plane B-B in FIG. 6B). The dielectric layer 605, which can be referred to as an ILD layer, fills the areas between the dummy gate structures 205. The dielectric layer 605 is formed to reduce the likelihood of and / or prevent damage to the source / drain regions 510 during a replacement gate process to replace the dummy gate structures 205. The dielectric layer 605 can be referred to as an ILD zero (ILD0) layer or another ILD layer.

[0065] In some implementations, a contact etch stop layer (CESL) 610 is conformally deposited (e.g., by a deposition tool) over the source / drain regions 510 prior to forming the dielectric layer 605. The dielectric layer 605 is then formed over the CESL 610. The CESL 610 can provide a mechanism to stop an etch process when forming contacts or vias to the source / drain regions 510.

[0066] The dielectric layer 605 can include an oxide (e.g., silicon oxide (SiO x ) and / or another oxide material), undoped silicate glass (USG), borosilicate glass (BSG), fluorosilicate glass (FSG), tetraethyl orthosilicate (TEOS), hydrogen silsesquioxane (HSQ), and / or another suitable dielectric material. In some implementations, the dielectric layer 605 includes an extremely low-k (ELK) dielectric material having a dielectric constant less than about 2.5. Examples of ELK dielectric materials include: carbon-doped silicon oxide (C-SiO x ), amorphous carbon-fluoride (a-C x F y ), parylene, bisbenzocyclobutene (BCB), polytetrafluoroethylene (PTFE), silicon oxycarbide (SiOC) polymer, porous hydrogen silsesquioxane (HSQ), porous methyl silsesquioxane (MSQ), porous polyarylether (PAE), and / or porous silicon oxide (SiO x ) and the like. The dielectric layer 605 can be deposited using a deposition process such as ALD, CVD, or another deposition technique.

[0067] CESL 610 can be formed of a dielectric material having a different etch selectivity than an adjacent layer or component. CESL 610 can include or be a nitrogen-containing material, a silicon-containing material, and / or a carbon-containing material. Further, CESL 610 can include or be silicon nitride (Si x N y ), silicon carbon nitride (SiCN), carbon nitride (CN), silicon oxynitride (SiON), silicon oxycarbide (SiCO), or combinations thereof, among others. CESL 610 can be deposited using a deposition process such as ALD, CVD, or other deposition techniques.

[0068] As noted above, Figure 6 are provided by way of example. Other examples can differ Figure 6 from those described.

[0069] Figure 7A and Figure 7B is an illustration of an example implementation 700 of the replacement gate (RPG) process described herein. Example implementation 700 includes an example of a replacement gate process for replacing dummy gate structures 205 with high-k / metal gate structures (e.g., replacement gate structures) using nanowire transistors of semiconductor devices 105. From Figure 2 multiple perspectives, including a perspective of cross-sectional plane A-A in Figure 2 , a perspective of cross-sectional plane B-B in Figure 2 , and a perspective of cross-sectional plane C-C in Figure 2 , respectively, illustrate Figure 7A and Figure 7B In some implementations, the operations described in connection with example implementation 700 are performed after the operations described in connection with Figures 1A-6 .

[0070] As noted above, Figure 7A cross-sectional plane B-B and cross-sectional plane C-C in , the replacement gate process includes a dummy gate removal operation. The dummy gate removal operation includes removing dummy gate structures 205 from semiconductor devices 105. Removal of dummy gate structures 205 leaves an opening (or recess) in dielectric layer 605 and provides access to underlying sacrificial nanowire layer 120. Dummy gate structures 205 can be removed in one or more etching operations. Such etching operations can include plasma etching techniques, wet chemical etching techniques, and / or another type of etching technique.

[0071] As noted above, Figure 7AFurther shown, the replacement gate process includes a nanostructure release operation (e.g., a SiGe release operation). The nanostructure release operation is performed to remove the sacrificial nanostructure layer 120 (e.g., a silicon germanium layer). This results in openings 705 between the nanostructure channels 315 (e.g., regions around the nanostructure channels 315). The sacrificial nanostructure layer 120 can be removed through the space previously occupied by the dummy gate structure 205. The nanostructure release operation can include performing an etching operation using an etching tool to remove the sacrificial nanostructure layer 120 based on a difference in etching selectivity between the material of the sacrificial nanostructure layer 120 and the material of the nanostructure channels 315 and between the material of the sacrificial nanostructure layer 120 and the material of the inner spacers 410. The inner spacers 410 can act as an etch stop layer in the etching operation to prevent the source / drain regions 510 from being etched.

[0072] As shown in FIG. 6, the semiconductor device 105 includes one or more vertical stacks of alternating nanostructure channels 315 and partial gate structures 710. The semiconductor device 105 can be formed by performing a replacement gate process on the semiconductor device 105 of FIG. 5. Figure 7B As shown in FIG. 6, the semiconductor device 105 includes one or more vertical stacks of alternating nanostructure channels 315 and partial gate structures 710. The semiconductor device 105 can be formed by performing a replacement gate process on the semiconductor device 105 of FIG. 5. Figure 7B As shown in FIG. 6, the semiconductor device 105 includes one or more vertical stacks of alternating nanostructure channels 315 and partial gate structures 710. The semiconductor device 105 can be formed by performing a replacement gate process on the semiconductor device 105 of FIG. 5.

[0073] The gate structures 710 can each include a gate dielectric layer 715 and a metal gate electrode 720. The metal gate electrode 720 can include one or more metal materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), and / or titanium (Ti), among others. Additionally and / or alternatively, the gate structures 710 can each include one or more work function metal layers for tuning the work function of the metal gate electrode 720.

[0074] The gate dielectric layers 715 can be conformal high-k dielectric liners that are deposited onto the nanostructure channels 315 and onto the sidewalls of the interior spacers 410 prior to formation of the gate electrodes 720. The gate structures 710 can each include additional layers, such as an interface layer, an adhesion layer, and / or a cap layer, among others. The gate dielectric layers 715 can include one or more high-k dielectric materials, such as silicon nitride (Si x N y ), hafnium oxide (HfO x ), lanthanum oxide (LaO x ), and / or another suitable high-k dielectric material.

[0075] Some of the source / drain regions 510 and gate structures 710 can be shared between two or more nanoscale transistors of the semiconductor device 105. In these implementations, one or more source / drain regions 510 and gate structures 710 can be connected or coupled to multiple nanostructure channels 315, as shown by the example in Figure 7B This enables multiple nanostructure channels 315 to be controlled by a single gate structure 710 and a pair of source / drain regions 510.

[0076] As noted above, Figure 7A and Figure 7B are provided by way of example. Other examples can differ from those described with respect to Figure 7A and Figure 7B .

[0077] Figures 8A-8G is an illustration of an example implementation 800 of the source / drain contact formation process described herein. In particular, the example implementation 800 includes the example of forming a source / drain contact such that the source / drain contact is recessed within a source / drain region 510 of a nanostructure transistor of the semiconductor device 105 to achieve lower contact resistance and lower current crowding between the source / drain contact and the source / drain region 510. The Figure 2 are shown from the perspective of the cross-sectional plane B-B in Figures 8A-8G In some implementations, the operations described in connection with the example implementation 800 are performed after the operations described in connection with Figures 1A-7B .

[0078] As shown in Figure 8A , an etch stop layer (ESL) 805 can be formed over and / or on the dielectric layer 605, and over and / or on the top of the gate structure 710. Another dielectric layer 810 can be formed over and / or on the ESL 805.

[0079] The ESL 805 can include one or more dielectric materials, such as silicon nitride (Six N y Silicon carbonitride (SiCN), carbon nitride (CN), silicon oxynitride (SiON), silicon carbon oxide (SiCO), or combinations thereof. The dielectric layer 810 may be referred to as an ILD layer (e.g., an ILD1 layer) and may include one or more dielectric materials, such as oxides (e.g., silicon oxide (SiO2)). x (and / or another oxide material), undoped silicate glass (USG), borosilicate glass (BSG), fluorosilicate glass (FSG), tetraethyl orthosilicate (TEOS), silsesquioxane (HSQ), and / or another suitable dielectric material. In some implementations, dielectric layer 810 includes an ELK dielectric material.

[0080] ESL 805 and / or dielectric layer 810 can be deposited using deposition tools employing PVD, ALD, CVD, and / or other suitable deposition techniques. ESL 805 and / or dielectric layer 810 can be deposited in one or more deposition operations. In some implementations, after depositing ESL 805 and / or dielectric layer 810, a planarization tool can be used to perform a planarization operation (e.g., CMP operation) to planarize the ESL 805 and / or dielectric layer 810.

[0081] like Figure 8B As shown, a contact recess 815 is formed through dielectric layer 810, through ESL 805, through dielectric layer 605, through CESL 610, and into the source / drain region 510. A first etching operation using an etching tool is performed to form the contact recess 815 to a first depth relative to the top of the source / drain region 510 (in Figure 8B (denoted as dimension D1). The contact recess 815 may extend into the second epitaxial layer 520 of the source / drain region 510. After the first etching operation, the bottom of the contact recess 815 may be below the top nanostructure channel 315 (e.g., nanostructure channel 315a) and at least reach the depth of the first internal spacer layer 410 (e.g., internal spacer 410a). However, the contact recess 815 may be formed such that the bottom of the contact recess 815 is located at a different depth in the semiconductor device 105 after the first etching operation.

[0082] In some implementations, a pattern in a photoresist layer is used to form the contact recess 815. In these implementations, a photoresist layer can be formed on the dielectric layer 810 using a deposition tool (e.g., using spin coating and / or another suitable deposition technique). An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the dielectric layer 810, ESL 805, dielectric layer 605, and / or the second epitaxial layer 520 of the source / drain region 510 based on the pattern to form the contact recess 815. In some implementations, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or another type of etching operation. In some implementations, the remaining portion of the photoresist layer can be removed using photoresist removal tools (e.g., using chemical strippers, plasma ashing, and / or another technique). In some implementations, a hard mask layer is used as an alternative technique for pattern-based formation of the contact recess 815.

[0083] In some implementations, the first depth (dimension D1) of the contact recess 815 extending into the source / drain region 510 after the first etching operation can be included in the range of about 1 nanometer to about 9 nanometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0084] like Figure 8C As shown, a sidewall liner 820 may be formed on a portion of the sidewall of the contact recess 815 above the source / drain region 510. The sidewall liner 820 may be formed as a protective liner that prevents the sidewall of the contact recess 815 from being etched during a subsequent second etch operation to increase the depth of the contact recess 815 (and thus, widening the lateral width of the contact recess 815). Additionally and / or alternatively, the sidewall liner 820 may include a barrier liner included to reduce and / or prevent material from diffusing from the source / drain contacts (e.g., the source / drain contacts formed in the contact recess 815) into the surrounding dielectric layer.

[0085] The sidewall liner 820 may include one or more dielectric materials. For example, the sidewall liner 820 may include silicon nitride (Si). x N yThe material can be, for example, Si3N4, silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiOCN), and / or another suitable dielectric material. The material of the sidewall liner 820 can differ from the material of the source / drain region 510 (e.g., different from the semiconductor material of the second epitaxial layer 520) to provide etch selectivity between the sidewall liner 820 and the source / drain region 510. This allows the source / drain region 510 to be further etched in a second etch operation to increase the depth of the contact recess 815, with minimal or no consumption of the sidewall liner 820.

[0086] To form the sidewall liner 820, a conformal dielectric material layer can be deposited on the sidewalls of the contact recess 815 (e.g., corresponding to the exposed surfaces of dielectric layer 605, ESL 805, and dielectric layer 810) and on the bottom surface of the contact recess 815 (e.g., corresponding to the exposed surface of the second epitaxial layer 520 of the source / drain region 510). The conformal dielectric material layer can be deposited using deposition techniques (ALD and / or CVD, etc.) using deposition tools.

[0087] An etching tool can be used to trim the portion of the conformal dielectric material layer located on the bottom surface of the contact recess 815, thereby removing the conformal dielectric material layer from the surface of the second epitaxial layer 520 of the source / drain region 510. In this way, the surface of the second epitaxial layer 520 of the source / drain region 510 is exposed again through the contact recess 815, and the remaining portion of the conformal dielectric material layer on the sidewall of the contact recess 815 corresponds to the sidewall liner 820.

[0088] Anisotropic etching techniques can be used to trim the portion of the conformal dielectric material layer located on the bottom surface of the contact recess 815, such that the portion of the conformal dielectric material layer located on the sidewall of the contact recess 815 is retained as a sidewall liner 820. For example, plasma-based etching techniques (e.g., reactive ion etching (RIE)) can be used to perform predominantly vertical (e.g., z-direction) etching to trim the conformal dielectric material layer. However, other etching techniques are within the scope of this disclosure.

[0089] like Figure 8D As shown, a second etching operation is performed (e.g., in the bonding process). Figure 8B Following the first etching operation described, the depth of the contact recess 815 in the source / drain region 510 is increased from a first depth (dimension D1) to a second depth (in...). Figure 8D (This is represented by dimension D2). In this way, the contact recess 815 extends further / deeper into the second epitaxial layer 520 of the source / drain region 510 after the second etching operation than after the first etching operation. For example, in bondingFigure 8B After the first etching operation described, the contact recess 815 can extend to a depth of a topmost nanowire channel (e.g., nanowire channel 315a). After the second etching operation, a bottommost portion of the contact recess 815 can be below an intermediate nanowire channel 315 (e.g., nanowire channel 315c) and at least to a depth of a second layer inner spacer 410 (e.g., inner spacer 410b). However, the contact recess 815 can be formed such that the bottommost portion of the contact recess 815 is at a different depth in the semiconductor device 105 after the second etching operation.

[0090] In some implementations, the second depth is included in a range of about 10 nanometers to about 60 nanometers. However, other values and ranges are within the scope of the present disclosure. In some implementations, a ratio of the second depth to the first depth is included in a range of about 1.1 : 1 to about 60: 1. However, other values and ranges are within the scope of the present disclosure.

[0091] The second etching operation can differ from the first etching operation in that the first etching operation is performed using a first etchant and the second etching operation is performed using a second etchant that is different from the first etchant. For example, the first etching operation can be performed using a plasma-based etchant and the second etching operation can be performed using a gas-based etchant.

[0092] Different etchants can be used for the first etching operation and the second etching operation to achieve different etch selectivities for the first etching operation and the second etching operation. For example, the first etchant used in the first etching operation can be selected to achieve a low etch selectivity between a dielectric layer (e.g., dielectric layer 605, ESL 805, dielectric layer 810) above the source / drain region 510 and the semiconductor material of the source / drain region 510 (e.g., the semiconductor material of the second epitaxial layer 520). This enables the formation of the contact recess 815 in the first etching operation that passes through the dielectric layer 605, ESL 805, dielectric layer 810, and into the source / drain region 510.

[0093] For the second etching operation, the second etchant can be selected to achieve high etch selectivity between the dielectric layer (e.g., dielectric layer 605, ESL 805, dielectric layer 810, sidewall liner 820) above the source / drain region 510 and the semiconductor material of the source / drain region 510 (e.g., the semiconductor material of the second epitaxial layer 520). Specifically, a gas-based etchant (e.g., chlorine-containing gas) and / or another suitable gas-based etchant can be used in the second etching operation such that the etching rate of the second etchant against the semiconductor material of the source / drain region 510 is greater than the etching rate of the second etchant against the dielectric material of the sidewall of the contact recess 815 (e.g., the silicon nitride material of the sidewall liner 820). This allows the depth of the contact recess 815 in the source / drain region 510 to be increased while the etching of the dielectric material of the sidewalls of the contact recess 815 is minimal to no (and therefore the increase in the lateral width of the contact recess 815 is minimal to no).

[0094] like Figure 8E As shown, a metal silicide layer 825 is formed at the bottom of the contact recess 815. Specifically, the metal silicide layer 825 can be formed from the surface of the source / drain region 510 exposed in the contact recess 815 (e.g., the surface of the second epitaxial layer 520 of the source / drain region 510). To form the metal silicide layer 825, a salicidation process can be performed. The salicidation process involves depositing a metal material layer on the surface of the second epitaxial layer 520 of the source / drain region 510 exposed in the contact recess 815 using a deposition tool (e.g., by CVD, ALD, PVD, and / or electroplating). An annealing operation can be performed to increase the temperature of the metal material layer and the surface of the second epitaxial layer 520 of the source / drain region 510 exposed in the contact recess 815, so that the metal material diffuses into the surface of the second epitaxial layer 520 of the source / drain region 510 exposed in the contact recess 815. This allows the formation of the metal silicide layer 825. In other words, the surface of the second epitaxial layer 520 of the source / drain region 510 exposed in the contact recess 815 can be transformed from a semiconductor surface to a metal silicide surface.

[0095] In some implementations, the metal material layer includes titanium (Ti), and the metal silicide layer 825 includes titanium silicide (TiSi). In some implementations, the metal material layer includes ruthenium (Ru), and the metal silicide layer 825 includes ruthenium silicide (RuSi). In some implementations, the metal material layer includes cobalt (Co), and the metal silicide layer 825 includes cobalt silicide (CoSi).

[0096] The metal silicide layer 825 is formed to a thickness ranging from about 3.5 nanometers to about 7 nanometers. Figure 8E (This is represented as dimension D3). However, other values ​​and ranges are also within the scope of this disclosure.

[0097] like Figure 8F As shown, the remaining area in the contact recess 815 can be filled with the material of the source / drain contact 830, such that the source / drain contact 830 extends through the dielectric layer 810, through the etch stop layer 805, and through the dielectric layer 605. Furthermore, the bottom of the source / drain contact 830 is recessed within the source / drain region 510. In this way, the source / drain contact 830 and the metal silicide layer 825 extend into the source / drain region 510 to a depth corresponding to dimension D2. The sidewall liner 820 may be located between the source / drain contact 830 and the dielectric layer 605, between the source / drain contact 830 and the etch stop layer 805, and / or between the source / drain contact 830 and the dielectric layer 810.

[0098] The source / drain contact 830 may include contact plugs, vias, conductive blocks, conductive pillars, and / or another type of conductive structure extending in the z-direction within the semiconductor device 105. The source / drain contact 830 may include one or more conductive materials, such as tungsten (W), ruthenium (Ru), cobalt (Co), titanium (Ti), molybdenum (Mo), copper (Cu), and / or aluminum (Al).

[0099] Material for the source / drain contact 830 can be deposited in the contact recess 815 using deposition tools employing CVD, ALD, PVD, electroplating, and / or another suitable deposition technique. In some implementations, a seed layer is deposited in the contact recess 815, and material for the source / drain contact 830 is deposited on the seed layer.

[0100] In some implementations, the source / drain contact 830 includes a multilayer structure. For example, the source / drain contact 830 may include one or more liners deposited on the sidewalls and bottom surfaces of the contact recess 815, and a body filler layer formed on the one or more liners. The one or more liners may include different materials. For example, the first liner may include silicon nitride (Si). x N y The first liner may include silicon dioxide (SiO2) and the second liner may include silicon dioxide (SiO2) x The first liner may comprise a titanium nitride (TiN) liner, and the second liner may comprise a silicon oxynitride (SiON) liner. The body layer may comprise the conductive material of the source / drain contacts 830.

[0101] The increased depth of the recess of the source / drain contact 830 within the source / drain region 510 of the semiconductor device 105 reduces the contact resistance between the source / drain contact 830 and the source / drain region 510 due to the increased contact area. Because the source / drain contact 830 is recessed within the source / drain region 510, in addition to the bottom surface of the source / drain contact 830 contacting the source / drain region 510, a portion of the sidewall of the source / drain contact 830 also contacts the source / drain region 510, thus achieving an increased contact area.

[0102] Additionally and / or alternatively, the increased depth of the recess within the source / drain region 510 of the source / drain contact 830 in the semiconductor device 105 can reduce current congestion in the source / drain region 510, as the source / drain contact 830 extends alongside the topmost nanostructured channel (e.g., nanostructured channel 315a) and, in some implementations, alongside an intermediate nanostructured channel (e.g., nanostructured channel 315b). This provides a more direct lateral travel path for charge carriers across the source / drain region 510 between the source / drain contact 830 and the nanostructured channel 315 (e.g., conversely, if the source / drain contact 830 terminated at the top of the source / drain recess 510, charge carriers would have to travel vertically in addition to horizontally to reach the nanostructured channels 315a and 315b).

[0103] like Figure 8G As shown, a planarization tool can be used to perform a planarization operation (e.g., a CMP operation) to planarize the semiconductor device 105. During the planarization operation, excess material is removed from the source / drain contacts 830, and the dielectric layer 810 can also be removed. The planarization operation can be stopped once ESL 805 is reached.

[0104] In this way, the semiconductor device 105 can include multiple nanowire channels 315 arranged in a first direction (e.g., nanowire channels 315a-c arranged in the z-direction) in the semiconductor device 105. The semiconductor device 105 can include a gate structure 710 that wraps around the multiple nanowire channels 315. The semiconductor device 105 can include a source / drain region 510 that is adjacent (e.g., laterally adjacent) to a side of the gate structure 710 and laterally adjacent to ends of the multiple nanowire channels 315 in a second direction that is substantially perpendicular to the first direction (e.g., in the y-direction). The semiconductor device 105 can include multiple internal spacers 410 (e.g., internal spacers 410a-c arranged in the z-direction) between the source / drain region 510 and the gate structure 710. The semiconductor device 105 can include a source / drain contact 830 that extends into the source / drain region 510 (e.g., in the z-direction) to a depth (e.g., dimension D2) that is below a topmost internal spacer (e.g., internal spacer 410a) and below a topmost nanowire channel (e.g., nanowire channel 315a). A second epitaxial layer 520 of the source / drain region 510 can surround a sidewall of the source / drain contact 830, and a first epitaxial layer 515 of the source / drain region 515 is between the second epitaxial region 520 and the nanowire channel 315.

[0105] The source / drain contact 830 can extend into the source / drain region 510 to a depth of an intermediate nanowire channel (e.g., nanowire channel 315b). For example, the source / drain contact 830 can extend into the source / drain region 510 to a depth below a top surface of the intermediate nanowire channel. As another example, the source / drain contact 830 can extend into the source / drain region 510 to a depth that is below or substantially equal to a bottom surface of the intermediate nanowire channel. The semiconductor device 105 can include a metal silicide layer 825 between the source / drain contact 830 and the source / drain region 510, and the metal silicide layer 825 can extend from a top of the source / drain region 510 to a bottom of the source / drain contact 830.

[0106] The source / drain contact 830 can electrically connect the source / drain region 510 to an interconnect layer (e.g., a back end region or a back end of line (BEOL) region) of the semiconductor device 105. This enables routing of electrical signals and / or power between one or more conductive structures (not shown) in the interconnect layer and the source / drain region 510 through the source / drain contact 830.

[0107] As Figure 8G As further shown, a lateral width (in the x-direction) of the source / drain contact 830 can be substantially equal to a lateral width of the source / drain region 510. For example, the source / drain contact 830 can be substantially laterally aligned with the source / drain region 510. As another example, the source / drain contact 830 can be laterally offset from the source / drain region 510. As a further example, the source / drain contact 830 can be laterally offset from the source / drain region 510 by a distance that is less than a lateral width of the source / drain region 510. Figure 8GThe lateral distance between the metal silicide layer 825 and the gate structure 710 laterally adjacent to the source / drain contact 830 (in the direction of the arrow 840) is denoted as dimension D5) and is included in a range of about 10 nanometers to about 30 nanometers. However, other values and ranges are within the scope of the present disclosure. The angle between segments of the metal silicide layer 825 on the sidewall of the source / drain contact 830 (in the direction of the arrow 850) is denoted as dimension D6) and is included in a range of about 2 nanometers to about 20 nanometers. However, other values and ranges are within the scope of the present disclosure. Figure 8G The lateral distance between the metal silicide layer 825 and the gate structure 710 laterally adjacent to the source / drain contact 830 (in the direction of the arrow 840) is denoted as dimension D5) and is included in a range of about 10 nanometers to about 30 nanometers. However, other values and ranges are within the scope of the present disclosure. The angle between segments of the metal silicide layer 825 on the sidewall of the source / drain contact 830 (in the direction of the arrow 850) is denoted as dimension D6) and is included in a range of about 2 nanometers to about 20 nanometers. However, other values and ranges are within the scope of the present disclosure. Figure 8G The lateral distance between the metal silicide layer 825 and the gate structure 710 laterally adjacent to the source / drain contact 830 (in the direction of the arrow 840) is denoted as dimension D5) and is included in a range of about 10 nanometers to about 30 nanometers. However, other values and ranges are within the scope of the present disclosure. The angle between segments of the metal silicide layer 825 on the sidewall of the source / drain contact 830 (in the direction of the arrow 850) is denoted as dimension D6) and is included in a range of about 2 nanometers to about 20 nanometers. However, other values and ranges are within the scope of the present disclosure.

[0108] As indicated above, Figures 8A-8G are provided by way of example. Other examples can differ Figures 8A-8G differently from what is described.

[0109] Figure 9 is an illustration of an example implementation 900 of the semiconductor device 105 described herein. The example implementation 900 of the semiconductor device 105 can be formed by a similar process described in connection with Figures 1A-8G but the first epitaxial layer 515 of the source / drain region 510 of the semiconductor device 105 is formed to include a merged epitaxial region 905, rather than the merged region 525 and the non-continuous second epitaxial region 530.

[0110] To implement the merged epitaxial region 905, the material of the first epitaxial layer 515 is grown epitaxially during the source / drain region formation process described in connection with FIG. 5 such that the merged region 525 and the non-continuous second epitaxial region 530 merge together to form a plurality of continuous regions of epitaxial material corresponding to the merged epitaxial region 905. The epitaxial material corresponding to the merged epitaxial region 905 spans the interior spacer 405 such that the second epitaxial layer 520 of the source / drain region 510 is spaced apart from (and does not contact) the interior spacer 405.

[0111] As indicated above, Figure 9 are provided by way of example. Other examples can differ Figure 9 differently from what is described.

[0112] Figure 10is an illustration of an example implementation 1000 of the semiconductor device 105 described herein. The example implementation 1000 of the semiconductor device 105 can be formed by combining Figures 1A-8G the similar processes described, but the source / drain contacts 830 in the example implementation 1000 of the semiconductor device 105 are recessed deeper in the source / drain regions 510 than Figures 8A-8G shown. For example, the source / drain contacts 830 in the example implementation 1000 extend to a depth (e.g., relative to the top of the source / drain regions 510) corresponding to a dimension D8, and the dimension D8 is greater than Figure 8D the dimension D2 in the semiconductor device 105.

[0113] To achieve this, an etching operation described in connection with Figure 8D is performed to increase the depth of the contact recesses 815 from the dimension D1 to the dimension D8. Thus, after the etching operation described in connection with Figure 8D the bottom of the contact recesses 815 is at a depth in the semiconductor device 105 that is approximately equal to or below the deepest nanowire channel (e.g., the nanowire channel 315c) of the semiconductor device 105 (e.g., the dimension D8). In some implementations, after the etching operation described in connection with Figure 8D the bottom of the contact recesses 815 is at a depth in the semiconductor device 105 that is approximately equal to or below the bottom surface of the deepest nanowire channel (e.g., the nanowire channel 315c) (e.g., the dimension D8).

[0114] A metal silicide layer 825 is then formed from the exposed portions of the second epitaxial layer 520 in the contact recesses 815, and a material for the source / drain contacts 830 is deposited on the metal silicide layer 825 such that the source / drain contacts 830 fill the remaining area in the contact recesses 815 and extend above the source / drain regions 510.

[0115] Thus, the metal silicide layer 825 and / or the source / drain contacts 830 can be located in the semiconductor device 105 at a depth that is approximately equal to or below the deepest nanowire channel (e.g., the nanowire channel 315c) and below the top and middle inner spacers (e.g., the inner spacers 405a and 410b) of the semiconductor device 105. In some implementations, the metal silicide layer 825 and / or the source / drain contacts 830 can be located in the semiconductor device 105 at a depth that is approximately equal to or below the bottom surface of the deepest nanowire channel (e.g., the nanowire channel 315c) and / or approximately equal to or below the top surface of the deepest inner spacer (e.g., the inner spacer 405c).

[0116] In the example implementation 1000 of the semiconductor device 105, the increased depth of the recessing of the source / drain contact 830 within the source / drain region 510 can further reduce contact resistance between the source / drain contact 830 and the source / drain region 510 due to a further increased contact area between the source / drain contact 830 and the source / drain region 510. Additionally and / or alternatively, in the example implementation 1000 of the semiconductor device 105, the increased depth of the recessing of the source / drain contact 830 within the source / drain region 510 can further reduce current crowding in the source / drain region 510 due to the source / drain contact 830 extending alongside the intermediate nanostructure channel (e.g., nanostructure channel 315b) and alongside the bottom-most nanostructure channel (e.g., nanostructure channel 315c). This provides a more direct lateral travel path for charge carriers between the source / drain contact 830 and the nanostructure channels 315 through the source / drain region 510 (e.g., as opposed to, if the source / drain contact 830 terminated at the top of the source / drain recess 510, charge carriers would have to travel vertically in addition to horizontally to reach the nanostructure channels 315b and 315c).

[0117] As noted above, Figure 10 are provided by way of example. Other examples can differ Figure 10 from the examples described.

[0118] Figure 11 is an illustration of an example implementation 1100 of the semiconductor device 105 described herein. The example implementation 1100 of the semiconductor device 105 can be formed by incorporating similar processes described Figures 1A-8G above, but the source / drain contact 830 in the example implementation 1100 of the semiconductor device 105 is recessed deeper in the source / drain region 510 than Figures 8A-8G shown in the example implementation 1000. For example, the source / drain contact 830 in the example implementation 1100 extends to a depth (e.g., relative to the top of the source / drain region 510) corresponding to a dimension D9, and the dimension D9 is greater than Figure 8D the dimension D2 in the example implementation 1000.

[0119] To achieve this, an etching operation is performed to increase the depth of the contact recess 815 from the dimension Dl to the dimension D9, incorporating Figure 8D the processes described above. Accordingly, the example implementation 1100 of the semiconductor device 105 can provide a further reduction in contact resistance between the source / drain contact 830 and the source / drain region 510 due to a further increased contact area between the source / drain contact 830 and the source / drain region 510. Additionally and / or alternatively, the example implementation 1100 of the semiconductor device 105 can further reduce current crowding in the source / drain region 510 due to the source / drain contact 830 extending alongside the intermediate nanostructure channel (e.g., nanostructure channel 315b) and alongside the bottom-most nanostructure channel (e.g., nanostructure channel 315c). This provides a more direct lateral travel path for charge carriers between the source / drain contact 830 and the nanostructure channels 315 through the source / drain region 510 (e.g., as opposed to, if the source / drain contact 830 terminated at the top of the source / drain recess 510, charge carriers would have to travel vertically in addition to horizontally to reach the nanostructure channels 315b and 315c). Figure 8DAfter the described etching operations, the bottom of the contact recess 815 is at a depth (e.g., dimension D9) in the semiconductor device 105 that is below a bottommost nanowire channel (e.g., nanowire channel 315c) of the semiconductor device 105. The recess 815 can extend to the depth of the mesa region 310 below the nanowire channel 315. The recess 815 can extend through the second epitaxial layer 520 and into the portion of the merged region 525 of the first epitaxial layer 515 that is below the second epitaxial layer 520.

[0120] A metal silicide layer 825 is then formed from the exposed portions of the second epitaxial layer 520 in the contact recess 815 and from the exposed portions of the merged region 525 of the first epitaxial layer 515 in the contact recess 815. Thus, the bottom of the metal silicide layer 825 can be in contact with the merged region 525 of the first epitaxial layer 515, and portions of the metal silicide layer 825 that extend along the sidewalls of the contact recess 815 can be in contact with the second epitaxial layer 520. Material for the source / drain contact 830 is deposited on the metal silicide layer 825 such that the source / drain contact 830 fills the remaining area in the contact recess 815 and extends over the source / drain region 510.

[0121] Thus, the metal silicide layer 825 and / or the source / drain contact 830 can be located in the semiconductor device 105 at a depth that is below a bottommost nanowire channel (e.g., nanowire channel 315c) and below a bottommost internal spacer (e.g., internal spacer 405c) of the semiconductor device 105. In some implementations, the metal silicide layer 825 and / or the source / drain contact 830 can be located in the semiconductor device 105 at a depth that is approximately equal to the depth of the mesa region 310 below the nanowire channel 315.

[0122] In the example implementation 1100 of the semiconductor device 105, the increased depth of the recessing of the source / drain contact 830 within the source / drain region 510 can further reduce contact resistance between the source / drain contact 830 and the source / drain region 510 due to a further increased contact area between the source / drain contact 830 and the source / drain region 510. Additionally and / or alternatively, in the example implementation 1100 of the semiconductor device 105, the increased depth of the recessing of the source / drain contact 830 within the source / drain region 510 can further reduce current crowding in the source / drain region 510 due to the source / drain contact 830 extending alongside the intermediate nanostructure channel (e.g., nanostructure channel 315b) and alongside the bottom-most nanostructure channel (e.g., nanostructure channel 315c). This provides a more direct lateral travel path for charge carriers between the source / drain contact 830 and the nanostructure channels 315 through the source / drain region 510 (e.g., as opposed to, if the source / drain contact 830 terminated at the top of the source / drain recess 510, charge carriers would have to travel vertically in addition to horizontally to reach the nanostructure channels 315b and 315c).

[0123] As noted above, Figure 11 are provided by way of example. Other examples can differ Figure 11 from the examples described.

[0124] Figure 12 is a flow diagram of an example process 1200 associated with forming a semiconductor device described herein. In some implementations, one or more of the process blocks of the process 1200 are performed using one or more semiconductor processing tools (e.g., a deposition tool, an exposure tool, a development tool, an etching tool, a planarization tool, an ion implantation tool, an annealing tool, a wafer / die transport tool, and / or another type of semiconductor processing tool). Figure 12

[0125] As Figure 12 shown, the process 1200 can include forming a plurality of nanostructure channels arranged in a direction substantially perpendicular to a substrate of the semiconductor device (block 1210). For example, the plurality of nanostructure channels (e.g., nanostructure channels 315) can be formed arranged in a direction (e.g., the z-direction) substantially perpendicular to a substrate (e.g., semiconductor substrate 110) of a semiconductor device (e.g., semiconductor device 105) using one or more semiconductor processing tools, as described herein.

[0126] As Figure 12 ​Further to the foregoing, the process 1200 can include forming a source / drain region adjacent to the plurality of nanostructure channels (block 1220). For example, one or more semiconductor processing tools can be used to form a source / drain region (e.g., source / drain region 510) adjacent to the plurality of nanostructure channels, as described herein.

[0127] As Figure 12 Further to the foregoing, the process 1200 can include forming a dielectric layer over the source / drain region (block 1230). For example, one or more semiconductor processing tools can be used to form a dielectric layer (e.g., dielectric layer 605) over the source / drain region, as described herein.

[0128] As Figure 12 Further to the foregoing, the process 1200 can include forming a gate structure wrapping at least three sides of the plurality of nanostructure channels (block 1240). For example, one or more semiconductor processing tools can be used to form a gate structure (e.g., gate structure 710) wrapping at least three sides of the plurality of nanostructure channels, as described herein.

[0129] As Figure 12 Further to the foregoing, the process 1200 can include forming a recess through the dielectric layer and into the source / drain region such that a bottom of the recess is at a depth in the semiconductor device that is below a topmost nanostructure channel of the plurality of nanostructure channels and substantially equal to or below a top surface of a second nanostructure channel of the plurality of nanostructure channels (block 1250). For example, one or more semiconductor processing tools can be used to form a recess (e.g., contact recess 815) through the dielectric layer and into the source / drain region such that a bottom of the recess is at a depth (e.g., dimension D2, dimension D8, dimension D9) in the semiconductor device that is below a topmost nanostructure channel (e.g., nanostructure channel 315a) and substantially equal to or below a top surface of a second nanostructure channel (e.g., nanostructure channel 315b) of the plurality of nanostructure channels, as described herein. In some implementations, the second nanostructure channel is below the topmost nanostructure channel.

[0130] As Figure 12 Further to the foregoing, the process 1200 can include forming a source / drain contact in the recess such that the source / drain contact extends into the source / drain region (block 1260). For example, one or more semiconductor processing tools can be used to form a source / drain contact (e.g., source / drain contact 830) in the recess such that the source / drain contact extends into the source / drain region, as described herein.

[0131] Process 1200 can include additional implementation ways, such as any single implementation way described below and / or in combination with one or more other process descriptions described elsewhere herein.

[0132] In a first implementation way, forming the recess includes forming the recess such that a bottom of the recess is at a depth (e.g., dimension D2) in the semiconductor device that is approximately equal to or below a bottom surface of the second nanowire channel.

[0133] In a second implementation way, alone or in combination with the first implementation way, forming the recess includes forming the recess such that a bottom of the recess is at a depth (e.g., dimension D8) in the semiconductor device that is approximately equal to or below a bottom surface of a bottommost nanowire channel (e.g., nanowire channel 315c) of the plurality of nanowire channels.

[0134] In a third implementation way, alone or in combination with one or more of the first and second implementation ways, forming the source / drain contact includes forming a metal silicide layer (e.g., metal silicide layer 825) in the recess, and forming the source / drain contact on the metal silicide layer.

[0135] In a fourth implementation way, alone or in combination with one or more of the first through third implementation ways, forming the source / drain region includes forming a first layer of epitaxially grown material (e.g., first epitaxial layer 515) in contact with the plurality of nanowire channels, and forming a second layer of epitaxially grown material (e.g., second epitaxial layer 520) on the first layer of epitaxially grown material, and forming the metal silicide layer includes forming the metal silicide layer such that the metal silicide layer is in contact with the second layer of epitaxially grown material and is spaced apart from the first layer of epitaxially grown material by the second layer of epitaxially grown material.

[0136] In a fifth implementation way, alone or in combination with one or more of the first through fourth implementation ways, the first layer of epitaxially grown material includes a plurality of non-contiguous portions (e.g., non-contiguous second epitaxial regions 530) in contact with the plurality of nanowire channels.

[0137] In a sixth implementation way, alone or in combination with one or more of the first through fifth implementation ways, the first layer of epitaxially grown material includes a plurality of contiguous portions (e.g., merged epitaxial regions 905) in contact with the plurality of nanowire channels.

[0138] In a seventh embodiment, alone or in combination with one or more of the first through sixth embodiment implementations, forming the source / drain region includes forming a first layer of epitaxially grown material (e.g., first epitaxial layer 515) in contact with the plurality of nanostructure channels, and forming a second layer of epitaxially grown material (e.g., second epitaxial layer 520) on the first layer of epitaxially grown material, and forming the recess includes forming the recess such that a bottom of the recess extends through the second layer of epitaxially grown material and into the first layer of epitaxially grown material, and forming the metal silicide layer includes forming the metal silicide layer such that a first portion of the metal silicide layer is in contact with the second layer of epitaxially grown material, and such that a second portion of the metal silicide layer is in contact with the first layer of epitaxially grown material.

[0139] Although Figure 12 An example block of the process 1200 is shown, but in some implementations, the process 1200 includes additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in FIG. 12. Additionally or alternatively, two or more of the blocks of the process 1200 can be performed in parallel. Figure 12

[0140] Figure 13 is a flow diagram of an example process 1300 associated with forming a semiconductor device described herein. In some implementations, one or more process blocks of the process 1300 are performed using one or more semiconductor processing tools (e.g., a deposition tool, an exposure tool, a development tool, an etching tool, a planarization tool, an ion implantation tool, an annealing tool, a wafer / die transport tool, and / or another type of semiconductor processing tool). Figure 13

[0141] As Figure 13 shown, the process 1300 can include forming a plurality of nanostructure channels arranged in a direction substantially perpendicular to a substrate of the semiconductor device (block 1310). For example, the plurality of nanostructure channels (e.g., nanostructure channels 315) arranged in a direction (e.g., the z-direction) substantially perpendicular to a substrate (e.g., semiconductor substrate 110) of a semiconductor device (e.g., semiconductor device 105) can be formed using one or more semiconductor processing tools, as described herein.

[0142] As Figure 13 further shown, the process 1300 can include forming a source / drain region adjacent to the plurality of nanostructure channels (block 1320). For example, a source / drain region (e.g., source / drain region 510) adjacent to the plurality of nanostructure channels can be formed using one or more semiconductor processing tools, as described herein.

[0143] As Figure 13 ​​As further shown, process 1300 can include forming a dielectric layer over the source / drain region (block 1330). For example, the dielectric layer (e.g., dielectric layer 605) can be formed over the source / drain region using one or more semiconductor processing tools, as described herein.

[0144] As further shown, process 1300 can include forming a gate structure that wraps at least three sides of the plurality of nanoscale channels (block 1340). For example, the gate structure (e.g., gate structure 710) that wraps at least three sides of the plurality of nanoscale channels can be formed using one or more semiconductor processing tools, as described herein. Figure 13 As further shown, process 1300 can include performing a first etching operation to form a recess through the dielectric layer and into the source / drain region such that a bottom of the recess is at a first depth in the recess (block 1350). For example, the first etching operation to form a recess (e.g., contact recess 815) through the dielectric layer and into the source / drain region such that a bottom of the recess is at a first depth (e.g., dimension Dl) in the recess can be performed using one or more semiconductor processing tools, as described herein.

[0145] Figure 13 As further shown, process 1300 can include performing a second etching operation to increase the recess from the first depth to a second depth below a topmost nanoscale channel of the plurality of nanoscale channels (block 1360). For example, the second etching operation to increase the recess from the first depth to a second depth (e.g., dimension D2, dimension D8, dimension D9) below a topmost nanoscale channel of the plurality of nanoscale channels can be performed using one or more semiconductor processing tools, as described herein.

[0146] As further shown, process 1300 can include forming a source / drain contact in the recess such that the source / drain contact extends into the source / drain region (block 1370). For example, the source / drain contact (e.g., source / drain contact 830) can be formed in the recess such that the source / drain contact extends into the source / drain region using one or more semiconductor processing tools, as described herein. Figure 13 As further shown, process 1300 can include forming a source / drain contact in the recess such that the source / drain contact extends into the source / drain region (block 1370). For example, the source / drain contact (e.g., source / drain contact 830) can be formed in the recess such that the source / drain contact extends into the source / drain region using one or more semiconductor processing tools, as described herein.

[0147] Figure 13 Process 1300 can include additional implementations, such as any single implementation or any combination of combinations of the implementations described below and / or in connection with one or more other processes described elsewhere herein.

[0148] Process 1300 can include additional implementations, such as any single implementation or any combination of combinations of the implementations described below and / or in connection with one or more other processes described elsewhere herein.

[0149] ​​In a first implementation, the process 1300 includes, after the first etching operation and before the second etching operation, forming a protective liner (e.g., the sidewall liner 820) on the sidewalls of the recess and on the top of the source / drain region in the recess, and performing a third etching operation to etch through the protective liner to expose the top of the source / drain region through the recess after the first etching operation and before the second etching operation.

[0150] In a second implementation, alone or in combination with the first implementation, performing the second etching operation includes performing the second etching operation while the protective liner is on the sidewalls of the recess.

[0151] In a third implementation, alone or in combination with one or more of the first and second implementations, performing the first etching operation includes performing the first etching operation using a first etchant, and performing the second etching operation includes performing the second etching operation using a second etchant, where the first etchant and the second etchant are different etchants.

[0152] In a fourth implementation, alone or in combination with one or more of the first through third implementations, a first etch rate of the second etchant for a material of the sidewalls of the recess is less than a second etch rate of the second etchant for a material of the source / drain region.

[0153] In a fifth implementation, alone or in combination with one or more of the first through fourth implementations, the second etchant includes a chlorine-containing gas.

[0154] In a sixth implementation, alone or in combination with one or more of the first through fifth implementations, a difference between a first etch rate of the second etchant for a material of the sidewalls of the recess and a second etch rate of the second etchant for a material of the source / drain region is greater than a difference between a third etch rate of the first etchant for the material of the sidewalls of the recess and a fourth etch rate of the first etchant for the material of the source / drain region.

[0155] Although Figure 13 Example blocks of the process 1300 are shown, but in some implementations, the process 1300 includes additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in FIG. 13. Additionally, or alternatively, two or more of the blocks of the process 1300 can be performed in parallel. Figure 13 Example blocks of the process 1300 are shown, but in some implementations, the process 1300 includes additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in FIG. 13. Additionally, or alternatively, two or more of the blocks of the process 1300 can be performed in parallel.

[0156] In this manner, the source / drain contacts of the nanostructure transistor are formed such that the source / drain contacts are recessed within the underlying source / drain regions of the nanostructure transistor using a multi-step etching process. Recessing the source / drain contacts within the source / drain regions provides a greater amount of surface area for the source / drain contacts to be in contact with the source / drain regions. This provides an increased contact surface area between the source / drain contacts and the source / drain regions, and the increased contact surface area provides a reduced contact resistance between the source / drain regions and the source / drain contacts due to a less restricted current flow path between the source / drain regions and the source / drain contacts. In this manner, the reduced contact resistance between the source / drain regions and the source / drain contacts enables greater power efficiency to be achieved for the nanostructure transistor, and / or enables increased switching speed to be achieved for the nanostructure transistor, etc.

[0157] As described in greater detail above, some implementations described herein provide a method. The method includes forming a plurality of nanostructure channels arranged in a direction substantially perpendicular to a substrate of a semiconductor device. The method includes forming a source / drain region adjacent to the plurality of nanostructure channels. The method includes forming a dielectric layer over the source / drain region. The method includes forming a gate structure wrapping at least three sides of the plurality of nanostructure channels. The method includes forming a recess through the dielectric layer and into the source / drain region such that a bottom of the recess is at a depth in the semiconductor device that is below a topmost nanostructure channel of the plurality of nanostructure channels and substantially equal to or below a top surface of a second nanostructure channel of the plurality of nanostructure channels, where the second nanostructure channel is below the topmost nanostructure channel. The method includes forming a source / drain contact in the recess such that the source / drain contact extends into the source / drain region.

[0158] As described in greater detail above, some implementations described herein provide a method. The method includes forming a plurality of nanostructure channels arranged in a direction substantially perpendicular to a substrate of a semiconductor device. The method includes forming a source / drain region adjacent to the plurality of nanostructure channels. The method includes forming a dielectric layer over the source / drain region. The method includes forming a gate structure wrapping at least three sides of the plurality of nanostructure channels. The method includes performing a first etching operation to form a recess through the dielectric layer and into the source / drain region such that a bottom of the recess is at a first depth in the recess. The method includes performing a second etching operation to increase the recess from the first depth to a second depth below a topmost nanostructure channel of the plurality of nanostructure channels. The method includes forming a source / drain contact in the recess such that the source / drain contact extends into the source / drain region.

[0159] As described in more detail above, some implementations described herein provide a semiconductor device. The semiconductor device includes a plurality of nanostructure channels arranged in a first direction in the semiconductor device. The semiconductor device includes a gate structure over the plurality of nanostructure channels, surrounding the plurality of nanostructure channels. The semiconductor device includes a source / drain region adjacent to a side of the gate structure and adjacent to an end of the plurality of nanostructure channels in a second direction that is substantially perpendicular to the first direction. The semiconductor device includes a CESL extending along a sidewall of the gate structure and a top surface of the source / drain region, and an interlayer dielectric layer over the CESL. The semiconductor device includes a plurality of internal spacers between the source / drain region and the gate structure. The semiconductor device includes a source / drain contact extending through the ILD layer, through the CESL, and into the source / drain region to a depth below a topmost internal spacer of the plurality of internal spacers.

[0160] The terms“about” and“substantially” can mean a value of a given quantity varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values are examples only and are not intended to limit. It should be understood that the terms“about” and“substantially” can refer to a percentage of a value of a given quantity in accordance with the present disclosure.

[0161] The features outlined above briefly describe several embodiments so that a person skilled in the art can better understand aspects of the present disclosure. It should be appreciated by those skilled in the art that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same functions and / or achieve the same results as the embodiments presented herein. Those skilled in the art should appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same functions and / or achieve the same results as the embodiments presented herein.

[0162] Example 1 is a method of forming a semiconductor device, comprising: forming a plurality of nanostructure channels, the plurality of nanostructure channels arranged in a direction substantially perpendicular to a substrate of the semiconductor device; forming a source / drain region adjacent to the plurality of nanostructure channels; forming a dielectric layer over the source / drain region; forming a gate structure wrapping at least three sides of the plurality of nanostructure channels; forming a recess through the dielectric layer and into the source / drain region such that a bottom of the recess is at a depth in the semiconductor device that is below a topmost nanostructure channel of the plurality of nanostructure channels and substantially equal to or below a top surface of a second nanostructure channel of the plurality of nanostructure channels, wherein the second nanostructure channel is below the topmost nanostructure channel; and forming a source / drain contact in the recess such that the source / drain contact extends into the source / drain region.

[0163] Example 2 is the method of Example 1, wherein forming the recess comprises: forming the recess such that the bottom of the recess is at a depth in the semiconductor device that is substantially equal to or below a bottom surface of the second nanostructure channel.

[0164] Example 3 is the method of Example 1, wherein forming the recess comprises: forming the recess such that the bottom of the recess is at a depth in the semiconductor device that is substantially equal to or below a bottom surface of a bottommost nanostructure channel of the plurality of nanostructure channels.

[0165] Example 4 is the method of Example 1, wherein forming the source / drain contact comprises: forming a metal silicide layer in the recess; and forming the source / drain contact on the metal silicide layer.

[0166] Example 5 is the method of Example 4, wherein forming the source / drain region comprises: forming a first layer of epitaxially grown material in contact with the plurality of nanostructure channels; and forming a second layer of epitaxially grown material on the first layer of epitaxially grown material, wherein forming the metal silicide layer comprises: forming the metal silicide layer such that the metal silicide layer is in contact with the second layer of epitaxially grown material and is spaced apart from the first layer of epitaxially grown material by the second layer of epitaxially grown material.

[0167] Example 6 is the method of Example 5, wherein the first layer of epitaxially grown material comprises a plurality of non-contiguous portions in contact with the plurality of nanostructure channels.

[0168] Example 7 is the method of Example 5, wherein the first layer of epitaxially grown material comprises a plurality of contiguous portions in contact with the plurality of nanostructure channels.

[0169] Example 8 is the method of example 4, wherein forming the source / drain region comprises: forming a first layer of epitaxially grown material in contact with the plurality of nanostructure channels; and forming a second layer of epitaxially grown material on the first layer of epitaxially grown material, wherein forming the recess comprises: forming the recess such that a bottom of the recess extends through the second layer of epitaxially grown material and into the first layer of epitaxially grown material, and wherein forming the metal silicide layer comprises: forming the metal silicide layer such that a first portion of the metal silicide layer is in contact with the second layer of epitaxially grown material, and such that a second portion of the metal silicide layer is in contact with first layer of epitaxially grown material.

[0170] Example 9 is a method of forming a semiconductor device, comprising: forming a plurality of nanostructure channels, the plurality of nanostructure channels arranged in a direction substantially perpendicular to a substrate of the semiconductor device; forming a source / drain region adjacent to the plurality of nanostructure channels; forming a dielectric layer over the source / drain region; forming a gate structure that wraps at least three sides of the plurality of nanostructure channels; performing a first etching operation to form a recess through the dielectric layer and into the source / drain region, such that a bottom of the recess is at a first depth in the recess; performing a second etching operation to increase the recess from the first depth to a second depth, the second depth being below a topmost nanostructure channel of the plurality of nanostructure channels; and forming a source / drain contact in the recess, such that the source / drain contact extends into the source / drain region.

[0171] Example 10 is the method of example 9, further comprising: after the first etching operation and before the second etching operation, forming a protective liner on sidewalls of the recess and on a top of the source / drain region in the recess; and after the first etching operation and before the second etching operation, performing a third etching operation to etch through the protective liner to expose the top of the source / drain region through the recess.

[0172] Example 11 is the method of example 10, wherein performing the second etching operation comprises: performing the second etching operation while the protective liner is on sidewalls of the recess.

[0173] Example 12 is the method of example 9, wherein performing the first etching operation comprises: performing the first etching operation using a first etchant; and wherein performing the second etching operation comprises: performing the second etching operation using a second etchant, wherein the first etchant and the second etchant are different etchants.

[0174] Example 13 is the method of example 12, wherein a first etch rate of the second etchant against a material of sidewalls of the recess is less than a second etch rate of the second etchant against a material of the source / drain region.

[0175] Example 14 is the method of example 12, wherein the second etchant comprises a chlorine-containing gas.

[0176] Example 15 is the method of example 12, wherein a difference between the first etch rate of the second etchant against a material of sidewalls of the recess and the second etch rate of the second etchant against a material of the source / drain region is greater than a difference between a third etch rate of the first etchant against a material of sidewalls of the recess and a fourth etch rate of the first etchant against a material of the source / drain region.

[0177] Example 16 is a semiconductor device comprising: a plurality of nanostructure channels arranged in a first direction in the semiconductor device; a gate structure over and surrounding the plurality of nanostructure channels; a source / drain region adjacent to a side of the gate structure and adjacent to an end of the plurality of nanostructure channels in a second direction substantially perpendicular to the first direction; a contact etch stop layer (CESL) extending along sidewalls of the gate structure and a top surface of the source / drain region; an interlayer dielectric (ILD) layer over the CESL; a plurality of internal spacers between the source / drain region and the gate structure; and a source / drain contact extending through the ILD layer, through the CESL, and into the source / drain region to a depth below a topmost internal spacer of the plurality of internal spacers.

[0178] Example 17 is the semiconductor device of example 16, wherein the source / drain region comprises: a first epitaxial region around a bottom of the source / drain contact; and a plurality of non-contiguous second epitaxial regions between the first epitaxial region and the plurality of nanostructure channels.

[0179] Example 18 is the semiconductor device of example 16, wherein the source / drain region comprises: a first epitaxial region around a bottom of the source / drain contact; and a second epitaxial region between the first epitaxial region and the plurality of nanostructure channels, and between the first epitaxial region and the plurality of internal spacers.

[0180] Example 19 is the semiconductor device of Example 16, wherein the source / drain region comprises: a first epitaxial region around sidewalls of the source / drain contact; and a second epitaxial region between the first epitaxial region and the plurality of nanostructure channels, wherein a bottom of the source / drain contact extends into the second epitaxial region.

[0181] Example 20 is the semiconductor device of Example 16, further comprising: a metal silicide layer between the source / drain contact and the source / drain region, wherein the metal silicide layer extends from a top of the source / drain region to a bottom of the source / drain contact.

Claims

1. A method of forming a semiconductor device, comprising: forming a plurality of nanostructure channels, the plurality of nanostructure channels being arranged in a direction that is substantially perpendicular to a substrate of the semiconductor device; forming a source / drain region adjacent to the plurality of nanostructure channels; forming a dielectric layer over the source / drain region; forming a gate structure that wraps around at least three sides of the plurality of nanostructure channels; forming a recess through the dielectric layer and into the source / drain region such that a bottom of the recess is at a depth in the semiconductor device that is below a topmost nanostructure channel of the plurality of nanostructure channels and is substantially equal to or below a top surface of a second nanostructure channel of the plurality of nanostructure channels, wherein the second nanostructure channel is below the topmost nanostructure channel; and forming a source / drain contact in the recess such that the source / drain contact extends into the source / drain region. forming the recess includes:

2. The method of claim 1, wherein, forming the recess such that the bottom of the recess is at a depth in the semiconductor device that is substantially equal to or below a bottom surface of the second nanostructure channel. forming the recess includes:

3. The method of claim 1, wherein, forming the recess such that the bottom of the recess is at a depth in the semiconductor device that is substantially equal to or below a bottom surface of a bottommost nanostructure channel of the plurality of nanostructure channels. forming the source / drain contact includes:

4. The method of claim 1, wherein, forming a metal silicide layer in the recess; and forming the source / drain contact on the metal silicide layer. forming the source / drain region includes:

5. The method of claim 4, wherein, forming a first layer of epitaxially grown material in contact with the plurality of nanostructure channels; and forming a second layer of epitaxially grown material on the first layer of epitaxially grown material, wherein forming the metal silicide layer includes: forming the metal silicide layer such that the metal silicide layer is in contact with the second layer of epitaxially grown material and is spaced apart from the first layer of epitaxially grown material by the second layer of epitaxially grown material. the first layer of epitaxially grown material includes a plurality of non-contiguous portions in contact with the plurality of nanostructure channels.

6. The method of claim 5, wherein, the first layer of epitaxially grown material includes a plurality of contiguous portions in contact with the plurality of nanostructure channels.

7. The method of claim 5, wherein, forming the source / drain region includes:

8. The method of claim 4, wherein, forming a first layer of epitaxially grown material in contact with the plurality of nanostructure channels; and forming a second layer of epitaxially grown material on the first layer of epitaxially grown material, wherein forming the recess includes: forming the recess such that the bottom of the recess extends through the second layer of epitaxially grown material and into the first layer of epitaxially grown material, and wherein forming the metal silicide layer includes: forming the metal silicide layer such that a first portion of the metal silicide layer is in contact with the second layer of epitaxially grown material and such that a second portion of the metal silicide layer is in contact with first layer of epitaxially grown material.

9. A method of forming a semiconductor device, comprising: forming a plurality of nanostructure channels, the plurality of nanostructure channels being arranged in a direction that is substantially perpendicular to a substrate of the semiconductor device; ​ forming a source / drain region adjacent to the plurality of nanostructure channels; forming a dielectric layer over the source / drain region; forming a gate structure that wraps at least three sides of the plurality of nanostructure channels; performing a first etch operation to form a recess through the dielectric layer and into the source / drain region such that a bottom of the recess is at a first depth in the recess; performing a second etch operation to increase the recess from the first depth to a second depth that is below a topmost nanostructure channel of the plurality of nanostructure channels; and forming a source / drain contact in the recess such that the source / drain contact extends into the source / drain region.

10. A semiconductor device, comprising: a plurality of nanostructure channels arranged in a first direction in the semiconductor device; a gate structure over and wrapping the plurality of nanostructure channels; a source / drain region adjacent to a side of the gate structure and adjacent to an end of the plurality of nanostructure channels in a second direction that is substantially perpendicular to the first direction; a contact etch stop layer (CESL) extending along a sidewall of the gate structure and a top surface of the source / drain region; an interlayer dielectric (ILD) layer over the CESL; a plurality of internal spacers between the source / drain region and the gate structure; and a source / drain contact extending through the ILD layer, through the CESL, and into the source / drain region to a depth below a topmost internal spacer of the plurality of internal spacers. ​

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