Semiconductor device fabrication methods
By injecting fluorine ions and performing an annealing process during the fabrication of CIS devices, the problems of leakage current and dark current were solved, thereby improving the performance of CIS devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NEXCHIP SEMICON CO LTD
- Filing Date
- 2025-12-30
- Publication Date
- 2026-06-30
AI Technical Summary
Current CIS device fabrication processes cannot simultaneously reduce leakage current, white pixel current, and dark current, thus preventing further performance improvements.
After forming the first gate structure and the second gate structure on the substrate surface, ion implantation is performed to form the source and drain regions, and the structure is covered by a first barrier layer. After removing the first barrier layer, fluorine ions are implanted in the pixel region of the substrate. After performing an annealing process, a second barrier layer is formed to cover the gate structure, avoiding damage and reducing leakage current and dark current.
By passivating the dangling bonds on the substrate surface, damage is repaired, white pixels and dark current are reduced, the bulging phenomenon of the second barrier layer is avoided, and device performance is improved.
Smart Images
Figure CN121463550B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, specifically to a method for fabricating a semiconductor device. Background Technology
[0002] Complementary Metal Oxide Semiconductor Image Sensors (CIS) have been widely used in consumer electronics, security monitoring, advanced driver-assistance systems (ADAS), and medical devices due to their advantages such as low power consumption, high performance, and ease of integration. Currently, the fabrication process for CIS devices cannot simultaneously reduce leakage current, white pixel current, and dark current, thus hindering further performance improvements. Summary of the Invention
[0003] In view of this, the embodiments of this application aim to provide a method for fabricating a semiconductor device to improve the existing fabrication process of CIS devices.
[0004] This application provides a method for fabricating a semiconductor device, comprising:
[0005] A substrate is provided, the substrate having pixel regions and logic regions;
[0006] A first gate structure and a second gate structure are formed on the substrate, wherein the first gate structure is located within the logic region and the second gate structure is located within the pixel region;
[0007] Ion implantation is performed on the substrates on both sides of the first gate structure to form a first source / drain region in the substrates on both sides of the first gate structure;
[0008] A first barrier layer is formed on the substrate, and the first barrier layer also conformally covers the outer surfaces of the first gate structure and the second gate structure;
[0009] Ion implantation is performed on the substrates on both sides of the second gate structure to form second source / drain regions within the substrates on both sides of the second gate structure;
[0010] Remove the first barrier layer and implant fluorine ions into at least a portion of the surface of the substrate located within the pixel region;
[0011] Perform the first annealing process; and,
[0012] A second barrier layer is formed on the substrate, and the second barrier layer also conformally covers the outer surfaces of the first gate structure and the second gate structure.
[0013] In some embodiments, after fluorine ions are implanted at least in the portion of the substrate surface located within the logic region, and before performing the first annealing process, the process further includes:
[0014] An oxide layer is formed on the substrate;
[0015] And, after performing the first annealing process, a second barrier layer is formed on the oxide layer.
[0016] In some embodiments, after removing the first barrier layer, an oxide layer is formed on the substrate, and fluorine ions are implanted at least at the interface between the oxide layer and a portion of the substrate surface located within the pixel region;
[0017] And, after performing the first annealing process, a second barrier layer is formed on the oxide layer.
[0018] In some embodiments, the oxide layer is formed at room temperature using a decoupled plasma oxidation process.
[0019] In some embodiments, after removing the first barrier layer, the logic region is covered, and fluorine ions are implanted into a portion of the surface of the substrate located within the pixel region; or, after removing the first barrier layer, fluorine ions are implanted into a portion of the surface of the substrate located within both the logic region and the pixel region.
[0020] In some embodiments, the hardness of the second barrier layer is greater than the hardness of the first barrier layer; or, the hardness of the top surface of the second barrier layer is greater than the hardness of the top surface of the first barrier layer.
[0021] In some embodiments, after the second barrier layer is formed on the substrate, a second annealing process is performed to make the hardness of the second barrier layer greater than that of the first barrier layer.
[0022] In some embodiments, after the second barrier layer is formed on the substrate, the surface of the second barrier layer is bombarded with plasma, or the top surface of the second barrier layer is surface treated in a nitrogen-containing gas to make the hardness of the top surface of the second barrier layer greater than that of the top surface of the first barrier layer.
[0023] In some embodiments, the second barrier layer includes a first sub-film layer and a second sub-film layer stacked sequentially from bottom to top, wherein the thickness of the second sub-film layer is less than the thickness of the first sub-film layer, and the hardness of the second sub-film layer is greater than the hardness of the first sub-film layer.
[0024] In some embodiments, after forming the second barrier layer on the substrate, the method further includes:
[0025] Remove the portion of the second barrier layer located on the first source / drain region and the second source / drain region;
[0026] A metal contact layer is formed on the first source / drain region and the second source / drain region.
[0027] This application provides a method for fabricating a semiconductor device, comprising: providing a substrate having a pixel region and a logic region; forming a first gate structure and a second gate structure on the substrate, the first gate structure being located within the logic region and the second gate structure being located within the pixel region; performing ion implantation on the substrate on both sides of the first gate structure to form first source / drain regions within the substrate on both sides of the first gate structure; forming a first barrier layer on the substrate, the first barrier layer further conformally covering the outer surfaces of the first gate structure and the second gate structure; performing ion implantation on the substrate on both sides of the second gate structure to form second source / drain regions within the substrate on both sides of the second gate structure; removing the first barrier layer and implanting fluorine ions at least in the portion of the substrate surface located within the pixel region; performing a first annealing process; and forming a second barrier layer on the substrate, the second barrier layer further conformally covering the outer surfaces of the first gate structure and the second gate structure. An unexpected effect of this application is that after removing the first barrier layer, fluorine ions are implanted at least in the portion of the substrate surface located within the pixel region. After the first annealing process, the fluorine ions can combine with dangling bonds on the substrate surface, thereby passivating the dangling bonds on the substrate surface and repairing the damage to the substrate surface caused by the removal of the first barrier layer. At the same time, the first annealing process is performed before the formation of the second barrier layer, which can release at least a portion of the fluorine in the first source / drain region in advance, avoiding bulging of the second barrier layer. Attached Figure Description
[0028] Figure 1 This is a schematic diagram of the structure in which the first gate structure and the second gate structure are formed on the substrate.
[0029] Figure 2 This is a schematic diagram of the structure that forms the first source-drain region within the logic region.
[0030] Figure 3 This is a schematic diagram of a structure in which a first barrier layer is formed on a substrate, a first gate structure, and a second gate structure.
[0031] Figure 4 This is a schematic diagram of the structure for forming a second source / drain region within a pixel area.
[0032] Figure 5 A schematic diagram of the structure caused by the annealing process resulting in bulging of the first barrier layer.
[0033] Figure 6This is an electron microscope image of the bulge in the first barrier layer.
[0034] Figure 7 This is a schematic diagram of the structure for removing the first barrier layer.
[0035] Figure 8 This is a schematic diagram of a structure in which a second barrier layer is formed on a substrate, a first gate structure, and a second gate structure.
[0036] Figure 9 CIS devices formed by conventional processes and those manufactured according to Figures 1-8 A comparison chart of parameters of CIS devices formed by the fabrication process.
[0037] Figure 10 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application.
[0038] Figure 11 This is a schematic diagram of a first gate structure and a second gate structure formed on a substrate, according to an embodiment of this application.
[0039] Figure 12 This is a schematic diagram of a structure in which ion implantation is performed on the substrates on both sides of a first gate structure to form a first source / drain region, according to an embodiment of this application.
[0040] Figure 13 This is a schematic diagram of a structure in which a first barrier layer is formed on a substrate, a first gate structure, and a second gate structure, according to an embodiment of this application.
[0041] Figure 14 This is a schematic diagram of a structure in which ion implantation is performed on the substrates on both sides of the second gate structure to form a second source / drain region, according to an embodiment of this application.
[0042] Figure 15 This is a schematic diagram of the structure for removing the first barrier layer according to an embodiment of this application.
[0043] Figure 16 This is a schematic diagram of a structure in which fluorine ions are partially implanted on the surface of a substrate within a pixel region, according to an embodiment of this application.
[0044] Figure 17 This is a schematic diagram of a structure in which an oxide layer is formed on the surface of a substrate, according to an embodiment of this application.
[0045] Figure 18 This is a schematic diagram of a structure provided in an embodiment of this application, in which fluorine ions are implanted at the interface between the oxide layer and the substrate.
[0046] Figure 19 This is a schematic diagram of a structure in which a second barrier layer is formed on an oxide layer, a first gate structure, and a second gate structure, according to an embodiment of this application.
[0047] Figure 20 This is a schematic diagram of a structure in which a metal contact layer is formed on a first source / drain region and a second source / drain region, according to an embodiment of this application.
[0048] The attached figures are labeled as follows:
[0049] 100 - Substrate; 100a - Logic region; 100b - Pixel region; 101 - Trench isolation structure; 201 - First gate structure; 202 - Second gate structure; 301 - First photoresist layer; 302 - Second photoresist layer; 303 - Third photoresist layer; 401 - First source / drain region; 402 - Second source / drain region; 501 - First barrier layer; 502 - Second barrier layer; 600 - Oxide layer; 700 - Metal contact layer. Detailed Implementation
[0050] Figures 1-8 This is a schematic diagram of the structure corresponding to the steps in a method for fabricating a CIS device.
[0051] like Figure 1 As shown, a substrate is provided, the substrate having a pixel region and a logic region, the pixel region and the logic region being isolated by a trench isolation structure, a first gate structure and a second gate structure being formed on the substrate, the first gate structure being located within the logic region and arranged at intervals within the logic region, and the second gate structure being located within the pixel region and arranged at intervals within the pixel region.
[0052] like Figure 2 As shown, a first photoresist layer is formed on the substrate, located within the pixel region and covering the substrate and the second gate structure within the pixel region. Using the first photoresist layer as a mask, ion implantation is performed on the substrate on both sides of the first gate structure, thereby forming a first source / drain region within the substrate on both sides of the first gate structure.
[0053] It should be noted that NMOS and PMOS transistors are typically formed in the logic region. Therefore, when performing ion implantation on the substrate on both sides of the first gate structure, P-type ions need to be implanted in at least a portion of the substrate on both sides of the first gate structure to form P-type first source / drain regions. The first gate structure and the P-type first source / drain regions on both sides can then constitute a PMOS transistor. The conventional P-type ions used for ion implantation are boron ions (B+). However, to avoid rapid diffusion of boron ions (B+) after implantation, boron difluoride (BF2) is usually implanted, using fluoride ions (F-) to suppress the diffusion of boron ions (B+).
[0054] like Figure 3 As shown, a first barrier layer is formed on the substrate. The first barrier layer conformally covers the outer surfaces of the substrate, the first gate structure, and the second gate structure, meaning that the first barrier layer can replicate the morphology of the previous layer.
[0055] like Figure 4 As shown, a second photoresist layer is formed on the first barrier layer. The second photoresist layer is located within the logic region and covers the first barrier layer within the logic region. Using the second photoresist layer as a mask, ion implantation is performed on the substrates on both sides of the second gate structure, thereby forming second source / drain regions within the substrates on both sides of the second gate structure. Since the first barrier layer is formed before ion implantation on the substrates on both sides of the second gate structure, and the first barrier layer covers the sidewalls of the second gate structure, ions will not be implanted into the substrate below the first barrier layer covering the sidewalls of the second gate structure during ion implantation. Therefore, the overlap between the second gate structure and the second source / drain regions can be reduced, thereby reducing the gate-induce-drain (GIDL) leakage current of the transistors in the pixel region.
[0056] It should be noted that the pixel region usually needs to form an NMOS transistor. Therefore, when performing ion implantation on the substrates on both sides of the second gate structure, N-type ions need to be implanted in the substrates on both sides of the second gate structure to form an N-type second source / drain region. The second gate structure and the N-type first source / drain regions on both sides can constitute an NMOS transistor. The N-type ions commonly used for ion implantation can be phosphorus ions (P+) or arsenic ions (AS+). Therefore, phosphorus ions (P+) and / or arsenic ions (AS+) can be implanted in the substrates on both sides of the second gate structure to form the second source / drain region.
[0057] like Figure 5 As shown, a first annealing process is performed to activate the doped impurity ions in the first and second source / drain regions. The temperature of the first annealing process is typically high (above 1000 degrees Celsius), which can cause the boron difluoride implanted in the first source / drain region within the logic region to decompose. After the boron difluoride decomposes, the fluorine escapes from the substrate and diffuses upwards into the first barrier layer, causing bulging on the surface of the first barrier layer (e.g., ...). Figure 5 The area indicated by the dashed circle. Figure 6 The image shows an electron microscope image of the bulge in the first barrier layer.
[0058] Based on this, such as Figure 7 As shown in Figure 8, the first barrier layer is removed by etching, and then a second barrier layer is reformed on the substrate. The second barrier layer can conformally cover the substrate, the first gate structure, and the second gate structure, that is, the second barrier layer can replicate the morphology of the previous layer. Removing the first barrier layer and forming the second barrier layer can indeed solve the bulging problem. However, since the etching process for removing the first barrier layer damages the surface of the substrate, photoelectron traps appear, which in turn leads to an increase in white pixels (WP) and dark current (DC).
[0059] Figure 9 CIS devices formed using conventional processes (without forming the first and second barrier layers) and those formed according to... Figures 1-8 A comparison chart of parameters of CIS devices formed by the fabrication process. For example... Figure 9 As shown, according to Figures 1-8 Although the fabrication process of CIS devices reduces leakage current (GIDL, in ppm), the white pixel (WP, in ppm) still has a lower leakage current. 100ppm) and dark current (DC, in e - The electrons per second (electrons per second) has increased significantly.
[0060] Based on this, this application provides a method for fabricating a semiconductor device, comprising: providing a substrate having a pixel region and a logic region; forming a first gate structure and a second gate structure on the substrate, the first gate structure being located within the logic region and the second gate structure being located within the pixel region; performing ion implantation on the substrate on both sides of the first gate structure to form a first source / drain region within the substrate on both sides of the first gate structure; forming a first barrier layer on the substrate, the first barrier layer also conformally covering the outer surfaces of the first gate structure and the second gate structure; performing ion implantation on the substrate on both sides of the second gate structure to form a second source / drain region within the substrate on both sides of the second gate structure; removing the first barrier layer and implanting fluorine ions at least in the portion of the substrate surface located within the pixel region; performing a first annealing process; and forming a second barrier layer on the substrate, the second barrier layer also conformally covering the outer surfaces of the first gate structure and the second gate structure. After removing the first barrier layer, this application implants fluorine ions into at least a portion of the substrate surface located within the pixel region. After the first annealing process, the fluorine ions can combine with dangling bonds on the substrate surface, thereby passivating the dangling bonds on the substrate surface and repairing the damage to the substrate surface caused by the removal of the first barrier layer, reducing the white pixels and dark current of the device. At the same time, the first annealing process is performed before the formation of the second barrier layer, and the first annealing process can release at least a portion of the fluorine in the first source / drain region in advance, avoiding bulging of the second barrier layer.
[0061] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0062] One embodiment of this application provides a method for fabricating a semiconductor device. Figure 10 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application. Figure 10As shown, the semiconductor device can be a CIS device, and its fabrication method includes:
[0063] Step S100: Provide a substrate having a pixel region and a logic region;
[0064] Step S200: A first gate structure and a second gate structure are formed on the substrate, wherein the first gate structure is located within a logic region and the second gate structure is located within a pixel region;
[0065] Step S300: Ion implantation is performed on the substrates on both sides of the first gate structure to form a first source / drain region in the substrates on both sides of the first gate structure;
[0066] Step S400: A first barrier layer is formed on the substrate, the first barrier layer also conformally covering the outer surfaces of the first gate structure and the second gate structure;
[0067] Step S500: Ion implantation is performed on the substrates on both sides of the second gate structure to form second source / drain regions in the substrates on both sides of the second gate structure.
[0068] Step S600: Remove the first barrier layer and implant fluorine ions at least in the portion of the substrate surface located within the pixel region;
[0069] Step S700: Perform the first annealing process; and,
[0070] Step S800: A second barrier layer is formed on the substrate, the second barrier layer also conformally covering the outer surfaces of the first gate structure and the second gate structure.
[0071] Figures 11-20 This is a schematic diagram of the structure corresponding to the respective steps of the method for fabricating a semiconductor device according to an embodiment of this application. Next, we will combine... Figures 11-20 The corresponding steps of the method for fabricating a semiconductor device provided in one embodiment of this application will be described in detail.
[0072] like Figure 11As shown, in step S100, a substrate 100 is provided. The substrate 100 can be any suitable semiconductor material, such as silicon (Si), silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), silicon germanium (GeSi), or sapphire (Al2O3). The substrate 100 can also be a semiconductor-on-insulator, such as silicon-on-insulator, silicon-on-insulator stacked, silicon-on-insulator stacked, silicon-on-insulator, and germanium-on-insulator, which can be selected according to the device fabrication requirements. In some embodiments, the substrate 100 is, for example, a silicon wafer with an epitaxial structure, and the epitaxial structure is, for example, a homoepitaxial layer. The substrate 100 has a pixel region 100b and a logic region 100a. The pixel region 100b and the logic region 100a can be separated by a trench isolation structure 101. Both the pixel region 100b and the logic region 100a can be used to form transistors. Generally speaking, the pixel region 100b can be used to form an NMOS transistor, and the logic region 100a can be used to form both an NMOS transistor and a PMOS transistor.
[0073] Please continue reading. Figure 11 Step S200 is executed: a first gate structure 201 and a second gate structure 202 are formed on the substrate 100. The first gate structure 201 is located within the logic region 100a and can be arranged at intervals within the logic region 100a. The second gate structure 202 is located within the pixel region 100b and can be arranged at intervals within the pixel region 100b. The first gate structure 201 and the second gate structure 202 can be formed simultaneously or in stages. The structures of the first gate structure 201 and the second gate structure 202 can be the same. For example, both the first gate structure 201 and the second gate structure 202 can include a gate oxide layer, a gate protective layer, and a gate electrode layer. The gate oxide layer and the gate electrode layer are stacked sequentially on the substrate 100, and the gate protective layer can cover the exposed surfaces of the gate oxide layer and the gate electrode layer.
[0074] In some embodiments, the gate oxide layer may be made of silicon oxide, the gate protection layer may be made of silicon oxide and / or silicon nitride, and the gate electrode layer may be made of polysilicon.
[0075] In some embodiments, the height of the second gate structure 202 may be greater than the height of the first gate structure 201, but should not be limited thereto.
[0076] like Figure 12As shown, in step S300, a first photoresist layer 301 is formed on the substrate 100. The first photoresist layer 301 is located at least within the pixel region 100b and covers the substrate 100 and the second gate structure 202 within the pixel region 100b. Using the first photoresist layer 301 as a mask, ion implantation is performed on the substrate 100 on both sides of the first gate structure 201 to form a first source / drain region 401 within the substrate 100 on both sides of the first gate structure 201. Since the logic region 100a is typically used to form NMOS and PMOS transistors, ion implantation on the substrate 100 on both sides of the first gate structure 201 can be performed stepwise. Figure 12 The logic region 100a in the example only shows one PMOS transistor. For example, P-type ion implantation can be performed on a portion of the substrate 100 on both sides of the first gate structure 201 to form a P-type first source / drain region 401 in the substrate 100 on both sides of the first gate structure 201. At this time, the first photoresist layer 301 needs to cover the substrate 100 in the pixel region 100b, the second gate structure 202, and the remaining first gate structure 201 and the substrate 100 on both sides in the logic region 100a. This portion of the first gate structure 201 and the P-type first source / drain regions 401 on both sides can constitute a PMOS transistor. Afterwards, the first photoresist layer 301 is removed, and then a PMOS transistor is formed. A new first photoresist layer 301 is formed, which needs to cover the substrate 100, the second gate structure 202, the P-type first source / drain region 401 in the logic region 100a, and the first gate structure 201 between the P-type first source / drain regions 401. Then, N-type ion implantation is performed on the substrate 100 on both sides of the remaining first gate structure 201 to form N-type first source / drain regions 401 in the substrate 100 on both sides of the remaining first gate structure 201. This part of the first gate structure 201 and the N-type first source / drain regions 401 on both sides can form an NMOS transistor. Of course, the formation order of the N-type first source / drain region 401 and the P-type first source / drain region 401 can be interchanged.
[0077] In some embodiments, the P-type ion is a boron ion (B+). To avoid rapid diffusion of boron ions (B+) after implantation, boron difluoride (BF2) is usually implanted, and fluoride ions (F-) are used to suppress the diffusion of boron ions (B+). The N-type ion can be a phosphorus ion (P+) or an arsenic ion (AS+).
[0078] like Figure 13As shown, in step S400, the first photoresist layer 301 is removed, and a first barrier layer 501 is formed on the substrate 100. The first barrier layer 501 also conformally covers the outer surfaces of the first gate structure 201 and the second gate structure 202. Furthermore, since the substrate 100 needs to be ion implanted subsequently, to avoid the first barrier layer 501 increasing the difficulty of subsequent ion implantation, the material of the first barrier layer 501 usually needs to be a relatively soft material, such as silicon oxide.
[0079] like Figure 14 As shown, in step S400, a second photoresist layer 302 is formed on the substrate 100. The second photoresist layer 302 is located within the logic region 100a and covers the substrate 100 and the first gate structure 201 within the logic region 100a. Using the second photoresist layer 302 as a mask, ion implantation is performed on the substrates 100 on both sides of the second gate structure 202 to form second source / drain regions 402 within the substrates 100 on both sides of the second gate structure 202. Since the pixel region 100b is typically used to form an NMOS transistor, N-type ion implantation can be performed on the substrates 100 on both sides of the second gate structure 202 to form N-type second source / drain regions 402 within the substrates 100 on both sides of the second gate structure 202.
[0080] like Figure 15 As shown, to avoid bulging of the first barrier layer 501, the first barrier layer 501 can be removed directly after removing the second photoresist layer 302. In some embodiments, an etching process can be used to remove the first barrier layer 501. To avoid damaging the first gate structure 201 and the second gate structure 202 when removing the first barrier layer 501, a plasma etching process can be used to remove the first barrier layer 501. However, when removing the first barrier layer 501, over-etching is usually performed to remove it completely. Since there is no stop layer between the first barrier layer 501 and the substrate 100, after removing the first barrier layer 501, during over-etching, the plasma will bombard the surface of the substrate 100, resulting in defects on the surface of the substrate 100.
[0081] like Figure 16As shown, a third photoresist layer 303 is formed on the substrate 100. The third photoresist layer 303 is located within the logic region 100a and covers the substrate 100 and the first gate structure 201 within the logic region 100a. At this time, the third photoresist layer 303 can cover the entire logic region 100a. Using the third photoresist layer 303 as a mask, fluorine ions are implanted into the portion of the surface of the substrate 100 located within the pixel region 100b. After the subsequent first annealing process, the fluorine ions can combine with the dangling bonds on the surface of the substrate 100 (the missing atoms in the silicon crystal are filled by fluorine to form stable silicon-fluorine bonds), thereby passivating the dangling bonds on the surface of the substrate 100, thereby repairing the damage to the surface of the substrate 100 caused by the removal of the first barrier layer 501, and reducing the white pixels and dark current of the device.
[0082] It should be noted that since the electrical parameters of the transistors in the logic region 100a are particularly important, and the implantation of fluorine ions on the surface of the substrate 100 may affect the electrical parameters of the transistors, fluorine ions are implanted only on the surface of the substrate 100 located in the pixel region 100b, and not on the surface of the substrate 100 located in the logic region 100a. This can prevent the electrical parameters of the transistors in the logic region 100a from drifting, and at the same time prevent the diffusion of doped ions in the first source-drain region 401 and the second source-drain region 402.
[0083] In some embodiments, instead of forming a third photoresist layer 303 on the substrate 100, fluorine ions may be implanted directly into the portion of the substrate 100 located in the pixel region 100b and the logic region 100a.
[0084] like Figure 17 As shown, the third photoresist layer 303 is removed, and an oxide layer 600 is formed on the substrate 100. The oxide layer 600 covers the surface of the substrate 100, thereby further repairing the defects on the surface of the substrate 100. At the same time, the oxide layer 600 can also protect the surface of the substrate 100 and prevent damage to the surface of the substrate 100 when the second barrier layer 502 is formed subsequently.
[0085] like Figure 18As shown, in some embodiments, after removing the first blocking layer 501, an oxide layer 600 can be formed on the substrate 100 first, so that the oxide layer 600 covers the surface of the substrate 100 and repairs the defects on the surface of the substrate 100. Then, a third photoresist layer 303 is formed on the oxide layer 600. The third photoresist layer 303 is located within the logic region 100a and covers the oxide layer 600 within the logic region 100a. At this time, the third photoresist layer 303 can still cover the entire logic region 100a. Then, using the third photoresist layer 303 as a mask, fluorine ions are implanted into the portion of the surface of the substrate 100 located within the pixel region 100b. The fluorine ions can be implanted at least at the interface between the portion of the surface of the substrate 100 located within the pixel region 100b and the oxide layer 600. In this case, fluoride ions can still combine with dangling bonds on the surface of substrate 100 after the first annealing process, passivating the dangling bonds on the surface of substrate 100, thereby repairing the damage to the surface of substrate 100 caused by the removal of the first barrier layer 501, reducing the white pixels and dark current of the device; at the same time, since an oxide layer 600 covers the substrate 100, it is easier to implant fluoride ions at the interface between substrate 100 and oxide layer 600 than to directly implant fluoride ions on the surface of substrate 100, and the requirements for the ion implantation process are less.
[0086] In some embodiments, the oxide layer 600 can be formed at room temperature using a decoupled plasma oxidation (DPO) process, thereby avoiding the need for high-temperature processes and reducing the possibility of device parameter drift.
[0087] Further, step S700 is executed, performing a first annealing process. The first annealing process can simultaneously activate the impurity ions doped in the first source / drain region 401 and the second source / drain region 402. At the same time, the first annealing process also causes the fluorine ions implanted on the surface of the substrate 100 to combine with the dangling bonds on the surface of the substrate 100, thereby passivating the dangling bonds on the surface of the substrate 100 and repairing the damage to the surface of the substrate 100 caused by the removal of the first barrier layer 501.
[0088] like Figure 19 As shown, in step S800, a second barrier layer 502 is formed on the substrate 100. The second barrier layer 502 also conformally covers the outer surfaces of the first gate structure 201 and the second gate structure 202. Since the first annealing process is performed before the formation of the second barrier layer 502, the first annealing process can release at least part of the fluorine in the first source / drain region 401 (the P-type first source / drain region 401) in advance, thus preventing bulging of the second barrier layer 502.
[0089] It should be noted that although the substrate 100 has an oxide layer 600 on its surface during the first annealing process, the thickness of this oxide layer 600 is relatively thin, for example, less than 100 nm. Even if fluorine escapes from the substrate 100 and enters the oxide layer 600, the oxide layer 600 is relatively thin, so the fluorine can pass through the oxide layer 600 and it is not easy to cause the oxide layer 600 to bulge.
[0090] Furthermore, the material of the second barrier layer 502 can be the same as that of the first barrier layer 501, for example, both can be silicon oxide. However, the material of the second barrier layer 502 can also be different from that of the first barrier layer 501.
[0091] In some embodiments, the hardness of the second barrier layer 502 can be greater than that of the first barrier layer 501. By increasing the hardness of the second barrier layer 502, the incomplete release of fluorine in the first source / drain region 401 of the P-type is prevented, thus avoiding the second barrier layer 502 from bubbling again. For example, the second barrier layer 502 can be made of silicon oxide and can be generated in a pure oxygen environment at 900℃~1200℃. At this time, the structure of the second barrier layer 502 is dense and the hardness is high (the density can reach 2.2g / cm³). Alternatively, after the second barrier layer 502 is formed on the substrate 100, a second annealing process can be performed at a temperature above 1300℃. The high temperature causes the atoms inside the silicon oxide to rearrange, reducing micropores and structural defects, and increasing the film density, thereby enhancing the hardness and mechanical strength of the second barrier layer 502. At the same time, the amorphous silicon oxide may partially crystallize to form a microcrystalline structure, further improving the hardness of the second barrier layer 502. Ultimately, the second barrier layer 502 is made of the same material as the first barrier layer 501 but has a different hardness. When etching the second barrier layer 502, there is no need to change the etching process, and the second barrier layer 502 can also be prevented from blistering again.
[0092] Of course, in some embodiments, the second barrier layer 502 can be made of a material with a greater hardness than the first barrier layer 501, so that the hardness of the second barrier layer 502 is greater than that of the first barrier layer 501. For example, the material of the first barrier layer 501 is silicon oxide and the material of the second barrier layer 502 is silicon oxynitride. In this case, the etching process may need to be adjusted when etching the second barrier layer 502 in the future.
[0093] In some embodiments, the hardness of the top surface of the second barrier layer 502 can be greater than the hardness of the top surface of the first barrier layer 501. For example, the material of the second barrier layer 502 can be silicon oxide. After the second barrier layer 502 is formed on the substrate 100, the surface of the second barrier layer 502 can be bombarded with plasma (such as argon ions) to eliminate microcracks and pores on the top surface of the second barrier layer 502 through physical sputtering, making the top surface of the second barrier layer 502 denser and thus improving the hardness of the top surface of the second barrier layer 502; alternatively, high-temperature molten nano-silicon carbide or silicon dioxide particles can be sprayed at high speed onto the second barrier layer 502. The top surface of the second barrier layer 502 is coated with a dense coating, thereby significantly improving the hardness and wear resistance of the top surface of the second barrier layer 502; or, the top surface of the second barrier layer 502 can be surface treated in a nitrogen-containing gas, where the nitrogen-containing gas combines with the oxygen on the top surface of the second barrier layer 502 to form a thin layer of silicon oxynitride, which can also improve the hardness of the top surface of the second barrier layer 502, ultimately making the hardness of the top surface of the second barrier layer 502 greater than that of the top surface of the first barrier layer 501.
[0094] Of course, the above describes an embodiment where the second barrier layer 502 is a single-layer structure. In some embodiments, the second barrier layer 502 can also be a double-layer structure. For example, the second barrier layer 502 may include a first sub-film layer and a second sub-film layer stacked sequentially from bottom to top. The thickness of the second sub-film layer may be less than the thickness of the first sub-film layer, and the hardness of the second sub-film layer may be greater than the hardness of the first sub-film layer. In this case, the material of the second sub-film layer may be silicon oxynitride, etc., and the material of the first sub-film layer may be silicon oxide, etc.
[0095] like Figure 20 As shown, after forming the second barrier layer 502, an etching process can be used to remove the oxide layer 600 and the second barrier layer 502 on the first source / drain region 401 and the second source / drain region 402, and then a metal contact layer 700 can be formed on the exposed first source / drain region 401 and the second source / drain region 402. The material of the metal contact layer 700 can typically be a metal silicide.
[0096] In summary, this embodiment provides a method for fabricating a semiconductor device, including providing a substrate 100 having a pixel region 100b and a logic region 100a; forming a first gate structure 201 and a second gate structure 202 on the substrate 100, the first gate structure 201 being located within the logic region 100a and the second gate structure 202 being located within the pixel region 100b; performing ion implantation on the substrate 100 on both sides of the first gate structure 201 to form a first source / drain region 401 within the substrate 100 on both sides of the first gate structure 201; and forming a first barrier layer 50 on the substrate 100. 1. The first barrier layer 501 also conformally covers the outer surfaces of the first gate structure 201 and the second gate structure 202; ion implantation is performed on the substrates 100 on both sides of the second gate structure 202 to form second source / drain regions 402 in the substrates 100 on both sides of the second gate structure 202; the first barrier layer 501 is removed, and fluorine ions are implanted at least in the portion of the surface of the substrate 100 located in the pixel region 100b; a first annealing process is performed; a second barrier layer 502 is formed on the substrate 100, and the second barrier layer 502 also conformally covers the outer surfaces of the first gate structure 201 and the second gate structure 202. After removing the first barrier layer 501, this application implants fluorine ions into at least a portion of the surface of the substrate 100 located within the pixel region 100b. After the first annealing process, the fluorine ions can combine with the dangling bonds on the surface of the substrate 100, thereby passivating the dangling bonds on the surface of the substrate 100 and repairing the damage to the surface of the substrate 100 caused by the removal of the first barrier layer 501, reducing the white pixels and dark current of the device. At the same time, the first annealing process is performed before the formation of the second barrier layer 502. The first annealing process can release at least a portion of the fluorine in the first source / drain region 401 in advance, avoiding bulging of the second barrier layer 502.
[0097] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.
[0098] It should also be noted that although preferred embodiments have been disclosed above, these embodiments are not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application, or modify them into equivalent embodiments, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application, without departing from the content of the technical solutions of this application, shall still fall within the scope of protection of the technical solutions of this application.
[0099] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.
[0100] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and is not intended to limit the scope of this application. It must be noted that the singular forms “a” and “an” as used herein include plural bases unless the context clearly indicates the opposite. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood as having the definition of logical “or”, not logical “exclusive OR”, unless the context clearly indicates the opposite. Furthermore, implementations of the methods and / or devices in the embodiments of this application may include performing selected tasks manually, automatically, or in combination.
Claims
1. A method for fabricating a semiconductor device, characterized in that, This includes the following steps, performed sequentially: A substrate is provided, the substrate having pixel regions and logic regions; A first gate structure and a second gate structure are formed on the substrate, wherein the first gate structure is located within the logic region and the second gate structure is located within the pixel region; Ion implantation is performed on the substrates on both sides of the first gate structure to form a first source / drain region in the substrates on both sides of the first gate structure; A first barrier layer is formed on the substrate, and the first barrier layer also conformally covers the outer surfaces of the first gate structure and the second gate structure; Ion implantation is performed on the substrates on both sides of the second gate structure to form second source / drain regions within the substrates on both sides of the second gate structure; Remove the first barrier layer and implant fluorine ions into at least a portion of the surface of the substrate located within the pixel region; Perform the first annealing process; and, A second barrier layer is formed on the substrate, and the second barrier layer also conformally covers the outer surfaces of the first gate structure and the second gate structure.
2. The method for fabricating a semiconductor device according to claim 1, characterized in that, After fluorine ion implantation at least in the portion of the substrate surface located within the pixel region, and before performing the first annealing process, the process further includes: An oxide layer is formed on the substrate; And, after performing the first annealing process, a second barrier layer is formed on the oxide layer.
3. The method for fabricating a semiconductor device according to claim 1, characterized in that, After removing the first barrier layer, an oxide layer is formed on the substrate, and fluorine ions are implanted at least at the interface between the oxide layer and the portion of the substrate surface located within the pixel region; And, after performing the first annealing process, a second barrier layer is formed on the oxide layer.
4. The method for fabricating a semiconductor device according to claim 2 or 3, characterized in that, The oxide layer is formed at room temperature using a decoupled plasma oxidation process.
5. The method for fabricating a semiconductor device according to claim 1, characterized in that, After removing the first barrier layer, the logic area is covered, and fluorine ions are implanted into the portion of the substrate surface located within the pixel area; Alternatively, after removing the first barrier layer, fluorine ions are injected into a portion of the surface of the substrate located within the logic region and the pixel region.
6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The hardness of the second barrier layer is greater than that of the first barrier layer; or, the hardness of the top surface of the second barrier layer is greater than that of the top surface of the first barrier layer.
7. The method for fabricating a semiconductor device according to claim 6, characterized in that, After the second barrier layer is formed on the substrate, a second annealing process is performed to make the hardness of the second barrier layer greater than that of the first barrier layer.
8. The method for fabricating a semiconductor device according to claim 6, characterized in that, After the second barrier layer is formed on the substrate, the surface of the second barrier layer is bombarded with plasma, or the top surface of the second barrier layer is surface treated in a nitrogen-containing gas to make the hardness of the top surface of the second barrier layer greater than that of the top surface of the first barrier layer.
9. The method for fabricating a semiconductor device according to claim 6, characterized in that, The second barrier layer includes a first sub-film layer and a second sub-film layer stacked sequentially from bottom to top. The thickness of the second sub-film layer is less than the thickness of the first sub-film layer, and the hardness of the second sub-film layer is greater than the hardness of the first sub-film layer.
10. The method for fabricating a semiconductor device according to claim 1, characterized in that, After forming the second barrier layer on the substrate, the method further includes: Remove the portion of the second barrier layer located on the first source / drain region and the second source / drain region; A metal contact layer is formed on the first source / drain region and the second source / drain region.