Display panel and electronic equipment

Abstract

The embodiment of the invention provides a display panel and electronic equipment, and relates to the technical field of display, the display panel comprises a substrate, a first conductive layer, a first insulating layer and a second conductive layer, the first conductive layer is located on one side of the substrate, the first conductive layer comprises a plurality of first wiring parts arranged at intervals, the first wiring parts extend in the first direction, and the second wiring parts extend in the second direction; at least part of the first wiring parts in the plurality of first wiring parts are arranged at intervals in the first direction; a plurality of first through holes are formed in the first insulating layer; the second conducting layer is located on the side, away from the first conducting layer, of the first insulating layer, the second conducting layer comprises a plurality of second conducting wires, the second conducting wires extend in the second direction, the second conducting wires are arranged at intervals in the first direction, and the second conducting wires are electrically connected with the first wiring part through the corresponding first through holes. According to the display panel, the wire resistance when the first wiring part is in short circuit with other conductive wires can be increased, so that the problem of heating of the display panel can be improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a display panel and an electronic device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and flat panel displays based on light-emitting diodes (LEDs) are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display panels.

[0003] However, there are still some problems with the display panel that need to be addressed. Summary of the Invention

[0004] To overcome the technical problems mentioned in the background, this application provides a display panel, which includes: Substrate; A first conductive layer is located on one side of the substrate. The first conductive layer includes a plurality of first traces spaced apart. The first traces extend along a first direction, and at least a portion of the plurality of first traces are spaced apart along the first direction. A first insulating layer is located on the side of the first conductive layer that is away from or close to the substrate, and a plurality of first through holes are provided on the first insulating layer along the thickness direction of the substrate; The second conductive layer is located on the side of the first insulating layer away from the first conductive layer. The second conductive layer includes a plurality of second conductive traces. The second conductive traces extend along a second direction. The plurality of second conductive traces are arranged at intervals along the first direction. The second conductive traces are electrically connected to the first trace portion through corresponding first through holes. The first direction intersects the second direction.

[0005] In some possible implementations, the display panel includes a bending area, at least a portion of the first trace is located in the bending area, and at least a portion of the first through hole is located in the bending area; Preferably, along the second direction, a plurality of the first wiring portions are spaced apart; Preferably, the display panel further includes a first display sub-region and a second display sub-region, the first display sub-region and the second display sub-region being located on opposite sides of the bending region, the first display sub-region, the bending region and the second display sub-region being arranged sequentially along the second direction, and along the thickness direction of the substrate, the first insulating layer is provided with a plurality of second through holes, the plurality of second through holes being located in the first display sub-region, the first conductive layer further includes a plurality of second wiring portions spaced apart, the plurality of second wiring portions being located in the first display sub-region, the second wiring portions extending along the first direction, at least a portion of the plurality of second wiring portions being spaced apart along the first direction, and the second conductive wirings being electrically connected to the second wiring portions through corresponding second through holes; Preferably, a plurality of second wiring portions are spaced apart along the second direction; Preferably, along the thickness direction of the substrate, the first insulating layer is provided with a plurality of third through holes, the plurality of third through holes being located in the second display sub-region. The first conductive layer further includes a plurality of third trace portions spaced apart, the plurality of third trace portions being located in the second display sub-region. The third trace portions extend along a first direction, and at least a portion of the plurality of third trace portions are spaced apart along the first direction. The second conductive trace is electrically connected to the third trace portion through the corresponding third through hole. Preferably, a plurality of the third wiring portions are spaced apart along the second direction; Preferably, along the second direction, a second conductive trace is electrically connected to a plurality of first trace portions through a corresponding first through-hole, electrically connected to a plurality of second trace portions through a corresponding second through-hole, and electrically connected to a plurality of third trace portions through a corresponding third through-hole; Preferably, the first direction includes a direction parallel to the extension direction of the bending axis of the bending region; Preferably, the first direction and the second direction are perpendicular to each other.

[0006] In some possible implementations, the distance from the bending axis of the bending area to the side of the first display sub-area away from the bending area is greater than or equal to 1 cm; Preferably, the distance from the bending axis of the bending area to the side of the second display sub-area away from the bending area is greater than or equal to 1 cm; Preferably, the orthographic projection of the side of the bending region away from the second display sub-region on the substrate overlaps with the orthographic projection of the side of the first display sub-region near the bending region on the substrate; Preferably, the orthographic projection of the side of the bending region away from the first display sub-region on the substrate overlaps with the orthographic projection of the side of the second display sub-region near the bending region on the substrate.

[0007] In some possible implementations, the display panel further includes a third display sub-region located on the side of the first display sub-region away from the bending region, and the first conductive layer further includes a plurality of first conductive traces located in the third display sub-region. The first conductive traces extend along a first direction, and the plurality of first conductive traces are spaced apart along a second direction. Along the thickness direction of the substrate, the first insulating layer is provided with a plurality of fourth through holes located in the third display sub-region. The second conductive traces located in the third display sub-region are electrically connected to the corresponding first conductive traces through the corresponding fourth through holes. Preferably, the display panel further includes a fourth display sub-region located away from the bending region in the second display sub-region, and the first conductive layer further includes a plurality of second conductive traces located in the fourth display sub-region. The second conductive traces extend along a first direction, and the plurality of second conductive traces are spaced apart along a second direction. Along the thickness direction of the substrate, the first insulating layer is provided with a plurality of fifth through holes located in the fourth display sub-region. The second conductive traces located in the fourth display sub-region are electrically connected to the corresponding second conductive traces through the corresponding fifth through holes. Preferably, the orthographic projection of the side of the third display sub-region closest to the first display sub-region on the substrate overlaps with the orthographic projection of the side of the first display sub-region closest to the third display sub-region on the substrate; Preferably, the orthographic projection of the side of the fourth display sub-region closest to the second display sub-region on the substrate overlaps with the orthographic projection of the side of the second display sub-region closest to the fourth display sub-region on the substrate.

[0008] In some possible implementations, the third display sub-region includes an opening region; Preferably, the edge of the orthographic projection of the third display sub-region onto the substrate includes a first arc. Preferably, the edge of the orthographic projection of the fourth display sub-region onto the substrate includes a second arc. Preferably, the orthographic projections of the plurality of first conductive traces located in the third display sub-region onto the substrate and the orthographic projections of the plurality of second conductive traces located in the third display sub-region onto the substrate form a mesh structure; Preferably, the orthographic projections of the plurality of second conductive traces located in the fourth display sub-region onto the substrate and the orthographic projections of the plurality of second conductive traces located in the fourth display sub-region onto the substrate form a mesh structure.

[0009] In some possible implementations, the display panel further includes: A pixel defining layer is located on the side of the second conductive layer away from the substrate, and the pixel defining layer encloses and forms a plurality of pixel openings; Multiple light-emitting units, at least a portion of which are located within the corresponding pixel opening, and a second trace portion is electrically connected to a pixel circuit of one or more of the light-emitting units; Preferably, one of the second wiring portions is electrically connected to a pixel circuit of 8 or fewer of the light-emitting units; Preferably, one of the third wiring portions is electrically connected to the pixel circuit of one or more of the light-emitting units; Preferably, one of the third wiring sections is electrically connected to a pixel circuit of 8 or fewer of the light-emitting units.

[0010] In some possible implementations, the display panel further includes: A pixel defining layer is located on the side of the second conductive layer away from the substrate, and the pixel defining layer encloses and forms a plurality of pixel openings; Multiple light-emitting units, at least a portion of which are located within the pixel opening, and the orthographic projection of a first trace portion on the substrate is electrically connected to a pixel circuit of one or more of the light-emitting units; Preferably, one of the first wiring portions is electrically connected to a pixel circuit of 8 or fewer of the light-emitting units.

[0011] In some possible implementations, the display panel further includes: A third conductive layer is located on the side of the first conductive layer away from the substrate. The third conductive layer includes a plurality of third conductive traces that extend along the second direction and are arranged along the first direction. The orthographic projection of the third conductive traces on the substrate overlaps with the orthographic projection of the first conductive traces on the substrate.

[0012] In some possible implementations, the second conductive trace provides an initialization voltage signal; Preferably, the third conductive trace includes a power supply voltage trace.

[0013] In some possible implementations, this application also provides an electronic device, which includes the display panel described in this application.

[0014] Compared with the prior art, this application has the following beneficial effects: The present application provides a display panel and electronic device, which can greatly increase the line resistance on the path between the first line section and other conductive lines by arranging multiple first line sections at intervals along a first direction. This can increase the line resistance when the first line section is short-circuited with other conductive lines, thereby improving the heat generation problem of the display panel. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 One of the top views of the display panel provided in the embodiments of this application; Figure 2 This is one of the partial top views of the bending area provided in the embodiments of this application; Figure 3 This is a second partial top view of the bending area provided in an embodiment of this application; Figure 4 Provided for the embodiments of this application Figure 2 Schematic diagram of the cross section at point AA; Figure 5 A second top view of the display panel provided in an embodiment of this application; Figure 6 This is a partial top view of the first display area provided in an embodiment of this application; Figure 7 Provided for the embodiments of this application Figure 6 Schematic diagram of the cross section at point BB; Figure 8 This is a partial top view of the second display area provided in an embodiment of this application; Figure 9 Provided for the embodiments of this application Figure 8 Cross-sectional view at point CC; Figure 10 This is a partial top view of the third display area provided in an embodiment of this application; Figure 11 Provided for the embodiments of this application Figure 10 Schematic diagram of the cross section at point DD; Figure 12 This is a partial top view of the fourth display area provided in an embodiment of this application; Figure 13 Provided for the embodiments of this application Figure 12 Schematic diagram of the cross section at the middle EE; Figure 14 A cross-sectional schematic diagram of a display panel including light-emitting units provided in an embodiment of this application; Figure 15 A top view of the display panel provided in the embodiments of this application, including a third conductive trace; Figure 16 Provided for the embodiments of this application Figure 15 Schematic diagram of the cross section at the middle FF; Figure 17 This is a schematic diagram of the pixel circuit provided in an embodiment of this application; Figure 18 A timing diagram of the pixel circuit provided in an embodiment of this application; Figure 19 This is a three-dimensional structural diagram of the electronic device provided in the embodiments of this application.

[0017] Reference numerals: 01, Display panel; 100, Electronic device; 1, Substrate; 2, First conductive layer; 21, First trace; 22, Second trace; 23, Third trace; 24, First conductive trace; 25, Second conductive trace; 3, First insulating layer; 31, First through-hole; 32, Second through-hole; 33, Third through-hole; 34, Fourth through-hole; 35, Fifth through-hole; 4, Second conductive layer; 41, Second conductive trace; 5, Bending shaft; 6, First electrode; 7, Light-emitting functional layer; 8, Second electrode layer; 9, Light-emitting unit; 10, Pixel defining layer; 101, Pixel opening; 11, Third conductive layer; 111, Third conductive trace; 12, Hole area; 13, First arc; 14, Second arc. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0020] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that, unless otherwise specified, different features in the embodiments of this application can be combined with each other.

[0021] Furthermore, when using terms such as "above," "above," "below," "below," and "relative" to define the positional relationship between two elements, this includes not only the state where the two elements are directly connected, but also the state where the two elements are separated by gaps or other elements. In addition, the terms "first," "second," and "third," etc., are only used for distinguishing descriptions and should not be interpreted as indicating or implying relative importance.

[0022] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.

[0023] The display panel in the related technology includes a bending area. The display panel includes a substrate, a first conductive layer located on one side of the substrate, and a second and a third conductive layer located on the side of the first conductive layer away from the substrate. The first conductive layer includes a plurality of first conductive traces, the second conductive layer includes a plurality of second conductive traces, and the third conductive layer includes a plurality of third conductive traces.

[0024] An insulating layer is also present between the first and second conductive traces, and the second conductive trace is electrically connected to the first conductive trace through a through-hole in the insulating layer. However, the area located in the bending region is susceptible to external interference, which can easily cause short circuits between the first and second conductive layers and other conductive layers, or between the first and second conductive layers. Short circuits generate heat, resulting in significant overheating of the display panel and causing inconvenience to the user.

[0025] To address the aforementioned technical problems, the following innovative technical solutions are designed. The specific implementation schemes of this application will be described in detail below with reference to the accompanying drawings. It should be noted that the deficiencies in the existing solutions are the result of practical experience and careful research. Therefore, the discovery process of the aforementioned technical problems and the solutions proposed in this embodiment below should be considered contributions made to this application during the invention process, and should not be construed as technical content known to those skilled in the art.

[0026] Please see Figures 1-4 This embodiment provides a display panel, which includes a bending region WZ and a substrate 1, a first conductive layer 2, a first insulating layer 3, and a second conductive layer 4.

[0027] The first conductive layer 2 is located on one side of the substrate 1. The first conductive layer 2 includes a plurality of first trace portions 21 spaced apart. At least a portion of the first trace portions 21 are located in the bending region WZ. The first trace portions 21 extend along the first direction X. At least a portion of the plurality of first trace portions 21 are arranged at intervals along the first direction X.

[0028] The first insulating layer 3 is located on the side of the first conductive layer 2 that is away from or close to the substrate 1. Along the thickness direction Z of the substrate 1, the first insulating layer 3 is provided with a plurality of first through holes 31, and at least some of the first through holes 31 are located in the bending region WZ.

[0029] The second conductive layer 4 is located on the side of the first insulating layer 3 away from the first conductive layer 2. The second conductive layer 4 includes a plurality of second conductive traces 41. The second conductive traces 41 extend along the second direction Y. The plurality of second conductive traces 41 are arranged at intervals along the first direction X. The second conductive traces 41 are electrically connected to the first trace portion 21 through corresponding first through holes 31. The first direction X intersects the second direction Y.

[0030] Among them, "multiple first wiring sections 21 are arranged at intervals along the first direction X" includes the following two cases.

[0031] For the first scenario, please refer to [link / reference] again. Figure 2 The extensions of the multiple first wiring sections 21 arranged at intervals along the first direction X are on the same straight line.

[0032] For the second scenario, please refer to [the relevant documentation]. Figure 3 Some of the first wiring portions 21 arranged at intervals along the first direction X can be slightly staggered, that is, the extension lines of some of the first wiring portions 21 arranged at intervals along the first direction X may not be on the same straight line.

[0033] In one specific embodiment, a plurality of first wiring portions 21 are spaced apart along the second direction Y.

[0034] Because the bending area WZ has a connecting part, when an external object hits the bending area WZ, it can easily cause cracks in the insulating layer or deformation in the insulating layer between the conductive layers. For example, the first insulating layer 3 between the first wiring portion 21 and other conductive layers in the bending area WZ may crack or deform, causing the first wiring portion 21 to contact and short-circuit with the conductive lines in other conductive layers. Alternatively, the first insulating layer 3 may crack or deform, causing the first wiring portion 21 to contact and short-circuit with the second conductive line 41. Or, the insulating layer between the second conductive line 41 and other conductive layers may crack or deform, causing the second conductive line 41 to contact and short-circuit with the conductive lines in other conductive layers.

[0035] In related technologies, multiple first trace portions 21 arranged along the first direction X are interconnected to form first conductive traces. That is, in related technologies, the same first conductive trace located in the bending region WZ is not interrupted in the first direction X, and the same first conductive trace is electrically connected to the second conductive trace 41 through multiple vias. The orthographic projections of the multiple first conductive traces and the multiple second conductive traces 41 on the substrate 1 form a mesh. Thus, when the first conductive trace located in the bending region WZ is short-circuited with conductive traces in other conductive layers, or when the first trace portion 21 is short-circuited with the second conductive trace 41, or when the second conductive trace 41 is short-circuited with conductive traces in other conductive layers, the line resistance along the short-circuit path is relatively small, which makes the display panel prone to overheating.

[0036] In this embodiment, the original first conductive trace located in the bending region WZ is broken to form multiple first trace portions 21. These multiple first trace portions 21 are arranged at intervals in the first direction X, and each first trace portion 21 is individually electrically connected to a corresponding second conductive trace 41 through a first through-hole 31 on the first insulating layer 3. Thus, even if the first trace portion 21 in the bending region WZ short-circuits with conductive traces in other conductive layers, the resistance along the short-circuit path is relatively large, making it less likely to generate excessive heat. This significantly improves the problem of heat generation caused by short circuits between the first trace portion 21 in the bending region WZ and conductive traces in other conductive layers.

[0037] Based on the above design, in this embodiment, by setting multiple first traces 21 to be arranged at intervals along the first direction X, the line resistance on the path between the first traces 21 and other conductive traces can be greatly increased, thereby increasing the line resistance when the first traces 21 are short-circuited with other conductive traces in the conductive layer, and thus improving the heat generation problem of the display panel.

[0038] For some possible implementations, please refer to Figure 1 , Figures 5-7 The display panel also includes a first display sub-area AA1 and a second display sub-area AA2, which are located on opposite sides of the bending area WZ. The first display sub-area AA1, the bending area WZ, and the second display sub-area AA2 are arranged sequentially along the second direction Y. Along the thickness direction Z of the substrate 1, the first insulating layer 3 is provided with a plurality of second through holes 32, which are located in the first display sub-area AA1. The first conductive layer 2 also includes a plurality of second wiring portions 22 spaced apart, which are located in the first display sub-area AA1. The second wiring portions 22 extend along the first direction X, and at least some of the second wiring portions 22 are spaced apart along the first direction X. The second conductive lines 41 are electrically connected to the second wiring portions 22 through the corresponding second through holes 32.

[0039] In one specific embodiment, a plurality of second wiring portions 22 are spaced apart along the second direction Y.

[0040] Optionally, the orthographic projection of the side of the bending region WZ away from the second display sub-region AA2 on the substrate 1 overlaps with the orthographic projection of the side of the first display sub-region AA1 close to the bending region WZ on the substrate 1.

[0041] The first display sub-area AA1 is close to the bending area WZ and is easily affected by the bending area WZ. The second trace portion 22 of the first display sub-area AA1 may also short-circuit with the conductive traces in other conductive layers.

[0042] In related technologies, multiple second traces 22 arranged along the first direction X are interconnected to form a first conductive trace. That is, in related technologies, the same first conductive trace located in the first display sub-region AA1 is not interrupted in the first direction X, and the same first conductive trace is electrically connected to the second conductive trace 41 through multiple vias. The orthographic projections of the multiple first conductive traces and the multiple second conductive traces 41 on the substrate 1 form a mesh. Thus, when the first conductive trace located in the first display sub-region AA1 short-circuits with conductive traces in other conductive layers, the line resistance along the short-circuit path of the first conductive trace is relatively small, making the display panel prone to overheating.

[0043] In this embodiment, the original first conductive trace located in the first display sub-region AA1 is disconnected to form multiple second trace portions 22. These multiple second trace portions 22 are arranged at intervals in the first direction X, and each second trace portion 22 is individually electrically connected to its corresponding second conductive trace 41 through a second through-hole 32 on the first insulating layer 3. Thus, even if a short circuit occurs between the second trace portion 22 of the first display sub-region AA1 and conductive traces in other conductive layers, it is less likely to generate significant heat, thereby greatly improving the problem of heat generation due to short circuits between the second trace portion 22 of the first display sub-region AA1 and conductive traces in other conductive layers.

[0044] Optionally, please see Figure 1 , Figure 5 , Figures 8-9 Along the thickness direction Z of the substrate 1, the first insulating layer 3 is provided with a plurality of third through holes 33, which are located in the second display sub-region AA2. The first conductive layer 2 also includes a plurality of third wiring portions 23 spaced apart, which are located in the second display sub-region AA2. The third wiring portions 23 extend along the first direction X, and at least some of the third wiring portions 23 are spaced apart along the first direction X. The second conductive trace 41 is electrically connected to the third wiring portion 23 through the corresponding third through hole 33.

[0045] In one specific embodiment, a plurality of third wiring portions 23 are spaced apart along the second direction Y.

[0046] Optionally, the orthographic projection of the side of the bending region WZ away from the first display sub-region AA1 on the substrate 1 overlaps with the orthographic projection of the side of the second display sub-region AA2 near the bending region WZ on the substrate 1.

[0047] The second display sub-area AA2 is close to the bending area WZ and is easily affected by the bending area WZ. The third trace 23 of the second display sub-area AA2 is also prone to short circuit with the conductive traces in other conductive layers.

[0048] In related technologies, multiple third traces 23 arranged along the first direction X are interconnected to form a first conductive trace. Specifically, in the related technologies, the same first conductive trace located in the second display sub-region AA2 is not interrupted in the first direction X, and the same first conductive trace is electrically connected to the second conductive trace 41 through multiple vias. The orthographic projections of the multiple first conductive traces and the multiple second conductive traces 41 on the substrate 1 form a mesh. Thus, when a first conductive trace located in the third display sub-region AA3 short-circuits with conductive traces in other conductive layers, the line resistance along the short-circuit path of the first conductive trace is relatively small, making the display panel prone to overheating.

[0049] In this embodiment, the original first conductive trace located in the second display sub-region AA2 is disconnected to form multiple third trace portions 23. These multiple third trace portions 23 are arranged at intervals in the first direction X, and each third trace portion 23 is individually electrically connected to the corresponding second conductive trace 41 through a third through-hole 33 on the first insulating layer 3. Thus, even if the third trace portion 23 of the second display sub-region AA2 short-circuits with conductive traces in other conductive layers, it is less likely to generate excessive heat, thereby greatly improving the problem of heat generation due to short circuits between the third trace portion 23 of the second display sub-region AA2 and conductive traces in other conductive layers.

[0050] Optionally, the first direction X includes the direction in which the bending axis 5 of the bending region WZ extends, and the first direction X is perpendicular to the second direction Y. When the display panel is bent, it bends along the central axis, where the central axis of the display panel when bent is the bending axis 5.

[0051] When the bending area WZ bends, it has a bending axis 5. The extension direction of the bending axis 5 is the first direction X, and the bending direction of the display panel is the second direction Y. The first direction X and the second direction Y are perpendicular to each other.

[0052] For some possible implementations, please refer to Figure 1 , Figure 5 , Figures 10-11The display panel also includes a third display sub-region AA3 located on the side of the first display sub-region AA1 away from the bending region WZ. The first conductive layer 2 also includes a plurality of first conductive traces 24 located in the third display sub-region AA3. The first conductive traces 24 extend along the first direction X and are spaced apart along the second direction Y. Along the thickness direction Z of the substrate 1, the first insulating layer 3 is provided with a plurality of fourth through holes 34 located in the third display sub-region AA3. The second conductive traces 41 located in the third display sub-region AA3 are electrically connected to the corresponding first conductive traces 24 through the corresponding fourth through holes 34.

[0053] Optionally, the orthographic projection of the side of the third display sub-region AA3 closest to the first display sub-region AA1 on the substrate 1 overlaps with the orthographic projection of the side of the first display sub-region AA1 closest to the third display sub-region AA3 on the substrate 1.

[0054] Optionally, the orthographic projection of the plurality of first conductive traces 24 located in the third display sub-region AA3 onto the substrate 1 and the orthographic projection of the plurality of second conductive traces 41 located in the third display sub-region AA3 onto the substrate 1 form a mesh structure.

[0055] The third display sub-region AA3 is far from the bending region WZ, and is less susceptible to influence. This means the first conductive trace 24 located in the third display sub-region AA3 is less likely to short-circuit with conductive traces in other conductive layers. Therefore, without disconnecting the first conductive trace 24 along the first direction X, the orthographic projections of the multiple first conductive traces 24 on the substrate 1 and the orthographic projections of the multiple second conductive traces 41 located in the third display sub-region AA3 on the substrate 1 form a mesh structure. In this way, while ensuring the first conductive traces 24 are less likely to short-circuit with conductive traces in other conductive layers, the signal transmission effect between the first conductive traces 24 and the second conductive traces 41 can be improved, thereby enhancing the display effect of the display panel.

[0056] Preferably, please refer to Figure 1 , Figure 5 , Figures 12-13 The display panel also includes a fourth display sub-region AA4 located away from the bending region WZ in the second display sub-region AA2. The first conductive layer 2 also includes a plurality of second conductive traces 25 located in the fourth display sub-region AA4. The second conductive traces 25 extend along the first direction X and are spaced apart along the second direction Y. Along the thickness direction Z of the substrate 1, the first insulating layer 3 is provided with a plurality of fifth through holes 35 located in the fourth display sub-region AA4. The second conductive traces 41 located in the fourth display sub-region AA4 are electrically connected to the corresponding second conductive traces 25 through the corresponding fifth through holes 35.

[0057] Optionally, the orthographic projection of the side of the fourth display sub-region AA4 closest to the second display sub-region AA2 on the substrate 1 overlaps with the orthographic projection of the side of the second display sub-region AA2 closest to the fourth display sub-region AA4 on the substrate 1.

[0058] Optionally, the orthographic projection of the plurality of second conductive traces 25 located in the fourth display sub-region AA4 onto the substrate 1 and the orthographic projection of the plurality of second conductive traces 41 located in the fourth display sub-region AA4 onto the substrate 1 form a mesh structure.

[0059] The fourth display sub-region AA4 is far from the bending region WZ, and is less susceptible to influence. This means the second conductive traces 25 located in the fourth display sub-region AA4 are less likely to short-circuit with conductive traces in other conductive layers. Therefore, without disconnecting the second conductive traces 25 in the fourth display sub-region AA4 along the first direction X, the orthographic projections of the multiple first conductive traces 24 on the substrate 1 and the orthographic projections of the multiple second conductive traces 41 located in the fourth display sub-region AA4 on the substrate 1 form a mesh structure. In this way, while ensuring the second conductive traces 25 are less likely to short-circuit with conductive traces in other conductive layers, the signal transmission effect between the second conductive traces 25 and the second conductive traces 41 can be improved, thereby enhancing the display effect of the display panel.

[0060] Optionally, the orthographic projections of a plurality of first trace portions 21 in the same row onto the substrate 1 are spaced apart along the first direction X, the orthographic projections of a plurality of second trace portions 22 in the same row onto the substrate 1 are spaced apart along the first direction X, and the orthographic projections of a plurality of third trace portions 23 in the same row onto the substrate 1 are spaced apart along the first direction X.

[0061] Optionally, the orthographic projections of the first conductive electron traces 24 in the same row onto the substrate 1 are continuously arranged along the first direction X, that is, the orthographic projections of the first conductive electron traces 24 in the same row onto the substrate 1 are the same orthographic projection, that is, the first conductive electron traces 24 in the same row are not separated.

[0062] Optionally, the orthographic projections of the second conductive electronic traces 25 in the same row onto the substrate 1 are continuously arranged along the first direction X, that is, the orthographic projections of the second conductive electronic traces 25 in the same row onto the substrate 1 are the same orthographic projection, that is, the second conductive electronic traces 25 in the same row are not separated.

[0063] Optionally, the materials of the first trace 21, the second trace 22, the third trace 23, the first conductive trace 24, and the second conductive trace 25 may all include a titanium-aluminum-titanium three-layer structure stacked sequentially.

[0064] In some possible implementations, please refer again. Figure 1The third display sub-region AA3 includes an opening region 12, and the edge of the orthographic projection of the third display sub-region AA3 on the substrate 1 includes a first arc 13.

[0065] In one specific embodiment, the first arc 13 is located on the side of the third display sub-area AA3 away from the bending area WZ.

[0066] For example, a camera can be installed under the screen in the hole area 12 to improve the performance of the display panel. The third display sub-area AA3 includes the arc-corner area and the hole area 12. The arc-corner area of ​​the third display sub-area AA3 is the area adjacent to the first arc line 13. That is, the first conductive electronic trace 24 in the area with the arc-corner area and the hole area 12 is not interrupted. In this way, the display effect of the area of ​​the display panel with the arc-corner area and the hole area 12 can be improved.

[0067] Optionally, the edge of the orthographic projection of the fourth display sub-region AA4 onto the substrate 1 includes a second arc 14. For example, in one specific embodiment, the second arc 14 is located on the side of the fourth display sub-region AA4 away from the bending region WZ. The fourth display sub-region AA4 includes an arc-corner region, which is the region adjacent to the second arc 14. That is, the second conductive electronic trace 25 with the arc-corner region is not interrupted, thereby improving the display effect of the arc-corner region of the display panel.

[0068] Optionally, the first conductive trace 24 and the second conductive trace 41 can be configured to bypass the hole region 12 when they are in the hole region 12, that is, to partially surround it. However, in general, the first conductive trace 24 still extends along the first direction X, and the second conductive trace 41 still extends along the second direction Y.

[0069] In some possible implementations, please refer again. Figure 1 The distance L1 from the bending axis 5 of the bending area WZ to the side of the first display sub-area AA1 away from the bending area WZ is greater than or equal to 1cm.

[0070] If the distance L1 is set too small, the distance between the third display sub-area AA3 and the bending area WZ will be too small, and the first conductive trace 24 located in the third display sub-area AA3 may be affected, thereby causing the first conductive trace 24 to short-circuit with the conductive traces in other conductive layers.

[0071] If the distance L1 is set too large, it will be detrimental to the signal transmission of the second conductive trace 41, thereby affecting the display effect of the display panel.

[0072] For example, the distance L1 can be 1cm, 1.1cm, 1.2cm, 1.3cm, 1.4cm, or 1.5cm, etc. By reasonably setting the distance L1, the first conductive trace 24 of the third display sub-area AA3 is less likely to be short-circuited, while the signal transmission effect of the second conductive trace 41 is better, without affecting the display effect of the display panel.

[0073] Optionally, the distance L2 from the bending axis 5 of the bending area WZ to the side of the second display sub-area AA2 away from the bending area WZ is greater than or equal to 1 cm.

[0074] If the distance L2 is set too small, the distance between the fourth display sub-area AA4 and the bending area WZ will be too small, and the second conductive trace 25 located in the fourth display sub-area AA4 may be affected, thereby causing the second conductive trace 25 to short-circuit with the conductive traces in other conductive layers.

[0075] If the distance L2 is set too large, it will be detrimental to the signal transmission of the second conductive trace 41, thereby affecting the display effect of the display panel.

[0076] For example, the distance L2 can be 1cm, 1.1cm, 1.2cm, 1.3cm, 1.4cm, or 1.5cm, etc. By reasonably setting the distance L2, the signal transmission effect of the second conductive trace 41 can be improved without affecting the display effect of the display panel, while ensuring that the second conductive trace 25 of the fourth display sub-area AA4 is less likely to be short-circuited.

[0077] For some possible implementations, please refer to Figure 14 The display panel also includes a pixel defining layer 10 and multiple light-emitting units 9.

[0078] The pixel defining layer 10 is located on the side of the second conductive layer 4 away from the substrate 1, and the pixel defining layer 10 encloses and forms a plurality of pixel openings 101.

[0079] At least a portion of the light-emitting unit 9 is located within the pixel opening 101. The light-emitting unit 9 includes a first electrode 6, a light-emitting functional layer 7, and a second electrode layer 8, which are sequentially stacked along a direction away from the substrate 1. The first electrode 6 may be an anode, and the second electrode layer 8 may be a cathode.

[0080] Optionally, the second conductive trace 41 provides an initialization voltage signal.

[0081] The display panel includes a chip and the same initialization signal line located on the upper and lower edges of the display panel. The initialization signal line located on the upper and lower edges of the display panel extends along the first direction Z. The initialization signal line is electrically connected to the chip and is also electrically connected to a plurality of second conductive traces 41. The initialization signal provided by the chip passes through the initialization signal, the second conductive traces 41, and the first trace portion 21, the first trace portion 22, the first trace portion 23, the first conductive electronic trace 24, and the second conductive electronic trace 25 that are electrically connected to the second conductive traces 41, and finally provides an initialization voltage signal for the pixel circuit of the corresponding light-emitting unit.

[0082] Optionally, along the second direction Y, a second conductive trace 41 is electrically connected to a plurality of first trace portions 21 through a corresponding first through-hole 31, to a plurality of second trace portions 22 through a corresponding second through-hole 32, and to a plurality of third trace portions 23 through a corresponding third through-hole 33. That is, the same second conductive trace 41 extending along the second direction Y is electrically connected to the first trace portions 21, second trace portions 22, and third trace portions 23 arranged at intervals along the second direction Y. In addition, the same second conductive trace 41 extending along the second direction Y can also be electrically connected to the first conductive traces 24 and second conductive traces 25 arranged at intervals along the second direction Y.

[0083] Optionally, the display panel further includes pixel circuits, with a first wiring portion 21 electrically connected to a pixel circuit having one or more light-emitting units 9 and a pixel circuit having eight or fewer light-emitting units 9.

[0084] The initialization voltage signal flowing through the second conductive trace 41 is transmitted to the first trace section 21. Then, one first trace section 21 provides initialization voltage signals to the pixel circuits corresponding to 1-8 light-emitting units 9. For example, one first trace section 21 provides initialization voltage signals to the pixel circuits corresponding to 1, 2, 3, 4, 5, 6, 7, or 8 light-emitting units 9. In this way, by reasonably setting the number of light-emitting units 9 corresponding to the initialization voltage signals provided by the first trace section 21, the display panel is less likely to overheat due to short circuits between the first trace section 21 and conductive traces in other conductive layers, thus minimizing the impact on the display effect.

[0085] Optionally, at least one light-emitting unit 9 shares a pixel circuit, that is, a pixel circuit provides a corresponding electrical signal to at least one light-emitting unit 9. For example, a pixel circuit drives one light-emitting unit 9 to emit light, a pixel circuit drives two light-emitting units 9 to emit light, a pixel circuit drives three light-emitting units 9 to emit light, and a pixel circuit drives four light-emitting units 9 to emit light.

[0086] Optionally, a second wiring section 22 is electrically connected to a pixel circuit with one or more light-emitting units 9 and less than or equal to eight light-emitting units 9.

[0087] The initialization voltage signal of the second conductive trace 41 is transmitted to the second trace section 22. Then, one second trace section 22 provides initialization voltage signals to the pixel circuits corresponding to 1-8 light-emitting units 9. For example, one second trace section 22 provides initialization voltage signals to the pixel circuits corresponding to 1, 2, 3, 4, 5, 6, 7, or 8 light-emitting units 9. By appropriately setting the number of light-emitting units 9 corresponding to the initialization voltage signals provided by the second trace section 22, the display panel is less likely to overheat due to short circuits between the second trace section 22 and other conductive traces in the conductive layer, thus minimizing the impact on the display effect.

[0088] Optionally, a third wiring section 23 is electrically connected to a pixel circuit with one or more light-emitting units 9 and less than or equal to eight light-emitting units 9.

[0089] The initialization voltage signal of the second conductive trace 41 is transmitted to the third trace section 23. Then, one third trace section 23 provides initialization voltage signals to the pixel circuits corresponding to 1-8 light-emitting units 9. For example, one third trace section 23 provides initialization voltage signals to the pixel circuits corresponding to 1, 2, 3, 4, 5, 6, 7, or 8 light-emitting units 9. By appropriately setting the number of light-emitting units 9 in the pixel circuits corresponding to the initialization voltage signals provided by the third trace section 23, the display panel is less likely to overheat due to short circuits between the third trace section 23 and conductive traces in other conductive layers, thus minimizing the impact on the display panel's display performance.

[0090] For some possible implementations, please refer to Figure 15 and Figure 16 The display panel also includes a third conductive layer 11, which is located on the side of the first conductive layer 2 away from the substrate 1. The third conductive layer 11 includes a plurality of third conductive lines 111, which extend along the second direction Y and are arranged along the first direction X. The orthographic projection of the third conductive lines 111 on the substrate 1 overlaps with the orthographic projection of the first conductive lines on the substrate 1.

[0091] Optionally, the third conductive trace 111 includes a power supply voltage trace.

[0092] The third conductive trace 111 can be located on the side of the second conductive trace 41 closer to the substrate 1, or on the side of the second conductive trace 41 farther from the substrate 1, or the third conductive trace 111 can be disposed on the same layer as the second conductive trace 41.

[0093] In one embodiment, under the action of external force, the insulating layer between the third conductive trace 111 and the first trace portion 21 is prone to cracking, thereby causing the third conductive trace 111 and the first trace portion 21 to short-circuit.

[0094] Since the first display sub-area AA1 and the second display sub-area AA2 are close to the bending area WZ, the insulation layer between the third conductive trace 111 and the second trace portion 22 is broken, causing the third conductive trace 111 to contact the second trace portion 22, or the insulation layer between the third conductive trace 111 and the third trace portion 23 is broken, causing the third conductive trace 111 to contact the third trace portion 23.

[0095] In this application, the original first conductive trace located in the bending region WZ is broken to form multiple first trace portions 21. These multiple first trace portions 21 are arranged at intervals in the first direction X, and each first trace portion 21 is individually electrically connected to a corresponding second conductive trace 41 through a first through-hole 31 on the first insulating layer 3. Thus, even if a short circuit occurs between the first trace portion 21 and the third conductive trace 111 in the bending region WZ, it is less likely to generate significant heat, thereby greatly improving the problem of heat generation due to a short circuit between the first trace portion 21 and the third conductive trace 111 in the bending region WZ.

[0096] The original first conductive trace located in the first display sub-region AA1 is disconnected to form multiple second trace portions 22. These multiple second trace portions 22 are arranged at intervals in the first direction X, and each second trace portion 22 is individually electrically connected to the corresponding second conductive trace 41 through a second through-hole 32 on the first insulating layer 3. Thus, even if a short circuit occurs between the second trace portion 22 and the third conductive trace 111 in the first display sub-region AA1, it is less likely to generate significant heat, thereby greatly improving the problem of heat generation due to a short circuit between the second trace portion 22 and the third conductive trace 111 in the bending region WZ.

[0097] The original first conductive trace located in the second display sub-area AA2 is disconnected to form multiple third trace portions 23. These multiple third trace portions 23 are arranged at intervals in the first direction X, and each third trace portion 23 is individually electrically connected to the corresponding second conductive trace 41 through a third through-hole 33 on the first insulating layer 3. In this way, even if a short circuit occurs between the third trace portion 23 and the third conductive trace 111 in the second display sub-area AA2, it is less likely to generate excessive heat. This greatly improves the problem of heat generation due to a short circuit between the third trace portion 23 and the third conductive trace 111 in the bending area WZ, thereby providing a better user experience.

[0098] For some possible implementations, please refer to Figure 17 The pixel circuit provided in this application may include a driving transistor T1, a storage capacitor Cst, a data writing transistor T2, a compensation transistor T3, a gate reset transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, an anode reset transistor T7, and a drain reset transistor T8.

[0099] In addition, in this embodiment, the display panel may include multiple traces of signals or voltages such as data voltage signal line Vdata, first scan number trace Scan1, second scan signal trace Scan2, third scan signal trace Scan3, fourth scan signal trace Scan4, light emission control signal trace EM, driving voltage trace VDD, first initialization trace Vref1, second initialization trace Vref2, third initialization trace Vref3, and common voltage trace VSS, which will not be described in detail in this embodiment.

[0100] The first terminal of the storage capacitor Cst is connected to the drive voltage trace VDD, and the second terminal of the storage capacitor Cst is connected to the gate of the drive transistor T1.

[0101] The first light-emitting control transistor T5 is connected between the driving voltage line VDD and the first terminal of the driving transistor T1, and the second light-emitting control transistor T6 is connected between the second terminal of the driving transistor T1 and the second terminal of the anode reset transistor T7. The gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are connected to the light-emitting control signal line EM. The first terminal of the driving transistor T1 is one of the source and drain, and the second terminal is the other of the source and drain.

[0102] The data write transistor T2 is connected between the data voltage signal line Vdata and the first terminal of the drive transistor T1. The gate of the data write transistor T2 is connected to the second scan signal line Scan2.

[0103] The compensation transistor T3 is connected between the second terminal of the driving transistor T1 and the gate of the driving transistor T1. The gate of the compensation transistor T3 is connected to the third scan signal trace Scan3.

[0104] An anode reset transistor T7 is connected between the first electrode 6 of the light-emitting unit 9 and the first initialization trace Vref1. The gate of the anode reset transistor T7 is connected to the first scan signal trace Scan1. The first initialization trace Vref1 is used to provide a first initialization voltage to the first electrode 6 of the light-emitting unit 9.

[0105] Gate reset transistor T4 is connected between the second terminal of compensation transistor T3 and the second initialization trace Vref2. The gate of gate reset transistor T4 is connected to the fourth scan signal trace Scan4. The second initialization trace Vref2 is used to provide a second initialization voltage to the gate of drive transistor T1.

[0106] The drain reset transistor T8 is connected between the compensation transistor T3, the drive transistor T1 and the third initialization line Vref3, and the gate of the drain reset transistor T8 is connected to the first scan signal line Scan1.

[0107] Please see Figure 18 The operation of the pixel driving circuit 3 includes a first initialization stage, a data writing stage, a second initialization stage, and a light emission stage.

[0108] In the first initialization phase, the third scan signal line Scan3 and the fourth scan signal line Scan4 are input to the on level, for example, high level. The compensation transistor T3 and the control gate reset transistor T4 are turned on. The initialization voltage input to the second initialization trace Vref2 is written to the gate of the driving transistor T1 to initialize the gate of the driving transistor T1.

[0109] During the data writing phase, the second scan signal line Scan2 and the third scan signal line Scan3 are turned on. For example, a low input level on the second scan signal line Scan2 indicates a turn-on level, and a high input level on the third scan signal line Scan3 indicates a turn-on level. This controls the data writing transistor T2 and the compensation transistor T3 to turn on. The data voltage input on the data voltage signal line Vdata is written to the gate of the driving transistor T1 through the data writing transistor T2, the driving transistor T1, and the compensation transistor T3. The gate writing voltage of the driving transistor T1 is the sum of the data voltage input on the data voltage signal line Vdata and the threshold voltage of the driving transistor T1.

[0110] In the second initialization phase, the first scan signal line Scan1 is input with a conduction level, for example, a low level, controlling the anode reset transistor T7 and the drain reset transistor T8 to conduct. The initialization voltage input to the first initialization trace Vref1 is written to the first electrode 6 of the light-emitting unit 9, initializing the first electrode 6 of the light-emitting unit 9. Simultaneously, the initialization voltage of the third initialization trace Vref3 is written to the second electrode (e.g., the drain) of the compensation transistor T3 and the driving transistor T1, initializing the second electrode of the compensation transistor T3 and the driving transistor T1.

[0111] During the light-emitting stage, the light-emitting control signal line EM is input with a conduction level, such as a low level, which controls the first light-emitting control transistor T5, the second light-emitting control transistor T6, the first sub-switch transistor T9, and the second sub-switch transistor T10 to conduct. The first light-emitting control transistor T5, the second light-emitting control transistor T6, the driving transistor T1, the first sub-switch transistor T9, and the second sub-switch transistor T10 form a driving current path. The driving transistor T1 provides the driving current, causing the light-emitting unit 9 to emit light.

[0112] Wherein, the driving voltage trace VDD is the one in this application, and the first trace portion 21, the first trace portion 22, the first trace portion 23, the first conductive trace 24, the second conductive trace 25 and the second conductive trace 41 can all include the first initialization trace Vref1, the second initialization trace Vref2 and the third initialization trace Vref3 in this embodiment, and the second conductive trace 41 is electrically connected to the first trace portion 21, the first trace portion 22, the first trace portion 23, the first conductive trace 24 and the second conductive trace 25 of the same type through the first through hole 31. For example, when the second conductive trace 41 is the first initialization trace Vref1, the second conductive trace 41 is electrically connected to the first trace portion 21, the first trace portion 22, the first trace portion 23, the first conductive trace 24 and the second conductive trace 25 of the first initialization trace Vref1 through the first through hole 31.

[0113] Optionally, the first initialization trace Vref1, the second initialization trace Vref2, and the third initialization trace Vref3 are arranged at regular periodic intervals along the first direction X. For example, the first initialization trace Vref1, the second initialization trace Vref2, and the third initialization trace Vref3 are arranged at intervals along the first direction X in sequence, and the first initialization trace Vref1, the second initialization trace Vref2, and the third initialization trace Vref3 are treated as a repeating unit, with each repeating unit arranged at intervals along the first direction X in sequence; or, the second initialization trace Vref2, the first initialization trace Vref1, the second initialization trace Vref2, and the third initialization trace Vref3 are arranged at intervals along the first direction X, and the second initialization trace Vref2, the first initialization trace Vref1, the second initialization trace Vref2, and the third initialization trace Vref3 are treated as a repeating unit, with each repeating unit arranged at intervals along the first direction X in sequence.

[0114] The first initialization trace Vref1, the second initialization trace Vref2, and the third initialization trace Vref3 are arranged in a regular periodic interval along the second direction Y. For example, the first initialization trace Vref1, the second initialization trace Vref2, and the third initialization trace Vref3 are arranged in sequence along the second direction Y at intervals, and the first initialization trace Vref1, the second initialization trace Vref2, and the third initialization trace Vref3 are repeated units, and each repeated unit is arranged in sequence along the first direction X at intervals.

[0115] In the above embodiment, "the first trace 21 and the second conductive trace 41 make contact and short-circuit" means that different types of first trace 21 and second conductive trace 41 make contact and short-circuit. For example, the first initialization trace Vref1 in the first conductive layer makes contact and short-circuit with the second initialization trace Vref2 in the second conductive layer.

[0116] This embodiment uses an 8T1C pixel circuit as an example. The circuit in this embodiment can also be a 2T1C or 7T1C pixel circuit, which will not be described in detail here.

[0117] For some possible implementations, please refer to Figure 19 This application also provides an electronic device 100, which includes the display panel 01 described in this application, or a display panel 01 prepared by the method described in this application. The electronic device 100 may include devices with image processing capabilities, such as mobile phones, desktop computers, laptops, tablets, automotive displays, wearable devices, etc. Because the electronic device 100 includes the display panel 01 described in this application, it is less prone to overheating and does not affect the display effect of the electronic device.

[0118] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0119] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A display panel, characterized in that, The display panel includes: Substrate; A first conductive layer is located on one side of the substrate. The first conductive layer includes a plurality of first traces spaced apart. The first traces extend along a first direction, and at least a portion of the plurality of first traces are spaced apart along the first direction. A first insulating layer is located on the side of the first conductive layer that is away from or close to the substrate, and a plurality of first through holes are provided on the first insulating layer along the thickness direction of the substrate; The second conductive layer is located on the side of the first insulating layer away from the first conductive layer. The second conductive layer includes a plurality of second conductive traces. The second conductive traces extend along a second direction. The plurality of second conductive traces are arranged at intervals along the first direction. The second conductive traces are electrically connected to the first trace portion through corresponding first through holes. The first direction intersects the second direction.

2. The display panel according to claim 1, characterized in that, The display panel includes a bending area, at least a portion of the first wiring portion is located in the bending area, and at least a portion of the first through hole is located in the bending area; Preferably, along the second direction, a plurality of the first wiring portions are spaced apart; Preferably, the display panel further includes a first display sub-region and a second display sub-region, the first display sub-region and the second display sub-region being located on opposite sides of the bending region, the first display sub-region, the bending region and the second display sub-region being arranged sequentially along the second direction, and along the thickness direction of the substrate, the first insulating layer is provided with a plurality of second through holes, the plurality of second through holes being located in the first display sub-region, the first conductive layer further includes a plurality of second wiring portions spaced apart, the plurality of second wiring portions being located in the first display sub-region, the second wiring portions extending along the first direction, at least a portion of the plurality of second wiring portions being spaced apart along the first direction, and the second conductive wirings being electrically connected to the second wiring portions through corresponding second through holes; Preferably, a plurality of second wiring portions are spaced apart along the second direction; Preferably, along the thickness direction of the substrate, the first insulating layer is provided with a plurality of third through holes, the plurality of third through holes being located in the second display sub-region. The first conductive layer further includes a plurality of third trace portions spaced apart, the plurality of third trace portions being located in the second display sub-region. The third trace portions extend along a first direction, and at least a portion of the plurality of third trace portions are spaced apart along the first direction. The second conductive trace is electrically connected to the third trace portion through the corresponding third through hole. Preferably, a plurality of the third wiring portions are spaced apart along the second direction; Preferably, along the second direction, a second conductive trace is electrically connected to a plurality of first trace portions through a corresponding first through-hole, electrically connected to a plurality of second trace portions through a corresponding second through-hole, and electrically connected to a plurality of third trace portions through a corresponding third through-hole; Preferably, the first direction includes a direction parallel to the extension direction of the bending axis of the bending region; Preferably, the first direction and the second direction are perpendicular to each other.

3. The display panel according to claim 2, characterized in that, The distance from the bending axis of the bending area to the side of the first display sub-area away from the bending area is greater than or equal to 1 cm; Preferably, the distance from the bending axis of the bending area to the side of the second display sub-area away from the bending area is greater than or equal to 1 cm; Preferably, the orthographic projection of the side of the bending region away from the second display sub-region on the substrate overlaps with the orthographic projection of the side of the first display sub-region near the bending region on the substrate; Preferably, the orthographic projection of the side of the bending region away from the first display sub-region on the substrate overlaps with the orthographic projection of the side of the second display sub-region near the bending region on the substrate.

4. The display panel according to claim 2, characterized in that, The display panel further includes a third display sub-region located on the side of the first display sub-region away from the bending area. The first conductive layer further includes a plurality of first conductive traces located in the third display sub-region. The first conductive traces extend along a first direction, and the plurality of first conductive traces are spaced apart along a second direction. Along the thickness direction of the substrate, the first insulating layer is provided with a plurality of fourth through holes located in the third display sub-region. The second conductive traces located in the third display sub-region are electrically connected to the corresponding first conductive traces through the corresponding fourth through holes. Preferably, the display panel further includes a fourth display sub-region located away from the bending region in the second display sub-region, and the first conductive layer further includes a plurality of second conductive traces located in the fourth display sub-region. The second conductive traces extend along a first direction, and the plurality of second conductive traces are spaced apart along a second direction. Along the thickness direction of the substrate, the first insulating layer is provided with a plurality of fifth through holes located in the fourth display sub-region. The second conductive traces located in the fourth display sub-region are electrically connected to the corresponding second conductive traces through the corresponding fifth through holes. Preferably, the orthographic projection of the side of the third display sub-region closest to the first display sub-region on the substrate overlaps with the orthographic projection of the side of the first display sub-region closest to the third display sub-region on the substrate; Preferably, the orthographic projection of the side of the fourth display sub-region closest to the second display sub-region on the substrate overlaps with the orthographic projection of the side of the second display sub-region closest to the fourth display sub-region on the substrate.

5. The display panel according to claim 4, characterized in that, The third display sub-area includes an opening area; Preferably, the edge of the orthographic projection of the third display sub-region onto the substrate includes a first arc. Preferably, the edge of the orthographic projection of the fourth display sub-region onto the substrate includes a second arc. Preferably, the orthographic projections of the plurality of first conductive traces located in the third display sub-region onto the substrate and the orthographic projections of the plurality of second conductive traces located in the third display sub-region onto the substrate form a mesh structure; Preferably, the orthographic projections of the plurality of second conductive traces located in the fourth display sub-region onto the substrate and the orthographic projections of the plurality of second conductive traces located in the fourth display sub-region onto the substrate form a mesh structure.

6. The display panel according to claim 2, characterized in that, The display panel also includes: A pixel defining layer is located on the side of the second conductive layer away from the substrate, and the pixel defining layer encloses and forms a plurality of pixel openings; Multiple light-emitting units, at least a portion of which are located within the corresponding pixel opening, and a second trace portion is electrically connected to a pixel circuit of one or more of the light-emitting units; Preferably, one of the second wiring portions is electrically connected to a pixel circuit of 8 or fewer of the light-emitting units; Preferably, one of the third wiring portions is electrically connected to the pixel circuit of one or more of the light-emitting units; Preferably, one of the third wiring sections is electrically connected to a pixel circuit of 8 or fewer of the light-emitting units.

7. The display panel according to claim 1, characterized in that, The display panel also includes: A pixel defining layer is located on the side of the second conductive layer away from the substrate, and the pixel defining layer encloses and forms a plurality of pixel openings; Multiple light-emitting units, at least a portion of which are located within the pixel opening, and the orthographic projection of a first trace portion on the substrate is electrically connected to a pixel circuit of one or more of the light-emitting units; Preferably, one of the first wiring portions is electrically connected to a pixel circuit of 8 or fewer of the light-emitting units.

8. The display panel according to any one of claims 1-7, characterized in that, The display panel also includes: A third conductive layer is located on the side of the first conductive layer away from the substrate. The third conductive layer includes a plurality of third conductive traces that extend along the second direction and are arranged along the first direction. The orthographic projection of the third conductive traces on the substrate overlaps with the orthographic projection of the first conductive traces on the substrate.

9. The display panel according to claim 8, characterized in that, The second conductive trace provides an initialization voltage signal; Preferably, the third conductive trace includes a power supply voltage trace.

10. An electronic device, characterized in that, The electronic device includes the display panel as described in any one of claims 1-9.

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